PPCISelLowering.cpp revision 558692fd0a31d4d3ae4fd09a3a02f80da2e44e5c
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the PPCISelLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCISelLowering.h"
15#include "PPCMachineFunctionInfo.h"
16#include "PPCPerfectShuffle.h"
17#include "PPCPredicates.h"
18#include "PPCTargetMachine.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/ADT/VectorExtras.h"
21#include "llvm/CodeGen/CallingConvLower.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/PseudoSourceValue.h"
27#include "llvm/CodeGen/SelectionDAG.h"
28#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29#include "llvm/CallingConv.h"
30#include "llvm/Constants.h"
31#include "llvm/Function.h"
32#include "llvm/Intrinsics.h"
33#include "llvm/Support/MathExtras.h"
34#include "llvm/Target/TargetOptions.h"
35#include "llvm/Support/CommandLine.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#include "llvm/DerivedTypes.h"
39using namespace llvm;
40
41static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
42                                     CCValAssign::LocInfo &LocInfo,
43                                     ISD::ArgFlagsTy &ArgFlags,
44                                     CCState &State);
45static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
46                                            MVT &LocVT,
47                                            CCValAssign::LocInfo &LocInfo,
48                                            ISD::ArgFlagsTy &ArgFlags,
49                                            CCState &State);
50static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
51                                              MVT &LocVT,
52                                              CCValAssign::LocInfo &LocInfo,
53                                              ISD::ArgFlagsTy &ArgFlags,
54                                              CCState &State);
55
56static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
57cl::desc("enable preincrement load/store generation on PPC (experimental)"),
58                                     cl::Hidden);
59
60static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
61  if (TM.getSubtargetImpl()->isDarwin())
62    return new TargetLoweringObjectFileMachO();
63
64  return new TargetLoweringObjectFileELF();
65}
66
67PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
68  : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
69
70  setPow2DivIsCheap();
71
72  // Use _setjmp/_longjmp instead of setjmp/longjmp.
73  setUseUnderscoreSetJmp(true);
74  setUseUnderscoreLongJmp(true);
75
76  // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
77  // arguments are at least 4/8 bytes aligned.
78  setMinStackArgumentAlignment(TM.getSubtarget<PPCSubtarget>().isPPC64() ? 8:4);
79
80  // Set up the register classes.
81  addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
82  addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
83  addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
84
85  // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
86  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
87  setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
88
89  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
90
91  // PowerPC has pre-inc load and store's.
92  setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
93  setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
94  setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
95  setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
96  setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
97  setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
98  setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
99  setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
100  setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
101  setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
102
103  // This is used in the ppcf128->int sequence.  Note it has different semantics
104  // from FP_ROUND:  that rounds to nearest, this rounds to zero.
105  setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
106
107  // PowerPC has no SREM/UREM instructions
108  setOperationAction(ISD::SREM, MVT::i32, Expand);
109  setOperationAction(ISD::UREM, MVT::i32, Expand);
110  setOperationAction(ISD::SREM, MVT::i64, Expand);
111  setOperationAction(ISD::UREM, MVT::i64, Expand);
112
113  // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
114  setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
115  setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
116  setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
117  setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
118  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
119  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
120  setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
121  setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
122
123  // We don't support sin/cos/sqrt/fmod/pow
124  setOperationAction(ISD::FSIN , MVT::f64, Expand);
125  setOperationAction(ISD::FCOS , MVT::f64, Expand);
126  setOperationAction(ISD::FREM , MVT::f64, Expand);
127  setOperationAction(ISD::FPOW , MVT::f64, Expand);
128  setOperationAction(ISD::FSIN , MVT::f32, Expand);
129  setOperationAction(ISD::FCOS , MVT::f32, Expand);
130  setOperationAction(ISD::FREM , MVT::f32, Expand);
131  setOperationAction(ISD::FPOW , MVT::f32, Expand);
132
133  setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
134
135  // If we're enabling GP optimizations, use hardware square root
136  if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
137    setOperationAction(ISD::FSQRT, MVT::f64, Expand);
138    setOperationAction(ISD::FSQRT, MVT::f32, Expand);
139  }
140
141  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
142  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
143
144  // PowerPC does not have BSWAP, CTPOP or CTTZ
145  setOperationAction(ISD::BSWAP, MVT::i32  , Expand);
146  setOperationAction(ISD::CTPOP, MVT::i32  , Expand);
147  setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
148  setOperationAction(ISD::BSWAP, MVT::i64  , Expand);
149  setOperationAction(ISD::CTPOP, MVT::i64  , Expand);
150  setOperationAction(ISD::CTTZ , MVT::i64  , Expand);
151
152  // PowerPC does not have ROTR
153  setOperationAction(ISD::ROTR, MVT::i32   , Expand);
154  setOperationAction(ISD::ROTR, MVT::i64   , Expand);
155
156  // PowerPC does not have Select
157  setOperationAction(ISD::SELECT, MVT::i32, Expand);
158  setOperationAction(ISD::SELECT, MVT::i64, Expand);
159  setOperationAction(ISD::SELECT, MVT::f32, Expand);
160  setOperationAction(ISD::SELECT, MVT::f64, Expand);
161
162  // PowerPC wants to turn select_cc of FP into fsel when possible.
163  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
164  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
165
166  // PowerPC wants to optimize integer setcc a bit
167  setOperationAction(ISD::SETCC, MVT::i32, Custom);
168
169  // PowerPC does not have BRCOND which requires SetCC
170  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
171
172  setOperationAction(ISD::BR_JT,  MVT::Other, Expand);
173
174  // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
175  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
176
177  // PowerPC does not have [U|S]INT_TO_FP
178  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
179  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
180
181  setOperationAction(ISD::BITCAST, MVT::f32, Expand);
182  setOperationAction(ISD::BITCAST, MVT::i32, Expand);
183  setOperationAction(ISD::BITCAST, MVT::i64, Expand);
184  setOperationAction(ISD::BITCAST, MVT::f64, Expand);
185
186  // We cannot sextinreg(i1).  Expand to shifts.
187  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
188
189  setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
190  setOperationAction(ISD::EHSELECTION,   MVT::i64, Expand);
191  setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
192  setOperationAction(ISD::EHSELECTION,   MVT::i32, Expand);
193
194
195  // We want to legalize GlobalAddress and ConstantPool nodes into the
196  // appropriate instructions to materialize the address.
197  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
198  setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
199  setOperationAction(ISD::BlockAddress,  MVT::i32, Custom);
200  setOperationAction(ISD::ConstantPool,  MVT::i32, Custom);
201  setOperationAction(ISD::JumpTable,     MVT::i32, Custom);
202  setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
203  setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
204  setOperationAction(ISD::BlockAddress,  MVT::i64, Custom);
205  setOperationAction(ISD::ConstantPool,  MVT::i64, Custom);
206  setOperationAction(ISD::JumpTable,     MVT::i64, Custom);
207
208  // TRAP is legal.
209  setOperationAction(ISD::TRAP, MVT::Other, Legal);
210
211  // TRAMPOLINE is custom lowered.
212  setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
213
214  // VASTART needs to be custom lowered to use the VarArgsFrameIndex
215  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
216
217  // VAARG is custom lowered with the 32-bit SVR4 ABI.
218  if (    TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
219      && !TM.getSubtarget<PPCSubtarget>().isPPC64())
220    setOperationAction(ISD::VAARG, MVT::Other, Custom);
221  else
222    setOperationAction(ISD::VAARG, MVT::Other, Expand);
223
224  // Use the default implementation.
225  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
226  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
227  setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand);
228  setOperationAction(ISD::STACKRESTORE      , MVT::Other, Custom);
229  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
230  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64  , Custom);
231
232  // We want to custom lower some of our intrinsics.
233  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
234
235  // Comparisons that require checking two conditions.
236  setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
237  setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
238  setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
239  setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
240  setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
241  setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
242  setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
243  setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
244  setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
245  setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
246  setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
247  setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
248
249  if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
250    // They also have instructions for converting between i64 and fp.
251    setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
252    setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
253    setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
254    setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
255    // This is just the low 32 bits of a (signed) fp->i64 conversion.
256    // We cannot do this with Promote because i64 is not a legal type.
257    setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
258
259    // FIXME: disable this lowered code.  This generates 64-bit register values,
260    // and we don't model the fact that the top part is clobbered by calls.  We
261    // need to flag these together so that the value isn't live across a call.
262    //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
263  } else {
264    // PowerPC does not have FP_TO_UINT on 32-bit implementations.
265    setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
266  }
267
268  if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
269    // 64-bit PowerPC implementations can support i64 types directly
270    addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
271    // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
272    setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
273    // 64-bit PowerPC wants to expand i128 shifts itself.
274    setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
275    setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
276    setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
277  } else {
278    // 32-bit PowerPC wants to expand i64 shifts itself.
279    setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
280    setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
281    setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
282  }
283
284  if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
285    // First set operation action for all vector types to expand. Then we
286    // will selectively turn on ones that can be effectively codegen'd.
287    for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
288         i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
289      MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
290
291      // add/sub are legal for all supported vector VT's.
292      setOperationAction(ISD::ADD , VT, Legal);
293      setOperationAction(ISD::SUB , VT, Legal);
294
295      // We promote all shuffles to v16i8.
296      setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
297      AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
298
299      // We promote all non-typed operations to v4i32.
300      setOperationAction(ISD::AND   , VT, Promote);
301      AddPromotedToType (ISD::AND   , VT, MVT::v4i32);
302      setOperationAction(ISD::OR    , VT, Promote);
303      AddPromotedToType (ISD::OR    , VT, MVT::v4i32);
304      setOperationAction(ISD::XOR   , VT, Promote);
305      AddPromotedToType (ISD::XOR   , VT, MVT::v4i32);
306      setOperationAction(ISD::LOAD  , VT, Promote);
307      AddPromotedToType (ISD::LOAD  , VT, MVT::v4i32);
308      setOperationAction(ISD::SELECT, VT, Promote);
309      AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
310      setOperationAction(ISD::STORE, VT, Promote);
311      AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
312
313      // No other operations are legal.
314      setOperationAction(ISD::MUL , VT, Expand);
315      setOperationAction(ISD::SDIV, VT, Expand);
316      setOperationAction(ISD::SREM, VT, Expand);
317      setOperationAction(ISD::UDIV, VT, Expand);
318      setOperationAction(ISD::UREM, VT, Expand);
319      setOperationAction(ISD::FDIV, VT, Expand);
320      setOperationAction(ISD::FNEG, VT, Expand);
321      setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
322      setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
323      setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
324      setOperationAction(ISD::UMUL_LOHI, VT, Expand);
325      setOperationAction(ISD::SMUL_LOHI, VT, Expand);
326      setOperationAction(ISD::UDIVREM, VT, Expand);
327      setOperationAction(ISD::SDIVREM, VT, Expand);
328      setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
329      setOperationAction(ISD::FPOW, VT, Expand);
330      setOperationAction(ISD::CTPOP, VT, Expand);
331      setOperationAction(ISD::CTLZ, VT, Expand);
332      setOperationAction(ISD::CTTZ, VT, Expand);
333    }
334
335    // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
336    // with merges, splats, etc.
337    setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
338
339    setOperationAction(ISD::AND   , MVT::v4i32, Legal);
340    setOperationAction(ISD::OR    , MVT::v4i32, Legal);
341    setOperationAction(ISD::XOR   , MVT::v4i32, Legal);
342    setOperationAction(ISD::LOAD  , MVT::v4i32, Legal);
343    setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
344    setOperationAction(ISD::STORE , MVT::v4i32, Legal);
345
346    addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
347    addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
348    addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
349    addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
350
351    setOperationAction(ISD::MUL, MVT::v4f32, Legal);
352    setOperationAction(ISD::MUL, MVT::v4i32, Custom);
353    setOperationAction(ISD::MUL, MVT::v8i16, Custom);
354    setOperationAction(ISD::MUL, MVT::v16i8, Custom);
355
356    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
357    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
358
359    setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
360    setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
361    setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
362    setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
363  }
364
365  setBooleanContents(ZeroOrOneBooleanContent);
366
367  if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
368    setStackPointerRegisterToSaveRestore(PPC::X1);
369    setExceptionPointerRegister(PPC::X3);
370    setExceptionSelectorRegister(PPC::X4);
371  } else {
372    setStackPointerRegisterToSaveRestore(PPC::R1);
373    setExceptionPointerRegister(PPC::R3);
374    setExceptionSelectorRegister(PPC::R4);
375  }
376
377  // We have target-specific dag combine patterns for the following nodes:
378  setTargetDAGCombine(ISD::SINT_TO_FP);
379  setTargetDAGCombine(ISD::STORE);
380  setTargetDAGCombine(ISD::BR_CC);
381  setTargetDAGCombine(ISD::BSWAP);
382
383  // Darwin long double math library functions have $LDBL128 appended.
384  if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
385    setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
386    setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
387    setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
388    setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
389    setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
390    setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
391    setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
392    setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
393    setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
394    setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
395  }
396
397  computeRegisterProperties();
398}
399
400/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
401/// function arguments in the caller parameter area.
402unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
403  const TargetMachine &TM = getTargetMachine();
404  // Darwin passes everything on 4 byte boundary.
405  if (TM.getSubtarget<PPCSubtarget>().isDarwin())
406    return 4;
407  // FIXME SVR4 TBD
408  return 4;
409}
410
411const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
412  switch (Opcode) {
413  default: return 0;
414  case PPCISD::FSEL:            return "PPCISD::FSEL";
415  case PPCISD::FCFID:           return "PPCISD::FCFID";
416  case PPCISD::FCTIDZ:          return "PPCISD::FCTIDZ";
417  case PPCISD::FCTIWZ:          return "PPCISD::FCTIWZ";
418  case PPCISD::STFIWX:          return "PPCISD::STFIWX";
419  case PPCISD::VMADDFP:         return "PPCISD::VMADDFP";
420  case PPCISD::VNMSUBFP:        return "PPCISD::VNMSUBFP";
421  case PPCISD::VPERM:           return "PPCISD::VPERM";
422  case PPCISD::Hi:              return "PPCISD::Hi";
423  case PPCISD::Lo:              return "PPCISD::Lo";
424  case PPCISD::TOC_ENTRY:       return "PPCISD::TOC_ENTRY";
425  case PPCISD::TOC_RESTORE:     return "PPCISD::TOC_RESTORE";
426  case PPCISD::LOAD:            return "PPCISD::LOAD";
427  case PPCISD::LOAD_TOC:        return "PPCISD::LOAD_TOC";
428  case PPCISD::DYNALLOC:        return "PPCISD::DYNALLOC";
429  case PPCISD::GlobalBaseReg:   return "PPCISD::GlobalBaseReg";
430  case PPCISD::SRL:             return "PPCISD::SRL";
431  case PPCISD::SRA:             return "PPCISD::SRA";
432  case PPCISD::SHL:             return "PPCISD::SHL";
433  case PPCISD::EXTSW_32:        return "PPCISD::EXTSW_32";
434  case PPCISD::STD_32:          return "PPCISD::STD_32";
435  case PPCISD::CALL_SVR4:       return "PPCISD::CALL_SVR4";
436  case PPCISD::CALL_Darwin:     return "PPCISD::CALL_Darwin";
437  case PPCISD::NOP:             return "PPCISD::NOP";
438  case PPCISD::MTCTR:           return "PPCISD::MTCTR";
439  case PPCISD::BCTRL_Darwin:    return "PPCISD::BCTRL_Darwin";
440  case PPCISD::BCTRL_SVR4:      return "PPCISD::BCTRL_SVR4";
441  case PPCISD::RET_FLAG:        return "PPCISD::RET_FLAG";
442  case PPCISD::MFCR:            return "PPCISD::MFCR";
443  case PPCISD::VCMP:            return "PPCISD::VCMP";
444  case PPCISD::VCMPo:           return "PPCISD::VCMPo";
445  case PPCISD::LBRX:            return "PPCISD::LBRX";
446  case PPCISD::STBRX:           return "PPCISD::STBRX";
447  case PPCISD::LARX:            return "PPCISD::LARX";
448  case PPCISD::STCX:            return "PPCISD::STCX";
449  case PPCISD::COND_BRANCH:     return "PPCISD::COND_BRANCH";
450  case PPCISD::MFFS:            return "PPCISD::MFFS";
451  case PPCISD::MTFSB0:          return "PPCISD::MTFSB0";
452  case PPCISD::MTFSB1:          return "PPCISD::MTFSB1";
453  case PPCISD::FADDRTZ:         return "PPCISD::FADDRTZ";
454  case PPCISD::MTFSF:           return "PPCISD::MTFSF";
455  case PPCISD::TC_RETURN:       return "PPCISD::TC_RETURN";
456  }
457}
458
459MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const {
460  return MVT::i32;
461}
462
463/// getFunctionAlignment - Return the Log2 alignment of this function.
464unsigned PPCTargetLowering::getFunctionAlignment(const Function *F) const {
465  if (getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin())
466    return F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4;
467  else
468    return 2;
469}
470
471//===----------------------------------------------------------------------===//
472// Node matching predicates, for use by the tblgen matching code.
473//===----------------------------------------------------------------------===//
474
475/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
476static bool isFloatingPointZero(SDValue Op) {
477  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
478    return CFP->getValueAPF().isZero();
479  else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
480    // Maybe this has already been legalized into the constant pool?
481    if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
482      if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
483        return CFP->getValueAPF().isZero();
484  }
485  return false;
486}
487
488/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode.  Return
489/// true if Op is undef or if it matches the specified value.
490static bool isConstantOrUndef(int Op, int Val) {
491  return Op < 0 || Op == Val;
492}
493
494/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
495/// VPKUHUM instruction.
496bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
497  if (!isUnary) {
498    for (unsigned i = 0; i != 16; ++i)
499      if (!isConstantOrUndef(N->getMaskElt(i),  i*2+1))
500        return false;
501  } else {
502    for (unsigned i = 0; i != 8; ++i)
503      if (!isConstantOrUndef(N->getMaskElt(i),    i*2+1) ||
504          !isConstantOrUndef(N->getMaskElt(i+8),  i*2+1))
505        return false;
506  }
507  return true;
508}
509
510/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
511/// VPKUWUM instruction.
512bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
513  if (!isUnary) {
514    for (unsigned i = 0; i != 16; i += 2)
515      if (!isConstantOrUndef(N->getMaskElt(i  ),  i*2+2) ||
516          !isConstantOrUndef(N->getMaskElt(i+1),  i*2+3))
517        return false;
518  } else {
519    for (unsigned i = 0; i != 8; i += 2)
520      if (!isConstantOrUndef(N->getMaskElt(i  ),  i*2+2) ||
521          !isConstantOrUndef(N->getMaskElt(i+1),  i*2+3) ||
522          !isConstantOrUndef(N->getMaskElt(i+8),  i*2+2) ||
523          !isConstantOrUndef(N->getMaskElt(i+9),  i*2+3))
524        return false;
525  }
526  return true;
527}
528
529/// isVMerge - Common function, used to match vmrg* shuffles.
530///
531static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
532                     unsigned LHSStart, unsigned RHSStart) {
533  assert(N->getValueType(0) == MVT::v16i8 &&
534         "PPC only supports shuffles by bytes!");
535  assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
536         "Unsupported merge size!");
537
538  for (unsigned i = 0; i != 8/UnitSize; ++i)     // Step over units
539    for (unsigned j = 0; j != UnitSize; ++j) {   // Step over bytes within unit
540      if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
541                             LHSStart+j+i*UnitSize) ||
542          !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
543                             RHSStart+j+i*UnitSize))
544        return false;
545    }
546  return true;
547}
548
549/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
550/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
551bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
552                             bool isUnary) {
553  if (!isUnary)
554    return isVMerge(N, UnitSize, 8, 24);
555  return isVMerge(N, UnitSize, 8, 8);
556}
557
558/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
559/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
560bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
561                             bool isUnary) {
562  if (!isUnary)
563    return isVMerge(N, UnitSize, 0, 16);
564  return isVMerge(N, UnitSize, 0, 0);
565}
566
567
568/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
569/// amount, otherwise return -1.
570int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
571  assert(N->getValueType(0) == MVT::v16i8 &&
572         "PPC only supports shuffles by bytes!");
573
574  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
575
576  // Find the first non-undef value in the shuffle mask.
577  unsigned i;
578  for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
579    /*search*/;
580
581  if (i == 16) return -1;  // all undef.
582
583  // Otherwise, check to see if the rest of the elements are consecutively
584  // numbered from this value.
585  unsigned ShiftAmt = SVOp->getMaskElt(i);
586  if (ShiftAmt < i) return -1;
587  ShiftAmt -= i;
588
589  if (!isUnary) {
590    // Check the rest of the elements to see if they are consecutive.
591    for (++i; i != 16; ++i)
592      if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
593        return -1;
594  } else {
595    // Check the rest of the elements to see if they are consecutive.
596    for (++i; i != 16; ++i)
597      if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
598        return -1;
599  }
600  return ShiftAmt;
601}
602
603/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
604/// specifies a splat of a single element that is suitable for input to
605/// VSPLTB/VSPLTH/VSPLTW.
606bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
607  assert(N->getValueType(0) == MVT::v16i8 &&
608         (EltSize == 1 || EltSize == 2 || EltSize == 4));
609
610  // This is a splat operation if each element of the permute is the same, and
611  // if the value doesn't reference the second vector.
612  unsigned ElementBase = N->getMaskElt(0);
613
614  // FIXME: Handle UNDEF elements too!
615  if (ElementBase >= 16)
616    return false;
617
618  // Check that the indices are consecutive, in the case of a multi-byte element
619  // splatted with a v16i8 mask.
620  for (unsigned i = 1; i != EltSize; ++i)
621    if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
622      return false;
623
624  for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
625    if (N->getMaskElt(i) < 0) continue;
626    for (unsigned j = 0; j != EltSize; ++j)
627      if (N->getMaskElt(i+j) != N->getMaskElt(j))
628        return false;
629  }
630  return true;
631}
632
633/// isAllNegativeZeroVector - Returns true if all elements of build_vector
634/// are -0.0.
635bool PPC::isAllNegativeZeroVector(SDNode *N) {
636  BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
637
638  APInt APVal, APUndef;
639  unsigned BitSize;
640  bool HasAnyUndefs;
641
642  if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
643    if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
644      return CFP->getValueAPF().isNegZero();
645
646  return false;
647}
648
649/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
650/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
651unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
652  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
653  assert(isSplatShuffleMask(SVOp, EltSize));
654  return SVOp->getMaskElt(0) / EltSize;
655}
656
657/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
658/// by using a vspltis[bhw] instruction of the specified element size, return
659/// the constant being splatted.  The ByteSize field indicates the number of
660/// bytes of each element [124] -> [bhw].
661SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
662  SDValue OpVal(0, 0);
663
664  // If ByteSize of the splat is bigger than the element size of the
665  // build_vector, then we have a case where we are checking for a splat where
666  // multiple elements of the buildvector are folded together into a single
667  // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
668  unsigned EltSize = 16/N->getNumOperands();
669  if (EltSize < ByteSize) {
670    unsigned Multiple = ByteSize/EltSize;   // Number of BV entries per spltval.
671    SDValue UniquedVals[4];
672    assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
673
674    // See if all of the elements in the buildvector agree across.
675    for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
676      if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
677      // If the element isn't a constant, bail fully out.
678      if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
679
680
681      if (UniquedVals[i&(Multiple-1)].getNode() == 0)
682        UniquedVals[i&(Multiple-1)] = N->getOperand(i);
683      else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
684        return SDValue();  // no match.
685    }
686
687    // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
688    // either constant or undef values that are identical for each chunk.  See
689    // if these chunks can form into a larger vspltis*.
690
691    // Check to see if all of the leading entries are either 0 or -1.  If
692    // neither, then this won't fit into the immediate field.
693    bool LeadingZero = true;
694    bool LeadingOnes = true;
695    for (unsigned i = 0; i != Multiple-1; ++i) {
696      if (UniquedVals[i].getNode() == 0) continue;  // Must have been undefs.
697
698      LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
699      LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
700    }
701    // Finally, check the least significant entry.
702    if (LeadingZero) {
703      if (UniquedVals[Multiple-1].getNode() == 0)
704        return DAG.getTargetConstant(0, MVT::i32);  // 0,0,0,undef
705      int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
706      if (Val < 16)
707        return DAG.getTargetConstant(Val, MVT::i32);  // 0,0,0,4 -> vspltisw(4)
708    }
709    if (LeadingOnes) {
710      if (UniquedVals[Multiple-1].getNode() == 0)
711        return DAG.getTargetConstant(~0U, MVT::i32);  // -1,-1,-1,undef
712      int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
713      if (Val >= -16)                            // -1,-1,-1,-2 -> vspltisw(-2)
714        return DAG.getTargetConstant(Val, MVT::i32);
715    }
716
717    return SDValue();
718  }
719
720  // Check to see if this buildvec has a single non-undef value in its elements.
721  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
722    if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
723    if (OpVal.getNode() == 0)
724      OpVal = N->getOperand(i);
725    else if (OpVal != N->getOperand(i))
726      return SDValue();
727  }
728
729  if (OpVal.getNode() == 0) return SDValue();  // All UNDEF: use implicit def.
730
731  unsigned ValSizeInBytes = EltSize;
732  uint64_t Value = 0;
733  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
734    Value = CN->getZExtValue();
735  } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
736    assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
737    Value = FloatToBits(CN->getValueAPF().convertToFloat());
738  }
739
740  // If the splat value is larger than the element value, then we can never do
741  // this splat.  The only case that we could fit the replicated bits into our
742  // immediate field for would be zero, and we prefer to use vxor for it.
743  if (ValSizeInBytes < ByteSize) return SDValue();
744
745  // If the element value is larger than the splat value, cut it in half and
746  // check to see if the two halves are equal.  Continue doing this until we
747  // get to ByteSize.  This allows us to handle 0x01010101 as 0x01.
748  while (ValSizeInBytes > ByteSize) {
749    ValSizeInBytes >>= 1;
750
751    // If the top half equals the bottom half, we're still ok.
752    if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
753         (Value                        & ((1 << (8*ValSizeInBytes))-1)))
754      return SDValue();
755  }
756
757  // Properly sign extend the value.
758  int ShAmt = (4-ByteSize)*8;
759  int MaskVal = ((int)Value << ShAmt) >> ShAmt;
760
761  // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
762  if (MaskVal == 0) return SDValue();
763
764  // Finally, if this value fits in a 5 bit sext field, return it
765  if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
766    return DAG.getTargetConstant(MaskVal, MVT::i32);
767  return SDValue();
768}
769
770//===----------------------------------------------------------------------===//
771//  Addressing Mode Selection
772//===----------------------------------------------------------------------===//
773
774/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
775/// or 64-bit immediate, and if the value can be accurately represented as a
776/// sign extension from a 16-bit value.  If so, this returns true and the
777/// immediate.
778static bool isIntS16Immediate(SDNode *N, short &Imm) {
779  if (N->getOpcode() != ISD::Constant)
780    return false;
781
782  Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
783  if (N->getValueType(0) == MVT::i32)
784    return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
785  else
786    return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
787}
788static bool isIntS16Immediate(SDValue Op, short &Imm) {
789  return isIntS16Immediate(Op.getNode(), Imm);
790}
791
792
793/// SelectAddressRegReg - Given the specified addressed, check to see if it
794/// can be represented as an indexed [r+r] operation.  Returns false if it
795/// can be more efficiently represented with [r+imm].
796bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
797                                            SDValue &Index,
798                                            SelectionDAG &DAG) const {
799  short imm = 0;
800  if (N.getOpcode() == ISD::ADD) {
801    if (isIntS16Immediate(N.getOperand(1), imm))
802      return false;    // r+i
803    if (N.getOperand(1).getOpcode() == PPCISD::Lo)
804      return false;    // r+i
805
806    Base = N.getOperand(0);
807    Index = N.getOperand(1);
808    return true;
809  } else if (N.getOpcode() == ISD::OR) {
810    if (isIntS16Immediate(N.getOperand(1), imm))
811      return false;    // r+i can fold it if we can.
812
813    // If this is an or of disjoint bitfields, we can codegen this as an add
814    // (for better address arithmetic) if the LHS and RHS of the OR are provably
815    // disjoint.
816    APInt LHSKnownZero, LHSKnownOne;
817    APInt RHSKnownZero, RHSKnownOne;
818    DAG.ComputeMaskedBits(N.getOperand(0),
819                          APInt::getAllOnesValue(N.getOperand(0)
820                            .getValueSizeInBits()),
821                          LHSKnownZero, LHSKnownOne);
822
823    if (LHSKnownZero.getBoolValue()) {
824      DAG.ComputeMaskedBits(N.getOperand(1),
825                            APInt::getAllOnesValue(N.getOperand(1)
826                              .getValueSizeInBits()),
827                            RHSKnownZero, RHSKnownOne);
828      // If all of the bits are known zero on the LHS or RHS, the add won't
829      // carry.
830      if (~(LHSKnownZero | RHSKnownZero) == 0) {
831        Base = N.getOperand(0);
832        Index = N.getOperand(1);
833        return true;
834      }
835    }
836  }
837
838  return false;
839}
840
841/// Returns true if the address N can be represented by a base register plus
842/// a signed 16-bit displacement [r+imm], and if it is not better
843/// represented as reg+reg.
844bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
845                                            SDValue &Base,
846                                            SelectionDAG &DAG) const {
847  // FIXME dl should come from parent load or store, not from address
848  DebugLoc dl = N.getDebugLoc();
849  // If this can be more profitably realized as r+r, fail.
850  if (SelectAddressRegReg(N, Disp, Base, DAG))
851    return false;
852
853  if (N.getOpcode() == ISD::ADD) {
854    short imm = 0;
855    if (isIntS16Immediate(N.getOperand(1), imm)) {
856      Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
857      if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
858        Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
859      } else {
860        Base = N.getOperand(0);
861      }
862      return true; // [r+i]
863    } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
864      // Match LOAD (ADD (X, Lo(G))).
865     assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
866             && "Cannot handle constant offsets yet!");
867      Disp = N.getOperand(1).getOperand(0);  // The global address.
868      assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
869             Disp.getOpcode() == ISD::TargetConstantPool ||
870             Disp.getOpcode() == ISD::TargetJumpTable);
871      Base = N.getOperand(0);
872      return true;  // [&g+r]
873    }
874  } else if (N.getOpcode() == ISD::OR) {
875    short imm = 0;
876    if (isIntS16Immediate(N.getOperand(1), imm)) {
877      // If this is an or of disjoint bitfields, we can codegen this as an add
878      // (for better address arithmetic) if the LHS and RHS of the OR are
879      // provably disjoint.
880      APInt LHSKnownZero, LHSKnownOne;
881      DAG.ComputeMaskedBits(N.getOperand(0),
882                            APInt::getAllOnesValue(N.getOperand(0)
883                                                   .getValueSizeInBits()),
884                            LHSKnownZero, LHSKnownOne);
885
886      if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
887        // If all of the bits are known zero on the LHS or RHS, the add won't
888        // carry.
889        Base = N.getOperand(0);
890        Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
891        return true;
892      }
893    }
894  } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
895    // Loading from a constant address.
896
897    // If this address fits entirely in a 16-bit sext immediate field, codegen
898    // this as "d, 0"
899    short Imm;
900    if (isIntS16Immediate(CN, Imm)) {
901      Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
902      Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
903                             CN->getValueType(0));
904      return true;
905    }
906
907    // Handle 32-bit sext immediates with LIS + addr mode.
908    if (CN->getValueType(0) == MVT::i32 ||
909        (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
910      int Addr = (int)CN->getZExtValue();
911
912      // Otherwise, break this down into an LIS + disp.
913      Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
914
915      Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
916      unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
917      Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
918      return true;
919    }
920  }
921
922  Disp = DAG.getTargetConstant(0, getPointerTy());
923  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
924    Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
925  else
926    Base = N;
927  return true;      // [r+0]
928}
929
930/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
931/// represented as an indexed [r+r] operation.
932bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
933                                                SDValue &Index,
934                                                SelectionDAG &DAG) const {
935  // Check to see if we can easily represent this as an [r+r] address.  This
936  // will fail if it thinks that the address is more profitably represented as
937  // reg+imm, e.g. where imm = 0.
938  if (SelectAddressRegReg(N, Base, Index, DAG))
939    return true;
940
941  // If the operand is an addition, always emit this as [r+r], since this is
942  // better (for code size, and execution, as the memop does the add for free)
943  // than emitting an explicit add.
944  if (N.getOpcode() == ISD::ADD) {
945    Base = N.getOperand(0);
946    Index = N.getOperand(1);
947    return true;
948  }
949
950  // Otherwise, do it the hard way, using R0 as the base register.
951  Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
952                         N.getValueType());
953  Index = N;
954  return true;
955}
956
957/// SelectAddressRegImmShift - Returns true if the address N can be
958/// represented by a base register plus a signed 14-bit displacement
959/// [r+imm*4].  Suitable for use by STD and friends.
960bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
961                                                 SDValue &Base,
962                                                 SelectionDAG &DAG) const {
963  // FIXME dl should come from the parent load or store, not the address
964  DebugLoc dl = N.getDebugLoc();
965  // If this can be more profitably realized as r+r, fail.
966  if (SelectAddressRegReg(N, Disp, Base, DAG))
967    return false;
968
969  if (N.getOpcode() == ISD::ADD) {
970    short imm = 0;
971    if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
972      Disp =  DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
973      if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
974        Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
975      } else {
976        Base = N.getOperand(0);
977      }
978      return true; // [r+i]
979    } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
980      // Match LOAD (ADD (X, Lo(G))).
981     assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
982             && "Cannot handle constant offsets yet!");
983      Disp = N.getOperand(1).getOperand(0);  // The global address.
984      assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
985             Disp.getOpcode() == ISD::TargetConstantPool ||
986             Disp.getOpcode() == ISD::TargetJumpTable);
987      Base = N.getOperand(0);
988      return true;  // [&g+r]
989    }
990  } else if (N.getOpcode() == ISD::OR) {
991    short imm = 0;
992    if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
993      // If this is an or of disjoint bitfields, we can codegen this as an add
994      // (for better address arithmetic) if the LHS and RHS of the OR are
995      // provably disjoint.
996      APInt LHSKnownZero, LHSKnownOne;
997      DAG.ComputeMaskedBits(N.getOperand(0),
998                            APInt::getAllOnesValue(N.getOperand(0)
999                                                   .getValueSizeInBits()),
1000                            LHSKnownZero, LHSKnownOne);
1001      if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1002        // If all of the bits are known zero on the LHS or RHS, the add won't
1003        // carry.
1004        Base = N.getOperand(0);
1005        Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1006        return true;
1007      }
1008    }
1009  } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1010    // Loading from a constant address.  Verify low two bits are clear.
1011    if ((CN->getZExtValue() & 3) == 0) {
1012      // If this address fits entirely in a 14-bit sext immediate field, codegen
1013      // this as "d, 0"
1014      short Imm;
1015      if (isIntS16Immediate(CN, Imm)) {
1016        Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1017        Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
1018        return true;
1019      }
1020
1021      // Fold the low-part of 32-bit absolute addresses into addr mode.
1022      if (CN->getValueType(0) == MVT::i32 ||
1023          (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1024        int Addr = (int)CN->getZExtValue();
1025
1026        // Otherwise, break this down into an LIS + disp.
1027        Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1028        Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1029        unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1030        Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1031        return true;
1032      }
1033    }
1034  }
1035
1036  Disp = DAG.getTargetConstant(0, getPointerTy());
1037  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1038    Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1039  else
1040    Base = N;
1041  return true;      // [r+0]
1042}
1043
1044
1045/// getPreIndexedAddressParts - returns true by value, base pointer and
1046/// offset pointer and addressing mode by reference if the node's address
1047/// can be legally represented as pre-indexed load / store address.
1048bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1049                                                  SDValue &Offset,
1050                                                  ISD::MemIndexedMode &AM,
1051                                                  SelectionDAG &DAG) const {
1052  // Disabled by default for now.
1053  if (!EnablePPCPreinc) return false;
1054
1055  SDValue Ptr;
1056  EVT VT;
1057  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1058    Ptr = LD->getBasePtr();
1059    VT = LD->getMemoryVT();
1060
1061  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1062    Ptr = ST->getBasePtr();
1063    VT  = ST->getMemoryVT();
1064  } else
1065    return false;
1066
1067  // PowerPC doesn't have preinc load/store instructions for vectors.
1068  if (VT.isVector())
1069    return false;
1070
1071  // TODO: Check reg+reg first.
1072
1073  // LDU/STU use reg+imm*4, others use reg+imm.
1074  if (VT != MVT::i64) {
1075    // reg + imm
1076    if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1077      return false;
1078  } else {
1079    // reg + imm * 4.
1080    if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1081      return false;
1082  }
1083
1084  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1085    // PPC64 doesn't have lwau, but it does have lwaux.  Reject preinc load of
1086    // sext i32 to i64 when addr mode is r+i.
1087    if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1088        LD->getExtensionType() == ISD::SEXTLOAD &&
1089        isa<ConstantSDNode>(Offset))
1090      return false;
1091  }
1092
1093  AM = ISD::PRE_INC;
1094  return true;
1095}
1096
1097//===----------------------------------------------------------------------===//
1098//  LowerOperation implementation
1099//===----------------------------------------------------------------------===//
1100
1101/// GetLabelAccessInfo - Return true if we should reference labels using a
1102/// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1103static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1104                               unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1105  HiOpFlags = PPCII::MO_HA16;
1106  LoOpFlags = PPCII::MO_LO16;
1107
1108  // Don't use the pic base if not in PIC relocation model.  Or if we are on a
1109  // non-darwin platform.  We don't support PIC on other platforms yet.
1110  bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1111               TM.getSubtarget<PPCSubtarget>().isDarwin();
1112  if (isPIC) {
1113    HiOpFlags |= PPCII::MO_PIC_FLAG;
1114    LoOpFlags |= PPCII::MO_PIC_FLAG;
1115  }
1116
1117  // If this is a reference to a global value that requires a non-lazy-ptr, make
1118  // sure that instruction lowering adds it.
1119  if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1120    HiOpFlags |= PPCII::MO_NLP_FLAG;
1121    LoOpFlags |= PPCII::MO_NLP_FLAG;
1122
1123    if (GV->hasHiddenVisibility()) {
1124      HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1125      LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1126    }
1127  }
1128
1129  return isPIC;
1130}
1131
1132static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1133                             SelectionDAG &DAG) {
1134  EVT PtrVT = HiPart.getValueType();
1135  SDValue Zero = DAG.getConstant(0, PtrVT);
1136  DebugLoc DL = HiPart.getDebugLoc();
1137
1138  SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1139  SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1140
1141  // With PIC, the first instruction is actually "GR+hi(&G)".
1142  if (isPIC)
1143    Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1144                     DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1145
1146  // Generate non-pic code that has direct accesses to the constant pool.
1147  // The address of the global is just (hi(&g)+lo(&g)).
1148  return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1149}
1150
1151SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1152                                             SelectionDAG &DAG) const {
1153  EVT PtrVT = Op.getValueType();
1154  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1155  const Constant *C = CP->getConstVal();
1156
1157  unsigned MOHiFlag, MOLoFlag;
1158  bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1159  SDValue CPIHi =
1160    DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1161  SDValue CPILo =
1162    DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1163  return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1164}
1165
1166SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1167  EVT PtrVT = Op.getValueType();
1168  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1169
1170  unsigned MOHiFlag, MOLoFlag;
1171  bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1172  SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1173  SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1174  return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1175}
1176
1177SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1178                                             SelectionDAG &DAG) const {
1179  EVT PtrVT = Op.getValueType();
1180
1181  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1182
1183  unsigned MOHiFlag, MOLoFlag;
1184  bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1185  SDValue TgtBAHi = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOHiFlag);
1186  SDValue TgtBALo = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOLoFlag);
1187  return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1188}
1189
1190SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1191                                              SelectionDAG &DAG) const {
1192  EVT PtrVT = Op.getValueType();
1193  GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1194  DebugLoc DL = GSDN->getDebugLoc();
1195  const GlobalValue *GV = GSDN->getGlobal();
1196
1197  // 64-bit SVR4 ABI code is always position-independent.
1198  // The actual address of the GlobalValue is stored in the TOC.
1199  if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1200    SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1201    return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1202                       DAG.getRegister(PPC::X2, MVT::i64));
1203  }
1204
1205  unsigned MOHiFlag, MOLoFlag;
1206  bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1207
1208  SDValue GAHi =
1209    DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1210  SDValue GALo =
1211    DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1212
1213  SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1214
1215  // If the global reference is actually to a non-lazy-pointer, we have to do an
1216  // extra load to get the address of the global.
1217  if (MOHiFlag & PPCII::MO_NLP_FLAG)
1218    Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1219                      false, false, 0);
1220  return Ptr;
1221}
1222
1223SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1224  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1225  DebugLoc dl = Op.getDebugLoc();
1226
1227  // If we're comparing for equality to zero, expose the fact that this is
1228  // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1229  // fold the new nodes.
1230  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1231    if (C->isNullValue() && CC == ISD::SETEQ) {
1232      EVT VT = Op.getOperand(0).getValueType();
1233      SDValue Zext = Op.getOperand(0);
1234      if (VT.bitsLT(MVT::i32)) {
1235        VT = MVT::i32;
1236        Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1237      }
1238      unsigned Log2b = Log2_32(VT.getSizeInBits());
1239      SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1240      SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1241                                DAG.getConstant(Log2b, MVT::i32));
1242      return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1243    }
1244    // Leave comparisons against 0 and -1 alone for now, since they're usually
1245    // optimized.  FIXME: revisit this when we can custom lower all setcc
1246    // optimizations.
1247    if (C->isAllOnesValue() || C->isNullValue())
1248      return SDValue();
1249  }
1250
1251  // If we have an integer seteq/setne, turn it into a compare against zero
1252  // by xor'ing the rhs with the lhs, which is faster than setting a
1253  // condition register, reading it back out, and masking the correct bit.  The
1254  // normal approach here uses sub to do this instead of xor.  Using xor exposes
1255  // the result to other bit-twiddling opportunities.
1256  EVT LHSVT = Op.getOperand(0).getValueType();
1257  if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1258    EVT VT = Op.getValueType();
1259    SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1260                                Op.getOperand(1));
1261    return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1262  }
1263  return SDValue();
1264}
1265
1266SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1267                                      const PPCSubtarget &Subtarget) const {
1268
1269  llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!");
1270  return SDValue(); // Not reached
1271}
1272
1273SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op,
1274                                           SelectionDAG &DAG) const {
1275  SDValue Chain = Op.getOperand(0);
1276  SDValue Trmp = Op.getOperand(1); // trampoline
1277  SDValue FPtr = Op.getOperand(2); // nested function
1278  SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1279  DebugLoc dl = Op.getDebugLoc();
1280
1281  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1282  bool isPPC64 = (PtrVT == MVT::i64);
1283  const Type *IntPtrTy =
1284    DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType(
1285                                                             *DAG.getContext());
1286
1287  TargetLowering::ArgListTy Args;
1288  TargetLowering::ArgListEntry Entry;
1289
1290  Entry.Ty = IntPtrTy;
1291  Entry.Node = Trmp; Args.push_back(Entry);
1292
1293  // TrampSize == (isPPC64 ? 48 : 40);
1294  Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1295                               isPPC64 ? MVT::i64 : MVT::i32);
1296  Args.push_back(Entry);
1297
1298  Entry.Node = FPtr; Args.push_back(Entry);
1299  Entry.Node = Nest; Args.push_back(Entry);
1300
1301  // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1302  std::pair<SDValue, SDValue> CallResult =
1303    LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()),
1304                false, false, false, false, 0, CallingConv::C, false,
1305                /*isReturnValueUsed=*/true,
1306                DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1307                Args, DAG, dl);
1308
1309  SDValue Ops[] =
1310    { CallResult.first, CallResult.second };
1311
1312  return DAG.getMergeValues(Ops, 2, dl);
1313}
1314
1315SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1316                                        const PPCSubtarget &Subtarget) const {
1317  MachineFunction &MF = DAG.getMachineFunction();
1318  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1319
1320  DebugLoc dl = Op.getDebugLoc();
1321
1322  if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1323    // vastart just stores the address of the VarArgsFrameIndex slot into the
1324    // memory location argument.
1325    EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1326    SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1327    const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1328    return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1329                        MachinePointerInfo(SV),
1330                        false, false, 0);
1331  }
1332
1333  // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1334  // We suppose the given va_list is already allocated.
1335  //
1336  // typedef struct {
1337  //  char gpr;     /* index into the array of 8 GPRs
1338  //                 * stored in the register save area
1339  //                 * gpr=0 corresponds to r3,
1340  //                 * gpr=1 to r4, etc.
1341  //                 */
1342  //  char fpr;     /* index into the array of 8 FPRs
1343  //                 * stored in the register save area
1344  //                 * fpr=0 corresponds to f1,
1345  //                 * fpr=1 to f2, etc.
1346  //                 */
1347  //  char *overflow_arg_area;
1348  //                /* location on stack that holds
1349  //                 * the next overflow argument
1350  //                 */
1351  //  char *reg_save_area;
1352  //               /* where r3:r10 and f1:f8 (if saved)
1353  //                * are stored
1354  //                */
1355  // } va_list[1];
1356
1357
1358  SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1359  SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1360
1361
1362  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1363
1364  SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1365                                            PtrVT);
1366  SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1367                                 PtrVT);
1368
1369  uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1370  SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1371
1372  uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1373  SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1374
1375  uint64_t FPROffset = 1;
1376  SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1377
1378  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1379
1380  // Store first byte : number of int regs
1381  SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1382                                         Op.getOperand(1),
1383                                         MachinePointerInfo(SV),
1384                                         MVT::i8, false, false, 0);
1385  uint64_t nextOffset = FPROffset;
1386  SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1387                                  ConstFPROffset);
1388
1389  // Store second byte : number of float regs
1390  SDValue secondStore =
1391    DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1392                      MachinePointerInfo(SV, nextOffset), MVT::i8,
1393                      false, false, 0);
1394  nextOffset += StackOffset;
1395  nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1396
1397  // Store second word : arguments given on stack
1398  SDValue thirdStore =
1399    DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1400                 MachinePointerInfo(SV, nextOffset),
1401                 false, false, 0);
1402  nextOffset += FrameOffset;
1403  nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1404
1405  // Store third word : arguments given in registers
1406  return DAG.getStore(thirdStore, dl, FR, nextPtr,
1407                      MachinePointerInfo(SV, nextOffset),
1408                      false, false, 0);
1409
1410}
1411
1412#include "PPCGenCallingConv.inc"
1413
1414static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1415                                     CCValAssign::LocInfo &LocInfo,
1416                                     ISD::ArgFlagsTy &ArgFlags,
1417                                     CCState &State) {
1418  return true;
1419}
1420
1421static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1422                                            MVT &LocVT,
1423                                            CCValAssign::LocInfo &LocInfo,
1424                                            ISD::ArgFlagsTy &ArgFlags,
1425                                            CCState &State) {
1426  static const unsigned ArgRegs[] = {
1427    PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1428    PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1429  };
1430  const unsigned NumArgRegs = array_lengthof(ArgRegs);
1431
1432  unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1433
1434  // Skip one register if the first unallocated register has an even register
1435  // number and there are still argument registers available which have not been
1436  // allocated yet. RegNum is actually an index into ArgRegs, which means we
1437  // need to skip a register if RegNum is odd.
1438  if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1439    State.AllocateReg(ArgRegs[RegNum]);
1440  }
1441
1442  // Always return false here, as this function only makes sure that the first
1443  // unallocated register has an odd register number and does not actually
1444  // allocate a register for the current argument.
1445  return false;
1446}
1447
1448static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1449                                              MVT &LocVT,
1450                                              CCValAssign::LocInfo &LocInfo,
1451                                              ISD::ArgFlagsTy &ArgFlags,
1452                                              CCState &State) {
1453  static const unsigned ArgRegs[] = {
1454    PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1455    PPC::F8
1456  };
1457
1458  const unsigned NumArgRegs = array_lengthof(ArgRegs);
1459
1460  unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1461
1462  // If there is only one Floating-point register left we need to put both f64
1463  // values of a split ppc_fp128 value on the stack.
1464  if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1465    State.AllocateReg(ArgRegs[RegNum]);
1466  }
1467
1468  // Always return false here, as this function only makes sure that the two f64
1469  // values a ppc_fp128 value is split into are both passed in registers or both
1470  // passed on the stack and does not actually allocate a register for the
1471  // current argument.
1472  return false;
1473}
1474
1475/// GetFPR - Get the set of FP registers that should be allocated for arguments,
1476/// on Darwin.
1477static const unsigned *GetFPR() {
1478  static const unsigned FPR[] = {
1479    PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1480    PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1481  };
1482
1483  return FPR;
1484}
1485
1486/// CalculateStackSlotSize - Calculates the size reserved for this argument on
1487/// the stack.
1488static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1489                                       unsigned PtrByteSize) {
1490  unsigned ArgSize = ArgVT.getSizeInBits()/8;
1491  if (Flags.isByVal())
1492    ArgSize = Flags.getByValSize();
1493  ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1494
1495  return ArgSize;
1496}
1497
1498SDValue
1499PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1500                                        CallingConv::ID CallConv, bool isVarArg,
1501                                        const SmallVectorImpl<ISD::InputArg>
1502                                          &Ins,
1503                                        DebugLoc dl, SelectionDAG &DAG,
1504                                        SmallVectorImpl<SDValue> &InVals)
1505                                          const {
1506  if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
1507    return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins,
1508                                     dl, DAG, InVals);
1509  } else {
1510    return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1511                                       dl, DAG, InVals);
1512  }
1513}
1514
1515SDValue
1516PPCTargetLowering::LowerFormalArguments_SVR4(
1517                                      SDValue Chain,
1518                                      CallingConv::ID CallConv, bool isVarArg,
1519                                      const SmallVectorImpl<ISD::InputArg>
1520                                        &Ins,
1521                                      DebugLoc dl, SelectionDAG &DAG,
1522                                      SmallVectorImpl<SDValue> &InVals) const {
1523
1524  // 32-bit SVR4 ABI Stack Frame Layout:
1525  //              +-----------------------------------+
1526  //        +-->  |            Back chain             |
1527  //        |     +-----------------------------------+
1528  //        |     | Floating-point register save area |
1529  //        |     +-----------------------------------+
1530  //        |     |    General register save area     |
1531  //        |     +-----------------------------------+
1532  //        |     |          CR save word             |
1533  //        |     +-----------------------------------+
1534  //        |     |         VRSAVE save word          |
1535  //        |     +-----------------------------------+
1536  //        |     |         Alignment padding         |
1537  //        |     +-----------------------------------+
1538  //        |     |     Vector register save area     |
1539  //        |     +-----------------------------------+
1540  //        |     |       Local variable space        |
1541  //        |     +-----------------------------------+
1542  //        |     |        Parameter list area        |
1543  //        |     +-----------------------------------+
1544  //        |     |           LR save word            |
1545  //        |     +-----------------------------------+
1546  // SP-->  +---  |            Back chain             |
1547  //              +-----------------------------------+
1548  //
1549  // Specifications:
1550  //   System V Application Binary Interface PowerPC Processor Supplement
1551  //   AltiVec Technology Programming Interface Manual
1552
1553  MachineFunction &MF = DAG.getMachineFunction();
1554  MachineFrameInfo *MFI = MF.getFrameInfo();
1555  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1556
1557  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1558  // Potential tail calls could cause overwriting of argument stack slots.
1559  bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast));
1560  unsigned PtrByteSize = 4;
1561
1562  // Assign locations to all of the incoming arguments.
1563  SmallVector<CCValAssign, 16> ArgLocs;
1564  CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1565                 *DAG.getContext());
1566
1567  // Reserve space for the linkage area on the stack.
1568  CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
1569
1570  CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
1571
1572  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1573    CCValAssign &VA = ArgLocs[i];
1574
1575    // Arguments stored in registers.
1576    if (VA.isRegLoc()) {
1577      TargetRegisterClass *RC;
1578      EVT ValVT = VA.getValVT();
1579
1580      switch (ValVT.getSimpleVT().SimpleTy) {
1581        default:
1582          llvm_unreachable("ValVT not supported by formal arguments Lowering");
1583        case MVT::i32:
1584          RC = PPC::GPRCRegisterClass;
1585          break;
1586        case MVT::f32:
1587          RC = PPC::F4RCRegisterClass;
1588          break;
1589        case MVT::f64:
1590          RC = PPC::F8RCRegisterClass;
1591          break;
1592        case MVT::v16i8:
1593        case MVT::v8i16:
1594        case MVT::v4i32:
1595        case MVT::v4f32:
1596          RC = PPC::VRRCRegisterClass;
1597          break;
1598      }
1599
1600      // Transform the arguments stored in physical registers into virtual ones.
1601      unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1602      SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1603
1604      InVals.push_back(ArgValue);
1605    } else {
1606      // Argument stored in memory.
1607      assert(VA.isMemLoc());
1608
1609      unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1610      int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1611                                      isImmutable);
1612
1613      // Create load nodes to retrieve arguments from the stack.
1614      SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1615      InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1616                                   MachinePointerInfo(),
1617                                   false, false, 0));
1618    }
1619  }
1620
1621  // Assign locations to all of the incoming aggregate by value arguments.
1622  // Aggregates passed by value are stored in the local variable space of the
1623  // caller's stack frame, right above the parameter list area.
1624  SmallVector<CCValAssign, 16> ByValArgLocs;
1625  CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(),
1626                      ByValArgLocs, *DAG.getContext());
1627
1628  // Reserve stack space for the allocations in CCInfo.
1629  CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1630
1631  CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal);
1632
1633  // Area that is at least reserved in the caller of this function.
1634  unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1635
1636  // Set the size that is at least reserved in caller of this function.  Tail
1637  // call optimized function's reserved stack space needs to be aligned so that
1638  // taking the difference between two stack areas will result in an aligned
1639  // stack.
1640  PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1641
1642  MinReservedArea =
1643    std::max(MinReservedArea,
1644             PPCFrameLowering::getMinCallFrameSize(false, false));
1645
1646  unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
1647    getStackAlignment();
1648  unsigned AlignMask = TargetAlign-1;
1649  MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1650
1651  FI->setMinReservedArea(MinReservedArea);
1652
1653  SmallVector<SDValue, 8> MemOps;
1654
1655  // If the function takes variable number of arguments, make a frame index for
1656  // the start of the first vararg value... for expansion of llvm.va_start.
1657  if (isVarArg) {
1658    static const unsigned GPArgRegs[] = {
1659      PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1660      PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1661    };
1662    const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
1663
1664    static const unsigned FPArgRegs[] = {
1665      PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1666      PPC::F8
1667    };
1668    const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
1669
1670    FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
1671                                                          NumGPArgRegs));
1672    FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
1673                                                          NumFPArgRegs));
1674
1675    // Make room for NumGPArgRegs and NumFPArgRegs.
1676    int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
1677                NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
1678
1679    FuncInfo->setVarArgsStackOffset(
1680      MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1681                             CCInfo.getNextStackOffset(), true));
1682
1683    FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
1684    SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1685
1686    // The fixed integer arguments of a variadic function are stored to the
1687    // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
1688    // the result of va_next.
1689    for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
1690      // Get an existing live-in vreg, or add a new one.
1691      unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
1692      if (!VReg)
1693        VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
1694
1695      SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1696      SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1697                                   MachinePointerInfo(), false, false, 0);
1698      MemOps.push_back(Store);
1699      // Increment the address by four for the next argument to store
1700      SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1701      FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1702    }
1703
1704    // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
1705    // is set.
1706    // The double arguments are stored to the VarArgsFrameIndex
1707    // on the stack.
1708    for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
1709      // Get an existing live-in vreg, or add a new one.
1710      unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
1711      if (!VReg)
1712        VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
1713
1714      SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
1715      SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1716                                   MachinePointerInfo(), false, false, 0);
1717      MemOps.push_back(Store);
1718      // Increment the address by eight for the next argument to store
1719      SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1720                                         PtrVT);
1721      FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1722    }
1723  }
1724
1725  if (!MemOps.empty())
1726    Chain = DAG.getNode(ISD::TokenFactor, dl,
1727                        MVT::Other, &MemOps[0], MemOps.size());
1728
1729  return Chain;
1730}
1731
1732SDValue
1733PPCTargetLowering::LowerFormalArguments_Darwin(
1734                                      SDValue Chain,
1735                                      CallingConv::ID CallConv, bool isVarArg,
1736                                      const SmallVectorImpl<ISD::InputArg>
1737                                        &Ins,
1738                                      DebugLoc dl, SelectionDAG &DAG,
1739                                      SmallVectorImpl<SDValue> &InVals) const {
1740  // TODO: add description of PPC stack frame format, or at least some docs.
1741  //
1742  MachineFunction &MF = DAG.getMachineFunction();
1743  MachineFrameInfo *MFI = MF.getFrameInfo();
1744  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1745
1746  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1747  bool isPPC64 = PtrVT == MVT::i64;
1748  // Potential tail calls could cause overwriting of argument stack slots.
1749  bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast));
1750  unsigned PtrByteSize = isPPC64 ? 8 : 4;
1751
1752  unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
1753  // Area that is at least reserved in caller of this function.
1754  unsigned MinReservedArea = ArgOffset;
1755
1756  static const unsigned GPR_32[] = {           // 32-bit registers.
1757    PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1758    PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1759  };
1760  static const unsigned GPR_64[] = {           // 64-bit registers.
1761    PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1762    PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1763  };
1764
1765  static const unsigned *FPR = GetFPR();
1766
1767  static const unsigned VR[] = {
1768    PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1769    PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1770  };
1771
1772  const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1773  const unsigned Num_FPR_Regs = 13;
1774  const unsigned Num_VR_Regs  = array_lengthof( VR);
1775
1776  unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1777
1778  const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1779
1780  // In 32-bit non-varargs functions, the stack space for vectors is after the
1781  // stack space for non-vectors.  We do not use this space unless we have
1782  // too many vectors to fit in registers, something that only occurs in
1783  // constructed examples:), but we have to walk the arglist to figure
1784  // that out...for the pathological case, compute VecArgOffset as the
1785  // start of the vector parameter area.  Computing VecArgOffset is the
1786  // entire point of the following loop.
1787  unsigned VecArgOffset = ArgOffset;
1788  if (!isVarArg && !isPPC64) {
1789    for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
1790         ++ArgNo) {
1791      EVT ObjectVT = Ins[ArgNo].VT;
1792      unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1793      ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1794
1795      if (Flags.isByVal()) {
1796        // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1797        ObjSize = Flags.getByValSize();
1798        unsigned ArgSize =
1799                ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1800        VecArgOffset += ArgSize;
1801        continue;
1802      }
1803
1804      switch(ObjectVT.getSimpleVT().SimpleTy) {
1805      default: llvm_unreachable("Unhandled argument type!");
1806      case MVT::i32:
1807      case MVT::f32:
1808        VecArgOffset += isPPC64 ? 8 : 4;
1809        break;
1810      case MVT::i64:  // PPC64
1811      case MVT::f64:
1812        VecArgOffset += 8;
1813        break;
1814      case MVT::v4f32:
1815      case MVT::v4i32:
1816      case MVT::v8i16:
1817      case MVT::v16i8:
1818        // Nothing to do, we're only looking at Nonvector args here.
1819        break;
1820      }
1821    }
1822  }
1823  // We've found where the vector parameter area in memory is.  Skip the
1824  // first 12 parameters; these don't use that memory.
1825  VecArgOffset = ((VecArgOffset+15)/16)*16;
1826  VecArgOffset += 12*16;
1827
1828  // Add DAG nodes to load the arguments or copy them out of registers.  On
1829  // entry to a function on PPC, the arguments start after the linkage area,
1830  // although the first ones are often in registers.
1831
1832  SmallVector<SDValue, 8> MemOps;
1833  unsigned nAltivecParamsAtEnd = 0;
1834  for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
1835    SDValue ArgVal;
1836    bool needsLoad = false;
1837    EVT ObjectVT = Ins[ArgNo].VT;
1838    unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1839    unsigned ArgSize = ObjSize;
1840    ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1841
1842    unsigned CurArgOffset = ArgOffset;
1843
1844    // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1845    if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1846        ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1847      if (isVarArg || isPPC64) {
1848        MinReservedArea = ((MinReservedArea+15)/16)*16;
1849        MinReservedArea += CalculateStackSlotSize(ObjectVT,
1850                                                  Flags,
1851                                                  PtrByteSize);
1852      } else  nAltivecParamsAtEnd++;
1853    } else
1854      // Calculate min reserved area.
1855      MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
1856                                                Flags,
1857                                                PtrByteSize);
1858
1859    // FIXME the codegen can be much improved in some cases.
1860    // We do not have to keep everything in memory.
1861    if (Flags.isByVal()) {
1862      // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1863      ObjSize = Flags.getByValSize();
1864      ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1865      // Objects of size 1 and 2 are right justified, everything else is
1866      // left justified.  This means the memory address is adjusted forwards.
1867      if (ObjSize==1 || ObjSize==2) {
1868        CurArgOffset = CurArgOffset + (4 - ObjSize);
1869      }
1870      // The value of the object is its address.
1871      int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
1872      SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1873      InVals.push_back(FIN);
1874      if (ObjSize==1 || ObjSize==2) {
1875        if (GPR_idx != Num_GPR_Regs) {
1876          unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1877          SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1878          SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
1879                                            MachinePointerInfo(),
1880                                            ObjSize==1 ? MVT::i8 : MVT::i16,
1881                                            false, false, 0);
1882          MemOps.push_back(Store);
1883          ++GPR_idx;
1884        }
1885
1886        ArgOffset += PtrByteSize;
1887
1888        continue;
1889      }
1890      for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1891        // Store whatever pieces of the object are in registers
1892        // to memory.  ArgVal will be address of the beginning of
1893        // the object.
1894        if (GPR_idx != Num_GPR_Regs) {
1895          unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1896          int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
1897          SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1898          SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1899          SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1900                                       MachinePointerInfo(),
1901                                       false, false, 0);
1902          MemOps.push_back(Store);
1903          ++GPR_idx;
1904          ArgOffset += PtrByteSize;
1905        } else {
1906          ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1907          break;
1908        }
1909      }
1910      continue;
1911    }
1912
1913    switch (ObjectVT.getSimpleVT().SimpleTy) {
1914    default: llvm_unreachable("Unhandled argument type!");
1915    case MVT::i32:
1916      if (!isPPC64) {
1917        if (GPR_idx != Num_GPR_Regs) {
1918          unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1919          ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1920          ++GPR_idx;
1921        } else {
1922          needsLoad = true;
1923          ArgSize = PtrByteSize;
1924        }
1925        // All int arguments reserve stack space in the Darwin ABI.
1926        ArgOffset += PtrByteSize;
1927        break;
1928      }
1929      // FALLTHROUGH
1930    case MVT::i64:  // PPC64
1931      if (GPR_idx != Num_GPR_Regs) {
1932        unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
1933        ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1934
1935        if (ObjectVT == MVT::i32) {
1936          // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1937          // value to MVT::i64 and then truncate to the correct register size.
1938          if (Flags.isSExt())
1939            ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
1940                                 DAG.getValueType(ObjectVT));
1941          else if (Flags.isZExt())
1942            ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
1943                                 DAG.getValueType(ObjectVT));
1944
1945          ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
1946        }
1947
1948        ++GPR_idx;
1949      } else {
1950        needsLoad = true;
1951        ArgSize = PtrByteSize;
1952      }
1953      // All int arguments reserve stack space in the Darwin ABI.
1954      ArgOffset += 8;
1955      break;
1956
1957    case MVT::f32:
1958    case MVT::f64:
1959      // Every 4 bytes of argument space consumes one of the GPRs available for
1960      // argument passing.
1961      if (GPR_idx != Num_GPR_Regs) {
1962        ++GPR_idx;
1963        if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1964          ++GPR_idx;
1965      }
1966      if (FPR_idx != Num_FPR_Regs) {
1967        unsigned VReg;
1968
1969        if (ObjectVT == MVT::f32)
1970          VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
1971        else
1972          VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
1973
1974        ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
1975        ++FPR_idx;
1976      } else {
1977        needsLoad = true;
1978      }
1979
1980      // All FP arguments reserve stack space in the Darwin ABI.
1981      ArgOffset += isPPC64 ? 8 : ObjSize;
1982      break;
1983    case MVT::v4f32:
1984    case MVT::v4i32:
1985    case MVT::v8i16:
1986    case MVT::v16i8:
1987      // Note that vector arguments in registers don't reserve stack space,
1988      // except in varargs functions.
1989      if (VR_idx != Num_VR_Regs) {
1990        unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
1991        ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
1992        if (isVarArg) {
1993          while ((ArgOffset % 16) != 0) {
1994            ArgOffset += PtrByteSize;
1995            if (GPR_idx != Num_GPR_Regs)
1996              GPR_idx++;
1997          }
1998          ArgOffset += 16;
1999          GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2000        }
2001        ++VR_idx;
2002      } else {
2003        if (!isVarArg && !isPPC64) {
2004          // Vectors go after all the nonvectors.
2005          CurArgOffset = VecArgOffset;
2006          VecArgOffset += 16;
2007        } else {
2008          // Vectors are aligned.
2009          ArgOffset = ((ArgOffset+15)/16)*16;
2010          CurArgOffset = ArgOffset;
2011          ArgOffset += 16;
2012        }
2013        needsLoad = true;
2014      }
2015      break;
2016    }
2017
2018    // We need to load the argument to a virtual register if we determined above
2019    // that we ran out of physical registers of the appropriate type.
2020    if (needsLoad) {
2021      int FI = MFI->CreateFixedObject(ObjSize,
2022                                      CurArgOffset + (ArgSize - ObjSize),
2023                                      isImmutable);
2024      SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2025      ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2026                           false, false, 0);
2027    }
2028
2029    InVals.push_back(ArgVal);
2030  }
2031
2032  // Set the size that is at least reserved in caller of this function.  Tail
2033  // call optimized function's reserved stack space needs to be aligned so that
2034  // taking the difference between two stack areas will result in an aligned
2035  // stack.
2036  PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2037  // Add the Altivec parameters at the end, if needed.
2038  if (nAltivecParamsAtEnd) {
2039    MinReservedArea = ((MinReservedArea+15)/16)*16;
2040    MinReservedArea += 16*nAltivecParamsAtEnd;
2041  }
2042  MinReservedArea =
2043    std::max(MinReservedArea,
2044             PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2045  unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2046    getStackAlignment();
2047  unsigned AlignMask = TargetAlign-1;
2048  MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2049  FI->setMinReservedArea(MinReservedArea);
2050
2051  // If the function takes variable number of arguments, make a frame index for
2052  // the start of the first vararg value... for expansion of llvm.va_start.
2053  if (isVarArg) {
2054    int Depth = ArgOffset;
2055
2056    FuncInfo->setVarArgsFrameIndex(
2057      MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2058                             Depth, true));
2059    SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2060
2061    // If this function is vararg, store any remaining integer argument regs
2062    // to their spots on the stack so that they may be loaded by deferencing the
2063    // result of va_next.
2064    for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2065      unsigned VReg;
2066
2067      if (isPPC64)
2068        VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2069      else
2070        VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2071
2072      SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2073      SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2074                                   MachinePointerInfo(), false, false, 0);
2075      MemOps.push_back(Store);
2076      // Increment the address by four for the next argument to store
2077      SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2078      FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2079    }
2080  }
2081
2082  if (!MemOps.empty())
2083    Chain = DAG.getNode(ISD::TokenFactor, dl,
2084                        MVT::Other, &MemOps[0], MemOps.size());
2085
2086  return Chain;
2087}
2088
2089/// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
2090/// linkage area for the Darwin ABI.
2091static unsigned
2092CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2093                                     bool isPPC64,
2094                                     bool isVarArg,
2095                                     unsigned CC,
2096                                     const SmallVectorImpl<ISD::OutputArg>
2097                                       &Outs,
2098                                     const SmallVectorImpl<SDValue> &OutVals,
2099                                     unsigned &nAltivecParamsAtEnd) {
2100  // Count how many bytes are to be pushed on the stack, including the linkage
2101  // area, and parameter passing area.  We start with 24/48 bytes, which is
2102  // prereserved space for [SP][CR][LR][3 x unused].
2103  unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2104  unsigned NumOps = Outs.size();
2105  unsigned PtrByteSize = isPPC64 ? 8 : 4;
2106
2107  // Add up all the space actually used.
2108  // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2109  // they all go in registers, but we must reserve stack space for them for
2110  // possible use by the caller.  In varargs or 64-bit calls, parameters are
2111  // assigned stack space in order, with padding so Altivec parameters are
2112  // 16-byte aligned.
2113  nAltivecParamsAtEnd = 0;
2114  for (unsigned i = 0; i != NumOps; ++i) {
2115    ISD::ArgFlagsTy Flags = Outs[i].Flags;
2116    EVT ArgVT = Outs[i].VT;
2117    // Varargs Altivec parameters are padded to a 16 byte boundary.
2118    if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2119        ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2120      if (!isVarArg && !isPPC64) {
2121        // Non-varargs Altivec parameters go after all the non-Altivec
2122        // parameters; handle those later so we know how much padding we need.
2123        nAltivecParamsAtEnd++;
2124        continue;
2125      }
2126      // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2127      NumBytes = ((NumBytes+15)/16)*16;
2128    }
2129    NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2130  }
2131
2132   // Allow for Altivec parameters at the end, if needed.
2133  if (nAltivecParamsAtEnd) {
2134    NumBytes = ((NumBytes+15)/16)*16;
2135    NumBytes += 16*nAltivecParamsAtEnd;
2136  }
2137
2138  // The prolog code of the callee may store up to 8 GPR argument registers to
2139  // the stack, allowing va_start to index over them in memory if its varargs.
2140  // Because we cannot tell if this is needed on the caller side, we have to
2141  // conservatively assume that it is needed.  As such, make sure we have at
2142  // least enough stack space for the caller to store the 8 GPRs.
2143  NumBytes = std::max(NumBytes,
2144                      PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2145
2146  // Tail call needs the stack to be aligned.
2147  if (CC==CallingConv::Fast && GuaranteedTailCallOpt) {
2148    unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2149      getStackAlignment();
2150    unsigned AlignMask = TargetAlign-1;
2151    NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2152  }
2153
2154  return NumBytes;
2155}
2156
2157/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2158/// adjusted to accommodate the arguments for the tailcall.
2159static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2160                                   unsigned ParamSize) {
2161
2162  if (!isTailCall) return 0;
2163
2164  PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2165  unsigned CallerMinReservedArea = FI->getMinReservedArea();
2166  int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2167  // Remember only if the new adjustement is bigger.
2168  if (SPDiff < FI->getTailCallSPDelta())
2169    FI->setTailCallSPDelta(SPDiff);
2170
2171  return SPDiff;
2172}
2173
2174/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2175/// for tail call optimization. Targets which want to do tail call
2176/// optimization should implement this function.
2177bool
2178PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2179                                                     CallingConv::ID CalleeCC,
2180                                                     bool isVarArg,
2181                                      const SmallVectorImpl<ISD::InputArg> &Ins,
2182                                                     SelectionDAG& DAG) const {
2183  if (!GuaranteedTailCallOpt)
2184    return false;
2185
2186  // Variable argument functions are not supported.
2187  if (isVarArg)
2188    return false;
2189
2190  MachineFunction &MF = DAG.getMachineFunction();
2191  CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2192  if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2193    // Functions containing by val parameters are not supported.
2194    for (unsigned i = 0; i != Ins.size(); i++) {
2195       ISD::ArgFlagsTy Flags = Ins[i].Flags;
2196       if (Flags.isByVal()) return false;
2197    }
2198
2199    // Non PIC/GOT  tail calls are supported.
2200    if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2201      return true;
2202
2203    // At the moment we can only do local tail calls (in same module, hidden
2204    // or protected) if we are generating PIC.
2205    if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2206      return G->getGlobal()->hasHiddenVisibility()
2207          || G->getGlobal()->hasProtectedVisibility();
2208  }
2209
2210  return false;
2211}
2212
2213/// isCallCompatibleAddress - Return the immediate to use if the specified
2214/// 32-bit value is representable in the immediate field of a BxA instruction.
2215static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2216  ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2217  if (!C) return 0;
2218
2219  int Addr = C->getZExtValue();
2220  if ((Addr & 3) != 0 ||  // Low 2 bits are implicitly zero.
2221      (Addr << 6 >> 6) != Addr)
2222    return 0;  // Top 6 bits have to be sext of immediate.
2223
2224  return DAG.getConstant((int)C->getZExtValue() >> 2,
2225                         DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2226}
2227
2228namespace {
2229
2230struct TailCallArgumentInfo {
2231  SDValue Arg;
2232  SDValue FrameIdxOp;
2233  int       FrameIdx;
2234
2235  TailCallArgumentInfo() : FrameIdx(0) {}
2236};
2237
2238}
2239
2240/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2241static void
2242StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2243                                           SDValue Chain,
2244                   const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2245                   SmallVector<SDValue, 8> &MemOpChains,
2246                   DebugLoc dl) {
2247  for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2248    SDValue Arg = TailCallArgs[i].Arg;
2249    SDValue FIN = TailCallArgs[i].FrameIdxOp;
2250    int FI = TailCallArgs[i].FrameIdx;
2251    // Store relative to framepointer.
2252    MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2253                                       MachinePointerInfo::getFixedStack(FI),
2254                                       false, false, 0));
2255  }
2256}
2257
2258/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2259/// the appropriate stack slot for the tail call optimized function call.
2260static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2261                                               MachineFunction &MF,
2262                                               SDValue Chain,
2263                                               SDValue OldRetAddr,
2264                                               SDValue OldFP,
2265                                               int SPDiff,
2266                                               bool isPPC64,
2267                                               bool isDarwinABI,
2268                                               DebugLoc dl) {
2269  if (SPDiff) {
2270    // Calculate the new stack slot for the return address.
2271    int SlotSize = isPPC64 ? 8 : 4;
2272    int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
2273                                                                   isDarwinABI);
2274    int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2275                                                          NewRetAddrLoc, true);
2276    EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2277    SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2278    Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2279                         MachinePointerInfo::getFixedStack(NewRetAddr),
2280                         false, false, 0);
2281
2282    // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2283    // slot as the FP is never overwritten.
2284    if (isDarwinABI) {
2285      int NewFPLoc =
2286        SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2287      int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
2288                                                          true);
2289      SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2290      Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2291                           MachinePointerInfo::getFixedStack(NewFPIdx),
2292                           false, false, 0);
2293    }
2294  }
2295  return Chain;
2296}
2297
2298/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2299/// the position of the argument.
2300static void
2301CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2302                         SDValue Arg, int SPDiff, unsigned ArgOffset,
2303                      SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2304  int Offset = ArgOffset + SPDiff;
2305  uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2306  int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2307  EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2308  SDValue FIN = DAG.getFrameIndex(FI, VT);
2309  TailCallArgumentInfo Info;
2310  Info.Arg = Arg;
2311  Info.FrameIdxOp = FIN;
2312  Info.FrameIdx = FI;
2313  TailCallArguments.push_back(Info);
2314}
2315
2316/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2317/// stack slot. Returns the chain as result and the loaded frame pointers in
2318/// LROpOut/FPOpout. Used when tail calling.
2319SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2320                                                        int SPDiff,
2321                                                        SDValue Chain,
2322                                                        SDValue &LROpOut,
2323                                                        SDValue &FPOpOut,
2324                                                        bool isDarwinABI,
2325                                                        DebugLoc dl) const {
2326  if (SPDiff) {
2327    // Load the LR and FP stack slot for later adjusting.
2328    EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2329    LROpOut = getReturnAddrFrameIndex(DAG);
2330    LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
2331                          false, false, 0);
2332    Chain = SDValue(LROpOut.getNode(), 1);
2333
2334    // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
2335    // slot as the FP is never overwritten.
2336    if (isDarwinABI) {
2337      FPOpOut = getFramePointerFrameIndex(DAG);
2338      FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
2339                            false, false, 0);
2340      Chain = SDValue(FPOpOut.getNode(), 1);
2341    }
2342  }
2343  return Chain;
2344}
2345
2346/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2347/// by "Src" to address "Dst" of size "Size".  Alignment information is
2348/// specified by the specific parameter attribute. The copy will be passed as
2349/// a byval function parameter.
2350/// Sometimes what we are copying is the end of a larger object, the part that
2351/// does not fit in registers.
2352static SDValue
2353CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2354                          ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2355                          DebugLoc dl) {
2356  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2357  return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2358                       false, false, MachinePointerInfo(0),
2359                       MachinePointerInfo(0));
2360}
2361
2362/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2363/// tail calls.
2364static void
2365LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2366                 SDValue Arg, SDValue PtrOff, int SPDiff,
2367                 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2368                 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2369                 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
2370                 DebugLoc dl) {
2371  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2372  if (!isTailCall) {
2373    if (isVector) {
2374      SDValue StackPtr;
2375      if (isPPC64)
2376        StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2377      else
2378        StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2379      PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2380                           DAG.getConstant(ArgOffset, PtrVT));
2381    }
2382    MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2383                                       MachinePointerInfo(), false, false, 0));
2384  // Calculate and remember argument location.
2385  } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2386                                  TailCallArguments);
2387}
2388
2389static
2390void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
2391                     DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
2392                     SDValue LROp, SDValue FPOp, bool isDarwinABI,
2393                     SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
2394  MachineFunction &MF = DAG.getMachineFunction();
2395
2396  // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2397  // might overwrite each other in case of tail call optimization.
2398  SmallVector<SDValue, 8> MemOpChains2;
2399  // Do not flag preceding copytoreg stuff together with the following stuff.
2400  InFlag = SDValue();
2401  StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2402                                    MemOpChains2, dl);
2403  if (!MemOpChains2.empty())
2404    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2405                        &MemOpChains2[0], MemOpChains2.size());
2406
2407  // Store the return address to the appropriate stack slot.
2408  Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2409                                        isPPC64, isDarwinABI, dl);
2410
2411  // Emit callseq_end just before tailcall node.
2412  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2413                             DAG.getIntPtrConstant(0, true), InFlag);
2414  InFlag = Chain.getValue(1);
2415}
2416
2417static
2418unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
2419                     SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
2420                     SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
2421                     SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
2422                     const PPCSubtarget &PPCSubTarget) {
2423
2424  bool isPPC64 = PPCSubTarget.isPPC64();
2425  bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
2426
2427  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2428  NodeTys.push_back(MVT::Other);   // Returns a chain
2429  NodeTys.push_back(MVT::Glue);    // Returns a flag for retval copy to use.
2430
2431  unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
2432
2433  bool needIndirectCall = true;
2434  if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
2435    // If this is an absolute destination address, use the munged value.
2436    Callee = SDValue(Dest, 0);
2437    needIndirectCall = false;
2438  }
2439
2440  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2441    // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
2442    // Use indirect calls for ALL functions calls in JIT mode, since the
2443    // far-call stubs may be outside relocation limits for a BL instruction.
2444    if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
2445      unsigned OpFlags = 0;
2446      if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
2447          (!PPCSubTarget.getTargetTriple().isMacOSX() ||
2448           PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
2449          (G->getGlobal()->isDeclaration() ||
2450           G->getGlobal()->isWeakForLinker())) {
2451        // PC-relative references to external symbols should go through $stub,
2452        // unless we're building with the leopard linker or later, which
2453        // automatically synthesizes these stubs.
2454        OpFlags = PPCII::MO_DARWIN_STUB;
2455      }
2456
2457      // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
2458      // every direct call is) turn it into a TargetGlobalAddress /
2459      // TargetExternalSymbol node so that legalize doesn't hack it.
2460      Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2461                                          Callee.getValueType(),
2462                                          0, OpFlags);
2463      needIndirectCall = false;
2464    }
2465  }
2466
2467  if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2468    unsigned char OpFlags = 0;
2469
2470    if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
2471        (!PPCSubTarget.getTargetTriple().isMacOSX() ||
2472         PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
2473      // PC-relative references to external symbols should go through $stub,
2474      // unless we're building with the leopard linker or later, which
2475      // automatically synthesizes these stubs.
2476      OpFlags = PPCII::MO_DARWIN_STUB;
2477    }
2478
2479    Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
2480                                         OpFlags);
2481    needIndirectCall = false;
2482  }
2483
2484  if (needIndirectCall) {
2485    // Otherwise, this is an indirect call.  We have to use a MTCTR/BCTRL pair
2486    // to do the call, we can't use PPCISD::CALL.
2487    SDValue MTCTROps[] = {Chain, Callee, InFlag};
2488
2489    if (isSVR4ABI && isPPC64) {
2490      // Function pointers in the 64-bit SVR4 ABI do not point to the function
2491      // entry point, but to the function descriptor (the function entry point
2492      // address is part of the function descriptor though).
2493      // The function descriptor is a three doubleword structure with the
2494      // following fields: function entry point, TOC base address and
2495      // environment pointer.
2496      // Thus for a call through a function pointer, the following actions need
2497      // to be performed:
2498      //   1. Save the TOC of the caller in the TOC save area of its stack
2499      //      frame (this is done in LowerCall_Darwin()).
2500      //   2. Load the address of the function entry point from the function
2501      //      descriptor.
2502      //   3. Load the TOC of the callee from the function descriptor into r2.
2503      //   4. Load the environment pointer from the function descriptor into
2504      //      r11.
2505      //   5. Branch to the function entry point address.
2506      //   6. On return of the callee, the TOC of the caller needs to be
2507      //      restored (this is done in FinishCall()).
2508      //
2509      // All those operations are flagged together to ensure that no other
2510      // operations can be scheduled in between. E.g. without flagging the
2511      // operations together, a TOC access in the caller could be scheduled
2512      // between the load of the callee TOC and the branch to the callee, which
2513      // results in the TOC access going through the TOC of the callee instead
2514      // of going through the TOC of the caller, which leads to incorrect code.
2515
2516      // Load the address of the function entry point from the function
2517      // descriptor.
2518      SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
2519      SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
2520                                        InFlag.getNode() ? 3 : 2);
2521      Chain = LoadFuncPtr.getValue(1);
2522      InFlag = LoadFuncPtr.getValue(2);
2523
2524      // Load environment pointer into r11.
2525      // Offset of the environment pointer within the function descriptor.
2526      SDValue PtrOff = DAG.getIntPtrConstant(16);
2527
2528      SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
2529      SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
2530                                       InFlag);
2531      Chain = LoadEnvPtr.getValue(1);
2532      InFlag = LoadEnvPtr.getValue(2);
2533
2534      SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
2535                                        InFlag);
2536      Chain = EnvVal.getValue(0);
2537      InFlag = EnvVal.getValue(1);
2538
2539      // Load TOC of the callee into r2. We are using a target-specific load
2540      // with r2 hard coded, because the result of a target-independent load
2541      // would never go directly into r2, since r2 is a reserved register (which
2542      // prevents the register allocator from allocating it), resulting in an
2543      // additional register being allocated and an unnecessary move instruction
2544      // being generated.
2545      VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2546      SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
2547                                       Callee, InFlag);
2548      Chain = LoadTOCPtr.getValue(0);
2549      InFlag = LoadTOCPtr.getValue(1);
2550
2551      MTCTROps[0] = Chain;
2552      MTCTROps[1] = LoadFuncPtr;
2553      MTCTROps[2] = InFlag;
2554    }
2555
2556    Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2557                        2 + (InFlag.getNode() != 0));
2558    InFlag = Chain.getValue(1);
2559
2560    NodeTys.clear();
2561    NodeTys.push_back(MVT::Other);
2562    NodeTys.push_back(MVT::Glue);
2563    Ops.push_back(Chain);
2564    CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
2565    Callee.setNode(0);
2566    // Add CTR register as callee so a bctr can be emitted later.
2567    if (isTailCall)
2568      Ops.push_back(DAG.getRegister(PPC::CTR, PtrVT));
2569  }
2570
2571  // If this is a direct call, pass the chain and the callee.
2572  if (Callee.getNode()) {
2573    Ops.push_back(Chain);
2574    Ops.push_back(Callee);
2575  }
2576  // If this is a tail call add stack pointer delta.
2577  if (isTailCall)
2578    Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2579
2580  // Add argument registers to the end of the list so that they are known live
2581  // into the call.
2582  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2583    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2584                                  RegsToPass[i].second.getValueType()));
2585
2586  return CallOpc;
2587}
2588
2589SDValue
2590PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2591                                   CallingConv::ID CallConv, bool isVarArg,
2592                                   const SmallVectorImpl<ISD::InputArg> &Ins,
2593                                   DebugLoc dl, SelectionDAG &DAG,
2594                                   SmallVectorImpl<SDValue> &InVals) const {
2595
2596  SmallVector<CCValAssign, 16> RVLocs;
2597  CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(),
2598                    RVLocs, *DAG.getContext());
2599  CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2600
2601  // Copy all of the result registers out of their specified physreg.
2602  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2603    CCValAssign &VA = RVLocs[i];
2604    EVT VT = VA.getValVT();
2605    assert(VA.isRegLoc() && "Can only return in registers!");
2606    Chain = DAG.getCopyFromReg(Chain, dl,
2607                               VA.getLocReg(), VT, InFlag).getValue(1);
2608    InVals.push_back(Chain.getValue(0));
2609    InFlag = Chain.getValue(2);
2610  }
2611
2612  return Chain;
2613}
2614
2615SDValue
2616PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
2617                              bool isTailCall, bool isVarArg,
2618                              SelectionDAG &DAG,
2619                              SmallVector<std::pair<unsigned, SDValue>, 8>
2620                                &RegsToPass,
2621                              SDValue InFlag, SDValue Chain,
2622                              SDValue &Callee,
2623                              int SPDiff, unsigned NumBytes,
2624                              const SmallVectorImpl<ISD::InputArg> &Ins,
2625                              SmallVectorImpl<SDValue> &InVals) const {
2626  std::vector<EVT> NodeTys;
2627  SmallVector<SDValue, 8> Ops;
2628  unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
2629                                 isTailCall, RegsToPass, Ops, NodeTys,
2630                                 PPCSubTarget);
2631
2632  // When performing tail call optimization the callee pops its arguments off
2633  // the stack. Account for this here so these bytes can be pushed back on in
2634  // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2635  int BytesCalleePops =
2636    (CallConv==CallingConv::Fast && GuaranteedTailCallOpt) ? NumBytes : 0;
2637
2638  if (InFlag.getNode())
2639    Ops.push_back(InFlag);
2640
2641  // Emit tail call.
2642  if (isTailCall) {
2643    // If this is the first return lowered for this function, add the regs
2644    // to the liveout set for the function.
2645    if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2646      SmallVector<CCValAssign, 16> RVLocs;
2647      CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2648                     *DAG.getContext());
2649      CCInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2650      for (unsigned i = 0; i != RVLocs.size(); ++i)
2651        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2652    }
2653
2654    assert(((Callee.getOpcode() == ISD::Register &&
2655             cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
2656            Callee.getOpcode() == ISD::TargetExternalSymbol ||
2657            Callee.getOpcode() == ISD::TargetGlobalAddress ||
2658            isa<ConstantSDNode>(Callee)) &&
2659    "Expecting an global address, external symbol, absolute value or register");
2660
2661    return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
2662  }
2663
2664  Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2665  InFlag = Chain.getValue(1);
2666
2667  // Add a NOP immediately after the branch instruction when using the 64-bit
2668  // SVR4 ABI. At link time, if caller and callee are in a different module and
2669  // thus have a different TOC, the call will be replaced with a call to a stub
2670  // function which saves the current TOC, loads the TOC of the callee and
2671  // branches to the callee. The NOP will be replaced with a load instruction
2672  // which restores the TOC of the caller from the TOC save slot of the current
2673  // stack frame. If caller and callee belong to the same module (and have the
2674  // same TOC), the NOP will remain unchanged.
2675  if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
2676    SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2677    if (CallOpc == PPCISD::BCTRL_SVR4) {
2678      // This is a call through a function pointer.
2679      // Restore the caller TOC from the save area into R2.
2680      // See PrepareCall() for more information about calls through function
2681      // pointers in the 64-bit SVR4 ABI.
2682      // We are using a target-specific load with r2 hard coded, because the
2683      // result of a target-independent load would never go directly into r2,
2684      // since r2 is a reserved register (which prevents the register allocator
2685      // from allocating it), resulting in an additional register being
2686      // allocated and an unnecessary move instruction being generated.
2687      Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
2688      InFlag = Chain.getValue(1);
2689    } else {
2690      // Otherwise insert NOP.
2691      InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Glue, InFlag);
2692    }
2693  }
2694
2695  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2696                             DAG.getIntPtrConstant(BytesCalleePops, true),
2697                             InFlag);
2698  if (!Ins.empty())
2699    InFlag = Chain.getValue(1);
2700
2701  return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2702                         Ins, dl, DAG, InVals);
2703}
2704
2705SDValue
2706PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2707                             CallingConv::ID CallConv, bool isVarArg,
2708                             bool &isTailCall,
2709                             const SmallVectorImpl<ISD::OutputArg> &Outs,
2710                             const SmallVectorImpl<SDValue> &OutVals,
2711                             const SmallVectorImpl<ISD::InputArg> &Ins,
2712                             DebugLoc dl, SelectionDAG &DAG,
2713                             SmallVectorImpl<SDValue> &InVals) const {
2714  if (isTailCall)
2715    isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
2716                                                   Ins, DAG);
2717
2718  if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
2719    return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
2720                          isTailCall, Outs, OutVals, Ins,
2721                          dl, DAG, InVals);
2722
2723  return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
2724                          isTailCall, Outs, OutVals, Ins,
2725                          dl, DAG, InVals);
2726}
2727
2728SDValue
2729PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
2730                                  CallingConv::ID CallConv, bool isVarArg,
2731                                  bool isTailCall,
2732                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
2733                                  const SmallVectorImpl<SDValue> &OutVals,
2734                                  const SmallVectorImpl<ISD::InputArg> &Ins,
2735                                  DebugLoc dl, SelectionDAG &DAG,
2736                                  SmallVectorImpl<SDValue> &InVals) const {
2737  // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description
2738  // of the 32-bit SVR4 ABI stack frame layout.
2739
2740  assert((CallConv == CallingConv::C ||
2741          CallConv == CallingConv::Fast) && "Unknown calling convention!");
2742
2743  unsigned PtrByteSize = 4;
2744
2745  MachineFunction &MF = DAG.getMachineFunction();
2746
2747  // Mark this function as potentially containing a function that contains a
2748  // tail call. As a consequence the frame pointer will be used for dynamicalloc
2749  // and restoring the callers stack pointer in this functions epilog. This is
2750  // done because by tail calling the called function might overwrite the value
2751  // in this function's (MF) stack pointer stack slot 0(SP).
2752  if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast)
2753    MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2754
2755  // Count how many bytes are to be pushed on the stack, including the linkage
2756  // area, parameter list area and the part of the local variable space which
2757  // contains copies of aggregates which are passed by value.
2758
2759  // Assign locations to all of the outgoing arguments.
2760  SmallVector<CCValAssign, 16> ArgLocs;
2761  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
2762                 ArgLocs, *DAG.getContext());
2763
2764  // Reserve space for the linkage area on the stack.
2765  CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2766
2767  if (isVarArg) {
2768    // Handle fixed and variable vector arguments differently.
2769    // Fixed vector arguments go into registers as long as registers are
2770    // available. Variable vector arguments always go into memory.
2771    unsigned NumArgs = Outs.size();
2772
2773    for (unsigned i = 0; i != NumArgs; ++i) {
2774      MVT ArgVT = Outs[i].VT;
2775      ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2776      bool Result;
2777
2778      if (Outs[i].IsFixed) {
2779        Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
2780                             CCInfo);
2781      } else {
2782        Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
2783                                    ArgFlags, CCInfo);
2784      }
2785
2786      if (Result) {
2787#ifndef NDEBUG
2788        errs() << "Call operand #" << i << " has unhandled type "
2789             << EVT(ArgVT).getEVTString() << "\n";
2790#endif
2791        llvm_unreachable(0);
2792      }
2793    }
2794  } else {
2795    // All arguments are treated the same.
2796    CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4);
2797  }
2798
2799  // Assign locations to all of the outgoing aggregate by value arguments.
2800  SmallVector<CCValAssign, 16> ByValArgLocs;
2801  CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), ByValArgLocs,
2802                      *DAG.getContext());
2803
2804  // Reserve stack space for the allocations in CCInfo.
2805  CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2806
2807  CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal);
2808
2809  // Size of the linkage area, parameter list area and the part of the local
2810  // space variable where copies of aggregates which are passed by value are
2811  // stored.
2812  unsigned NumBytes = CCByValInfo.getNextStackOffset();
2813
2814  // Calculate by how many bytes the stack has to be adjusted in case of tail
2815  // call optimization.
2816  int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2817
2818  // Adjust the stack pointer for the new arguments...
2819  // These operations are automatically eliminated by the prolog/epilog pass
2820  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2821  SDValue CallSeqStart = Chain;
2822
2823  // Load the return address and frame pointer so it can be moved somewhere else
2824  // later.
2825  SDValue LROp, FPOp;
2826  Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
2827                                       dl);
2828
2829  // Set up a copy of the stack pointer for use loading and storing any
2830  // arguments that may not fit in the registers available for argument
2831  // passing.
2832  SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2833
2834  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2835  SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2836  SmallVector<SDValue, 8> MemOpChains;
2837
2838  // Walk the register/memloc assignments, inserting copies/loads.
2839  for (unsigned i = 0, j = 0, e = ArgLocs.size();
2840       i != e;
2841       ++i) {
2842    CCValAssign &VA = ArgLocs[i];
2843    SDValue Arg = OutVals[i];
2844    ISD::ArgFlagsTy Flags = Outs[i].Flags;
2845
2846    if (Flags.isByVal()) {
2847      // Argument is an aggregate which is passed by value, thus we need to
2848      // create a copy of it in the local variable space of the current stack
2849      // frame (which is the stack frame of the caller) and pass the address of
2850      // this copy to the callee.
2851      assert((j < ByValArgLocs.size()) && "Index out of bounds!");
2852      CCValAssign &ByValVA = ByValArgLocs[j++];
2853      assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
2854
2855      // Memory reserved in the local variable space of the callers stack frame.
2856      unsigned LocMemOffset = ByValVA.getLocMemOffset();
2857
2858      SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2859      PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2860
2861      // Create a copy of the argument in the local area of the current
2862      // stack frame.
2863      SDValue MemcpyCall =
2864        CreateCopyOfByValArgument(Arg, PtrOff,
2865                                  CallSeqStart.getNode()->getOperand(0),
2866                                  Flags, DAG, dl);
2867
2868      // This must go outside the CALLSEQ_START..END.
2869      SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2870                           CallSeqStart.getNode()->getOperand(1));
2871      DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2872                             NewCallSeqStart.getNode());
2873      Chain = CallSeqStart = NewCallSeqStart;
2874
2875      // Pass the address of the aggregate copy on the stack either in a
2876      // physical register or in the parameter list area of the current stack
2877      // frame to the callee.
2878      Arg = PtrOff;
2879    }
2880
2881    if (VA.isRegLoc()) {
2882      // Put argument in a physical register.
2883      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2884    } else {
2885      // Put argument in the parameter list area of the current stack frame.
2886      assert(VA.isMemLoc());
2887      unsigned LocMemOffset = VA.getLocMemOffset();
2888
2889      if (!isTailCall) {
2890        SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2891        PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2892
2893        MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2894                                           MachinePointerInfo(),
2895                                           false, false, 0));
2896      } else {
2897        // Calculate and remember argument location.
2898        CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
2899                                 TailCallArguments);
2900      }
2901    }
2902  }
2903
2904  if (!MemOpChains.empty())
2905    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2906                        &MemOpChains[0], MemOpChains.size());
2907
2908  // Build a sequence of copy-to-reg nodes chained together with token chain
2909  // and flag operands which copy the outgoing args into the appropriate regs.
2910  SDValue InFlag;
2911  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2912    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2913                             RegsToPass[i].second, InFlag);
2914    InFlag = Chain.getValue(1);
2915  }
2916
2917  // Set CR6 to true if this is a vararg call.
2918  if (isVarArg) {
2919    SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0);
2920    Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
2921    InFlag = Chain.getValue(1);
2922  }
2923
2924  if (isTailCall)
2925    PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
2926                    false, TailCallArguments);
2927
2928  return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
2929                    RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
2930                    Ins, InVals);
2931}
2932
2933SDValue
2934PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
2935                                    CallingConv::ID CallConv, bool isVarArg,
2936                                    bool isTailCall,
2937                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
2938                                    const SmallVectorImpl<SDValue> &OutVals,
2939                                    const SmallVectorImpl<ISD::InputArg> &Ins,
2940                                    DebugLoc dl, SelectionDAG &DAG,
2941                                    SmallVectorImpl<SDValue> &InVals) const {
2942
2943  unsigned NumOps  = Outs.size();
2944
2945  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2946  bool isPPC64 = PtrVT == MVT::i64;
2947  unsigned PtrByteSize = isPPC64 ? 8 : 4;
2948
2949  MachineFunction &MF = DAG.getMachineFunction();
2950
2951  // Mark this function as potentially containing a function that contains a
2952  // tail call. As a consequence the frame pointer will be used for dynamicalloc
2953  // and restoring the callers stack pointer in this functions epilog. This is
2954  // done because by tail calling the called function might overwrite the value
2955  // in this function's (MF) stack pointer stack slot 0(SP).
2956  if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast)
2957    MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2958
2959  unsigned nAltivecParamsAtEnd = 0;
2960
2961  // Count how many bytes are to be pushed on the stack, including the linkage
2962  // area, and parameter passing area.  We start with 24/48 bytes, which is
2963  // prereserved space for [SP][CR][LR][3 x unused].
2964  unsigned NumBytes =
2965    CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
2966                                         Outs, OutVals,
2967                                         nAltivecParamsAtEnd);
2968
2969  // Calculate by how many bytes the stack has to be adjusted in case of tail
2970  // call optimization.
2971  int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2972
2973  // To protect arguments on the stack from being clobbered in a tail call,
2974  // force all the loads to happen before doing any other lowering.
2975  if (isTailCall)
2976    Chain = DAG.getStackArgumentTokenFactor(Chain);
2977
2978  // Adjust the stack pointer for the new arguments...
2979  // These operations are automatically eliminated by the prolog/epilog pass
2980  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2981  SDValue CallSeqStart = Chain;
2982
2983  // Load the return address and frame pointer so it can be move somewhere else
2984  // later.
2985  SDValue LROp, FPOp;
2986  Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
2987                                       dl);
2988
2989  // Set up a copy of the stack pointer for use loading and storing any
2990  // arguments that may not fit in the registers available for argument
2991  // passing.
2992  SDValue StackPtr;
2993  if (isPPC64)
2994    StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2995  else
2996    StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2997
2998  // Figure out which arguments are going to go in registers, and which in
2999  // memory.  Also, if this is a vararg function, floating point operations
3000  // must be stored to our stack, and loaded into integer regs as well, if
3001  // any integer regs are available for argument passing.
3002  unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
3003  unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3004
3005  static const unsigned GPR_32[] = {           // 32-bit registers.
3006    PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3007    PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3008  };
3009  static const unsigned GPR_64[] = {           // 64-bit registers.
3010    PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3011    PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3012  };
3013  static const unsigned *FPR = GetFPR();
3014
3015  static const unsigned VR[] = {
3016    PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3017    PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3018  };
3019  const unsigned NumGPRs = array_lengthof(GPR_32);
3020  const unsigned NumFPRs = 13;
3021  const unsigned NumVRs  = array_lengthof(VR);
3022
3023  const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
3024
3025  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3026  SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3027
3028  SmallVector<SDValue, 8> MemOpChains;
3029  for (unsigned i = 0; i != NumOps; ++i) {
3030    SDValue Arg = OutVals[i];
3031    ISD::ArgFlagsTy Flags = Outs[i].Flags;
3032
3033    // PtrOff will be used to store the current argument to the stack if a
3034    // register cannot be found for it.
3035    SDValue PtrOff;
3036
3037    PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3038
3039    PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3040
3041    // On PPC64, promote integers to 64-bit values.
3042    if (isPPC64 && Arg.getValueType() == MVT::i32) {
3043      // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3044      unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3045      Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3046    }
3047
3048    // FIXME memcpy is used way more than necessary.  Correctness first.
3049    if (Flags.isByVal()) {
3050      unsigned Size = Flags.getByValSize();
3051      if (Size==1 || Size==2) {
3052        // Very small objects are passed right-justified.
3053        // Everything else is passed left-justified.
3054        EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
3055        if (GPR_idx != NumGPRs) {
3056          SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3057                                        MachinePointerInfo(), VT,
3058                                        false, false, 0);
3059          MemOpChains.push_back(Load.getValue(1));
3060          RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3061
3062          ArgOffset += PtrByteSize;
3063        } else {
3064          SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
3065          SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3066          SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
3067                                CallSeqStart.getNode()->getOperand(0),
3068                                Flags, DAG, dl);
3069          // This must go outside the CALLSEQ_START..END.
3070          SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3071                               CallSeqStart.getNode()->getOperand(1));
3072          DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3073                                 NewCallSeqStart.getNode());
3074          Chain = CallSeqStart = NewCallSeqStart;
3075          ArgOffset += PtrByteSize;
3076        }
3077        continue;
3078      }
3079      // Copy entire object into memory.  There are cases where gcc-generated
3080      // code assumes it is there, even if it could be put entirely into
3081      // registers.  (This is not what the doc says.)
3082      SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3083                            CallSeqStart.getNode()->getOperand(0),
3084                            Flags, DAG, dl);
3085      // This must go outside the CALLSEQ_START..END.
3086      SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3087                           CallSeqStart.getNode()->getOperand(1));
3088      DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
3089      Chain = CallSeqStart = NewCallSeqStart;
3090      // And copy the pieces of it that fit into registers.
3091      for (unsigned j=0; j<Size; j+=PtrByteSize) {
3092        SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3093        SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3094        if (GPR_idx != NumGPRs) {
3095          SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3096                                     MachinePointerInfo(),
3097                                     false, false, 0);
3098          MemOpChains.push_back(Load.getValue(1));
3099          RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3100          ArgOffset += PtrByteSize;
3101        } else {
3102          ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3103          break;
3104        }
3105      }
3106      continue;
3107    }
3108
3109    switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3110    default: llvm_unreachable("Unexpected ValueType for argument!");
3111    case MVT::i32:
3112    case MVT::i64:
3113      if (GPR_idx != NumGPRs) {
3114        RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3115      } else {
3116        LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3117                         isPPC64, isTailCall, false, MemOpChains,
3118                         TailCallArguments, dl);
3119      }
3120      ArgOffset += PtrByteSize;
3121      break;
3122    case MVT::f32:
3123    case MVT::f64:
3124      if (FPR_idx != NumFPRs) {
3125        RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3126
3127        if (isVarArg) {
3128          SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3129                                       MachinePointerInfo(), false, false, 0);
3130          MemOpChains.push_back(Store);
3131
3132          // Float varargs are always shadowed in available integer registers
3133          if (GPR_idx != NumGPRs) {
3134            SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3135                                       MachinePointerInfo(), false, false, 0);
3136            MemOpChains.push_back(Load.getValue(1));
3137            RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3138          }
3139          if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
3140            SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3141            PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3142            SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3143                                       MachinePointerInfo(),
3144                                       false, false, 0);
3145            MemOpChains.push_back(Load.getValue(1));
3146            RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3147          }
3148        } else {
3149          // If we have any FPRs remaining, we may also have GPRs remaining.
3150          // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
3151          // GPRs.
3152          if (GPR_idx != NumGPRs)
3153            ++GPR_idx;
3154          if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
3155              !isPPC64)  // PPC64 has 64-bit GPR's obviously :)
3156            ++GPR_idx;
3157        }
3158      } else {
3159        LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3160                         isPPC64, isTailCall, false, MemOpChains,
3161                         TailCallArguments, dl);
3162      }
3163      if (isPPC64)
3164        ArgOffset += 8;
3165      else
3166        ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
3167      break;
3168    case MVT::v4f32:
3169    case MVT::v4i32:
3170    case MVT::v8i16:
3171    case MVT::v16i8:
3172      if (isVarArg) {
3173        // These go aligned on the stack, or in the corresponding R registers
3174        // when within range.  The Darwin PPC ABI doc claims they also go in
3175        // V registers; in fact gcc does this only for arguments that are
3176        // prototyped, not for those that match the ...  We do it for all
3177        // arguments, seems to work.
3178        while (ArgOffset % 16 !=0) {
3179          ArgOffset += PtrByteSize;
3180          if (GPR_idx != NumGPRs)
3181            GPR_idx++;
3182        }
3183        // We could elide this store in the case where the object fits
3184        // entirely in R registers.  Maybe later.
3185        PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3186                            DAG.getConstant(ArgOffset, PtrVT));
3187        SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3188                                     MachinePointerInfo(), false, false, 0);
3189        MemOpChains.push_back(Store);
3190        if (VR_idx != NumVRs) {
3191          SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
3192                                     MachinePointerInfo(),
3193                                     false, false, 0);
3194          MemOpChains.push_back(Load.getValue(1));
3195          RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
3196        }
3197        ArgOffset += 16;
3198        for (unsigned i=0; i<16; i+=PtrByteSize) {
3199          if (GPR_idx == NumGPRs)
3200            break;
3201          SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3202                                  DAG.getConstant(i, PtrVT));
3203          SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
3204                                     false, false, 0);
3205          MemOpChains.push_back(Load.getValue(1));
3206          RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3207        }
3208        break;
3209      }
3210
3211      // Non-varargs Altivec params generally go in registers, but have
3212      // stack space allocated at the end.
3213      if (VR_idx != NumVRs) {
3214        // Doesn't have GPR space allocated.
3215        RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
3216      } else if (nAltivecParamsAtEnd==0) {
3217        // We are emitting Altivec params in order.
3218        LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3219                         isPPC64, isTailCall, true, MemOpChains,
3220                         TailCallArguments, dl);
3221        ArgOffset += 16;
3222      }
3223      break;
3224    }
3225  }
3226  // If all Altivec parameters fit in registers, as they usually do,
3227  // they get stack space following the non-Altivec parameters.  We
3228  // don't track this here because nobody below needs it.
3229  // If there are more Altivec parameters than fit in registers emit
3230  // the stores here.
3231  if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
3232    unsigned j = 0;
3233    // Offset is aligned; skip 1st 12 params which go in V registers.
3234    ArgOffset = ((ArgOffset+15)/16)*16;
3235    ArgOffset += 12*16;
3236    for (unsigned i = 0; i != NumOps; ++i) {
3237      SDValue Arg = OutVals[i];
3238      EVT ArgType = Outs[i].VT;
3239      if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
3240          ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
3241        if (++j > NumVRs) {
3242          SDValue PtrOff;
3243          // We are emitting Altivec params in order.
3244          LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3245                           isPPC64, isTailCall, true, MemOpChains,
3246                           TailCallArguments, dl);
3247          ArgOffset += 16;
3248        }
3249      }
3250    }
3251  }
3252
3253  if (!MemOpChains.empty())
3254    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3255                        &MemOpChains[0], MemOpChains.size());
3256
3257  // Check if this is an indirect call (MTCTR/BCTRL).
3258  // See PrepareCall() for more information about calls through function
3259  // pointers in the 64-bit SVR4 ABI.
3260  if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() &&
3261      !dyn_cast<GlobalAddressSDNode>(Callee) &&
3262      !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3263      !isBLACompatibleAddress(Callee, DAG)) {
3264    // Load r2 into a virtual register and store it to the TOC save area.
3265    SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
3266    // TOC save area offset.
3267    SDValue PtrOff = DAG.getIntPtrConstant(40);
3268    SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3269    Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
3270                         false, false, 0);
3271  }
3272
3273  // On Darwin, R12 must contain the address of an indirect callee.  This does
3274  // not mean the MTCTR instruction must use R12; it's easier to model this as
3275  // an extra parameter, so do that.
3276  if (!isTailCall &&
3277      !dyn_cast<GlobalAddressSDNode>(Callee) &&
3278      !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3279      !isBLACompatibleAddress(Callee, DAG))
3280    RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
3281                                                   PPC::R12), Callee));
3282
3283  // Build a sequence of copy-to-reg nodes chained together with token chain
3284  // and flag operands which copy the outgoing args into the appropriate regs.
3285  SDValue InFlag;
3286  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3287    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3288                             RegsToPass[i].second, InFlag);
3289    InFlag = Chain.getValue(1);
3290  }
3291
3292  if (isTailCall)
3293    PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
3294                    FPOp, true, TailCallArguments);
3295
3296  return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3297                    RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3298                    Ins, InVals);
3299}
3300
3301SDValue
3302PPCTargetLowering::LowerReturn(SDValue Chain,
3303                               CallingConv::ID CallConv, bool isVarArg,
3304                               const SmallVectorImpl<ISD::OutputArg> &Outs,
3305                               const SmallVectorImpl<SDValue> &OutVals,
3306                               DebugLoc dl, SelectionDAG &DAG) const {
3307
3308  SmallVector<CCValAssign, 16> RVLocs;
3309  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
3310                 RVLocs, *DAG.getContext());
3311  CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
3312
3313  // If this is the first return lowered for this function, add the regs to the
3314  // liveout set for the function.
3315  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3316    for (unsigned i = 0; i != RVLocs.size(); ++i)
3317      DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3318  }
3319
3320  SDValue Flag;
3321
3322  // Copy the result values into the output registers.
3323  for (unsigned i = 0; i != RVLocs.size(); ++i) {
3324    CCValAssign &VA = RVLocs[i];
3325    assert(VA.isRegLoc() && "Can only return in registers!");
3326    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3327                             OutVals[i], Flag);
3328    Flag = Chain.getValue(1);
3329  }
3330
3331  if (Flag.getNode())
3332    return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
3333  else
3334    return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
3335}
3336
3337SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
3338                                   const PPCSubtarget &Subtarget) const {
3339  // When we pop the dynamic allocation we need to restore the SP link.
3340  DebugLoc dl = Op.getDebugLoc();
3341
3342  // Get the corect type for pointers.
3343  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3344
3345  // Construct the stack pointer operand.
3346  bool isPPC64 = Subtarget.isPPC64();
3347  unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
3348  SDValue StackPtr = DAG.getRegister(SP, PtrVT);
3349
3350  // Get the operands for the STACKRESTORE.
3351  SDValue Chain = Op.getOperand(0);
3352  SDValue SaveSP = Op.getOperand(1);
3353
3354  // Load the old link SP.
3355  SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
3356                                   MachinePointerInfo(),
3357                                   false, false, 0);
3358
3359  // Restore the stack pointer.
3360  Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
3361
3362  // Store the old link SP.
3363  return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
3364                      false, false, 0);
3365}
3366
3367
3368
3369SDValue
3370PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
3371  MachineFunction &MF = DAG.getMachineFunction();
3372  bool isPPC64 = PPCSubTarget.isPPC64();
3373  bool isDarwinABI = PPCSubTarget.isDarwinABI();
3374  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3375
3376  // Get current frame pointer save index.  The users of this index will be
3377  // primarily DYNALLOC instructions.
3378  PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3379  int RASI = FI->getReturnAddrSaveIndex();
3380
3381  // If the frame pointer save index hasn't been defined yet.
3382  if (!RASI) {
3383    // Find out what the fix offset of the frame pointer save area.
3384    int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
3385    // Allocate the frame index for frame pointer save area.
3386    RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
3387    // Save the result.
3388    FI->setReturnAddrSaveIndex(RASI);
3389  }
3390  return DAG.getFrameIndex(RASI, PtrVT);
3391}
3392
3393SDValue
3394PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
3395  MachineFunction &MF = DAG.getMachineFunction();
3396  bool isPPC64 = PPCSubTarget.isPPC64();
3397  bool isDarwinABI = PPCSubTarget.isDarwinABI();
3398  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3399
3400  // Get current frame pointer save index.  The users of this index will be
3401  // primarily DYNALLOC instructions.
3402  PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3403  int FPSI = FI->getFramePointerSaveIndex();
3404
3405  // If the frame pointer save index hasn't been defined yet.
3406  if (!FPSI) {
3407    // Find out what the fix offset of the frame pointer save area.
3408    int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
3409                                                           isDarwinABI);
3410
3411    // Allocate the frame index for frame pointer save area.
3412    FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
3413    // Save the result.
3414    FI->setFramePointerSaveIndex(FPSI);
3415  }
3416  return DAG.getFrameIndex(FPSI, PtrVT);
3417}
3418
3419SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3420                                         SelectionDAG &DAG,
3421                                         const PPCSubtarget &Subtarget) const {
3422  // Get the inputs.
3423  SDValue Chain = Op.getOperand(0);
3424  SDValue Size  = Op.getOperand(1);
3425  DebugLoc dl = Op.getDebugLoc();
3426
3427  // Get the corect type for pointers.
3428  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3429  // Negate the size.
3430  SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
3431                                  DAG.getConstant(0, PtrVT), Size);
3432  // Construct a node for the frame pointer save index.
3433  SDValue FPSIdx = getFramePointerFrameIndex(DAG);
3434  // Build a DYNALLOC node.
3435  SDValue Ops[3] = { Chain, NegSize, FPSIdx };
3436  SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
3437  return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
3438}
3439
3440/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
3441/// possible.
3442SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3443  // Not FP? Not a fsel.
3444  if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
3445      !Op.getOperand(2).getValueType().isFloatingPoint())
3446    return Op;
3447
3448  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3449
3450  // Cannot handle SETEQ/SETNE.
3451  if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
3452
3453  EVT ResVT = Op.getValueType();
3454  EVT CmpVT = Op.getOperand(0).getValueType();
3455  SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3456  SDValue TV  = Op.getOperand(2), FV  = Op.getOperand(3);
3457  DebugLoc dl = Op.getDebugLoc();
3458
3459  // If the RHS of the comparison is a 0.0, we don't need to do the
3460  // subtraction at all.
3461  if (isFloatingPointZero(RHS))
3462    switch (CC) {
3463    default: break;       // SETUO etc aren't handled by fsel.
3464    case ISD::SETULT:
3465    case ISD::SETLT:
3466      std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
3467    case ISD::SETOGE:
3468    case ISD::SETGE:
3469      if (LHS.getValueType() == MVT::f32)   // Comparison is always 64-bits
3470        LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3471      return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
3472    case ISD::SETUGT:
3473    case ISD::SETGT:
3474      std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
3475    case ISD::SETOLE:
3476    case ISD::SETLE:
3477      if (LHS.getValueType() == MVT::f32)   // Comparison is always 64-bits
3478        LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3479      return DAG.getNode(PPCISD::FSEL, dl, ResVT,
3480                         DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
3481    }
3482
3483  SDValue Cmp;
3484  switch (CC) {
3485  default: break;       // SETUO etc aren't handled by fsel.
3486  case ISD::SETULT:
3487  case ISD::SETLT:
3488    Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3489    if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
3490      Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3491      return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3492  case ISD::SETOGE:
3493  case ISD::SETGE:
3494    Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3495    if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
3496      Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3497      return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3498  case ISD::SETUGT:
3499  case ISD::SETGT:
3500    Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3501    if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
3502      Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3503      return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3504  case ISD::SETOLE:
3505  case ISD::SETLE:
3506    Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3507    if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
3508      Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3509      return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3510  }
3511  return Op;
3512}
3513
3514// FIXME: Split this code up when LegalizeDAGTypes lands.
3515SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
3516                                           DebugLoc dl) const {
3517  assert(Op.getOperand(0).getValueType().isFloatingPoint());
3518  SDValue Src = Op.getOperand(0);
3519  if (Src.getValueType() == MVT::f32)
3520    Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
3521
3522  SDValue Tmp;
3523  switch (Op.getValueType().getSimpleVT().SimpleTy) {
3524  default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
3525  case MVT::i32:
3526    Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
3527                                                         PPCISD::FCTIDZ,
3528                      dl, MVT::f64, Src);
3529    break;
3530  case MVT::i64:
3531    Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
3532    break;
3533  }
3534
3535  // Convert the FP value to an int value through memory.
3536  SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
3537
3538  // Emit a store to the stack slot.
3539  SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
3540                               MachinePointerInfo(), false, false, 0);
3541
3542  // Result is a load from the stack slot.  If loading 4 bytes, make sure to
3543  // add in a bias.
3544  if (Op.getValueType() == MVT::i32)
3545    FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
3546                        DAG.getConstant(4, FIPtr.getValueType()));
3547  return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(),
3548                     false, false, 0);
3549}
3550
3551SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op,
3552                                           SelectionDAG &DAG) const {
3553  DebugLoc dl = Op.getDebugLoc();
3554  // Don't handle ppc_fp128 here; let it be lowered to a libcall.
3555  if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
3556    return SDValue();
3557
3558  if (Op.getOperand(0).getValueType() == MVT::i64) {
3559    SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0));
3560    SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
3561    if (Op.getValueType() == MVT::f32)
3562      FP = DAG.getNode(ISD::FP_ROUND, dl,
3563                       MVT::f32, FP, DAG.getIntPtrConstant(0));
3564    return FP;
3565  }
3566
3567  assert(Op.getOperand(0).getValueType() == MVT::i32 &&
3568         "Unhandled SINT_TO_FP type in custom expander!");
3569  // Since we only generate this in 64-bit mode, we can take advantage of
3570  // 64-bit registers.  In particular, sign extend the input value into the
3571  // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
3572  // then lfd it and fcfid it.
3573  MachineFunction &MF = DAG.getMachineFunction();
3574  MachineFrameInfo *FrameInfo = MF.getFrameInfo();
3575  int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
3576  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3577  SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3578
3579  SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
3580                                Op.getOperand(0));
3581
3582  // STD the extended value into the stack slot.
3583  MachineMemOperand *MMO =
3584    MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
3585                            MachineMemOperand::MOStore, 8, 8);
3586  SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
3587  SDValue Store =
3588    DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),
3589                            Ops, 4, MVT::i64, MMO);
3590  // Load the value as a double.
3591  SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(),
3592                           false, false, 0);
3593
3594  // FCFID it and return it.
3595  SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
3596  if (Op.getValueType() == MVT::f32)
3597    FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
3598  return FP;
3599}
3600
3601SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3602                                            SelectionDAG &DAG) const {
3603  DebugLoc dl = Op.getDebugLoc();
3604  /*
3605   The rounding mode is in bits 30:31 of FPSR, and has the following
3606   settings:
3607     00 Round to nearest
3608     01 Round to 0
3609     10 Round to +inf
3610     11 Round to -inf
3611
3612  FLT_ROUNDS, on the other hand, expects the following:
3613    -1 Undefined
3614     0 Round to 0
3615     1 Round to nearest
3616     2 Round to +inf
3617     3 Round to -inf
3618
3619  To perform the conversion, we do:
3620    ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
3621  */
3622
3623  MachineFunction &MF = DAG.getMachineFunction();
3624  EVT VT = Op.getValueType();
3625  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3626  std::vector<EVT> NodeTys;
3627  SDValue MFFSreg, InFlag;
3628
3629  // Save FP Control Word to register
3630  NodeTys.push_back(MVT::f64);    // return register
3631  NodeTys.push_back(MVT::Glue);   // unused in this context
3632  SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3633
3634  // Save FP register to stack slot
3635  int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
3636  SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
3637  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
3638                               StackSlot, MachinePointerInfo(), false, false,0);
3639
3640  // Load FP Control Word from low 32 bits of stack slot.
3641  SDValue Four = DAG.getConstant(4, PtrVT);
3642  SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
3643  SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
3644                            false, false, 0);
3645
3646  // Transform as necessary
3647  SDValue CWD1 =
3648    DAG.getNode(ISD::AND, dl, MVT::i32,
3649                CWD, DAG.getConstant(3, MVT::i32));
3650  SDValue CWD2 =
3651    DAG.getNode(ISD::SRL, dl, MVT::i32,
3652                DAG.getNode(ISD::AND, dl, MVT::i32,
3653                            DAG.getNode(ISD::XOR, dl, MVT::i32,
3654                                        CWD, DAG.getConstant(3, MVT::i32)),
3655                            DAG.getConstant(3, MVT::i32)),
3656                DAG.getConstant(1, MVT::i32));
3657
3658  SDValue RetVal =
3659    DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
3660
3661  return DAG.getNode((VT.getSizeInBits() < 16 ?
3662                      ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3663}
3664
3665SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3666  EVT VT = Op.getValueType();
3667  unsigned BitWidth = VT.getSizeInBits();
3668  DebugLoc dl = Op.getDebugLoc();
3669  assert(Op.getNumOperands() == 3 &&
3670         VT == Op.getOperand(1).getValueType() &&
3671         "Unexpected SHL!");
3672
3673  // Expand into a bunch of logical ops.  Note that these ops
3674  // depend on the PPC behavior for oversized shift amounts.
3675  SDValue Lo = Op.getOperand(0);
3676  SDValue Hi = Op.getOperand(1);
3677  SDValue Amt = Op.getOperand(2);
3678  EVT AmtVT = Amt.getValueType();
3679
3680  SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3681                             DAG.getConstant(BitWidth, AmtVT), Amt);
3682  SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3683  SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3684  SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3685  SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3686                             DAG.getConstant(-BitWidth, AmtVT));
3687  SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3688  SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3689  SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3690  SDValue OutOps[] = { OutLo, OutHi };
3691  return DAG.getMergeValues(OutOps, 2, dl);
3692}
3693
3694SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3695  EVT VT = Op.getValueType();
3696  DebugLoc dl = Op.getDebugLoc();
3697  unsigned BitWidth = VT.getSizeInBits();
3698  assert(Op.getNumOperands() == 3 &&
3699         VT == Op.getOperand(1).getValueType() &&
3700         "Unexpected SRL!");
3701
3702  // Expand into a bunch of logical ops.  Note that these ops
3703  // depend on the PPC behavior for oversized shift amounts.
3704  SDValue Lo = Op.getOperand(0);
3705  SDValue Hi = Op.getOperand(1);
3706  SDValue Amt = Op.getOperand(2);
3707  EVT AmtVT = Amt.getValueType();
3708
3709  SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3710                             DAG.getConstant(BitWidth, AmtVT), Amt);
3711  SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3712  SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3713  SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3714  SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3715                             DAG.getConstant(-BitWidth, AmtVT));
3716  SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3717  SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3718  SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3719  SDValue OutOps[] = { OutLo, OutHi };
3720  return DAG.getMergeValues(OutOps, 2, dl);
3721}
3722
3723SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
3724  DebugLoc dl = Op.getDebugLoc();
3725  EVT VT = Op.getValueType();
3726  unsigned BitWidth = VT.getSizeInBits();
3727  assert(Op.getNumOperands() == 3 &&
3728         VT == Op.getOperand(1).getValueType() &&
3729         "Unexpected SRA!");
3730
3731  // Expand into a bunch of logical ops, followed by a select_cc.
3732  SDValue Lo = Op.getOperand(0);
3733  SDValue Hi = Op.getOperand(1);
3734  SDValue Amt = Op.getOperand(2);
3735  EVT AmtVT = Amt.getValueType();
3736
3737  SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3738                             DAG.getConstant(BitWidth, AmtVT), Amt);
3739  SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3740  SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3741  SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3742  SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3743                             DAG.getConstant(-BitWidth, AmtVT));
3744  SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3745  SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3746  SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3747                                  Tmp4, Tmp6, ISD::SETLE);
3748  SDValue OutOps[] = { OutLo, OutHi };
3749  return DAG.getMergeValues(OutOps, 2, dl);
3750}
3751
3752//===----------------------------------------------------------------------===//
3753// Vector related lowering.
3754//
3755
3756/// BuildSplatI - Build a canonical splati of Val with an element size of
3757/// SplatSize.  Cast the result to VT.
3758static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
3759                             SelectionDAG &DAG, DebugLoc dl) {
3760  assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3761
3762  static const EVT VTys[] = { // canonical VT to use for each size.
3763    MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3764  };
3765
3766  EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3767
3768  // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3769  if (Val == -1)
3770    SplatSize = 1;
3771
3772  EVT CanonicalVT = VTys[SplatSize-1];
3773
3774  // Build a canonical splat for this value.
3775  SDValue Elt = DAG.getConstant(Val, MVT::i32);
3776  SmallVector<SDValue, 8> Ops;
3777  Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3778  SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3779                              &Ops[0], Ops.size());
3780  return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
3781}
3782
3783/// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3784/// specified intrinsic ID.
3785static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3786                                SelectionDAG &DAG, DebugLoc dl,
3787                                EVT DestVT = MVT::Other) {
3788  if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3789  return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3790                     DAG.getConstant(IID, MVT::i32), LHS, RHS);
3791}
3792
3793/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3794/// specified intrinsic ID.
3795static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3796                                SDValue Op2, SelectionDAG &DAG,
3797                                DebugLoc dl, EVT DestVT = MVT::Other) {
3798  if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3799  return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3800                     DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3801}
3802
3803
3804/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3805/// amount.  The result has the specified value type.
3806static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3807                             EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3808  // Force LHS/RHS to be the right type.
3809  LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
3810  RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
3811
3812  int Ops[16];
3813  for (unsigned i = 0; i != 16; ++i)
3814    Ops[i] = i + Amt;
3815  SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
3816  return DAG.getNode(ISD::BITCAST, dl, VT, T);
3817}
3818
3819// If this is a case we can't handle, return null and let the default
3820// expansion code take care of it.  If we CAN select this case, and if it
3821// selects to a single instruction, return Op.  Otherwise, if we can codegen
3822// this case more efficiently than a constant pool load, lower it to the
3823// sequence of ops that should be used.
3824SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
3825                                             SelectionDAG &DAG) const {
3826  DebugLoc dl = Op.getDebugLoc();
3827  BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3828  assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
3829
3830  // Check if this is a splat of a constant value.
3831  APInt APSplatBits, APSplatUndef;
3832  unsigned SplatBitSize;
3833  bool HasAnyUndefs;
3834  if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
3835                             HasAnyUndefs, 0, true) || SplatBitSize > 32)
3836    return SDValue();
3837
3838  unsigned SplatBits = APSplatBits.getZExtValue();
3839  unsigned SplatUndef = APSplatUndef.getZExtValue();
3840  unsigned SplatSize = SplatBitSize / 8;
3841
3842  // First, handle single instruction cases.
3843
3844  // All zeros?
3845  if (SplatBits == 0) {
3846    // Canonicalize all zero vectors to be v4i32.
3847    if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3848      SDValue Z = DAG.getConstant(0, MVT::i32);
3849      Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
3850      Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
3851    }
3852    return Op;
3853  }
3854
3855  // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3856  int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
3857                    (32-SplatBitSize));
3858  if (SextVal >= -16 && SextVal <= 15)
3859    return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
3860
3861
3862  // Two instruction sequences.
3863
3864  // If this value is in the range [-32,30] and is even, use:
3865  //    tmp = VSPLTI[bhw], result = add tmp, tmp
3866  if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3867    SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
3868    Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
3869    return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3870  }
3871
3872  // If this is 0x8000_0000 x 4, turn into vspltisw + vslw.  If it is
3873  // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000).  This is important
3874  // for fneg/fabs.
3875  if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3876    // Make -1 and vspltisw -1:
3877    SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
3878
3879    // Make the VSLW intrinsic, computing 0x8000_0000.
3880    SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3881                                   OnesV, DAG, dl);
3882
3883    // xor by OnesV to invert it.
3884    Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
3885    return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3886  }
3887
3888  // Check to see if this is a wide variety of vsplti*, binop self cases.
3889  static const signed char SplatCsts[] = {
3890    -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3891    -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3892  };
3893
3894  for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3895    // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3896    // cases which are ambiguous (e.g. formation of 0x8000_0000).  'vsplti -1'
3897    int i = SplatCsts[idx];
3898
3899    // Figure out what shift amount will be used by altivec if shifted by i in
3900    // this splat size.
3901    unsigned TypeShiftAmt = i & (SplatBitSize-1);
3902
3903    // vsplti + shl self.
3904    if (SextVal == (i << (int)TypeShiftAmt)) {
3905      SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3906      static const unsigned IIDs[] = { // Intrinsic to use for each size.
3907        Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3908        Intrinsic::ppc_altivec_vslw
3909      };
3910      Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3911      return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3912    }
3913
3914    // vsplti + srl self.
3915    if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3916      SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3917      static const unsigned IIDs[] = { // Intrinsic to use for each size.
3918        Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3919        Intrinsic::ppc_altivec_vsrw
3920      };
3921      Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3922      return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3923    }
3924
3925    // vsplti + sra self.
3926    if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3927      SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3928      static const unsigned IIDs[] = { // Intrinsic to use for each size.
3929        Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3930        Intrinsic::ppc_altivec_vsraw
3931      };
3932      Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3933      return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3934    }
3935
3936    // vsplti + rol self.
3937    if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3938                         ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3939      SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3940      static const unsigned IIDs[] = { // Intrinsic to use for each size.
3941        Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3942        Intrinsic::ppc_altivec_vrlw
3943      };
3944      Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3945      return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3946    }
3947
3948    // t = vsplti c, result = vsldoi t, t, 1
3949    if (SextVal == ((i << 8) | (i < 0 ? 0xFF : 0))) {
3950      SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3951      return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
3952    }
3953    // t = vsplti c, result = vsldoi t, t, 2
3954    if (SextVal == ((i << 16) | (i < 0 ? 0xFFFF : 0))) {
3955      SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3956      return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
3957    }
3958    // t = vsplti c, result = vsldoi t, t, 3
3959    if (SextVal == ((i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
3960      SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3961      return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
3962    }
3963  }
3964
3965  // Three instruction sequences.
3966
3967  // Odd, in range [17,31]:  (vsplti C)-(vsplti -16).
3968  if (SextVal >= 0 && SextVal <= 31) {
3969    SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
3970    SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3971    LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
3972    return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
3973  }
3974  // Odd, in range [-31,-17]:  (vsplti C)+(vsplti -16).
3975  if (SextVal >= -31 && SextVal <= 0) {
3976    SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
3977    SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3978    LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
3979    return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
3980  }
3981
3982  return SDValue();
3983}
3984
3985/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3986/// the specified operations to build the shuffle.
3987static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3988                                      SDValue RHS, SelectionDAG &DAG,
3989                                      DebugLoc dl) {
3990  unsigned OpNum = (PFEntry >> 26) & 0x0F;
3991  unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3992  unsigned RHSID = (PFEntry >>  0) & ((1 << 13)-1);
3993
3994  enum {
3995    OP_COPY = 0,  // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3996    OP_VMRGHW,
3997    OP_VMRGLW,
3998    OP_VSPLTISW0,
3999    OP_VSPLTISW1,
4000    OP_VSPLTISW2,
4001    OP_VSPLTISW3,
4002    OP_VSLDOI4,
4003    OP_VSLDOI8,
4004    OP_VSLDOI12
4005  };
4006
4007  if (OpNum == OP_COPY) {
4008    if (LHSID == (1*9+2)*9+3) return LHS;
4009    assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4010    return RHS;
4011  }
4012
4013  SDValue OpLHS, OpRHS;
4014  OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4015  OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4016
4017  int ShufIdxs[16];
4018  switch (OpNum) {
4019  default: llvm_unreachable("Unknown i32 permute!");
4020  case OP_VMRGHW:
4021    ShufIdxs[ 0] =  0; ShufIdxs[ 1] =  1; ShufIdxs[ 2] =  2; ShufIdxs[ 3] =  3;
4022    ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
4023    ShufIdxs[ 8] =  4; ShufIdxs[ 9] =  5; ShufIdxs[10] =  6; ShufIdxs[11] =  7;
4024    ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
4025    break;
4026  case OP_VMRGLW:
4027    ShufIdxs[ 0] =  8; ShufIdxs[ 1] =  9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
4028    ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
4029    ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
4030    ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
4031    break;
4032  case OP_VSPLTISW0:
4033    for (unsigned i = 0; i != 16; ++i)
4034      ShufIdxs[i] = (i&3)+0;
4035    break;
4036  case OP_VSPLTISW1:
4037    for (unsigned i = 0; i != 16; ++i)
4038      ShufIdxs[i] = (i&3)+4;
4039    break;
4040  case OP_VSPLTISW2:
4041    for (unsigned i = 0; i != 16; ++i)
4042      ShufIdxs[i] = (i&3)+8;
4043    break;
4044  case OP_VSPLTISW3:
4045    for (unsigned i = 0; i != 16; ++i)
4046      ShufIdxs[i] = (i&3)+12;
4047    break;
4048  case OP_VSLDOI4:
4049    return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
4050  case OP_VSLDOI8:
4051    return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
4052  case OP_VSLDOI12:
4053    return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
4054  }
4055  EVT VT = OpLHS.getValueType();
4056  OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
4057  OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
4058  SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
4059  return DAG.getNode(ISD::BITCAST, dl, VT, T);
4060}
4061
4062/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE.  If this
4063/// is a shuffle we can handle in a single instruction, return it.  Otherwise,
4064/// return the code it can be lowered into.  Worst case, it can always be
4065/// lowered into a vperm.
4066SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4067                                               SelectionDAG &DAG) const {
4068  DebugLoc dl = Op.getDebugLoc();
4069  SDValue V1 = Op.getOperand(0);
4070  SDValue V2 = Op.getOperand(1);
4071  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4072  EVT VT = Op.getValueType();
4073
4074  // Cases that are handled by instructions that take permute immediates
4075  // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
4076  // selected by the instruction selector.
4077  if (V2.getOpcode() == ISD::UNDEF) {
4078    if (PPC::isSplatShuffleMask(SVOp, 1) ||
4079        PPC::isSplatShuffleMask(SVOp, 2) ||
4080        PPC::isSplatShuffleMask(SVOp, 4) ||
4081        PPC::isVPKUWUMShuffleMask(SVOp, true) ||
4082        PPC::isVPKUHUMShuffleMask(SVOp, true) ||
4083        PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
4084        PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
4085        PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
4086        PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
4087        PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
4088        PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
4089        PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
4090      return Op;
4091    }
4092  }
4093
4094  // Altivec has a variety of "shuffle immediates" that take two vector inputs
4095  // and produce a fixed permutation.  If any of these match, do not lower to
4096  // VPERM.
4097  if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
4098      PPC::isVPKUHUMShuffleMask(SVOp, false) ||
4099      PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
4100      PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
4101      PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
4102      PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
4103      PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
4104      PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
4105      PPC::isVMRGHShuffleMask(SVOp, 4, false))
4106    return Op;
4107
4108  // Check to see if this is a shuffle of 4-byte values.  If so, we can use our
4109  // perfect shuffle table to emit an optimal matching sequence.
4110  SmallVector<int, 16> PermMask;
4111  SVOp->getMask(PermMask);
4112
4113  unsigned PFIndexes[4];
4114  bool isFourElementShuffle = true;
4115  for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
4116    unsigned EltNo = 8;   // Start out undef.
4117    for (unsigned j = 0; j != 4; ++j) {  // Intra-element byte.
4118      if (PermMask[i*4+j] < 0)
4119        continue;   // Undef, ignore it.
4120
4121      unsigned ByteSource = PermMask[i*4+j];
4122      if ((ByteSource & 3) != j) {
4123        isFourElementShuffle = false;
4124        break;
4125      }
4126
4127      if (EltNo == 8) {
4128        EltNo = ByteSource/4;
4129      } else if (EltNo != ByteSource/4) {
4130        isFourElementShuffle = false;
4131        break;
4132      }
4133    }
4134    PFIndexes[i] = EltNo;
4135  }
4136
4137  // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
4138  // perfect shuffle vector to determine if it is cost effective to do this as
4139  // discrete instructions, or whether we should use a vperm.
4140  if (isFourElementShuffle) {
4141    // Compute the index in the perfect shuffle table.
4142    unsigned PFTableIndex =
4143      PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4144
4145    unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4146    unsigned Cost  = (PFEntry >> 30);
4147
4148    // Determining when to avoid vperm is tricky.  Many things affect the cost
4149    // of vperm, particularly how many times the perm mask needs to be computed.
4150    // For example, if the perm mask can be hoisted out of a loop or is already
4151    // used (perhaps because there are multiple permutes with the same shuffle
4152    // mask?) the vperm has a cost of 1.  OTOH, hoisting the permute mask out of
4153    // the loop requires an extra register.
4154    //
4155    // As a compromise, we only emit discrete instructions if the shuffle can be
4156    // generated in 3 or fewer operations.  When we have loop information
4157    // available, if this block is within a loop, we should avoid using vperm
4158    // for 3-operation perms and use a constant pool load instead.
4159    if (Cost < 3)
4160      return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4161  }
4162
4163  // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
4164  // vector that will get spilled to the constant pool.
4165  if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
4166
4167  // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
4168  // that it is in input element units, not in bytes.  Convert now.
4169  EVT EltVT = V1.getValueType().getVectorElementType();
4170  unsigned BytesPerElement = EltVT.getSizeInBits()/8;
4171
4172  SmallVector<SDValue, 16> ResultMask;
4173  for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4174    unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
4175
4176    for (unsigned j = 0; j != BytesPerElement; ++j)
4177      ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
4178                                           MVT::i32));
4179  }
4180
4181  SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
4182                                    &ResultMask[0], ResultMask.size());
4183  return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
4184}
4185
4186/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
4187/// altivec comparison.  If it is, return true and fill in Opc/isDot with
4188/// information about the intrinsic.
4189static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
4190                                  bool &isDot) {
4191  unsigned IntrinsicID =
4192    cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
4193  CompareOpc = -1;
4194  isDot = false;
4195  switch (IntrinsicID) {
4196  default: return false;
4197    // Comparison predicates.
4198  case Intrinsic::ppc_altivec_vcmpbfp_p:  CompareOpc = 966; isDot = 1; break;
4199  case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
4200  case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc =   6; isDot = 1; break;
4201  case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc =  70; isDot = 1; break;
4202  case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
4203  case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
4204  case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
4205  case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
4206  case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
4207  case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
4208  case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
4209  case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
4210  case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
4211
4212    // Normal Comparisons.
4213  case Intrinsic::ppc_altivec_vcmpbfp:    CompareOpc = 966; isDot = 0; break;
4214  case Intrinsic::ppc_altivec_vcmpeqfp:   CompareOpc = 198; isDot = 0; break;
4215  case Intrinsic::ppc_altivec_vcmpequb:   CompareOpc =   6; isDot = 0; break;
4216  case Intrinsic::ppc_altivec_vcmpequh:   CompareOpc =  70; isDot = 0; break;
4217  case Intrinsic::ppc_altivec_vcmpequw:   CompareOpc = 134; isDot = 0; break;
4218  case Intrinsic::ppc_altivec_vcmpgefp:   CompareOpc = 454; isDot = 0; break;
4219  case Intrinsic::ppc_altivec_vcmpgtfp:   CompareOpc = 710; isDot = 0; break;
4220  case Intrinsic::ppc_altivec_vcmpgtsb:   CompareOpc = 774; isDot = 0; break;
4221  case Intrinsic::ppc_altivec_vcmpgtsh:   CompareOpc = 838; isDot = 0; break;
4222  case Intrinsic::ppc_altivec_vcmpgtsw:   CompareOpc = 902; isDot = 0; break;
4223  case Intrinsic::ppc_altivec_vcmpgtub:   CompareOpc = 518; isDot = 0; break;
4224  case Intrinsic::ppc_altivec_vcmpgtuh:   CompareOpc = 582; isDot = 0; break;
4225  case Intrinsic::ppc_altivec_vcmpgtuw:   CompareOpc = 646; isDot = 0; break;
4226  }
4227  return true;
4228}
4229
4230/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
4231/// lower, do it, otherwise return null.
4232SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
4233                                                   SelectionDAG &DAG) const {
4234  // If this is a lowered altivec predicate compare, CompareOpc is set to the
4235  // opcode number of the comparison.
4236  DebugLoc dl = Op.getDebugLoc();
4237  int CompareOpc;
4238  bool isDot;
4239  if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
4240    return SDValue();    // Don't custom lower most intrinsics.
4241
4242  // If this is a non-dot comparison, make the VCMP node and we are done.
4243  if (!isDot) {
4244    SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
4245                              Op.getOperand(1), Op.getOperand(2),
4246                              DAG.getConstant(CompareOpc, MVT::i32));
4247    return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
4248  }
4249
4250  // Create the PPCISD altivec 'dot' comparison node.
4251  SDValue Ops[] = {
4252    Op.getOperand(2),  // LHS
4253    Op.getOperand(3),  // RHS
4254    DAG.getConstant(CompareOpc, MVT::i32)
4255  };
4256  std::vector<EVT> VTs;
4257  VTs.push_back(Op.getOperand(2).getValueType());
4258  VTs.push_back(MVT::Glue);
4259  SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4260
4261  // Now that we have the comparison, emit a copy from the CR to a GPR.
4262  // This is flagged to the above dot comparison.
4263  SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
4264                                DAG.getRegister(PPC::CR6, MVT::i32),
4265                                CompNode.getValue(1));
4266
4267  // Unpack the result based on how the target uses it.
4268  unsigned BitNo;   // Bit # of CR6.
4269  bool InvertBit;   // Invert result?
4270  switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
4271  default:  // Can't happen, don't crash on invalid number though.
4272  case 0:   // Return the value of the EQ bit of CR6.
4273    BitNo = 0; InvertBit = false;
4274    break;
4275  case 1:   // Return the inverted value of the EQ bit of CR6.
4276    BitNo = 0; InvertBit = true;
4277    break;
4278  case 2:   // Return the value of the LT bit of CR6.
4279    BitNo = 2; InvertBit = false;
4280    break;
4281  case 3:   // Return the inverted value of the LT bit of CR6.
4282    BitNo = 2; InvertBit = true;
4283    break;
4284  }
4285
4286  // Shift the bit into the low position.
4287  Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
4288                      DAG.getConstant(8-(3-BitNo), MVT::i32));
4289  // Isolate the bit.
4290  Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
4291                      DAG.getConstant(1, MVT::i32));
4292
4293  // If we are supposed to, toggle the bit.
4294  if (InvertBit)
4295    Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
4296                        DAG.getConstant(1, MVT::i32));
4297  return Flags;
4298}
4299
4300SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
4301                                                   SelectionDAG &DAG) const {
4302  DebugLoc dl = Op.getDebugLoc();
4303  // Create a stack slot that is 16-byte aligned.
4304  MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4305  int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
4306  EVT PtrVT = getPointerTy();
4307  SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4308
4309  // Store the input value into Value#0 of the stack slot.
4310  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
4311                               Op.getOperand(0), FIdx, MachinePointerInfo(),
4312                               false, false, 0);
4313  // Load it out.
4314  return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
4315                     false, false, 0);
4316}
4317
4318SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
4319  DebugLoc dl = Op.getDebugLoc();
4320  if (Op.getValueType() == MVT::v4i32) {
4321    SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4322
4323    SDValue Zero  = BuildSplatI(  0, 1, MVT::v4i32, DAG, dl);
4324    SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
4325
4326    SDValue RHSSwap =   // = vrlw RHS, 16
4327      BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
4328
4329    // Shrinkify inputs to v8i16.
4330    LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
4331    RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
4332    RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
4333
4334    // Low parts multiplied together, generating 32-bit results (we ignore the
4335    // top parts).
4336    SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
4337                                        LHS, RHS, DAG, dl, MVT::v4i32);
4338
4339    SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
4340                                      LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
4341    // Shift the high parts up 16 bits.
4342    HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
4343                              Neg16, DAG, dl);
4344    return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
4345  } else if (Op.getValueType() == MVT::v8i16) {
4346    SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4347
4348    SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
4349
4350    return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
4351                            LHS, RHS, Zero, DAG, dl);
4352  } else if (Op.getValueType() == MVT::v16i8) {
4353    SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4354
4355    // Multiply the even 8-bit parts, producing 16-bit sums.
4356    SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
4357                                           LHS, RHS, DAG, dl, MVT::v8i16);
4358    EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
4359
4360    // Multiply the odd 8-bit parts, producing 16-bit sums.
4361    SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
4362                                          LHS, RHS, DAG, dl, MVT::v8i16);
4363    OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
4364
4365    // Merge the results together.
4366    int Ops[16];
4367    for (unsigned i = 0; i != 8; ++i) {
4368      Ops[i*2  ] = 2*i+1;
4369      Ops[i*2+1] = 2*i+1+16;
4370    }
4371    return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
4372  } else {
4373    llvm_unreachable("Unknown mul to lower!");
4374  }
4375}
4376
4377/// LowerOperation - Provide custom lowering hooks for some operations.
4378///
4379SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4380  switch (Op.getOpcode()) {
4381  default: llvm_unreachable("Wasn't expecting to be able to lower this!");
4382  case ISD::ConstantPool:       return LowerConstantPool(Op, DAG);
4383  case ISD::BlockAddress:       return LowerBlockAddress(Op, DAG);
4384  case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
4385  case ISD::GlobalTLSAddress:   llvm_unreachable("TLS not implemented for PPC");
4386  case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
4387  case ISD::SETCC:              return LowerSETCC(Op, DAG);
4388  case ISD::TRAMPOLINE:         return LowerTRAMPOLINE(Op, DAG);
4389  case ISD::VASTART:
4390    return LowerVASTART(Op, DAG, PPCSubTarget);
4391
4392  case ISD::VAARG:
4393    return LowerVAARG(Op, DAG, PPCSubTarget);
4394
4395  case ISD::STACKRESTORE:       return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
4396  case ISD::DYNAMIC_STACKALLOC:
4397    return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
4398
4399  case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
4400  case ISD::FP_TO_UINT:
4401  case ISD::FP_TO_SINT:         return LowerFP_TO_INT(Op, DAG,
4402                                                       Op.getDebugLoc());
4403  case ISD::SINT_TO_FP:         return LowerSINT_TO_FP(Op, DAG);
4404  case ISD::FLT_ROUNDS_:        return LowerFLT_ROUNDS_(Op, DAG);
4405
4406  // Lower 64-bit shifts.
4407  case ISD::SHL_PARTS:          return LowerSHL_PARTS(Op, DAG);
4408  case ISD::SRL_PARTS:          return LowerSRL_PARTS(Op, DAG);
4409  case ISD::SRA_PARTS:          return LowerSRA_PARTS(Op, DAG);
4410
4411  // Vector-related lowering.
4412  case ISD::BUILD_VECTOR:       return LowerBUILD_VECTOR(Op, DAG);
4413  case ISD::VECTOR_SHUFFLE:     return LowerVECTOR_SHUFFLE(Op, DAG);
4414  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4415  case ISD::SCALAR_TO_VECTOR:   return LowerSCALAR_TO_VECTOR(Op, DAG);
4416  case ISD::MUL:                return LowerMUL(Op, DAG);
4417
4418  // Frame & Return address.
4419  case ISD::RETURNADDR:         return LowerRETURNADDR(Op, DAG);
4420  case ISD::FRAMEADDR:          return LowerFRAMEADDR(Op, DAG);
4421  }
4422  return SDValue();
4423}
4424
4425void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
4426                                           SmallVectorImpl<SDValue>&Results,
4427                                           SelectionDAG &DAG) const {
4428  DebugLoc dl = N->getDebugLoc();
4429  switch (N->getOpcode()) {
4430  default:
4431    assert(false && "Do not know how to custom type legalize this operation!");
4432    return;
4433  case ISD::FP_ROUND_INREG: {
4434    assert(N->getValueType(0) == MVT::ppcf128);
4435    assert(N->getOperand(0).getValueType() == MVT::ppcf128);
4436    SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4437                             MVT::f64, N->getOperand(0),
4438                             DAG.getIntPtrConstant(0));
4439    SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4440                             MVT::f64, N->getOperand(0),
4441                             DAG.getIntPtrConstant(1));
4442
4443    // This sequence changes FPSCR to do round-to-zero, adds the two halves
4444    // of the long double, and puts FPSCR back the way it was.  We do not
4445    // actually model FPSCR.
4446    std::vector<EVT> NodeTys;
4447    SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
4448
4449    NodeTys.push_back(MVT::f64);   // Return register
4450    NodeTys.push_back(MVT::Glue);    // Returns a flag for later insns
4451    Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4452    MFFSreg = Result.getValue(0);
4453    InFlag = Result.getValue(1);
4454
4455    NodeTys.clear();
4456    NodeTys.push_back(MVT::Glue);   // Returns a flag
4457    Ops[0] = DAG.getConstant(31, MVT::i32);
4458    Ops[1] = InFlag;
4459    Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
4460    InFlag = Result.getValue(0);
4461
4462    NodeTys.clear();
4463    NodeTys.push_back(MVT::Glue);   // Returns a flag
4464    Ops[0] = DAG.getConstant(30, MVT::i32);
4465    Ops[1] = InFlag;
4466    Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
4467    InFlag = Result.getValue(0);
4468
4469    NodeTys.clear();
4470    NodeTys.push_back(MVT::f64);    // result of add
4471    NodeTys.push_back(MVT::Glue);   // Returns a flag
4472    Ops[0] = Lo;
4473    Ops[1] = Hi;
4474    Ops[2] = InFlag;
4475    Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
4476    FPreg = Result.getValue(0);
4477    InFlag = Result.getValue(1);
4478
4479    NodeTys.clear();
4480    NodeTys.push_back(MVT::f64);
4481    Ops[0] = DAG.getConstant(1, MVT::i32);
4482    Ops[1] = MFFSreg;
4483    Ops[2] = FPreg;
4484    Ops[3] = InFlag;
4485    Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
4486    FPreg = Result.getValue(0);
4487
4488    // We know the low half is about to be thrown away, so just use something
4489    // convenient.
4490    Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
4491                                FPreg, FPreg));
4492    return;
4493  }
4494  case ISD::FP_TO_SINT:
4495    Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
4496    return;
4497  }
4498}
4499
4500
4501//===----------------------------------------------------------------------===//
4502//  Other Lowering Code
4503//===----------------------------------------------------------------------===//
4504
4505MachineBasicBlock *
4506PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4507                                    bool is64bit, unsigned BinOpcode) const {
4508  // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4509  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4510
4511  const BasicBlock *LLVM_BB = BB->getBasicBlock();
4512  MachineFunction *F = BB->getParent();
4513  MachineFunction::iterator It = BB;
4514  ++It;
4515
4516  unsigned dest = MI->getOperand(0).getReg();
4517  unsigned ptrA = MI->getOperand(1).getReg();
4518  unsigned ptrB = MI->getOperand(2).getReg();
4519  unsigned incr = MI->getOperand(3).getReg();
4520  DebugLoc dl = MI->getDebugLoc();
4521
4522  MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4523  MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4524  F->insert(It, loopMBB);
4525  F->insert(It, exitMBB);
4526  exitMBB->splice(exitMBB->begin(), BB,
4527                  llvm::next(MachineBasicBlock::iterator(MI)),
4528                  BB->end());
4529  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4530
4531  MachineRegisterInfo &RegInfo = F->getRegInfo();
4532  unsigned TmpReg = (!BinOpcode) ? incr :
4533    RegInfo.createVirtualRegister(
4534       is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4535                 (const TargetRegisterClass *) &PPC::GPRCRegClass);
4536
4537  //  thisMBB:
4538  //   ...
4539  //   fallthrough --> loopMBB
4540  BB->addSuccessor(loopMBB);
4541
4542  //  loopMBB:
4543  //   l[wd]arx dest, ptr
4544  //   add r0, dest, incr
4545  //   st[wd]cx. r0, ptr
4546  //   bne- loopMBB
4547  //   fallthrough --> exitMBB
4548  BB = loopMBB;
4549  BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4550    .addReg(ptrA).addReg(ptrB);
4551  if (BinOpcode)
4552    BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
4553  BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4554    .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
4555  BuildMI(BB, dl, TII->get(PPC::BCC))
4556    .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4557  BB->addSuccessor(loopMBB);
4558  BB->addSuccessor(exitMBB);
4559
4560  //  exitMBB:
4561  //   ...
4562  BB = exitMBB;
4563  return BB;
4564}
4565
4566MachineBasicBlock *
4567PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
4568                                            MachineBasicBlock *BB,
4569                                            bool is8bit,    // operation
4570                                            unsigned BinOpcode) const {
4571  // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4572  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4573  // In 64 bit mode we have to use 64 bits for addresses, even though the
4574  // lwarx/stwcx are 32 bits.  With the 32-bit atomics we can use address
4575  // registers without caring whether they're 32 or 64, but here we're
4576  // doing actual arithmetic on the addresses.
4577  bool is64bit = PPCSubTarget.isPPC64();
4578  unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
4579
4580  const BasicBlock *LLVM_BB = BB->getBasicBlock();
4581  MachineFunction *F = BB->getParent();
4582  MachineFunction::iterator It = BB;
4583  ++It;
4584
4585  unsigned dest = MI->getOperand(0).getReg();
4586  unsigned ptrA = MI->getOperand(1).getReg();
4587  unsigned ptrB = MI->getOperand(2).getReg();
4588  unsigned incr = MI->getOperand(3).getReg();
4589  DebugLoc dl = MI->getDebugLoc();
4590
4591  MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4592  MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4593  F->insert(It, loopMBB);
4594  F->insert(It, exitMBB);
4595  exitMBB->splice(exitMBB->begin(), BB,
4596                  llvm::next(MachineBasicBlock::iterator(MI)),
4597                  BB->end());
4598  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4599
4600  MachineRegisterInfo &RegInfo = F->getRegInfo();
4601  const TargetRegisterClass *RC =
4602    is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4603              (const TargetRegisterClass *) &PPC::GPRCRegClass;
4604  unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4605  unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4606  unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4607  unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4608  unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4609  unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4610  unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4611  unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4612  unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4613  unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4614  unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4615  unsigned Ptr1Reg;
4616  unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4617
4618  //  thisMBB:
4619  //   ...
4620  //   fallthrough --> loopMBB
4621  BB->addSuccessor(loopMBB);
4622
4623  // The 4-byte load must be aligned, while a char or short may be
4624  // anywhere in the word.  Hence all this nasty bookkeeping code.
4625  //   add ptr1, ptrA, ptrB [copy if ptrA==0]
4626  //   rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4627  //   xori shift, shift1, 24 [16]
4628  //   rlwinm ptr, ptr1, 0, 0, 29
4629  //   slw incr2, incr, shift
4630  //   li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4631  //   slw mask, mask2, shift
4632  //  loopMBB:
4633  //   lwarx tmpDest, ptr
4634  //   add tmp, tmpDest, incr2
4635  //   andc tmp2, tmpDest, mask
4636  //   and tmp3, tmp, mask
4637  //   or tmp4, tmp3, tmp2
4638  //   stwcx. tmp4, ptr
4639  //   bne- loopMBB
4640  //   fallthrough --> exitMBB
4641  //   srw dest, tmpDest, shift
4642  if (ptrA != ZeroReg) {
4643    Ptr1Reg = RegInfo.createVirtualRegister(RC);
4644    BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4645      .addReg(ptrA).addReg(ptrB);
4646  } else {
4647    Ptr1Reg = ptrB;
4648  }
4649  BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4650      .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4651  BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4652      .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4653  if (is64bit)
4654    BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4655      .addReg(Ptr1Reg).addImm(0).addImm(61);
4656  else
4657    BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4658      .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4659  BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
4660      .addReg(incr).addReg(ShiftReg);
4661  if (is8bit)
4662    BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4663  else {
4664    BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4665    BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
4666  }
4667  BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4668      .addReg(Mask2Reg).addReg(ShiftReg);
4669
4670  BB = loopMBB;
4671  BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4672    .addReg(ZeroReg).addReg(PtrReg);
4673  if (BinOpcode)
4674    BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
4675      .addReg(Incr2Reg).addReg(TmpDestReg);
4676  BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4677    .addReg(TmpDestReg).addReg(MaskReg);
4678  BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4679    .addReg(TmpReg).addReg(MaskReg);
4680  BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4681    .addReg(Tmp3Reg).addReg(Tmp2Reg);
4682  BuildMI(BB, dl, TII->get(PPC::STWCX))
4683    .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
4684  BuildMI(BB, dl, TII->get(PPC::BCC))
4685    .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4686  BB->addSuccessor(loopMBB);
4687  BB->addSuccessor(exitMBB);
4688
4689  //  exitMBB:
4690  //   ...
4691  BB = exitMBB;
4692  BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
4693    .addReg(ShiftReg);
4694  return BB;
4695}
4696
4697MachineBasicBlock *
4698PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4699                                               MachineBasicBlock *BB) const {
4700  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4701
4702  // To "insert" these instructions we actually have to insert their
4703  // control-flow patterns.
4704  const BasicBlock *LLVM_BB = BB->getBasicBlock();
4705  MachineFunction::iterator It = BB;
4706  ++It;
4707
4708  MachineFunction *F = BB->getParent();
4709
4710  if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4711      MI->getOpcode() == PPC::SELECT_CC_I8 ||
4712      MI->getOpcode() == PPC::SELECT_CC_F4 ||
4713      MI->getOpcode() == PPC::SELECT_CC_F8 ||
4714      MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4715
4716    // The incoming instruction knows the destination vreg to set, the
4717    // condition code register to branch on, the true/false values to
4718    // select between, and a branch opcode to use.
4719
4720    //  thisMBB:
4721    //  ...
4722    //   TrueVal = ...
4723    //   cmpTY ccX, r1, r2
4724    //   bCC copy1MBB
4725    //   fallthrough --> copy0MBB
4726    MachineBasicBlock *thisMBB = BB;
4727    MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4728    MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4729    unsigned SelectPred = MI->getOperand(4).getImm();
4730    DebugLoc dl = MI->getDebugLoc();
4731    F->insert(It, copy0MBB);
4732    F->insert(It, sinkMBB);
4733
4734    // Transfer the remainder of BB and its successor edges to sinkMBB.
4735    sinkMBB->splice(sinkMBB->begin(), BB,
4736                    llvm::next(MachineBasicBlock::iterator(MI)),
4737                    BB->end());
4738    sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4739
4740    // Next, add the true and fallthrough blocks as its successors.
4741    BB->addSuccessor(copy0MBB);
4742    BB->addSuccessor(sinkMBB);
4743
4744    BuildMI(BB, dl, TII->get(PPC::BCC))
4745      .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4746
4747    //  copy0MBB:
4748    //   %FalseValue = ...
4749    //   # fallthrough to sinkMBB
4750    BB = copy0MBB;
4751
4752    // Update machine-CFG edges
4753    BB->addSuccessor(sinkMBB);
4754
4755    //  sinkMBB:
4756    //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4757    //  ...
4758    BB = sinkMBB;
4759    BuildMI(*BB, BB->begin(), dl,
4760            TII->get(PPC::PHI), MI->getOperand(0).getReg())
4761      .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4762      .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4763  }
4764  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4765    BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4766  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4767    BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4768  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4769    BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4770  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4771    BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4772
4773  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4774    BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4775  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4776    BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4777  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4778    BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4779  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4780    BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4781
4782  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4783    BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4784  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4785    BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4786  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4787    BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4788  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4789    BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4790
4791  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4792    BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4793  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4794    BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4795  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4796    BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4797  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4798    BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4799
4800  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4801    BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4802  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4803    BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4804  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4805    BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4806  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4807    BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4808
4809  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4810    BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4811  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4812    BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4813  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4814    BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4815  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4816    BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4817
4818  else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4819    BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4820  else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4821    BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4822  else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4823    BB = EmitAtomicBinary(MI, BB, false, 0);
4824  else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4825    BB = EmitAtomicBinary(MI, BB, true, 0);
4826
4827  else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4828           MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4829    bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4830
4831    unsigned dest   = MI->getOperand(0).getReg();
4832    unsigned ptrA   = MI->getOperand(1).getReg();
4833    unsigned ptrB   = MI->getOperand(2).getReg();
4834    unsigned oldval = MI->getOperand(3).getReg();
4835    unsigned newval = MI->getOperand(4).getReg();
4836    DebugLoc dl     = MI->getDebugLoc();
4837
4838    MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4839    MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4840    MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4841    MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4842    F->insert(It, loop1MBB);
4843    F->insert(It, loop2MBB);
4844    F->insert(It, midMBB);
4845    F->insert(It, exitMBB);
4846    exitMBB->splice(exitMBB->begin(), BB,
4847                    llvm::next(MachineBasicBlock::iterator(MI)),
4848                    BB->end());
4849    exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4850
4851    //  thisMBB:
4852    //   ...
4853    //   fallthrough --> loopMBB
4854    BB->addSuccessor(loop1MBB);
4855
4856    // loop1MBB:
4857    //   l[wd]arx dest, ptr
4858    //   cmp[wd] dest, oldval
4859    //   bne- midMBB
4860    // loop2MBB:
4861    //   st[wd]cx. newval, ptr
4862    //   bne- loopMBB
4863    //   b exitBB
4864    // midMBB:
4865    //   st[wd]cx. dest, ptr
4866    // exitBB:
4867    BB = loop1MBB;
4868    BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4869      .addReg(ptrA).addReg(ptrB);
4870    BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
4871      .addReg(oldval).addReg(dest);
4872    BuildMI(BB, dl, TII->get(PPC::BCC))
4873      .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4874    BB->addSuccessor(loop2MBB);
4875    BB->addSuccessor(midMBB);
4876
4877    BB = loop2MBB;
4878    BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4879      .addReg(newval).addReg(ptrA).addReg(ptrB);
4880    BuildMI(BB, dl, TII->get(PPC::BCC))
4881      .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4882    BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4883    BB->addSuccessor(loop1MBB);
4884    BB->addSuccessor(exitMBB);
4885
4886    BB = midMBB;
4887    BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4888      .addReg(dest).addReg(ptrA).addReg(ptrB);
4889    BB->addSuccessor(exitMBB);
4890
4891    //  exitMBB:
4892    //   ...
4893    BB = exitMBB;
4894  } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
4895             MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
4896    // We must use 64-bit registers for addresses when targeting 64-bit,
4897    // since we're actually doing arithmetic on them.  Other registers
4898    // can be 32-bit.
4899    bool is64bit = PPCSubTarget.isPPC64();
4900    bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
4901
4902    unsigned dest   = MI->getOperand(0).getReg();
4903    unsigned ptrA   = MI->getOperand(1).getReg();
4904    unsigned ptrB   = MI->getOperand(2).getReg();
4905    unsigned oldval = MI->getOperand(3).getReg();
4906    unsigned newval = MI->getOperand(4).getReg();
4907    DebugLoc dl     = MI->getDebugLoc();
4908
4909    MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4910    MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4911    MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4912    MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4913    F->insert(It, loop1MBB);
4914    F->insert(It, loop2MBB);
4915    F->insert(It, midMBB);
4916    F->insert(It, exitMBB);
4917    exitMBB->splice(exitMBB->begin(), BB,
4918                    llvm::next(MachineBasicBlock::iterator(MI)),
4919                    BB->end());
4920    exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4921
4922    MachineRegisterInfo &RegInfo = F->getRegInfo();
4923    const TargetRegisterClass *RC =
4924      is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4925                (const TargetRegisterClass *) &PPC::GPRCRegClass;
4926    unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4927    unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4928    unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4929    unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
4930    unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
4931    unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
4932    unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
4933    unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4934    unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4935    unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4936    unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4937    unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4938    unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4939    unsigned Ptr1Reg;
4940    unsigned TmpReg = RegInfo.createVirtualRegister(RC);
4941    unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
4942    //  thisMBB:
4943    //   ...
4944    //   fallthrough --> loopMBB
4945    BB->addSuccessor(loop1MBB);
4946
4947    // The 4-byte load must be aligned, while a char or short may be
4948    // anywhere in the word.  Hence all this nasty bookkeeping code.
4949    //   add ptr1, ptrA, ptrB [copy if ptrA==0]
4950    //   rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4951    //   xori shift, shift1, 24 [16]
4952    //   rlwinm ptr, ptr1, 0, 0, 29
4953    //   slw newval2, newval, shift
4954    //   slw oldval2, oldval,shift
4955    //   li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4956    //   slw mask, mask2, shift
4957    //   and newval3, newval2, mask
4958    //   and oldval3, oldval2, mask
4959    // loop1MBB:
4960    //   lwarx tmpDest, ptr
4961    //   and tmp, tmpDest, mask
4962    //   cmpw tmp, oldval3
4963    //   bne- midMBB
4964    // loop2MBB:
4965    //   andc tmp2, tmpDest, mask
4966    //   or tmp4, tmp2, newval3
4967    //   stwcx. tmp4, ptr
4968    //   bne- loop1MBB
4969    //   b exitBB
4970    // midMBB:
4971    //   stwcx. tmpDest, ptr
4972    // exitBB:
4973    //   srw dest, tmpDest, shift
4974    if (ptrA != ZeroReg) {
4975      Ptr1Reg = RegInfo.createVirtualRegister(RC);
4976      BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4977        .addReg(ptrA).addReg(ptrB);
4978    } else {
4979      Ptr1Reg = ptrB;
4980    }
4981    BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4982        .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4983    BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4984        .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4985    if (is64bit)
4986      BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4987        .addReg(Ptr1Reg).addImm(0).addImm(61);
4988    else
4989      BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4990        .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4991    BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
4992        .addReg(newval).addReg(ShiftReg);
4993    BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
4994        .addReg(oldval).addReg(ShiftReg);
4995    if (is8bit)
4996      BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4997    else {
4998      BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4999      BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
5000        .addReg(Mask3Reg).addImm(65535);
5001    }
5002    BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
5003        .addReg(Mask2Reg).addReg(ShiftReg);
5004    BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
5005        .addReg(NewVal2Reg).addReg(MaskReg);
5006    BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
5007        .addReg(OldVal2Reg).addReg(MaskReg);
5008
5009    BB = loop1MBB;
5010    BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
5011        .addReg(ZeroReg).addReg(PtrReg);
5012    BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
5013        .addReg(TmpDestReg).addReg(MaskReg);
5014    BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
5015        .addReg(TmpReg).addReg(OldVal3Reg);
5016    BuildMI(BB, dl, TII->get(PPC::BCC))
5017        .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
5018    BB->addSuccessor(loop2MBB);
5019    BB->addSuccessor(midMBB);
5020
5021    BB = loop2MBB;
5022    BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
5023        .addReg(TmpDestReg).addReg(MaskReg);
5024    BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
5025        .addReg(Tmp2Reg).addReg(NewVal3Reg);
5026    BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
5027        .addReg(ZeroReg).addReg(PtrReg);
5028    BuildMI(BB, dl, TII->get(PPC::BCC))
5029      .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
5030    BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
5031    BB->addSuccessor(loop1MBB);
5032    BB->addSuccessor(exitMBB);
5033
5034    BB = midMBB;
5035    BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
5036      .addReg(ZeroReg).addReg(PtrReg);
5037    BB->addSuccessor(exitMBB);
5038
5039    //  exitMBB:
5040    //   ...
5041    BB = exitMBB;
5042    BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
5043      .addReg(ShiftReg);
5044  } else {
5045    llvm_unreachable("Unexpected instr type to insert");
5046  }
5047
5048  MI->eraseFromParent();   // The pseudo instruction is gone now.
5049  return BB;
5050}
5051
5052//===----------------------------------------------------------------------===//
5053// Target Optimization Hooks
5054//===----------------------------------------------------------------------===//
5055
5056SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
5057                                             DAGCombinerInfo &DCI) const {
5058  const TargetMachine &TM = getTargetMachine();
5059  SelectionDAG &DAG = DCI.DAG;
5060  DebugLoc dl = N->getDebugLoc();
5061  switch (N->getOpcode()) {
5062  default: break;
5063  case PPCISD::SHL:
5064    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5065      if (C->isNullValue())   // 0 << V -> 0.
5066        return N->getOperand(0);
5067    }
5068    break;
5069  case PPCISD::SRL:
5070    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5071      if (C->isNullValue())   // 0 >>u V -> 0.
5072        return N->getOperand(0);
5073    }
5074    break;
5075  case PPCISD::SRA:
5076    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5077      if (C->isNullValue() ||   //  0 >>s V -> 0.
5078          C->isAllOnesValue())    // -1 >>s V -> -1.
5079        return N->getOperand(0);
5080    }
5081    break;
5082
5083  case ISD::SINT_TO_FP:
5084    if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
5085      if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
5086        // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
5087        // We allow the src/dst to be either f32/f64, but the intermediate
5088        // type must be i64.
5089        if (N->getOperand(0).getValueType() == MVT::i64 &&
5090            N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
5091          SDValue Val = N->getOperand(0).getOperand(0);
5092          if (Val.getValueType() == MVT::f32) {
5093            Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5094            DCI.AddToWorklist(Val.getNode());
5095          }
5096
5097          Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
5098          DCI.AddToWorklist(Val.getNode());
5099          Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
5100          DCI.AddToWorklist(Val.getNode());
5101          if (N->getValueType(0) == MVT::f32) {
5102            Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
5103                              DAG.getIntPtrConstant(0));
5104            DCI.AddToWorklist(Val.getNode());
5105          }
5106          return Val;
5107        } else if (N->getOperand(0).getValueType() == MVT::i32) {
5108          // If the intermediate type is i32, we can avoid the load/store here
5109          // too.
5110        }
5111      }
5112    }
5113    break;
5114  case ISD::STORE:
5115    // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
5116    if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
5117        !cast<StoreSDNode>(N)->isTruncatingStore() &&
5118        N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
5119        N->getOperand(1).getValueType() == MVT::i32 &&
5120        N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
5121      SDValue Val = N->getOperand(1).getOperand(0);
5122      if (Val.getValueType() == MVT::f32) {
5123        Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5124        DCI.AddToWorklist(Val.getNode());
5125      }
5126      Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
5127      DCI.AddToWorklist(Val.getNode());
5128
5129      Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
5130                        N->getOperand(2), N->getOperand(3));
5131      DCI.AddToWorklist(Val.getNode());
5132      return Val;
5133    }
5134
5135    // Turn STORE (BSWAP) -> sthbrx/stwbrx.
5136    if (cast<StoreSDNode>(N)->isUnindexed() &&
5137        N->getOperand(1).getOpcode() == ISD::BSWAP &&
5138        N->getOperand(1).getNode()->hasOneUse() &&
5139        (N->getOperand(1).getValueType() == MVT::i32 ||
5140         N->getOperand(1).getValueType() == MVT::i16)) {
5141      SDValue BSwapOp = N->getOperand(1).getOperand(0);
5142      // Do an any-extend to 32-bits if this is a half-word input.
5143      if (BSwapOp.getValueType() == MVT::i16)
5144        BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
5145
5146      SDValue Ops[] = {
5147        N->getOperand(0), BSwapOp, N->getOperand(2),
5148        DAG.getValueType(N->getOperand(1).getValueType())
5149      };
5150      return
5151        DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
5152                                Ops, array_lengthof(Ops),
5153                                cast<StoreSDNode>(N)->getMemoryVT(),
5154                                cast<StoreSDNode>(N)->getMemOperand());
5155    }
5156    break;
5157  case ISD::BSWAP:
5158    // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
5159    if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
5160        N->getOperand(0).hasOneUse() &&
5161        (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
5162      SDValue Load = N->getOperand(0);
5163      LoadSDNode *LD = cast<LoadSDNode>(Load);
5164      // Create the byte-swapping load.
5165      SDValue Ops[] = {
5166        LD->getChain(),    // Chain
5167        LD->getBasePtr(),  // Ptr
5168        DAG.getValueType(N->getValueType(0)) // VT
5169      };
5170      SDValue BSLoad =
5171        DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
5172                                DAG.getVTList(MVT::i32, MVT::Other), Ops, 3,
5173                                LD->getMemoryVT(), LD->getMemOperand());
5174
5175      // If this is an i16 load, insert the truncate.
5176      SDValue ResVal = BSLoad;
5177      if (N->getValueType(0) == MVT::i16)
5178        ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
5179
5180      // First, combine the bswap away.  This makes the value produced by the
5181      // load dead.
5182      DCI.CombineTo(N, ResVal);
5183
5184      // Next, combine the load away, we give it a bogus result value but a real
5185      // chain result.  The result value is dead because the bswap is dead.
5186      DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
5187
5188      // Return N so it doesn't get rechecked!
5189      return SDValue(N, 0);
5190    }
5191
5192    break;
5193  case PPCISD::VCMP: {
5194    // If a VCMPo node already exists with exactly the same operands as this
5195    // node, use its result instead of this node (VCMPo computes both a CR6 and
5196    // a normal output).
5197    //
5198    if (!N->getOperand(0).hasOneUse() &&
5199        !N->getOperand(1).hasOneUse() &&
5200        !N->getOperand(2).hasOneUse()) {
5201
5202      // Scan all of the users of the LHS, looking for VCMPo's that match.
5203      SDNode *VCMPoNode = 0;
5204
5205      SDNode *LHSN = N->getOperand(0).getNode();
5206      for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
5207           UI != E; ++UI)
5208        if (UI->getOpcode() == PPCISD::VCMPo &&
5209            UI->getOperand(1) == N->getOperand(1) &&
5210            UI->getOperand(2) == N->getOperand(2) &&
5211            UI->getOperand(0) == N->getOperand(0)) {
5212          VCMPoNode = *UI;
5213          break;
5214        }
5215
5216      // If there is no VCMPo node, or if the flag value has a single use, don't
5217      // transform this.
5218      if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
5219        break;
5220
5221      // Look at the (necessarily single) use of the flag value.  If it has a
5222      // chain, this transformation is more complex.  Note that multiple things
5223      // could use the value result, which we should ignore.
5224      SDNode *FlagUser = 0;
5225      for (SDNode::use_iterator UI = VCMPoNode->use_begin();
5226           FlagUser == 0; ++UI) {
5227        assert(UI != VCMPoNode->use_end() && "Didn't find user!");
5228        SDNode *User = *UI;
5229        for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
5230          if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
5231            FlagUser = User;
5232            break;
5233          }
5234        }
5235      }
5236
5237      // If the user is a MFCR instruction, we know this is safe.  Otherwise we
5238      // give up for right now.
5239      if (FlagUser->getOpcode() == PPCISD::MFCR)
5240        return SDValue(VCMPoNode, 0);
5241    }
5242    break;
5243  }
5244  case ISD::BR_CC: {
5245    // If this is a branch on an altivec predicate comparison, lower this so
5246    // that we don't have to do a MFCR: instead, branch directly on CR6.  This
5247    // lowering is done pre-legalize, because the legalizer lowers the predicate
5248    // compare down to code that is difficult to reassemble.
5249    ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
5250    SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
5251    int CompareOpc;
5252    bool isDot;
5253
5254    if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
5255        isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
5256        getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
5257      assert(isDot && "Can't compare against a vector result!");
5258
5259      // If this is a comparison against something other than 0/1, then we know
5260      // that the condition is never/always true.
5261      unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
5262      if (Val != 0 && Val != 1) {
5263        if (CC == ISD::SETEQ)      // Cond never true, remove branch.
5264          return N->getOperand(0);
5265        // Always !=, turn it into an unconditional branch.
5266        return DAG.getNode(ISD::BR, dl, MVT::Other,
5267                           N->getOperand(0), N->getOperand(4));
5268      }
5269
5270      bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
5271
5272      // Create the PPCISD altivec 'dot' comparison node.
5273      std::vector<EVT> VTs;
5274      SDValue Ops[] = {
5275        LHS.getOperand(2),  // LHS of compare
5276        LHS.getOperand(3),  // RHS of compare
5277        DAG.getConstant(CompareOpc, MVT::i32)
5278      };
5279      VTs.push_back(LHS.getOperand(2).getValueType());
5280      VTs.push_back(MVT::Glue);
5281      SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5282
5283      // Unpack the result based on how the target uses it.
5284      PPC::Predicate CompOpc;
5285      switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
5286      default:  // Can't happen, don't crash on invalid number though.
5287      case 0:   // Branch on the value of the EQ bit of CR6.
5288        CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
5289        break;
5290      case 1:   // Branch on the inverted value of the EQ bit of CR6.
5291        CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
5292        break;
5293      case 2:   // Branch on the value of the LT bit of CR6.
5294        CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
5295        break;
5296      case 3:   // Branch on the inverted value of the LT bit of CR6.
5297        CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
5298        break;
5299      }
5300
5301      return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
5302                         DAG.getConstant(CompOpc, MVT::i32),
5303                         DAG.getRegister(PPC::CR6, MVT::i32),
5304                         N->getOperand(4), CompNode.getValue(1));
5305    }
5306    break;
5307  }
5308  }
5309
5310  return SDValue();
5311}
5312
5313//===----------------------------------------------------------------------===//
5314// Inline Assembly Support
5315//===----------------------------------------------------------------------===//
5316
5317void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5318                                                       const APInt &Mask,
5319                                                       APInt &KnownZero,
5320                                                       APInt &KnownOne,
5321                                                       const SelectionDAG &DAG,
5322                                                       unsigned Depth) const {
5323  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5324  switch (Op.getOpcode()) {
5325  default: break;
5326  case PPCISD::LBRX: {
5327    // lhbrx is known to have the top bits cleared out.
5328    if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
5329      KnownZero = 0xFFFF0000;
5330    break;
5331  }
5332  case ISD::INTRINSIC_WO_CHAIN: {
5333    switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
5334    default: break;
5335    case Intrinsic::ppc_altivec_vcmpbfp_p:
5336    case Intrinsic::ppc_altivec_vcmpeqfp_p:
5337    case Intrinsic::ppc_altivec_vcmpequb_p:
5338    case Intrinsic::ppc_altivec_vcmpequh_p:
5339    case Intrinsic::ppc_altivec_vcmpequw_p:
5340    case Intrinsic::ppc_altivec_vcmpgefp_p:
5341    case Intrinsic::ppc_altivec_vcmpgtfp_p:
5342    case Intrinsic::ppc_altivec_vcmpgtsb_p:
5343    case Intrinsic::ppc_altivec_vcmpgtsh_p:
5344    case Intrinsic::ppc_altivec_vcmpgtsw_p:
5345    case Intrinsic::ppc_altivec_vcmpgtub_p:
5346    case Intrinsic::ppc_altivec_vcmpgtuh_p:
5347    case Intrinsic::ppc_altivec_vcmpgtuw_p:
5348      KnownZero = ~1U;  // All bits but the low one are known to be zero.
5349      break;
5350    }
5351  }
5352  }
5353}
5354
5355
5356/// getConstraintType - Given a constraint, return the type of
5357/// constraint it is for this target.
5358PPCTargetLowering::ConstraintType
5359PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
5360  if (Constraint.size() == 1) {
5361    switch (Constraint[0]) {
5362    default: break;
5363    case 'b':
5364    case 'r':
5365    case 'f':
5366    case 'v':
5367    case 'y':
5368      return C_RegisterClass;
5369    }
5370  }
5371  return TargetLowering::getConstraintType(Constraint);
5372}
5373
5374/// Examine constraint type and operand type and determine a weight value.
5375/// This object must already have been set up with the operand type
5376/// and the current alternative constraint selected.
5377TargetLowering::ConstraintWeight
5378PPCTargetLowering::getSingleConstraintMatchWeight(
5379    AsmOperandInfo &info, const char *constraint) const {
5380  ConstraintWeight weight = CW_Invalid;
5381  Value *CallOperandVal = info.CallOperandVal;
5382    // If we don't have a value, we can't do a match,
5383    // but allow it at the lowest weight.
5384  if (CallOperandVal == NULL)
5385    return CW_Default;
5386  const Type *type = CallOperandVal->getType();
5387  // Look at the constraint type.
5388  switch (*constraint) {
5389  default:
5390    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
5391    break;
5392  case 'b':
5393    if (type->isIntegerTy())
5394      weight = CW_Register;
5395    break;
5396  case 'f':
5397    if (type->isFloatTy())
5398      weight = CW_Register;
5399    break;
5400  case 'd':
5401    if (type->isDoubleTy())
5402      weight = CW_Register;
5403    break;
5404  case 'v':
5405    if (type->isVectorTy())
5406      weight = CW_Register;
5407    break;
5408  case 'y':
5409    weight = CW_Register;
5410    break;
5411  }
5412  return weight;
5413}
5414
5415std::pair<unsigned, const TargetRegisterClass*>
5416PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5417                                                EVT VT) const {
5418  if (Constraint.size() == 1) {
5419    // GCC RS6000 Constraint Letters
5420    switch (Constraint[0]) {
5421    case 'b':   // R1-R31
5422    case 'r':   // R0-R31
5423      if (VT == MVT::i64 && PPCSubTarget.isPPC64())
5424        return std::make_pair(0U, PPC::G8RCRegisterClass);
5425      return std::make_pair(0U, PPC::GPRCRegisterClass);
5426    case 'f':
5427      if (VT == MVT::f32)
5428        return std::make_pair(0U, PPC::F4RCRegisterClass);
5429      else if (VT == MVT::f64)
5430        return std::make_pair(0U, PPC::F8RCRegisterClass);
5431      break;
5432    case 'v':
5433      return std::make_pair(0U, PPC::VRRCRegisterClass);
5434    case 'y':   // crrc
5435      return std::make_pair(0U, PPC::CRRCRegisterClass);
5436    }
5437  }
5438
5439  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5440}
5441
5442
5443/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5444/// vector.  If it is invalid, don't add anything to Ops.
5445void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
5446                                                     std::vector<SDValue>&Ops,
5447                                                     SelectionDAG &DAG) const {
5448  SDValue Result(0,0);
5449  switch (Letter) {
5450  default: break;
5451  case 'I':
5452  case 'J':
5453  case 'K':
5454  case 'L':
5455  case 'M':
5456  case 'N':
5457  case 'O':
5458  case 'P': {
5459    ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
5460    if (!CST) return; // Must be an immediate to match.
5461    unsigned Value = CST->getZExtValue();
5462    switch (Letter) {
5463    default: llvm_unreachable("Unknown constraint letter!");
5464    case 'I':  // "I" is a signed 16-bit constant.
5465      if ((short)Value == (int)Value)
5466        Result = DAG.getTargetConstant(Value, Op.getValueType());
5467      break;
5468    case 'J':  // "J" is a constant with only the high-order 16 bits nonzero.
5469    case 'L':  // "L" is a signed 16-bit constant shifted left 16 bits.
5470      if ((short)Value == 0)
5471        Result = DAG.getTargetConstant(Value, Op.getValueType());
5472      break;
5473    case 'K':  // "K" is a constant with only the low-order 16 bits nonzero.
5474      if ((Value >> 16) == 0)
5475        Result = DAG.getTargetConstant(Value, Op.getValueType());
5476      break;
5477    case 'M':  // "M" is a constant that is greater than 31.
5478      if (Value > 31)
5479        Result = DAG.getTargetConstant(Value, Op.getValueType());
5480      break;
5481    case 'N':  // "N" is a positive constant that is an exact power of two.
5482      if ((int)Value > 0 && isPowerOf2_32(Value))
5483        Result = DAG.getTargetConstant(Value, Op.getValueType());
5484      break;
5485    case 'O':  // "O" is the constant zero.
5486      if (Value == 0)
5487        Result = DAG.getTargetConstant(Value, Op.getValueType());
5488      break;
5489    case 'P':  // "P" is a constant whose negation is a signed 16-bit constant.
5490      if ((short)-Value == (int)-Value)
5491        Result = DAG.getTargetConstant(Value, Op.getValueType());
5492      break;
5493    }
5494    break;
5495  }
5496  }
5497
5498  if (Result.getNode()) {
5499    Ops.push_back(Result);
5500    return;
5501  }
5502
5503  // Handle standard constraint letters.
5504  TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
5505}
5506
5507// isLegalAddressingMode - Return true if the addressing mode represented
5508// by AM is legal for this target, for a load/store of the specified type.
5509bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5510                                              const Type *Ty) const {
5511  // FIXME: PPC does not allow r+i addressing modes for vectors!
5512
5513  // PPC allows a sign-extended 16-bit immediate field.
5514  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
5515    return false;
5516
5517  // No global is ever allowed as a base.
5518  if (AM.BaseGV)
5519    return false;
5520
5521  // PPC only support r+r,
5522  switch (AM.Scale) {
5523  case 0:  // "r+i" or just "i", depending on HasBaseReg.
5524    break;
5525  case 1:
5526    if (AM.HasBaseReg && AM.BaseOffs)  // "r+r+i" is not allowed.
5527      return false;
5528    // Otherwise we have r+r or r+i.
5529    break;
5530  case 2:
5531    if (AM.HasBaseReg || AM.BaseOffs)  // 2*r+r  or  2*r+i is not allowed.
5532      return false;
5533    // Allow 2*r as r+r.
5534    break;
5535  default:
5536    // No other scales are supported.
5537    return false;
5538  }
5539
5540  return true;
5541}
5542
5543/// isLegalAddressImmediate - Return true if the integer value can be used
5544/// as the offset of the target addressing mode for load / store of the
5545/// given type.
5546bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
5547  // PPC allows a sign-extended 16-bit immediate field.
5548  return (V > -(1 << 16) && V < (1 << 16)-1);
5549}
5550
5551bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
5552  return false;
5553}
5554
5555SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
5556                                           SelectionDAG &DAG) const {
5557  MachineFunction &MF = DAG.getMachineFunction();
5558  MachineFrameInfo *MFI = MF.getFrameInfo();
5559  MFI->setReturnAddressIsTaken(true);
5560
5561  DebugLoc dl = Op.getDebugLoc();
5562  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5563
5564  // Make sure the function does not optimize away the store of the RA to
5565  // the stack.
5566  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
5567  FuncInfo->setLRStoreRequired();
5568  bool isPPC64 = PPCSubTarget.isPPC64();
5569  bool isDarwinABI = PPCSubTarget.isDarwinABI();
5570
5571  if (Depth > 0) {
5572    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5573    SDValue Offset =
5574
5575      DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
5576                      isPPC64? MVT::i64 : MVT::i32);
5577    return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
5578                       DAG.getNode(ISD::ADD, dl, getPointerTy(),
5579                                   FrameAddr, Offset),
5580                       MachinePointerInfo(), false, false, 0);
5581  }
5582
5583  // Just load the return address off the stack.
5584  SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
5585  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
5586                     RetAddrFI, MachinePointerInfo(), false, false, 0);
5587}
5588
5589SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
5590                                          SelectionDAG &DAG) const {
5591  DebugLoc dl = Op.getDebugLoc();
5592  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5593
5594  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5595  bool isPPC64 = PtrVT == MVT::i64;
5596
5597  MachineFunction &MF = DAG.getMachineFunction();
5598  MachineFrameInfo *MFI = MF.getFrameInfo();
5599  MFI->setFrameAddressIsTaken(true);
5600  bool is31 = (DisableFramePointerElim(MF) || MFI->hasVarSizedObjects()) &&
5601                  MFI->getStackSize() &&
5602                  !MF.getFunction()->hasFnAttr(Attribute::Naked);
5603  unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) :
5604                                (is31 ? PPC::R31 : PPC::R1);
5605  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
5606                                         PtrVT);
5607  while (Depth--)
5608    FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
5609                            FrameAddr, MachinePointerInfo(), false, false, 0);
5610  return FrameAddr;
5611}
5612
5613bool
5614PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5615  // The PowerPC target isn't yet aware of offsets.
5616  return false;
5617}
5618
5619/// getOptimalMemOpType - Returns the target specific optimal type for load
5620/// and store operations as a result of memset, memcpy, and memmove
5621/// lowering. If DstAlign is zero that means it's safe to destination
5622/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
5623/// means there isn't a need to check it against alignment requirement,
5624/// probably because the source does not need to be loaded. If
5625/// 'NonScalarIntSafe' is true, that means it's safe to return a
5626/// non-scalar-integer type, e.g. empty string source, constant, or loaded
5627/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
5628/// constant so it does not need to be loaded.
5629/// It returns EVT::Other if the type should be determined using generic
5630/// target-independent logic.
5631EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
5632                                           unsigned DstAlign, unsigned SrcAlign,
5633                                           bool NonScalarIntSafe,
5634                                           bool MemcpyStrSrc,
5635                                           MachineFunction &MF) const {
5636  if (this->PPCSubTarget.isPPC64()) {
5637    return MVT::i64;
5638  } else {
5639    return MVT::i32;
5640  }
5641}
5642