PPCISelLowering.cpp revision 66ffe6be0c7b50100a00cb0cc87a5d4983818572
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPredicates.h" 17#include "PPCTargetMachine.h" 18#include "PPCPerfectShuffle.h" 19#include "llvm/ADT/VectorExtras.h" 20#include "llvm/Analysis/ScalarEvolutionExpressions.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/SelectionDAG.h" 26#include "llvm/CodeGen/SSARegMap.h" 27#include "llvm/Constants.h" 28#include "llvm/Function.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/Support/MathExtras.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/Support/CommandLine.h" 33using namespace llvm; 34 35static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", 36cl::desc("enable preincrement load/store generation on PPC (experimental)"), 37 cl::Hidden); 38 39PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 40 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { 41 42 setPow2DivIsCheap(); 43 44 // Use _setjmp/_longjmp instead of setjmp/longjmp. 45 setUseUnderscoreSetJmp(true); 46 setUseUnderscoreLongJmp(true); 47 48 // Set up the register classes. 49 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 50 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 51 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 52 53 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 54 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand); 55 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); 56 57 // PowerPC does not have truncstore for i1. 58 setStoreXAction(MVT::i1, Promote); 59 60 // PowerPC has pre-inc load and store's. 61 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 62 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 63 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 64 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 65 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 66 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 67 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 68 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 69 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 70 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 71 72 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 73 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 74 75 // PowerPC has no intrinsics for these particular operations 76 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 77 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 78 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 79 80 // PowerPC has no SREM/UREM instructions 81 setOperationAction(ISD::SREM, MVT::i32, Expand); 82 setOperationAction(ISD::UREM, MVT::i32, Expand); 83 setOperationAction(ISD::SREM, MVT::i64, Expand); 84 setOperationAction(ISD::UREM, MVT::i64, Expand); 85 86 // We don't support sin/cos/sqrt/fmod 87 setOperationAction(ISD::FSIN , MVT::f64, Expand); 88 setOperationAction(ISD::FCOS , MVT::f64, Expand); 89 setOperationAction(ISD::FREM , MVT::f64, Expand); 90 setOperationAction(ISD::FSIN , MVT::f32, Expand); 91 setOperationAction(ISD::FCOS , MVT::f32, Expand); 92 setOperationAction(ISD::FREM , MVT::f32, Expand); 93 94 // If we're enabling GP optimizations, use hardware square root 95 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 96 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 97 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 98 } 99 100 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 101 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 102 103 // PowerPC does not have BSWAP, CTPOP or CTTZ 104 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 105 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 106 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 107 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 108 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 109 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 110 111 // PowerPC does not have ROTR 112 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 113 114 // PowerPC does not have Select 115 setOperationAction(ISD::SELECT, MVT::i32, Expand); 116 setOperationAction(ISD::SELECT, MVT::i64, Expand); 117 setOperationAction(ISD::SELECT, MVT::f32, Expand); 118 setOperationAction(ISD::SELECT, MVT::f64, Expand); 119 120 // PowerPC wants to turn select_cc of FP into fsel when possible. 121 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 122 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 123 124 // PowerPC wants to optimize integer setcc a bit 125 setOperationAction(ISD::SETCC, MVT::i32, Custom); 126 127 // PowerPC does not have BRCOND which requires SetCC 128 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 129 130 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 131 132 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 133 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 134 135 // PowerPC does not have [U|S]INT_TO_FP 136 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 137 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 138 139 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 140 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 141 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 142 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 143 144 // We cannot sextinreg(i1). Expand to shifts. 145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 146 147 // Support label based line numbers. 148 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 149 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 150 if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) { 151 setOperationAction(ISD::LABEL, MVT::Other, Expand); 152 } else { 153 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 154 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 155 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 156 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 157 } 158 159 // We want to legalize GlobalAddress and ConstantPool nodes into the 160 // appropriate instructions to materialize the address. 161 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 162 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 163 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 164 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 165 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 166 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 167 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 168 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 169 170 // RET must be custom lowered, to meet ABI requirements 171 setOperationAction(ISD::RET , MVT::Other, Custom); 172 173 setOperationAction(ISD::ADJUST_TRAMP, MVT::i32, Expand); 174 setOperationAction(ISD::ADJUST_TRAMP, MVT::i64, Expand); 175 176 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 177 setOperationAction(ISD::VASTART , MVT::Other, Custom); 178 179 // VAARG is custom lowered with ELF 32 ABI 180 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI()) 181 setOperationAction(ISD::VAARG, MVT::Other, Custom); 182 else 183 setOperationAction(ISD::VAARG, MVT::Other, Expand); 184 185 // Use the default implementation. 186 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 187 setOperationAction(ISD::VAEND , MVT::Other, Expand); 188 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 189 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 190 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 191 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 192 193 // We want to custom lower some of our intrinsics. 194 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 195 196 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 197 // They also have instructions for converting between i64 and fp. 198 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 199 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 200 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 201 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 202 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 203 204 // FIXME: disable this lowered code. This generates 64-bit register values, 205 // and we don't model the fact that the top part is clobbered by calls. We 206 // need to flag these together so that the value isn't live across a call. 207 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 208 209 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 210 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 211 } else { 212 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 213 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 214 } 215 216 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 217 // 64 bit PowerPC implementations can support i64 types directly 218 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 219 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 220 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 221 } else { 222 // 32 bit PowerPC wants to expand i64 shifts itself. 223 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 224 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 225 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 226 } 227 228 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 229 // First set operation action for all vector types to expand. Then we 230 // will selectively turn on ones that can be effectively codegen'd. 231 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 232 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 233 // add/sub are legal for all supported vector VT's. 234 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); 235 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); 236 237 // We promote all shuffles to v16i8. 238 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); 239 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); 240 241 // We promote all non-typed operations to v4i32. 242 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote); 243 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32); 244 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote); 245 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32); 246 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote); 247 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32); 248 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote); 249 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32); 250 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); 251 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32); 252 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote); 253 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32); 254 255 // No other operations are legal. 256 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); 257 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); 258 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); 259 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); 260 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); 261 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); 262 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand); 263 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 264 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 265 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); 266 267 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); 268 } 269 270 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 271 // with merges, splats, etc. 272 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 273 274 setOperationAction(ISD::AND , MVT::v4i32, Legal); 275 setOperationAction(ISD::OR , MVT::v4i32, Legal); 276 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 277 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 278 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 279 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 280 281 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 282 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 283 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 284 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 285 286 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 287 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 288 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 289 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 290 291 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 292 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 293 294 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 295 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 296 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 297 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 298 } 299 300 setSetCCResultType(MVT::i32); 301 setShiftAmountType(MVT::i32); 302 setSetCCResultContents(ZeroOrOneSetCCResult); 303 304 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 305 setStackPointerRegisterToSaveRestore(PPC::X1); 306 setExceptionPointerRegister(PPC::X3); 307 setExceptionSelectorRegister(PPC::X4); 308 } else { 309 setStackPointerRegisterToSaveRestore(PPC::R1); 310 setExceptionPointerRegister(PPC::R3); 311 setExceptionSelectorRegister(PPC::R4); 312 } 313 314 // We have target-specific dag combine patterns for the following nodes: 315 setTargetDAGCombine(ISD::SINT_TO_FP); 316 setTargetDAGCombine(ISD::STORE); 317 setTargetDAGCombine(ISD::BR_CC); 318 setTargetDAGCombine(ISD::BSWAP); 319 320 computeRegisterProperties(); 321} 322 323const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 324 switch (Opcode) { 325 default: return 0; 326 case PPCISD::FSEL: return "PPCISD::FSEL"; 327 case PPCISD::FCFID: return "PPCISD::FCFID"; 328 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 329 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 330 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 331 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 332 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 333 case PPCISD::VPERM: return "PPCISD::VPERM"; 334 case PPCISD::Hi: return "PPCISD::Hi"; 335 case PPCISD::Lo: return "PPCISD::Lo"; 336 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 337 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 338 case PPCISD::SRL: return "PPCISD::SRL"; 339 case PPCISD::SRA: return "PPCISD::SRA"; 340 case PPCISD::SHL: return "PPCISD::SHL"; 341 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 342 case PPCISD::STD_32: return "PPCISD::STD_32"; 343 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF"; 344 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho"; 345 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 346 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho"; 347 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF"; 348 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 349 case PPCISD::MFCR: return "PPCISD::MFCR"; 350 case PPCISD::VCMP: return "PPCISD::VCMP"; 351 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 352 case PPCISD::LBRX: return "PPCISD::LBRX"; 353 case PPCISD::STBRX: return "PPCISD::STBRX"; 354 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 355 } 356} 357 358//===----------------------------------------------------------------------===// 359// Node matching predicates, for use by the tblgen matching code. 360//===----------------------------------------------------------------------===// 361 362/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 363static bool isFloatingPointZero(SDOperand Op) { 364 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 365 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 366 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { 367 // Maybe this has already been legalized into the constant pool? 368 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 369 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 370 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 371 } 372 return false; 373} 374 375/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 376/// true if Op is undef or if it matches the specified value. 377static bool isConstantOrUndef(SDOperand Op, unsigned Val) { 378 return Op.getOpcode() == ISD::UNDEF || 379 cast<ConstantSDNode>(Op)->getValue() == Val; 380} 381 382/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 383/// VPKUHUM instruction. 384bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { 385 if (!isUnary) { 386 for (unsigned i = 0; i != 16; ++i) 387 if (!isConstantOrUndef(N->getOperand(i), i*2+1)) 388 return false; 389 } else { 390 for (unsigned i = 0; i != 8; ++i) 391 if (!isConstantOrUndef(N->getOperand(i), i*2+1) || 392 !isConstantOrUndef(N->getOperand(i+8), i*2+1)) 393 return false; 394 } 395 return true; 396} 397 398/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 399/// VPKUWUM instruction. 400bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { 401 if (!isUnary) { 402 for (unsigned i = 0; i != 16; i += 2) 403 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 404 !isConstantOrUndef(N->getOperand(i+1), i*2+3)) 405 return false; 406 } else { 407 for (unsigned i = 0; i != 8; i += 2) 408 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 409 !isConstantOrUndef(N->getOperand(i+1), i*2+3) || 410 !isConstantOrUndef(N->getOperand(i+8), i*2+2) || 411 !isConstantOrUndef(N->getOperand(i+9), i*2+3)) 412 return false; 413 } 414 return true; 415} 416 417/// isVMerge - Common function, used to match vmrg* shuffles. 418/// 419static bool isVMerge(SDNode *N, unsigned UnitSize, 420 unsigned LHSStart, unsigned RHSStart) { 421 assert(N->getOpcode() == ISD::BUILD_VECTOR && 422 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 423 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 424 "Unsupported merge size!"); 425 426 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 427 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 428 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), 429 LHSStart+j+i*UnitSize) || 430 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), 431 RHSStart+j+i*UnitSize)) 432 return false; 433 } 434 return true; 435} 436 437/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 438/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 439bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 440 if (!isUnary) 441 return isVMerge(N, UnitSize, 8, 24); 442 return isVMerge(N, UnitSize, 8, 8); 443} 444 445/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 446/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 447bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 448 if (!isUnary) 449 return isVMerge(N, UnitSize, 0, 16); 450 return isVMerge(N, UnitSize, 0, 0); 451} 452 453 454/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 455/// amount, otherwise return -1. 456int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 457 assert(N->getOpcode() == ISD::BUILD_VECTOR && 458 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 459 // Find the first non-undef value in the shuffle mask. 460 unsigned i; 461 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) 462 /*search*/; 463 464 if (i == 16) return -1; // all undef. 465 466 // Otherwise, check to see if the rest of the elements are consequtively 467 // numbered from this value. 468 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue(); 469 if (ShiftAmt < i) return -1; 470 ShiftAmt -= i; 471 472 if (!isUnary) { 473 // Check the rest of the elements to see if they are consequtive. 474 for (++i; i != 16; ++i) 475 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) 476 return -1; 477 } else { 478 // Check the rest of the elements to see if they are consequtive. 479 for (++i; i != 16; ++i) 480 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) 481 return -1; 482 } 483 484 return ShiftAmt; 485} 486 487/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 488/// specifies a splat of a single element that is suitable for input to 489/// VSPLTB/VSPLTH/VSPLTW. 490bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { 491 assert(N->getOpcode() == ISD::BUILD_VECTOR && 492 N->getNumOperands() == 16 && 493 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 494 495 // This is a splat operation if each element of the permute is the same, and 496 // if the value doesn't reference the second vector. 497 unsigned ElementBase = 0; 498 SDOperand Elt = N->getOperand(0); 499 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) 500 ElementBase = EltV->getValue(); 501 else 502 return false; // FIXME: Handle UNDEF elements too! 503 504 if (cast<ConstantSDNode>(Elt)->getValue() >= 16) 505 return false; 506 507 // Check that they are consequtive. 508 for (unsigned i = 1; i != EltSize; ++i) { 509 if (!isa<ConstantSDNode>(N->getOperand(i)) || 510 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase) 511 return false; 512 } 513 514 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); 515 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 516 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 517 assert(isa<ConstantSDNode>(N->getOperand(i)) && 518 "Invalid VECTOR_SHUFFLE mask!"); 519 for (unsigned j = 0; j != EltSize; ++j) 520 if (N->getOperand(i+j) != N->getOperand(j)) 521 return false; 522 } 523 524 return true; 525} 526 527/// isAllNegativeZeroVector - Returns true if all elements of build_vector 528/// are -0.0. 529bool PPC::isAllNegativeZeroVector(SDNode *N) { 530 assert(N->getOpcode() == ISD::BUILD_VECTOR); 531 if (PPC::isSplatShuffleMask(N, N->getNumOperands())) 532 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N)) 533 return CFP->isExactlyValue(-0.0); 534 return false; 535} 536 537/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 538/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 539unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 540 assert(isSplatShuffleMask(N, EltSize)); 541 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize; 542} 543 544/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 545/// by using a vspltis[bhw] instruction of the specified element size, return 546/// the constant being splatted. The ByteSize field indicates the number of 547/// bytes of each element [124] -> [bhw]. 548SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 549 SDOperand OpVal(0, 0); 550 551 // If ByteSize of the splat is bigger than the element size of the 552 // build_vector, then we have a case where we are checking for a splat where 553 // multiple elements of the buildvector are folded together into a single 554 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 555 unsigned EltSize = 16/N->getNumOperands(); 556 if (EltSize < ByteSize) { 557 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 558 SDOperand UniquedVals[4]; 559 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 560 561 // See if all of the elements in the buildvector agree across. 562 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 563 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 564 // If the element isn't a constant, bail fully out. 565 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand(); 566 567 568 if (UniquedVals[i&(Multiple-1)].Val == 0) 569 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 570 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 571 return SDOperand(); // no match. 572 } 573 574 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 575 // either constant or undef values that are identical for each chunk. See 576 // if these chunks can form into a larger vspltis*. 577 578 // Check to see if all of the leading entries are either 0 or -1. If 579 // neither, then this won't fit into the immediate field. 580 bool LeadingZero = true; 581 bool LeadingOnes = true; 582 for (unsigned i = 0; i != Multiple-1; ++i) { 583 if (UniquedVals[i].Val == 0) continue; // Must have been undefs. 584 585 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 586 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 587 } 588 // Finally, check the least significant entry. 589 if (LeadingZero) { 590 if (UniquedVals[Multiple-1].Val == 0) 591 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 592 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue(); 593 if (Val < 16) 594 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 595 } 596 if (LeadingOnes) { 597 if (UniquedVals[Multiple-1].Val == 0) 598 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 599 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended(); 600 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 601 return DAG.getTargetConstant(Val, MVT::i32); 602 } 603 604 return SDOperand(); 605 } 606 607 // Check to see if this buildvec has a single non-undef value in its elements. 608 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 609 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 610 if (OpVal.Val == 0) 611 OpVal = N->getOperand(i); 612 else if (OpVal != N->getOperand(i)) 613 return SDOperand(); 614 } 615 616 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def. 617 618 unsigned ValSizeInBytes = 0; 619 uint64_t Value = 0; 620 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 621 Value = CN->getValue(); 622 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8; 623 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 624 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 625 Value = FloatToBits(CN->getValue()); 626 ValSizeInBytes = 4; 627 } 628 629 // If the splat value is larger than the element value, then we can never do 630 // this splat. The only case that we could fit the replicated bits into our 631 // immediate field for would be zero, and we prefer to use vxor for it. 632 if (ValSizeInBytes < ByteSize) return SDOperand(); 633 634 // If the element value is larger than the splat value, cut it in half and 635 // check to see if the two halves are equal. Continue doing this until we 636 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 637 while (ValSizeInBytes > ByteSize) { 638 ValSizeInBytes >>= 1; 639 640 // If the top half equals the bottom half, we're still ok. 641 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 642 (Value & ((1 << (8*ValSizeInBytes))-1))) 643 return SDOperand(); 644 } 645 646 // Properly sign extend the value. 647 int ShAmt = (4-ByteSize)*8; 648 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 649 650 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 651 if (MaskVal == 0) return SDOperand(); 652 653 // Finally, if this value fits in a 5 bit sext field, return it 654 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 655 return DAG.getTargetConstant(MaskVal, MVT::i32); 656 return SDOperand(); 657} 658 659//===----------------------------------------------------------------------===// 660// Addressing Mode Selection 661//===----------------------------------------------------------------------===// 662 663/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 664/// or 64-bit immediate, and if the value can be accurately represented as a 665/// sign extension from a 16-bit value. If so, this returns true and the 666/// immediate. 667static bool isIntS16Immediate(SDNode *N, short &Imm) { 668 if (N->getOpcode() != ISD::Constant) 669 return false; 670 671 Imm = (short)cast<ConstantSDNode>(N)->getValue(); 672 if (N->getValueType(0) == MVT::i32) 673 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue(); 674 else 675 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue(); 676} 677static bool isIntS16Immediate(SDOperand Op, short &Imm) { 678 return isIntS16Immediate(Op.Val, Imm); 679} 680 681 682/// SelectAddressRegReg - Given the specified addressed, check to see if it 683/// can be represented as an indexed [r+r] operation. Returns false if it 684/// can be more efficiently represented with [r+imm]. 685bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base, 686 SDOperand &Index, 687 SelectionDAG &DAG) { 688 short imm = 0; 689 if (N.getOpcode() == ISD::ADD) { 690 if (isIntS16Immediate(N.getOperand(1), imm)) 691 return false; // r+i 692 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 693 return false; // r+i 694 695 Base = N.getOperand(0); 696 Index = N.getOperand(1); 697 return true; 698 } else if (N.getOpcode() == ISD::OR) { 699 if (isIntS16Immediate(N.getOperand(1), imm)) 700 return false; // r+i can fold it if we can. 701 702 // If this is an or of disjoint bitfields, we can codegen this as an add 703 // (for better address arithmetic) if the LHS and RHS of the OR are provably 704 // disjoint. 705 uint64_t LHSKnownZero, LHSKnownOne; 706 uint64_t RHSKnownZero, RHSKnownOne; 707 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 708 709 if (LHSKnownZero) { 710 DAG.ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne); 711 // If all of the bits are known zero on the LHS or RHS, the add won't 712 // carry. 713 if ((LHSKnownZero | RHSKnownZero) == ~0U) { 714 Base = N.getOperand(0); 715 Index = N.getOperand(1); 716 return true; 717 } 718 } 719 } 720 721 return false; 722} 723 724/// Returns true if the address N can be represented by a base register plus 725/// a signed 16-bit displacement [r+imm], and if it is not better 726/// represented as reg+reg. 727bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp, 728 SDOperand &Base, SelectionDAG &DAG){ 729 // If this can be more profitably realized as r+r, fail. 730 if (SelectAddressRegReg(N, Disp, Base, DAG)) 731 return false; 732 733 if (N.getOpcode() == ISD::ADD) { 734 short imm = 0; 735 if (isIntS16Immediate(N.getOperand(1), imm)) { 736 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 737 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 738 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 739 } else { 740 Base = N.getOperand(0); 741 } 742 return true; // [r+i] 743 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 744 // Match LOAD (ADD (X, Lo(G))). 745 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 746 && "Cannot handle constant offsets yet!"); 747 Disp = N.getOperand(1).getOperand(0); // The global address. 748 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 749 Disp.getOpcode() == ISD::TargetConstantPool || 750 Disp.getOpcode() == ISD::TargetJumpTable); 751 Base = N.getOperand(0); 752 return true; // [&g+r] 753 } 754 } else if (N.getOpcode() == ISD::OR) { 755 short imm = 0; 756 if (isIntS16Immediate(N.getOperand(1), imm)) { 757 // If this is an or of disjoint bitfields, we can codegen this as an add 758 // (for better address arithmetic) if the LHS and RHS of the OR are 759 // provably disjoint. 760 uint64_t LHSKnownZero, LHSKnownOne; 761 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 762 if ((LHSKnownZero|~(unsigned)imm) == ~0U) { 763 // If all of the bits are known zero on the LHS or RHS, the add won't 764 // carry. 765 Base = N.getOperand(0); 766 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 767 return true; 768 } 769 } 770 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 771 // Loading from a constant address. 772 773 // If this address fits entirely in a 16-bit sext immediate field, codegen 774 // this as "d, 0" 775 short Imm; 776 if (isIntS16Immediate(CN, Imm)) { 777 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 778 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 779 return true; 780 } 781 782 // Handle 32-bit sext immediates with LIS + addr mode. 783 if (CN->getValueType(0) == MVT::i32 || 784 (int64_t)CN->getValue() == (int)CN->getValue()) { 785 int Addr = (int)CN->getValue(); 786 787 // Otherwise, break this down into an LIS + disp. 788 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 789 790 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 791 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 792 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 793 return true; 794 } 795 } 796 797 Disp = DAG.getTargetConstant(0, getPointerTy()); 798 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 799 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 800 else 801 Base = N; 802 return true; // [r+0] 803} 804 805/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 806/// represented as an indexed [r+r] operation. 807bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, 808 SDOperand &Index, 809 SelectionDAG &DAG) { 810 // Check to see if we can easily represent this as an [r+r] address. This 811 // will fail if it thinks that the address is more profitably represented as 812 // reg+imm, e.g. where imm = 0. 813 if (SelectAddressRegReg(N, Base, Index, DAG)) 814 return true; 815 816 // If the operand is an addition, always emit this as [r+r], since this is 817 // better (for code size, and execution, as the memop does the add for free) 818 // than emitting an explicit add. 819 if (N.getOpcode() == ISD::ADD) { 820 Base = N.getOperand(0); 821 Index = N.getOperand(1); 822 return true; 823 } 824 825 // Otherwise, do it the hard way, using R0 as the base register. 826 Base = DAG.getRegister(PPC::R0, N.getValueType()); 827 Index = N; 828 return true; 829} 830 831/// SelectAddressRegImmShift - Returns true if the address N can be 832/// represented by a base register plus a signed 14-bit displacement 833/// [r+imm*4]. Suitable for use by STD and friends. 834bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, 835 SDOperand &Base, 836 SelectionDAG &DAG) { 837 // If this can be more profitably realized as r+r, fail. 838 if (SelectAddressRegReg(N, Disp, Base, DAG)) 839 return false; 840 841 if (N.getOpcode() == ISD::ADD) { 842 short imm = 0; 843 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 844 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 845 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 846 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 847 } else { 848 Base = N.getOperand(0); 849 } 850 return true; // [r+i] 851 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 852 // Match LOAD (ADD (X, Lo(G))). 853 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 854 && "Cannot handle constant offsets yet!"); 855 Disp = N.getOperand(1).getOperand(0); // The global address. 856 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 857 Disp.getOpcode() == ISD::TargetConstantPool || 858 Disp.getOpcode() == ISD::TargetJumpTable); 859 Base = N.getOperand(0); 860 return true; // [&g+r] 861 } 862 } else if (N.getOpcode() == ISD::OR) { 863 short imm = 0; 864 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 865 // If this is an or of disjoint bitfields, we can codegen this as an add 866 // (for better address arithmetic) if the LHS and RHS of the OR are 867 // provably disjoint. 868 uint64_t LHSKnownZero, LHSKnownOne; 869 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 870 if ((LHSKnownZero|~(unsigned)imm) == ~0U) { 871 // If all of the bits are known zero on the LHS or RHS, the add won't 872 // carry. 873 Base = N.getOperand(0); 874 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 875 return true; 876 } 877 } 878 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 879 // Loading from a constant address. Verify low two bits are clear. 880 if ((CN->getValue() & 3) == 0) { 881 // If this address fits entirely in a 14-bit sext immediate field, codegen 882 // this as "d, 0" 883 short Imm; 884 if (isIntS16Immediate(CN, Imm)) { 885 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 886 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 887 return true; 888 } 889 890 // Fold the low-part of 32-bit absolute addresses into addr mode. 891 if (CN->getValueType(0) == MVT::i32 || 892 (int64_t)CN->getValue() == (int)CN->getValue()) { 893 int Addr = (int)CN->getValue(); 894 895 // Otherwise, break this down into an LIS + disp. 896 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 897 898 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 899 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 900 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 901 return true; 902 } 903 } 904 } 905 906 Disp = DAG.getTargetConstant(0, getPointerTy()); 907 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 908 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 909 else 910 Base = N; 911 return true; // [r+0] 912} 913 914 915/// getPreIndexedAddressParts - returns true by value, base pointer and 916/// offset pointer and addressing mode by reference if the node's address 917/// can be legally represented as pre-indexed load / store address. 918bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 919 SDOperand &Offset, 920 ISD::MemIndexedMode &AM, 921 SelectionDAG &DAG) { 922 // Disabled by default for now. 923 if (!EnablePPCPreinc) return false; 924 925 SDOperand Ptr; 926 MVT::ValueType VT; 927 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 928 Ptr = LD->getBasePtr(); 929 VT = LD->getLoadedVT(); 930 931 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 932 ST = ST; 933 Ptr = ST->getBasePtr(); 934 VT = ST->getStoredVT(); 935 } else 936 return false; 937 938 // PowerPC doesn't have preinc load/store instructions for vectors. 939 if (MVT::isVector(VT)) 940 return false; 941 942 // TODO: Check reg+reg first. 943 944 // LDU/STU use reg+imm*4, others use reg+imm. 945 if (VT != MVT::i64) { 946 // reg + imm 947 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 948 return false; 949 } else { 950 // reg + imm * 4. 951 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 952 return false; 953 } 954 955 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 956 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 957 // sext i32 to i64 when addr mode is r+i. 958 if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 && 959 LD->getExtensionType() == ISD::SEXTLOAD && 960 isa<ConstantSDNode>(Offset)) 961 return false; 962 } 963 964 AM = ISD::PRE_INC; 965 return true; 966} 967 968//===----------------------------------------------------------------------===// 969// LowerOperation implementation 970//===----------------------------------------------------------------------===// 971 972static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 973 MVT::ValueType PtrVT = Op.getValueType(); 974 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 975 Constant *C = CP->getConstVal(); 976 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 977 SDOperand Zero = DAG.getConstant(0, PtrVT); 978 979 const TargetMachine &TM = DAG.getTarget(); 980 981 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); 982 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); 983 984 // If this is a non-darwin platform, we don't support non-static relo models 985 // yet. 986 if (TM.getRelocationModel() == Reloc::Static || 987 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 988 // Generate non-pic code that has direct accesses to the constant pool. 989 // The address of the global is just (hi(&g)+lo(&g)). 990 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 991 } 992 993 if (TM.getRelocationModel() == Reloc::PIC_) { 994 // With PIC, the first instruction is actually "GR+hi(&G)". 995 Hi = DAG.getNode(ISD::ADD, PtrVT, 996 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 997 } 998 999 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1000 return Lo; 1001} 1002 1003static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { 1004 MVT::ValueType PtrVT = Op.getValueType(); 1005 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1006 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1007 SDOperand Zero = DAG.getConstant(0, PtrVT); 1008 1009 const TargetMachine &TM = DAG.getTarget(); 1010 1011 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); 1012 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); 1013 1014 // If this is a non-darwin platform, we don't support non-static relo models 1015 // yet. 1016 if (TM.getRelocationModel() == Reloc::Static || 1017 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1018 // Generate non-pic code that has direct accesses to the constant pool. 1019 // The address of the global is just (hi(&g)+lo(&g)). 1020 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1021 } 1022 1023 if (TM.getRelocationModel() == Reloc::PIC_) { 1024 // With PIC, the first instruction is actually "GR+hi(&G)". 1025 Hi = DAG.getNode(ISD::ADD, PtrVT, 1026 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1027 } 1028 1029 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1030 return Lo; 1031} 1032 1033static SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { 1034 assert(0 && "TLS not implemented for PPC."); 1035} 1036 1037static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { 1038 MVT::ValueType PtrVT = Op.getValueType(); 1039 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1040 GlobalValue *GV = GSDN->getGlobal(); 1041 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); 1042 SDOperand Zero = DAG.getConstant(0, PtrVT); 1043 1044 const TargetMachine &TM = DAG.getTarget(); 1045 1046 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); 1047 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); 1048 1049 // If this is a non-darwin platform, we don't support non-static relo models 1050 // yet. 1051 if (TM.getRelocationModel() == Reloc::Static || 1052 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1053 // Generate non-pic code that has direct accesses to globals. 1054 // The address of the global is just (hi(&g)+lo(&g)). 1055 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1056 } 1057 1058 if (TM.getRelocationModel() == Reloc::PIC_) { 1059 // With PIC, the first instruction is actually "GR+hi(&G)". 1060 Hi = DAG.getNode(ISD::ADD, PtrVT, 1061 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1062 } 1063 1064 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1065 1066 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV)) 1067 return Lo; 1068 1069 // If the global is weak or external, we have to go through the lazy 1070 // resolution stub. 1071 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); 1072} 1073 1074static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) { 1075 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1076 1077 // If we're comparing for equality to zero, expose the fact that this is 1078 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1079 // fold the new nodes. 1080 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1081 if (C->isNullValue() && CC == ISD::SETEQ) { 1082 MVT::ValueType VT = Op.getOperand(0).getValueType(); 1083 SDOperand Zext = Op.getOperand(0); 1084 if (VT < MVT::i32) { 1085 VT = MVT::i32; 1086 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); 1087 } 1088 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); 1089 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); 1090 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, 1091 DAG.getConstant(Log2b, MVT::i32)); 1092 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); 1093 } 1094 // Leave comparisons against 0 and -1 alone for now, since they're usually 1095 // optimized. FIXME: revisit this when we can custom lower all setcc 1096 // optimizations. 1097 if (C->isAllOnesValue() || C->isNullValue()) 1098 return SDOperand(); 1099 } 1100 1101 // If we have an integer seteq/setne, turn it into a compare against zero 1102 // by xor'ing the rhs with the lhs, which is faster than setting a 1103 // condition register, reading it back out, and masking the correct bit. The 1104 // normal approach here uses sub to do this instead of xor. Using xor exposes 1105 // the result to other bit-twiddling opportunities. 1106 MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); 1107 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1108 MVT::ValueType VT = Op.getValueType(); 1109 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), 1110 Op.getOperand(1)); 1111 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); 1112 } 1113 return SDOperand(); 1114} 1115 1116static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG, 1117 int VarArgsFrameIndex, 1118 int VarArgsStackOffset, 1119 unsigned VarArgsNumGPR, 1120 unsigned VarArgsNumFPR, 1121 const PPCSubtarget &Subtarget) { 1122 1123 assert(0 && "VAARG in ELF32 ABI not implemented yet!"); 1124} 1125 1126static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 1127 int VarArgsFrameIndex, 1128 int VarArgsStackOffset, 1129 unsigned VarArgsNumGPR, 1130 unsigned VarArgsNumFPR, 1131 const PPCSubtarget &Subtarget) { 1132 1133 if (Subtarget.isMachoABI()) { 1134 // vastart just stores the address of the VarArgsFrameIndex slot into the 1135 // memory location argument. 1136 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1137 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1138 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 1139 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), 1140 SV->getOffset()); 1141 } 1142 1143 // For ELF 32 ABI we follow the layout of the va_list struct. 1144 // We suppose the given va_list is already allocated. 1145 // 1146 // typedef struct { 1147 // char gpr; /* index into the array of 8 GPRs 1148 // * stored in the register save area 1149 // * gpr=0 corresponds to r3, 1150 // * gpr=1 to r4, etc. 1151 // */ 1152 // char fpr; /* index into the array of 8 FPRs 1153 // * stored in the register save area 1154 // * fpr=0 corresponds to f1, 1155 // * fpr=1 to f2, etc. 1156 // */ 1157 // char *overflow_arg_area; 1158 // /* location on stack that holds 1159 // * the next overflow argument 1160 // */ 1161 // char *reg_save_area; 1162 // /* where r3:r10 and f1:f8 (if saved) 1163 // * are stored 1164 // */ 1165 // } va_list[1]; 1166 1167 1168 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8); 1169 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8); 1170 1171 1172 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1173 1174 SDOperand StackOffset = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); 1175 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1176 1177 SDOperand ConstFrameOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, 1178 PtrVT); 1179 SDOperand ConstStackOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8 - 1, 1180 PtrVT); 1181 SDOperand ConstFPROffset = DAG.getConstant(1, PtrVT); 1182 1183 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 1184 1185 // Store first byte : number of int regs 1186 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, 1187 Op.getOperand(1), SV->getValue(), 1188 SV->getOffset()); 1189 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), 1190 ConstFPROffset); 1191 1192 // Store second byte : number of float regs 1193 SDOperand secondStore = DAG.getStore(firstStore, ArgFPR, nextPtr, 1194 SV->getValue(), SV->getOffset()); 1195 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset); 1196 1197 // Store second word : arguments given on stack 1198 SDOperand thirdStore = DAG.getStore(secondStore, StackOffset, nextPtr, 1199 SV->getValue(), SV->getOffset()); 1200 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset); 1201 1202 // Store third word : arguments given in registers 1203 return DAG.getStore(thirdStore, FR, nextPtr, SV->getValue(), 1204 SV->getOffset()); 1205 1206} 1207 1208#include "PPCGenCallingConv.inc" 1209 1210/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1211/// depending on which subtarget is selected. 1212static const unsigned *GetFPR(const PPCSubtarget &Subtarget) { 1213 if (Subtarget.isMachoABI()) { 1214 static const unsigned FPR[] = { 1215 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1216 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1217 }; 1218 return FPR; 1219 } 1220 1221 1222 static const unsigned FPR[] = { 1223 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1224 PPC::F8 1225 }; 1226 return FPR; 1227} 1228 1229static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, 1230 int &VarArgsFrameIndex, 1231 int &VarArgsStackOffset, 1232 unsigned &VarArgsNumGPR, 1233 unsigned &VarArgsNumFPR, 1234 const PPCSubtarget &Subtarget) { 1235 // TODO: add description of PPC stack frame format, or at least some docs. 1236 // 1237 MachineFunction &MF = DAG.getMachineFunction(); 1238 MachineFrameInfo *MFI = MF.getFrameInfo(); 1239 SSARegMap *RegMap = MF.getSSARegMap(); 1240 SmallVector<SDOperand, 8> ArgValues; 1241 SDOperand Root = Op.getOperand(0); 1242 1243 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1244 bool isPPC64 = PtrVT == MVT::i64; 1245 bool isMachoABI = Subtarget.isMachoABI(); 1246 bool isELF32_ABI = Subtarget.isELF32_ABI(); 1247 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1248 1249 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1250 1251 static const unsigned GPR_32[] = { // 32-bit registers. 1252 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1253 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1254 }; 1255 static const unsigned GPR_64[] = { // 64-bit registers. 1256 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1257 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1258 }; 1259 1260 static const unsigned *FPR = GetFPR(Subtarget); 1261 1262 static const unsigned VR[] = { 1263 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1264 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1265 }; 1266 1267 const unsigned Num_GPR_Regs = sizeof(GPR_32)/sizeof(GPR_32[0]); 1268 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8; 1269 const unsigned Num_VR_Regs = sizeof( VR)/sizeof( VR[0]); 1270 1271 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1272 1273 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1274 1275 // Add DAG nodes to load the arguments or copy them out of registers. On 1276 // entry to a function on PPC, the arguments start after the linkage area, 1277 // although the first ones are often in registers. 1278 // 1279 // In the ELF 32 ABI, GPRs and stack are double word align: an argument 1280 // represented with two words (long long or double) must be copied to an 1281 // even GPR_idx value or to an even ArgOffset value. 1282 1283 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { 1284 SDOperand ArgVal; 1285 bool needsLoad = false; 1286 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); 1287 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; 1288 unsigned ArgSize = ObjSize; 1289 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue(); 1290 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs; 1291 // See if next argument requires stack alignment in ELF 1292 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) && 1293 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) && 1294 (!(Flags & AlignFlag))); 1295 1296 unsigned CurArgOffset = ArgOffset; 1297 switch (ObjectVT) { 1298 default: assert(0 && "Unhandled argument type!"); 1299 case MVT::i32: 1300 // Double word align in ELF 1301 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2); 1302 if (GPR_idx != Num_GPR_Regs) { 1303 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1304 MF.addLiveIn(GPR[GPR_idx], VReg); 1305 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1306 ++GPR_idx; 1307 } else { 1308 needsLoad = true; 1309 ArgSize = PtrByteSize; 1310 } 1311 // Stack align in ELF 1312 if (needsLoad && Expand && isELF32_ABI) 1313 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1314 // All int arguments reserve stack space in Macho ABI. 1315 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize; 1316 break; 1317 1318 case MVT::i64: // PPC64 1319 if (GPR_idx != Num_GPR_Regs) { 1320 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass); 1321 MF.addLiveIn(GPR[GPR_idx], VReg); 1322 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); 1323 ++GPR_idx; 1324 } else { 1325 needsLoad = true; 1326 } 1327 // All int arguments reserve stack space in Macho ABI. 1328 if (isMachoABI || needsLoad) ArgOffset += 8; 1329 break; 1330 1331 case MVT::f32: 1332 case MVT::f64: 1333 // Every 4 bytes of argument space consumes one of the GPRs available for 1334 // argument passing. 1335 if (GPR_idx != Num_GPR_Regs && isMachoABI) { 1336 ++GPR_idx; 1337 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 1338 ++GPR_idx; 1339 } 1340 if (FPR_idx != Num_FPR_Regs) { 1341 unsigned VReg; 1342 if (ObjectVT == MVT::f32) 1343 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); 1344 else 1345 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 1346 MF.addLiveIn(FPR[FPR_idx], VReg); 1347 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1348 ++FPR_idx; 1349 } else { 1350 needsLoad = true; 1351 } 1352 1353 // Stack align in ELF 1354 if (needsLoad && Expand && isELF32_ABI) 1355 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1356 // All FP arguments reserve stack space in Macho ABI. 1357 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize; 1358 break; 1359 case MVT::v4f32: 1360 case MVT::v4i32: 1361 case MVT::v8i16: 1362 case MVT::v16i8: 1363 // Note that vector arguments in registers don't reserve stack space. 1364 if (VR_idx != Num_VR_Regs) { 1365 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass); 1366 MF.addLiveIn(VR[VR_idx], VReg); 1367 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1368 ++VR_idx; 1369 } else { 1370 // This should be simple, but requires getting 16-byte aligned stack 1371 // values. 1372 assert(0 && "Loading VR argument not implemented yet!"); 1373 needsLoad = true; 1374 } 1375 break; 1376 } 1377 1378 // We need to load the argument to a virtual register if we determined above 1379 // that we ran out of physical registers of the appropriate type 1380 if (needsLoad) { 1381 // If the argument is actually used, emit a load from the right stack 1382 // slot. 1383 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { 1384 int FI = MFI->CreateFixedObject(ObjSize, 1385 CurArgOffset + (ArgSize - ObjSize)); 1386 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); 1387 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 1388 } else { 1389 // Don't emit a dead load. 1390 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT); 1391 } 1392 } 1393 1394 ArgValues.push_back(ArgVal); 1395 } 1396 1397 // If the function takes variable number of arguments, make a frame index for 1398 // the start of the first vararg value... for expansion of llvm.va_start. 1399 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1400 if (isVarArg) { 1401 1402 int depth; 1403 if (isELF32_ABI) { 1404 VarArgsNumGPR = GPR_idx; 1405 VarArgsNumFPR = FPR_idx; 1406 1407 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame 1408 // pointer. 1409 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 + 1410 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 + 1411 MVT::getSizeInBits(PtrVT)/8); 1412 1413 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, 1414 ArgOffset); 1415 1416 } 1417 else 1418 depth = ArgOffset; 1419 1420 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, 1421 depth); 1422 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1423 1424 SmallVector<SDOperand, 8> MemOps; 1425 1426 // In ELF 32 ABI, the fixed integer arguments of a variadic function are 1427 // stored to the VarArgsFrameIndex on the stack. 1428 if (isELF32_ABI) { 1429 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) { 1430 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT); 1431 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); 1432 MemOps.push_back(Store); 1433 // Increment the address by four for the next argument to store 1434 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); 1435 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1436 } 1437 } 1438 1439 // If this function is vararg, store any remaining integer argument regs 1440 // to their spots on the stack so that they may be loaded by deferencing the 1441 // result of va_next. 1442 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 1443 unsigned VReg; 1444 if (isPPC64) 1445 VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass); 1446 else 1447 VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1448 1449 MF.addLiveIn(GPR[GPR_idx], VReg); 1450 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 1451 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1452 MemOps.push_back(Store); 1453 // Increment the address by four for the next argument to store 1454 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); 1455 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1456 } 1457 1458 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex 1459 // on the stack. 1460 if (isELF32_ABI) { 1461 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) { 1462 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64); 1463 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); 1464 MemOps.push_back(Store); 1465 // Increment the address by eight for the next argument to store 1466 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, 1467 PtrVT); 1468 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1469 } 1470 1471 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) { 1472 unsigned VReg; 1473 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 1474 1475 MF.addLiveIn(FPR[FPR_idx], VReg); 1476 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64); 1477 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1478 MemOps.push_back(Store); 1479 // Increment the address by eight for the next argument to store 1480 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, 1481 PtrVT); 1482 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1483 } 1484 } 1485 1486 if (!MemOps.empty()) 1487 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); 1488 } 1489 1490 ArgValues.push_back(Root); 1491 1492 // Return the new list of results. 1493 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 1494 Op.Val->value_end()); 1495 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); 1496} 1497 1498/// isCallCompatibleAddress - Return the immediate to use if the specified 1499/// 32-bit value is representable in the immediate field of a BxA instruction. 1500static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) { 1501 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1502 if (!C) return 0; 1503 1504 int Addr = C->getValue(); 1505 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 1506 (Addr << 6 >> 6) != Addr) 1507 return 0; // Top 6 bits have to be sext of immediate. 1508 1509 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val; 1510} 1511 1512 1513static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG, 1514 const PPCSubtarget &Subtarget) { 1515 SDOperand Chain = Op.getOperand(0); 1516 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1517 SDOperand Callee = Op.getOperand(4); 1518 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 1519 1520 bool isMachoABI = Subtarget.isMachoABI(); 1521 bool isELF32_ABI = Subtarget.isELF32_ABI(); 1522 1523 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1524 bool isPPC64 = PtrVT == MVT::i64; 1525 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1526 1527 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in 1528 // SelectExpr to use to put the arguments in the appropriate registers. 1529 std::vector<SDOperand> args_to_use; 1530 1531 // Count how many bytes are to be pushed on the stack, including the linkage 1532 // area, and parameter passing area. We start with 24/48 bytes, which is 1533 // prereserved space for [SP][CR][LR][3 x unused]. 1534 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1535 1536 // Add up all the space actually used. 1537 for (unsigned i = 0; i != NumOps; ++i) { 1538 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8; 1539 ArgSize = std::max(ArgSize, PtrByteSize); 1540 NumBytes += ArgSize; 1541 } 1542 1543 // The prolog code of the callee may store up to 8 GPR argument registers to 1544 // the stack, allowing va_start to index over them in memory if its varargs. 1545 // Because we cannot tell if this is needed on the caller side, we have to 1546 // conservatively assume that it is needed. As such, make sure we have at 1547 // least enough stack space for the caller to store the 8 GPRs. 1548 NumBytes = std::max(NumBytes, 1549 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI)); 1550 1551 // Adjust the stack pointer for the new arguments... 1552 // These operations are automatically eliminated by the prolog/epilog pass 1553 Chain = DAG.getCALLSEQ_START(Chain, 1554 DAG.getConstant(NumBytes, PtrVT)); 1555 1556 // Set up a copy of the stack pointer for use loading and storing any 1557 // arguments that may not fit in the registers available for argument 1558 // passing. 1559 SDOperand StackPtr; 1560 if (isPPC64) 1561 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 1562 else 1563 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 1564 1565 // Figure out which arguments are going to go in registers, and which in 1566 // memory. Also, if this is a vararg function, floating point operations 1567 // must be stored to our stack, and loaded into integer regs as well, if 1568 // any integer regs are available for argument passing. 1569 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1570 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1571 1572 static const unsigned GPR_32[] = { // 32-bit registers. 1573 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1574 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1575 }; 1576 static const unsigned GPR_64[] = { // 64-bit registers. 1577 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1578 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1579 }; 1580 static const unsigned *FPR = GetFPR(Subtarget); 1581 1582 static const unsigned VR[] = { 1583 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1584 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1585 }; 1586 const unsigned NumGPRs = sizeof(GPR_32)/sizeof(GPR_32[0]); 1587 const unsigned NumFPRs = isMachoABI ? 13 : 8; 1588 const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]); 1589 1590 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1591 1592 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 1593 SmallVector<SDOperand, 8> MemOpChains; 1594 for (unsigned i = 0; i != NumOps; ++i) { 1595 bool inMem = false; 1596 SDOperand Arg = Op.getOperand(5+2*i); 1597 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue(); 1598 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs; 1599 // See if next argument requires stack alignment in ELF 1600 unsigned next = 5+2*(i+1)+1; 1601 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) && 1602 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) && 1603 (!(Flags & AlignFlag))); 1604 1605 // PtrOff will be used to store the current argument to the stack if a 1606 // register cannot be found for it. 1607 SDOperand PtrOff; 1608 1609 // Stack align in ELF 32 1610 if (isELF32_ABI && Expand) 1611 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize, 1612 StackPtr.getValueType()); 1613 else 1614 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 1615 1616 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); 1617 1618 // On PPC64, promote integers to 64-bit values. 1619 if (isPPC64 && Arg.getValueType() == MVT::i32) { 1620 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 1621 1622 Arg = DAG.getNode(ExtOp, MVT::i64, Arg); 1623 } 1624 1625 switch (Arg.getValueType()) { 1626 default: assert(0 && "Unexpected ValueType for argument!"); 1627 case MVT::i32: 1628 case MVT::i64: 1629 // Double word align in ELF 1630 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2); 1631 if (GPR_idx != NumGPRs) { 1632 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 1633 } else { 1634 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1635 inMem = true; 1636 } 1637 if (inMem || isMachoABI) { 1638 // Stack align in ELF 1639 if (isELF32_ABI && Expand) 1640 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1641 1642 ArgOffset += PtrByteSize; 1643 } 1644 break; 1645 case MVT::f32: 1646 case MVT::f64: 1647 if (isVarArg) { 1648 // Float varargs need to be promoted to double. 1649 if (Arg.getValueType() == MVT::f32) 1650 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg); 1651 } 1652 1653 if (FPR_idx != NumFPRs) { 1654 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 1655 1656 if (isVarArg) { 1657 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); 1658 MemOpChains.push_back(Store); 1659 1660 // Float varargs are always shadowed in available integer registers 1661 if (GPR_idx != NumGPRs) { 1662 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1663 MemOpChains.push_back(Load.getValue(1)); 1664 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 1665 Load)); 1666 } 1667 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 1668 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 1669 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); 1670 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1671 MemOpChains.push_back(Load.getValue(1)); 1672 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 1673 Load)); 1674 } 1675 } else { 1676 // If we have any FPRs remaining, we may also have GPRs remaining. 1677 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 1678 // GPRs. 1679 if (isMachoABI) { 1680 if (GPR_idx != NumGPRs) 1681 ++GPR_idx; 1682 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 1683 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 1684 ++GPR_idx; 1685 } 1686 } 1687 } else { 1688 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1689 inMem = true; 1690 } 1691 if (inMem || isMachoABI) { 1692 // Stack align in ELF 1693 if (isELF32_ABI && Expand) 1694 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1695 if (isPPC64) 1696 ArgOffset += 8; 1697 else 1698 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 1699 } 1700 break; 1701 case MVT::v4f32: 1702 case MVT::v4i32: 1703 case MVT::v8i16: 1704 case MVT::v16i8: 1705 assert(!isVarArg && "Don't support passing vectors to varargs yet!"); 1706 assert(VR_idx != NumVRs && 1707 "Don't support passing more than 12 vector args yet!"); 1708 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 1709 break; 1710 } 1711 } 1712 if (!MemOpChains.empty()) 1713 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1714 &MemOpChains[0], MemOpChains.size()); 1715 1716 // Build a sequence of copy-to-reg nodes chained together with token chain 1717 // and flag operands which copy the outgoing args into the appropriate regs. 1718 SDOperand InFlag; 1719 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1720 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1721 InFlag); 1722 InFlag = Chain.getValue(1); 1723 } 1724 1725 // With the ELF 32 ABI, set CR6 to true if this is a vararg call. 1726 if (isVarArg && isELF32_ABI) { 1727 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0); 1728 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag); 1729 InFlag = Chain.getValue(1); 1730 } 1731 1732 std::vector<MVT::ValueType> NodeTys; 1733 NodeTys.push_back(MVT::Other); // Returns a chain 1734 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 1735 1736 SmallVector<SDOperand, 8> Ops; 1737 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF; 1738 1739 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1740 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1741 // node so that legalize doesn't hack it. 1742 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1743 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); 1744 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 1745 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); 1746 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) 1747 // If this is an absolute destination address, use the munged value. 1748 Callee = SDOperand(Dest, 0); 1749 else { 1750 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 1751 // to do the call, we can't use PPCISD::CALL. 1752 SDOperand MTCTROps[] = {Chain, Callee, InFlag}; 1753 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0)); 1754 InFlag = Chain.getValue(1); 1755 1756 // Copy the callee address into R12 on darwin. 1757 if (isMachoABI) { 1758 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag); 1759 InFlag = Chain.getValue(1); 1760 } 1761 1762 NodeTys.clear(); 1763 NodeTys.push_back(MVT::Other); 1764 NodeTys.push_back(MVT::Flag); 1765 Ops.push_back(Chain); 1766 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF; 1767 Callee.Val = 0; 1768 } 1769 1770 // If this is a direct call, pass the chain and the callee. 1771 if (Callee.Val) { 1772 Ops.push_back(Chain); 1773 Ops.push_back(Callee); 1774 } 1775 1776 // Add argument registers to the end of the list so that they are known live 1777 // into the call. 1778 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1779 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1780 RegsToPass[i].second.getValueType())); 1781 1782 if (InFlag.Val) 1783 Ops.push_back(InFlag); 1784 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 1785 InFlag = Chain.getValue(1); 1786 1787 SDOperand ResultVals[3]; 1788 unsigned NumResults = 0; 1789 NodeTys.clear(); 1790 1791 // If the call has results, copy the values out of the ret val registers. 1792 switch (Op.Val->getValueType(0)) { 1793 default: assert(0 && "Unexpected ret value!"); 1794 case MVT::Other: break; 1795 case MVT::i32: 1796 if (Op.Val->getValueType(1) == MVT::i32) { 1797 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); 1798 ResultVals[0] = Chain.getValue(0); 1799 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, 1800 Chain.getValue(2)).getValue(1); 1801 ResultVals[1] = Chain.getValue(0); 1802 NumResults = 2; 1803 NodeTys.push_back(MVT::i32); 1804 } else { 1805 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); 1806 ResultVals[0] = Chain.getValue(0); 1807 NumResults = 1; 1808 } 1809 NodeTys.push_back(MVT::i32); 1810 break; 1811 case MVT::i64: 1812 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1); 1813 ResultVals[0] = Chain.getValue(0); 1814 NumResults = 1; 1815 NodeTys.push_back(MVT::i64); 1816 break; 1817 case MVT::f32: 1818 case MVT::f64: 1819 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0), 1820 InFlag).getValue(1); 1821 ResultVals[0] = Chain.getValue(0); 1822 NumResults = 1; 1823 NodeTys.push_back(Op.Val->getValueType(0)); 1824 break; 1825 case MVT::v4f32: 1826 case MVT::v4i32: 1827 case MVT::v8i16: 1828 case MVT::v16i8: 1829 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0), 1830 InFlag).getValue(1); 1831 ResultVals[0] = Chain.getValue(0); 1832 NumResults = 1; 1833 NodeTys.push_back(Op.Val->getValueType(0)); 1834 break; 1835 } 1836 1837 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 1838 DAG.getConstant(NumBytes, PtrVT)); 1839 NodeTys.push_back(MVT::Other); 1840 1841 // If the function returns void, just return the chain. 1842 if (NumResults == 0) 1843 return Chain; 1844 1845 // Otherwise, merge everything together with a MERGE_VALUES node. 1846 ResultVals[NumResults++] = Chain; 1847 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, 1848 ResultVals, NumResults); 1849 return Res.getValue(Op.ResNo); 1850} 1851 1852static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) { 1853 SmallVector<CCValAssign, 16> RVLocs; 1854 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 1855 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1856 CCState CCInfo(CC, isVarArg, TM, RVLocs); 1857 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC); 1858 1859 // If this is the first return lowered for this function, add the regs to the 1860 // liveout set for the function. 1861 if (DAG.getMachineFunction().liveout_empty()) { 1862 for (unsigned i = 0; i != RVLocs.size(); ++i) 1863 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg()); 1864 } 1865 1866 SDOperand Chain = Op.getOperand(0); 1867 SDOperand Flag; 1868 1869 // Copy the result values into the output registers. 1870 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1871 CCValAssign &VA = RVLocs[i]; 1872 assert(VA.isRegLoc() && "Can only return in registers!"); 1873 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); 1874 Flag = Chain.getValue(1); 1875 } 1876 1877 if (Flag.Val) 1878 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag); 1879 else 1880 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain); 1881} 1882 1883static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, 1884 const PPCSubtarget &Subtarget) { 1885 // When we pop the dynamic allocation we need to restore the SP link. 1886 1887 // Get the corect type for pointers. 1888 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1889 1890 // Construct the stack pointer operand. 1891 bool IsPPC64 = Subtarget.isPPC64(); 1892 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1; 1893 SDOperand StackPtr = DAG.getRegister(SP, PtrVT); 1894 1895 // Get the operands for the STACKRESTORE. 1896 SDOperand Chain = Op.getOperand(0); 1897 SDOperand SaveSP = Op.getOperand(1); 1898 1899 // Load the old link SP. 1900 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0); 1901 1902 // Restore the stack pointer. 1903 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP); 1904 1905 // Store the old link SP. 1906 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0); 1907} 1908 1909static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG, 1910 const PPCSubtarget &Subtarget) { 1911 MachineFunction &MF = DAG.getMachineFunction(); 1912 bool IsPPC64 = Subtarget.isPPC64(); 1913 bool isMachoABI = Subtarget.isMachoABI(); 1914 1915 // Get current frame pointer save index. The users of this index will be 1916 // primarily DYNALLOC instructions. 1917 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1918 int FPSI = FI->getFramePointerSaveIndex(); 1919 1920 // If the frame pointer save index hasn't been defined yet. 1921 if (!FPSI) { 1922 // Find out what the fix offset of the frame pointer save area. 1923 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI); 1924 1925 // Allocate the frame index for frame pointer save area. 1926 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 1927 // Save the result. 1928 FI->setFramePointerSaveIndex(FPSI); 1929 } 1930 1931 // Get the inputs. 1932 SDOperand Chain = Op.getOperand(0); 1933 SDOperand Size = Op.getOperand(1); 1934 1935 // Get the corect type for pointers. 1936 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1937 // Negate the size. 1938 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT, 1939 DAG.getConstant(0, PtrVT), Size); 1940 // Construct a node for the frame pointer save index. 1941 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT); 1942 // Build a DYNALLOC node. 1943 SDOperand Ops[3] = { Chain, NegSize, FPSIdx }; 1944 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 1945 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3); 1946} 1947 1948 1949/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 1950/// possible. 1951static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { 1952 // Not FP? Not a fsel. 1953 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 1954 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 1955 return SDOperand(); 1956 1957 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1958 1959 // Cannot handle SETEQ/SETNE. 1960 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand(); 1961 1962 MVT::ValueType ResVT = Op.getValueType(); 1963 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 1964 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 1965 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 1966 1967 // If the RHS of the comparison is a 0.0, we don't need to do the 1968 // subtraction at all. 1969 if (isFloatingPointZero(RHS)) 1970 switch (CC) { 1971 default: break; // SETUO etc aren't handled by fsel. 1972 case ISD::SETULT: 1973 case ISD::SETOLT: 1974 case ISD::SETLT: 1975 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 1976 case ISD::SETUGE: 1977 case ISD::SETOGE: 1978 case ISD::SETGE: 1979 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 1980 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 1981 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 1982 case ISD::SETUGT: 1983 case ISD::SETOGT: 1984 case ISD::SETGT: 1985 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 1986 case ISD::SETULE: 1987 case ISD::SETOLE: 1988 case ISD::SETLE: 1989 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 1990 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 1991 return DAG.getNode(PPCISD::FSEL, ResVT, 1992 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 1993 } 1994 1995 SDOperand Cmp; 1996 switch (CC) { 1997 default: break; // SETUO etc aren't handled by fsel. 1998 case ISD::SETULT: 1999 case ISD::SETOLT: 2000 case ISD::SETLT: 2001 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2002 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2003 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2004 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2005 case ISD::SETUGE: 2006 case ISD::SETOGE: 2007 case ISD::SETGE: 2008 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2009 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2010 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2011 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2012 case ISD::SETUGT: 2013 case ISD::SETOGT: 2014 case ISD::SETGT: 2015 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2016 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2017 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2018 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2019 case ISD::SETULE: 2020 case ISD::SETOLE: 2021 case ISD::SETLE: 2022 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2023 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2024 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2025 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2026 } 2027 return SDOperand(); 2028} 2029 2030static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 2031 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 2032 SDOperand Src = Op.getOperand(0); 2033 if (Src.getValueType() == MVT::f32) 2034 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 2035 2036 SDOperand Tmp; 2037 switch (Op.getValueType()) { 2038 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 2039 case MVT::i32: 2040 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 2041 break; 2042 case MVT::i64: 2043 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 2044 break; 2045 } 2046 2047 // Convert the FP value to an int value through memory. 2048 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp); 2049 if (Op.getValueType() == MVT::i32) 2050 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits); 2051 return Bits; 2052} 2053 2054static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 2055 if (Op.getOperand(0).getValueType() == MVT::i64) { 2056 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 2057 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 2058 if (Op.getValueType() == MVT::f32) 2059 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 2060 return FP; 2061 } 2062 2063 assert(Op.getOperand(0).getValueType() == MVT::i32 && 2064 "Unhandled SINT_TO_FP type in custom expander!"); 2065 // Since we only generate this in 64-bit mode, we can take advantage of 2066 // 64-bit registers. In particular, sign extend the input value into the 2067 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 2068 // then lfd it and fcfid it. 2069 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2070 int FrameIdx = FrameInfo->CreateStackObject(8, 8); 2071 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2072 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2073 2074 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, 2075 Op.getOperand(0)); 2076 2077 // STD the extended value into the stack slot. 2078 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, 2079 DAG.getEntryNode(), Ext64, FIdx, 2080 DAG.getSrcValue(NULL)); 2081 // Load the value as a double. 2082 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); 2083 2084 // FCFID it and return it. 2085 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); 2086 if (Op.getValueType() == MVT::f32) 2087 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 2088 return FP; 2089} 2090 2091static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { 2092 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2093 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 2094 2095 // Expand into a bunch of logical ops. Note that these ops 2096 // depend on the PPC behavior for oversized shift amounts. 2097 SDOperand Lo = Op.getOperand(0); 2098 SDOperand Hi = Op.getOperand(1); 2099 SDOperand Amt = Op.getOperand(2); 2100 2101 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 2102 DAG.getConstant(32, MVT::i32), Amt); 2103 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); 2104 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); 2105 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 2106 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 2107 DAG.getConstant(-32U, MVT::i32)); 2108 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); 2109 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 2110 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); 2111 SDOperand OutOps[] = { OutLo, OutHi }; 2112 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 2113 OutOps, 2); 2114} 2115 2116static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { 2117 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2118 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!"); 2119 2120 // Otherwise, expand into a bunch of logical ops. Note that these ops 2121 // depend on the PPC behavior for oversized shift amounts. 2122 SDOperand Lo = Op.getOperand(0); 2123 SDOperand Hi = Op.getOperand(1); 2124 SDOperand Amt = Op.getOperand(2); 2125 2126 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 2127 DAG.getConstant(32, MVT::i32), Amt); 2128 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 2129 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 2130 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 2131 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 2132 DAG.getConstant(-32U, MVT::i32)); 2133 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); 2134 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 2135 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); 2136 SDOperand OutOps[] = { OutLo, OutHi }; 2137 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 2138 OutOps, 2); 2139} 2140 2141static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { 2142 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2143 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 2144 2145 // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 2146 SDOperand Lo = Op.getOperand(0); 2147 SDOperand Hi = Op.getOperand(1); 2148 SDOperand Amt = Op.getOperand(2); 2149 2150 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 2151 DAG.getConstant(32, MVT::i32), Amt); 2152 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 2153 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 2154 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 2155 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 2156 DAG.getConstant(-32U, MVT::i32)); 2157 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); 2158 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); 2159 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 2160 Tmp4, Tmp6, ISD::SETLE); 2161 SDOperand OutOps[] = { OutLo, OutHi }; 2162 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 2163 OutOps, 2); 2164} 2165 2166//===----------------------------------------------------------------------===// 2167// Vector related lowering. 2168// 2169 2170// If this is a vector of constants or undefs, get the bits. A bit in 2171// UndefBits is set if the corresponding element of the vector is an 2172// ISD::UNDEF value. For undefs, the corresponding VectorBits values are 2173// zero. Return true if this is not an array of constants, false if it is. 2174// 2175static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], 2176 uint64_t UndefBits[2]) { 2177 // Start with zero'd results. 2178 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; 2179 2180 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType()); 2181 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 2182 SDOperand OpVal = BV->getOperand(i); 2183 2184 unsigned PartNo = i >= e/2; // In the upper 128 bits? 2185 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. 2186 2187 uint64_t EltBits = 0; 2188 if (OpVal.getOpcode() == ISD::UNDEF) { 2189 uint64_t EltUndefBits = ~0U >> (32-EltBitSize); 2190 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); 2191 continue; 2192 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 2193 EltBits = CN->getValue() & (~0U >> (32-EltBitSize)); 2194 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 2195 assert(CN->getValueType(0) == MVT::f32 && 2196 "Only one legal FP vector type!"); 2197 EltBits = FloatToBits(CN->getValue()); 2198 } else { 2199 // Nonconstant element. 2200 return true; 2201 } 2202 2203 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); 2204 } 2205 2206 //printf("%llx %llx %llx %llx\n", 2207 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); 2208 return false; 2209} 2210 2211// If this is a splat (repetition) of a value across the whole vector, return 2212// the smallest size that splats it. For example, "0x01010101010101..." is a 2213// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 2214// SplatSize = 1 byte. 2215static bool isConstantSplat(const uint64_t Bits128[2], 2216 const uint64_t Undef128[2], 2217 unsigned &SplatBits, unsigned &SplatUndef, 2218 unsigned &SplatSize) { 2219 2220 // Don't let undefs prevent splats from matching. See if the top 64-bits are 2221 // the same as the lower 64-bits, ignoring undefs. 2222 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0])) 2223 return false; // Can't be a splat if two pieces don't match. 2224 2225 uint64_t Bits64 = Bits128[0] | Bits128[1]; 2226 uint64_t Undef64 = Undef128[0] & Undef128[1]; 2227 2228 // Check that the top 32-bits are the same as the lower 32-bits, ignoring 2229 // undefs. 2230 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64)) 2231 return false; // Can't be a splat if two pieces don't match. 2232 2233 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32); 2234 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32); 2235 2236 // If the top 16-bits are different than the lower 16-bits, ignoring 2237 // undefs, we have an i32 splat. 2238 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) { 2239 SplatBits = Bits32; 2240 SplatUndef = Undef32; 2241 SplatSize = 4; 2242 return true; 2243 } 2244 2245 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16); 2246 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16); 2247 2248 // If the top 8-bits are different than the lower 8-bits, ignoring 2249 // undefs, we have an i16 splat. 2250 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) { 2251 SplatBits = Bits16; 2252 SplatUndef = Undef16; 2253 SplatSize = 2; 2254 return true; 2255 } 2256 2257 // Otherwise, we have an 8-bit splat. 2258 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); 2259 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); 2260 SplatSize = 1; 2261 return true; 2262} 2263 2264/// BuildSplatI - Build a canonical splati of Val with an element size of 2265/// SplatSize. Cast the result to VT. 2266static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT, 2267 SelectionDAG &DAG) { 2268 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 2269 2270 static const MVT::ValueType VTys[] = { // canonical VT to use for each size. 2271 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 2272 }; 2273 2274 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 2275 2276 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 2277 if (Val == -1) 2278 SplatSize = 1; 2279 2280 MVT::ValueType CanonicalVT = VTys[SplatSize-1]; 2281 2282 // Build a canonical splat for this value. 2283 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT)); 2284 SmallVector<SDOperand, 8> Ops; 2285 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt); 2286 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, 2287 &Ops[0], Ops.size()); 2288 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res); 2289} 2290 2291/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 2292/// specified intrinsic ID. 2293static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS, 2294 SelectionDAG &DAG, 2295 MVT::ValueType DestVT = MVT::Other) { 2296 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 2297 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 2298 DAG.getConstant(IID, MVT::i32), LHS, RHS); 2299} 2300 2301/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 2302/// specified intrinsic ID. 2303static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1, 2304 SDOperand Op2, SelectionDAG &DAG, 2305 MVT::ValueType DestVT = MVT::Other) { 2306 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 2307 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 2308 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 2309} 2310 2311 2312/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 2313/// amount. The result has the specified value type. 2314static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt, 2315 MVT::ValueType VT, SelectionDAG &DAG) { 2316 // Force LHS/RHS to be the right type. 2317 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); 2318 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); 2319 2320 SDOperand Ops[16]; 2321 for (unsigned i = 0; i != 16; ++i) 2322 Ops[i] = DAG.getConstant(i+Amt, MVT::i32); 2323 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, 2324 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16)); 2325 return DAG.getNode(ISD::BIT_CONVERT, VT, T); 2326} 2327 2328// If this is a case we can't handle, return null and let the default 2329// expansion code take care of it. If we CAN select this case, and if it 2330// selects to a single instruction, return Op. Otherwise, if we can codegen 2331// this case more efficiently than a constant pool load, lower it to the 2332// sequence of ops that should be used. 2333static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2334 // If this is a vector of constants or undefs, get the bits. A bit in 2335 // UndefBits is set if the corresponding element of the vector is an 2336 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are 2337 // zero. 2338 uint64_t VectorBits[2]; 2339 uint64_t UndefBits[2]; 2340 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) 2341 return SDOperand(); // Not a constant vector. 2342 2343 // If this is a splat (repetition) of a value across the whole vector, return 2344 // the smallest size that splats it. For example, "0x01010101010101..." is a 2345 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 2346 // SplatSize = 1 byte. 2347 unsigned SplatBits, SplatUndef, SplatSize; 2348 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){ 2349 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0; 2350 2351 // First, handle single instruction cases. 2352 2353 // All zeros? 2354 if (SplatBits == 0) { 2355 // Canonicalize all zero vectors to be v4i32. 2356 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 2357 SDOperand Z = DAG.getConstant(0, MVT::i32); 2358 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); 2359 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); 2360 } 2361 return Op; 2362 } 2363 2364 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 2365 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); 2366 if (SextVal >= -16 && SextVal <= 15) 2367 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG); 2368 2369 2370 // Two instruction sequences. 2371 2372 // If this value is in the range [-32,30] and is even, use: 2373 // tmp = VSPLTI[bhw], result = add tmp, tmp 2374 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 2375 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG); 2376 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op); 2377 } 2378 2379 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 2380 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 2381 // for fneg/fabs. 2382 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 2383 // Make -1 and vspltisw -1: 2384 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); 2385 2386 // Make the VSLW intrinsic, computing 0x8000_0000. 2387 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 2388 OnesV, DAG); 2389 2390 // xor by OnesV to invert it. 2391 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); 2392 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2393 } 2394 2395 // Check to see if this is a wide variety of vsplti*, binop self cases. 2396 unsigned SplatBitSize = SplatSize*8; 2397 static const signed char SplatCsts[] = { 2398 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 2399 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 2400 }; 2401 2402 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){ 2403 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 2404 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 2405 int i = SplatCsts[idx]; 2406 2407 // Figure out what shift amount will be used by altivec if shifted by i in 2408 // this splat size. 2409 unsigned TypeShiftAmt = i & (SplatBitSize-1); 2410 2411 // vsplti + shl self. 2412 if (SextVal == (i << (int)TypeShiftAmt)) { 2413 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2414 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2415 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 2416 Intrinsic::ppc_altivec_vslw 2417 }; 2418 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2419 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2420 } 2421 2422 // vsplti + srl self. 2423 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2424 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2425 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2426 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 2427 Intrinsic::ppc_altivec_vsrw 2428 }; 2429 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2430 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2431 } 2432 2433 // vsplti + sra self. 2434 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2435 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2436 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2437 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 2438 Intrinsic::ppc_altivec_vsraw 2439 }; 2440 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2441 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2442 } 2443 2444 // vsplti + rol self. 2445 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 2446 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 2447 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2448 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2449 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 2450 Intrinsic::ppc_altivec_vrlw 2451 }; 2452 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2453 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2454 } 2455 2456 // t = vsplti c, result = vsldoi t, t, 1 2457 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { 2458 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2459 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG); 2460 } 2461 // t = vsplti c, result = vsldoi t, t, 2 2462 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { 2463 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2464 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG); 2465 } 2466 // t = vsplti c, result = vsldoi t, t, 3 2467 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { 2468 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2469 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG); 2470 } 2471 } 2472 2473 // Three instruction sequences. 2474 2475 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 2476 if (SextVal >= 0 && SextVal <= 31) { 2477 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG); 2478 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 2479 LHS = DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS); 2480 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 2481 } 2482 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 2483 if (SextVal >= -31 && SextVal <= 0) { 2484 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG); 2485 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 2486 LHS = DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS); 2487 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 2488 } 2489 } 2490 2491 return SDOperand(); 2492} 2493 2494/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 2495/// the specified operations to build the shuffle. 2496static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, 2497 SDOperand RHS, SelectionDAG &DAG) { 2498 unsigned OpNum = (PFEntry >> 26) & 0x0F; 2499 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 2500 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 2501 2502 enum { 2503 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 2504 OP_VMRGHW, 2505 OP_VMRGLW, 2506 OP_VSPLTISW0, 2507 OP_VSPLTISW1, 2508 OP_VSPLTISW2, 2509 OP_VSPLTISW3, 2510 OP_VSLDOI4, 2511 OP_VSLDOI8, 2512 OP_VSLDOI12 2513 }; 2514 2515 if (OpNum == OP_COPY) { 2516 if (LHSID == (1*9+2)*9+3) return LHS; 2517 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 2518 return RHS; 2519 } 2520 2521 SDOperand OpLHS, OpRHS; 2522 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG); 2523 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG); 2524 2525 unsigned ShufIdxs[16]; 2526 switch (OpNum) { 2527 default: assert(0 && "Unknown i32 permute!"); 2528 case OP_VMRGHW: 2529 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 2530 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 2531 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 2532 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 2533 break; 2534 case OP_VMRGLW: 2535 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 2536 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 2537 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 2538 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 2539 break; 2540 case OP_VSPLTISW0: 2541 for (unsigned i = 0; i != 16; ++i) 2542 ShufIdxs[i] = (i&3)+0; 2543 break; 2544 case OP_VSPLTISW1: 2545 for (unsigned i = 0; i != 16; ++i) 2546 ShufIdxs[i] = (i&3)+4; 2547 break; 2548 case OP_VSPLTISW2: 2549 for (unsigned i = 0; i != 16; ++i) 2550 ShufIdxs[i] = (i&3)+8; 2551 break; 2552 case OP_VSPLTISW3: 2553 for (unsigned i = 0; i != 16; ++i) 2554 ShufIdxs[i] = (i&3)+12; 2555 break; 2556 case OP_VSLDOI4: 2557 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG); 2558 case OP_VSLDOI8: 2559 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG); 2560 case OP_VSLDOI12: 2561 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); 2562 } 2563 SDOperand Ops[16]; 2564 for (unsigned i = 0; i != 16; ++i) 2565 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32); 2566 2567 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS, 2568 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 2569} 2570 2571/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 2572/// is a shuffle we can handle in a single instruction, return it. Otherwise, 2573/// return the code it can be lowered into. Worst case, it can always be 2574/// lowered into a vperm. 2575static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { 2576 SDOperand V1 = Op.getOperand(0); 2577 SDOperand V2 = Op.getOperand(1); 2578 SDOperand PermMask = Op.getOperand(2); 2579 2580 // Cases that are handled by instructions that take permute immediates 2581 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 2582 // selected by the instruction selector. 2583 if (V2.getOpcode() == ISD::UNDEF) { 2584 if (PPC::isSplatShuffleMask(PermMask.Val, 1) || 2585 PPC::isSplatShuffleMask(PermMask.Val, 2) || 2586 PPC::isSplatShuffleMask(PermMask.Val, 4) || 2587 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || 2588 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || 2589 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || 2590 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || 2591 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || 2592 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || 2593 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || 2594 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || 2595 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { 2596 return Op; 2597 } 2598 } 2599 2600 // Altivec has a variety of "shuffle immediates" that take two vector inputs 2601 // and produce a fixed permutation. If any of these match, do not lower to 2602 // VPERM. 2603 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || 2604 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || 2605 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || 2606 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || 2607 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || 2608 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || 2609 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || 2610 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || 2611 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) 2612 return Op; 2613 2614 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 2615 // perfect shuffle table to emit an optimal matching sequence. 2616 unsigned PFIndexes[4]; 2617 bool isFourElementShuffle = true; 2618 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 2619 unsigned EltNo = 8; // Start out undef. 2620 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 2621 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF) 2622 continue; // Undef, ignore it. 2623 2624 unsigned ByteSource = 2625 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue(); 2626 if ((ByteSource & 3) != j) { 2627 isFourElementShuffle = false; 2628 break; 2629 } 2630 2631 if (EltNo == 8) { 2632 EltNo = ByteSource/4; 2633 } else if (EltNo != ByteSource/4) { 2634 isFourElementShuffle = false; 2635 break; 2636 } 2637 } 2638 PFIndexes[i] = EltNo; 2639 } 2640 2641 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 2642 // perfect shuffle vector to determine if it is cost effective to do this as 2643 // discrete instructions, or whether we should use a vperm. 2644 if (isFourElementShuffle) { 2645 // Compute the index in the perfect shuffle table. 2646 unsigned PFTableIndex = 2647 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 2648 2649 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 2650 unsigned Cost = (PFEntry >> 30); 2651 2652 // Determining when to avoid vperm is tricky. Many things affect the cost 2653 // of vperm, particularly how many times the perm mask needs to be computed. 2654 // For example, if the perm mask can be hoisted out of a loop or is already 2655 // used (perhaps because there are multiple permutes with the same shuffle 2656 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 2657 // the loop requires an extra register. 2658 // 2659 // As a compromise, we only emit discrete instructions if the shuffle can be 2660 // generated in 3 or fewer operations. When we have loop information 2661 // available, if this block is within a loop, we should avoid using vperm 2662 // for 3-operation perms and use a constant pool load instead. 2663 if (Cost < 3) 2664 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG); 2665 } 2666 2667 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 2668 // vector that will get spilled to the constant pool. 2669 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 2670 2671 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 2672 // that it is in input element units, not in bytes. Convert now. 2673 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType()); 2674 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; 2675 2676 SmallVector<SDOperand, 16> ResultMask; 2677 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { 2678 unsigned SrcElt; 2679 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) 2680 SrcElt = 0; 2681 else 2682 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue(); 2683 2684 for (unsigned j = 0; j != BytesPerElement; ++j) 2685 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 2686 MVT::i8)); 2687 } 2688 2689 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, 2690 &ResultMask[0], ResultMask.size()); 2691 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); 2692} 2693 2694/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 2695/// altivec comparison. If it is, return true and fill in Opc/isDot with 2696/// information about the intrinsic. 2697static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc, 2698 bool &isDot) { 2699 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue(); 2700 CompareOpc = -1; 2701 isDot = false; 2702 switch (IntrinsicID) { 2703 default: return false; 2704 // Comparison predicates. 2705 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 2706 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 2707 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 2708 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 2709 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 2710 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 2711 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 2712 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 2713 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 2714 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 2715 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 2716 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 2717 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 2718 2719 // Normal Comparisons. 2720 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 2721 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 2722 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 2723 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 2724 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 2725 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 2726 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 2727 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 2728 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 2729 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 2730 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 2731 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 2732 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 2733 } 2734 return true; 2735} 2736 2737/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 2738/// lower, do it, otherwise return null. 2739static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { 2740 // If this is a lowered altivec predicate compare, CompareOpc is set to the 2741 // opcode number of the comparison. 2742 int CompareOpc; 2743 bool isDot; 2744 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 2745 return SDOperand(); // Don't custom lower most intrinsics. 2746 2747 // If this is a non-dot comparison, make the VCMP node and we are done. 2748 if (!isDot) { 2749 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), 2750 Op.getOperand(1), Op.getOperand(2), 2751 DAG.getConstant(CompareOpc, MVT::i32)); 2752 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); 2753 } 2754 2755 // Create the PPCISD altivec 'dot' comparison node. 2756 SDOperand Ops[] = { 2757 Op.getOperand(2), // LHS 2758 Op.getOperand(3), // RHS 2759 DAG.getConstant(CompareOpc, MVT::i32) 2760 }; 2761 std::vector<MVT::ValueType> VTs; 2762 VTs.push_back(Op.getOperand(2).getValueType()); 2763 VTs.push_back(MVT::Flag); 2764 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 2765 2766 // Now that we have the comparison, emit a copy from the CR to a GPR. 2767 // This is flagged to the above dot comparison. 2768 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, 2769 DAG.getRegister(PPC::CR6, MVT::i32), 2770 CompNode.getValue(1)); 2771 2772 // Unpack the result based on how the target uses it. 2773 unsigned BitNo; // Bit # of CR6. 2774 bool InvertBit; // Invert result? 2775 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { 2776 default: // Can't happen, don't crash on invalid number though. 2777 case 0: // Return the value of the EQ bit of CR6. 2778 BitNo = 0; InvertBit = false; 2779 break; 2780 case 1: // Return the inverted value of the EQ bit of CR6. 2781 BitNo = 0; InvertBit = true; 2782 break; 2783 case 2: // Return the value of the LT bit of CR6. 2784 BitNo = 2; InvertBit = false; 2785 break; 2786 case 3: // Return the inverted value of the LT bit of CR6. 2787 BitNo = 2; InvertBit = true; 2788 break; 2789 } 2790 2791 // Shift the bit into the low position. 2792 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, 2793 DAG.getConstant(8-(3-BitNo), MVT::i32)); 2794 // Isolate the bit. 2795 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, 2796 DAG.getConstant(1, MVT::i32)); 2797 2798 // If we are supposed to, toggle the bit. 2799 if (InvertBit) 2800 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, 2801 DAG.getConstant(1, MVT::i32)); 2802 return Flags; 2803} 2804 2805static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2806 // Create a stack slot that is 16-byte aligned. 2807 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2808 int FrameIdx = FrameInfo->CreateStackObject(16, 16); 2809 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2810 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2811 2812 // Store the input value into Value#0 of the stack slot. 2813 SDOperand Store = DAG.getStore(DAG.getEntryNode(), 2814 Op.getOperand(0), FIdx, NULL, 0); 2815 // Load it out. 2816 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); 2817} 2818 2819static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { 2820 if (Op.getValueType() == MVT::v4i32) { 2821 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2822 2823 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); 2824 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. 2825 2826 SDOperand RHSSwap = // = vrlw RHS, 16 2827 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG); 2828 2829 // Shrinkify inputs to v8i16. 2830 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS); 2831 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS); 2832 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap); 2833 2834 // Low parts multiplied together, generating 32-bit results (we ignore the 2835 // top parts). 2836 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 2837 LHS, RHS, DAG, MVT::v4i32); 2838 2839 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 2840 LHS, RHSSwap, Zero, DAG, MVT::v4i32); 2841 // Shift the high parts up 16 bits. 2842 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG); 2843 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd); 2844 } else if (Op.getValueType() == MVT::v8i16) { 2845 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2846 2847 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); 2848 2849 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 2850 LHS, RHS, Zero, DAG); 2851 } else if (Op.getValueType() == MVT::v16i8) { 2852 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2853 2854 // Multiply the even 8-bit parts, producing 16-bit sums. 2855 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 2856 LHS, RHS, DAG, MVT::v8i16); 2857 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts); 2858 2859 // Multiply the odd 8-bit parts, producing 16-bit sums. 2860 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 2861 LHS, RHS, DAG, MVT::v8i16); 2862 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); 2863 2864 // Merge the results together. 2865 SDOperand Ops[16]; 2866 for (unsigned i = 0; i != 8; ++i) { 2867 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); 2868 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); 2869 } 2870 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts, 2871 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 2872 } else { 2873 assert(0 && "Unknown mul to lower!"); 2874 abort(); 2875 } 2876} 2877 2878/// LowerOperation - Provide custom lowering hooks for some operations. 2879/// 2880SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 2881 switch (Op.getOpcode()) { 2882 default: assert(0 && "Wasn't expecting to be able to lower this!"); 2883 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 2884 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 2885 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 2886 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 2887 case ISD::SETCC: return LowerSETCC(Op, DAG); 2888 case ISD::VASTART: 2889 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 2890 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 2891 2892 case ISD::VAARG: 2893 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 2894 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 2895 2896 case ISD::FORMAL_ARGUMENTS: 2897 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex, 2898 VarArgsStackOffset, VarArgsNumGPR, 2899 VarArgsNumFPR, PPCSubTarget); 2900 2901 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget); 2902 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine()); 2903 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 2904 case ISD::DYNAMIC_STACKALLOC: 2905 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 2906 2907 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 2908 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 2909 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 2910 2911 // Lower 64-bit shifts. 2912 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 2913 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 2914 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 2915 2916 // Vector-related lowering. 2917 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 2918 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 2919 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 2920 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 2921 case ISD::MUL: return LowerMUL(Op, DAG); 2922 2923 // Frame & Return address. Currently unimplemented 2924 case ISD::RETURNADDR: break; 2925 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 2926 } 2927 return SDOperand(); 2928} 2929 2930//===----------------------------------------------------------------------===// 2931// Other Lowering Code 2932//===----------------------------------------------------------------------===// 2933 2934MachineBasicBlock * 2935PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 2936 MachineBasicBlock *BB) { 2937 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2938 assert((MI->getOpcode() == PPC::SELECT_CC_I4 || 2939 MI->getOpcode() == PPC::SELECT_CC_I8 || 2940 MI->getOpcode() == PPC::SELECT_CC_F4 || 2941 MI->getOpcode() == PPC::SELECT_CC_F8 || 2942 MI->getOpcode() == PPC::SELECT_CC_VRRC) && 2943 "Unexpected instr type to insert"); 2944 2945 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 2946 // control-flow pattern. The incoming instruction knows the destination vreg 2947 // to set, the condition code register to branch on, the true/false values to 2948 // select between, and a branch opcode to use. 2949 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2950 ilist<MachineBasicBlock>::iterator It = BB; 2951 ++It; 2952 2953 // thisMBB: 2954 // ... 2955 // TrueVal = ... 2956 // cmpTY ccX, r1, r2 2957 // bCC copy1MBB 2958 // fallthrough --> copy0MBB 2959 MachineBasicBlock *thisMBB = BB; 2960 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 2961 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 2962 unsigned SelectPred = MI->getOperand(4).getImm(); 2963 BuildMI(BB, TII->get(PPC::BCC)) 2964 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 2965 MachineFunction *F = BB->getParent(); 2966 F->getBasicBlockList().insert(It, copy0MBB); 2967 F->getBasicBlockList().insert(It, sinkMBB); 2968 // Update machine-CFG edges by first adding all successors of the current 2969 // block to the new block which will contain the Phi node for the select. 2970 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 2971 e = BB->succ_end(); i != e; ++i) 2972 sinkMBB->addSuccessor(*i); 2973 // Next, remove all successors of the current block, and add the true 2974 // and fallthrough blocks as its successors. 2975 while(!BB->succ_empty()) 2976 BB->removeSuccessor(BB->succ_begin()); 2977 BB->addSuccessor(copy0MBB); 2978 BB->addSuccessor(sinkMBB); 2979 2980 // copy0MBB: 2981 // %FalseValue = ... 2982 // # fallthrough to sinkMBB 2983 BB = copy0MBB; 2984 2985 // Update machine-CFG edges 2986 BB->addSuccessor(sinkMBB); 2987 2988 // sinkMBB: 2989 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 2990 // ... 2991 BB = sinkMBB; 2992 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg()) 2993 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 2994 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 2995 2996 delete MI; // The pseudo instruction is gone now. 2997 return BB; 2998} 2999 3000//===----------------------------------------------------------------------===// 3001// Target Optimization Hooks 3002//===----------------------------------------------------------------------===// 3003 3004SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, 3005 DAGCombinerInfo &DCI) const { 3006 TargetMachine &TM = getTargetMachine(); 3007 SelectionDAG &DAG = DCI.DAG; 3008 switch (N->getOpcode()) { 3009 default: break; 3010 case PPCISD::SHL: 3011 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3012 if (C->getValue() == 0) // 0 << V -> 0. 3013 return N->getOperand(0); 3014 } 3015 break; 3016 case PPCISD::SRL: 3017 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3018 if (C->getValue() == 0) // 0 >>u V -> 0. 3019 return N->getOperand(0); 3020 } 3021 break; 3022 case PPCISD::SRA: 3023 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3024 if (C->getValue() == 0 || // 0 >>s V -> 0. 3025 C->isAllOnesValue()) // -1 >>s V -> -1. 3026 return N->getOperand(0); 3027 } 3028 break; 3029 3030 case ISD::SINT_TO_FP: 3031 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 3032 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 3033 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 3034 // We allow the src/dst to be either f32/f64, but the intermediate 3035 // type must be i64. 3036 if (N->getOperand(0).getValueType() == MVT::i64) { 3037 SDOperand Val = N->getOperand(0).getOperand(0); 3038 if (Val.getValueType() == MVT::f32) { 3039 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 3040 DCI.AddToWorklist(Val.Val); 3041 } 3042 3043 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); 3044 DCI.AddToWorklist(Val.Val); 3045 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); 3046 DCI.AddToWorklist(Val.Val); 3047 if (N->getValueType(0) == MVT::f32) { 3048 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val); 3049 DCI.AddToWorklist(Val.Val); 3050 } 3051 return Val; 3052 } else if (N->getOperand(0).getValueType() == MVT::i32) { 3053 // If the intermediate type is i32, we can avoid the load/store here 3054 // too. 3055 } 3056 } 3057 } 3058 break; 3059 case ISD::STORE: 3060 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 3061 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 3062 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 3063 N->getOperand(1).getValueType() == MVT::i32) { 3064 SDOperand Val = N->getOperand(1).getOperand(0); 3065 if (Val.getValueType() == MVT::f32) { 3066 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 3067 DCI.AddToWorklist(Val.Val); 3068 } 3069 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); 3070 DCI.AddToWorklist(Val.Val); 3071 3072 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, 3073 N->getOperand(2), N->getOperand(3)); 3074 DCI.AddToWorklist(Val.Val); 3075 return Val; 3076 } 3077 3078 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 3079 if (N->getOperand(1).getOpcode() == ISD::BSWAP && 3080 N->getOperand(1).Val->hasOneUse() && 3081 (N->getOperand(1).getValueType() == MVT::i32 || 3082 N->getOperand(1).getValueType() == MVT::i16)) { 3083 SDOperand BSwapOp = N->getOperand(1).getOperand(0); 3084 // Do an any-extend to 32-bits if this is a half-word input. 3085 if (BSwapOp.getValueType() == MVT::i16) 3086 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp); 3087 3088 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp, 3089 N->getOperand(2), N->getOperand(3), 3090 DAG.getValueType(N->getOperand(1).getValueType())); 3091 } 3092 break; 3093 case ISD::BSWAP: 3094 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 3095 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) && 3096 N->getOperand(0).hasOneUse() && 3097 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 3098 SDOperand Load = N->getOperand(0); 3099 LoadSDNode *LD = cast<LoadSDNode>(Load); 3100 // Create the byte-swapping load. 3101 std::vector<MVT::ValueType> VTs; 3102 VTs.push_back(MVT::i32); 3103 VTs.push_back(MVT::Other); 3104 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset()); 3105 SDOperand Ops[] = { 3106 LD->getChain(), // Chain 3107 LD->getBasePtr(), // Ptr 3108 SV, // SrcValue 3109 DAG.getValueType(N->getValueType(0)) // VT 3110 }; 3111 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); 3112 3113 // If this is an i16 load, insert the truncate. 3114 SDOperand ResVal = BSLoad; 3115 if (N->getValueType(0) == MVT::i16) 3116 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad); 3117 3118 // First, combine the bswap away. This makes the value produced by the 3119 // load dead. 3120 DCI.CombineTo(N, ResVal); 3121 3122 // Next, combine the load away, we give it a bogus result value but a real 3123 // chain result. The result value is dead because the bswap is dead. 3124 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1)); 3125 3126 // Return N so it doesn't get rechecked! 3127 return SDOperand(N, 0); 3128 } 3129 3130 break; 3131 case PPCISD::VCMP: { 3132 // If a VCMPo node already exists with exactly the same operands as this 3133 // node, use its result instead of this node (VCMPo computes both a CR6 and 3134 // a normal output). 3135 // 3136 if (!N->getOperand(0).hasOneUse() && 3137 !N->getOperand(1).hasOneUse() && 3138 !N->getOperand(2).hasOneUse()) { 3139 3140 // Scan all of the users of the LHS, looking for VCMPo's that match. 3141 SDNode *VCMPoNode = 0; 3142 3143 SDNode *LHSN = N->getOperand(0).Val; 3144 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 3145 UI != E; ++UI) 3146 if ((*UI)->getOpcode() == PPCISD::VCMPo && 3147 (*UI)->getOperand(1) == N->getOperand(1) && 3148 (*UI)->getOperand(2) == N->getOperand(2) && 3149 (*UI)->getOperand(0) == N->getOperand(0)) { 3150 VCMPoNode = *UI; 3151 break; 3152 } 3153 3154 // If there is no VCMPo node, or if the flag value has a single use, don't 3155 // transform this. 3156 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 3157 break; 3158 3159 // Look at the (necessarily single) use of the flag value. If it has a 3160 // chain, this transformation is more complex. Note that multiple things 3161 // could use the value result, which we should ignore. 3162 SDNode *FlagUser = 0; 3163 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 3164 FlagUser == 0; ++UI) { 3165 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 3166 SDNode *User = *UI; 3167 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 3168 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) { 3169 FlagUser = User; 3170 break; 3171 } 3172 } 3173 } 3174 3175 // If the user is a MFCR instruction, we know this is safe. Otherwise we 3176 // give up for right now. 3177 if (FlagUser->getOpcode() == PPCISD::MFCR) 3178 return SDOperand(VCMPoNode, 0); 3179 } 3180 break; 3181 } 3182 case ISD::BR_CC: { 3183 // If this is a branch on an altivec predicate comparison, lower this so 3184 // that we don't have to do a MFCR: instead, branch directly on CR6. This 3185 // lowering is done pre-legalize, because the legalizer lowers the predicate 3186 // compare down to code that is difficult to reassemble. 3187 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 3188 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3); 3189 int CompareOpc; 3190 bool isDot; 3191 3192 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 3193 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 3194 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 3195 assert(isDot && "Can't compare against a vector result!"); 3196 3197 // If this is a comparison against something other than 0/1, then we know 3198 // that the condition is never/always true. 3199 unsigned Val = cast<ConstantSDNode>(RHS)->getValue(); 3200 if (Val != 0 && Val != 1) { 3201 if (CC == ISD::SETEQ) // Cond never true, remove branch. 3202 return N->getOperand(0); 3203 // Always !=, turn it into an unconditional branch. 3204 return DAG.getNode(ISD::BR, MVT::Other, 3205 N->getOperand(0), N->getOperand(4)); 3206 } 3207 3208 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 3209 3210 // Create the PPCISD altivec 'dot' comparison node. 3211 std::vector<MVT::ValueType> VTs; 3212 SDOperand Ops[] = { 3213 LHS.getOperand(2), // LHS of compare 3214 LHS.getOperand(3), // RHS of compare 3215 DAG.getConstant(CompareOpc, MVT::i32) 3216 }; 3217 VTs.push_back(LHS.getOperand(2).getValueType()); 3218 VTs.push_back(MVT::Flag); 3219 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 3220 3221 // Unpack the result based on how the target uses it. 3222 PPC::Predicate CompOpc; 3223 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) { 3224 default: // Can't happen, don't crash on invalid number though. 3225 case 0: // Branch on the value of the EQ bit of CR6. 3226 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 3227 break; 3228 case 1: // Branch on the inverted value of the EQ bit of CR6. 3229 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 3230 break; 3231 case 2: // Branch on the value of the LT bit of CR6. 3232 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 3233 break; 3234 case 3: // Branch on the inverted value of the LT bit of CR6. 3235 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 3236 break; 3237 } 3238 3239 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), 3240 DAG.getConstant(CompOpc, MVT::i32), 3241 DAG.getRegister(PPC::CR6, MVT::i32), 3242 N->getOperand(4), CompNode.getValue(1)); 3243 } 3244 break; 3245 } 3246 } 3247 3248 return SDOperand(); 3249} 3250 3251//===----------------------------------------------------------------------===// 3252// Inline Assembly Support 3253//===----------------------------------------------------------------------===// 3254 3255void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 3256 uint64_t Mask, 3257 uint64_t &KnownZero, 3258 uint64_t &KnownOne, 3259 const SelectionDAG &DAG, 3260 unsigned Depth) const { 3261 KnownZero = 0; 3262 KnownOne = 0; 3263 switch (Op.getOpcode()) { 3264 default: break; 3265 case PPCISD::LBRX: { 3266 // lhbrx is known to have the top bits cleared out. 3267 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16) 3268 KnownZero = 0xFFFF0000; 3269 break; 3270 } 3271 case ISD::INTRINSIC_WO_CHAIN: { 3272 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) { 3273 default: break; 3274 case Intrinsic::ppc_altivec_vcmpbfp_p: 3275 case Intrinsic::ppc_altivec_vcmpeqfp_p: 3276 case Intrinsic::ppc_altivec_vcmpequb_p: 3277 case Intrinsic::ppc_altivec_vcmpequh_p: 3278 case Intrinsic::ppc_altivec_vcmpequw_p: 3279 case Intrinsic::ppc_altivec_vcmpgefp_p: 3280 case Intrinsic::ppc_altivec_vcmpgtfp_p: 3281 case Intrinsic::ppc_altivec_vcmpgtsb_p: 3282 case Intrinsic::ppc_altivec_vcmpgtsh_p: 3283 case Intrinsic::ppc_altivec_vcmpgtsw_p: 3284 case Intrinsic::ppc_altivec_vcmpgtub_p: 3285 case Intrinsic::ppc_altivec_vcmpgtuh_p: 3286 case Intrinsic::ppc_altivec_vcmpgtuw_p: 3287 KnownZero = ~1U; // All bits but the low one are known to be zero. 3288 break; 3289 } 3290 } 3291 } 3292} 3293 3294 3295/// getConstraintType - Given a constraint, return the type of 3296/// constraint it is for this target. 3297PPCTargetLowering::ConstraintType 3298PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 3299 if (Constraint.size() == 1) { 3300 switch (Constraint[0]) { 3301 default: break; 3302 case 'b': 3303 case 'r': 3304 case 'f': 3305 case 'v': 3306 case 'y': 3307 return C_RegisterClass; 3308 } 3309 } 3310 return TargetLowering::getConstraintType(Constraint); 3311} 3312 3313std::pair<unsigned, const TargetRegisterClass*> 3314PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 3315 MVT::ValueType VT) const { 3316 if (Constraint.size() == 1) { 3317 // GCC RS6000 Constraint Letters 3318 switch (Constraint[0]) { 3319 case 'b': // R1-R31 3320 case 'r': // R0-R31 3321 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 3322 return std::make_pair(0U, PPC::G8RCRegisterClass); 3323 return std::make_pair(0U, PPC::GPRCRegisterClass); 3324 case 'f': 3325 if (VT == MVT::f32) 3326 return std::make_pair(0U, PPC::F4RCRegisterClass); 3327 else if (VT == MVT::f64) 3328 return std::make_pair(0U, PPC::F8RCRegisterClass); 3329 break; 3330 case 'v': 3331 return std::make_pair(0U, PPC::VRRCRegisterClass); 3332 case 'y': // crrc 3333 return std::make_pair(0U, PPC::CRRCRegisterClass); 3334 } 3335 } 3336 3337 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3338} 3339 3340 3341// isOperandValidForConstraint 3342SDOperand PPCTargetLowering:: 3343isOperandValidForConstraint(SDOperand Op, char Letter, SelectionDAG &DAG) { 3344 switch (Letter) { 3345 default: break; 3346 case 'I': 3347 case 'J': 3348 case 'K': 3349 case 'L': 3350 case 'M': 3351 case 'N': 3352 case 'O': 3353 case 'P': { 3354 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 3355 if (!CST) return SDOperand(0, 0); // Must be an immediate to match. 3356 unsigned Value = CST->getValue(); 3357 switch (Letter) { 3358 default: assert(0 && "Unknown constraint letter!"); 3359 case 'I': // "I" is a signed 16-bit constant. 3360 if ((short)Value == (int)Value) 3361 return DAG.getTargetConstant(Value, Op.getValueType()); 3362 break; 3363 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 3364 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 3365 if ((short)Value == 0) 3366 return DAG.getTargetConstant(Value, Op.getValueType()); 3367 break; 3368 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 3369 if ((Value >> 16) == 0) 3370 return DAG.getTargetConstant(Value, Op.getValueType()); 3371 break; 3372 case 'M': // "M" is a constant that is greater than 31. 3373 if (Value > 31) 3374 return DAG.getTargetConstant(Value, Op.getValueType()); 3375 break; 3376 case 'N': // "N" is a positive constant that is an exact power of two. 3377 if ((int)Value > 0 && isPowerOf2_32(Value)) 3378 return DAG.getTargetConstant(Value, Op.getValueType()); 3379 break; 3380 case 'O': // "O" is the constant zero. 3381 if (Value == 0) 3382 return DAG.getTargetConstant(Value, Op.getValueType()); 3383 break; 3384 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 3385 if ((short)-Value == (int)-Value) 3386 return DAG.getTargetConstant(Value, Op.getValueType()); 3387 break; 3388 } 3389 break; 3390 } 3391 } 3392 3393 // Handle standard constraint letters. 3394 return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG); 3395} 3396 3397// isLegalAddressingMode - Return true if the addressing mode represented 3398// by AM is legal for this target, for a load/store of the specified type. 3399bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 3400 const Type *Ty) const { 3401 // FIXME: PPC does not allow r+i addressing modes for vectors! 3402 3403 // PPC allows a sign-extended 16-bit immediate field. 3404 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3405 return false; 3406 3407 // No global is ever allowed as a base. 3408 if (AM.BaseGV) 3409 return false; 3410 3411 // PPC only support r+r, 3412 switch (AM.Scale) { 3413 case 0: // "r+i" or just "i", depending on HasBaseReg. 3414 break; 3415 case 1: 3416 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3417 return false; 3418 // Otherwise we have r+r or r+i. 3419 break; 3420 case 2: 3421 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3422 return false; 3423 // Allow 2*r as r+r. 3424 break; 3425 default: 3426 // No other scales are supported. 3427 return false; 3428 } 3429 3430 return true; 3431} 3432 3433/// isLegalAddressImmediate - Return true if the integer value can be used 3434/// as the offset of the target addressing mode for load / store of the 3435/// given type. 3436bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{ 3437 // PPC allows a sign-extended 16-bit immediate field. 3438 return (V > -(1 << 16) && V < (1 << 16)-1); 3439} 3440 3441bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 3442 return false; 3443} 3444 3445SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) 3446{ 3447 // Depths > 0 not supported yet! 3448 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 3449 return SDOperand(); 3450 3451 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3452 bool isPPC64 = PtrVT == MVT::i64; 3453 3454 MachineFunction &MF = DAG.getMachineFunction(); 3455 MachineFrameInfo *MFI = MF.getFrameInfo(); 3456 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects()) 3457 && MFI->getStackSize(); 3458 3459 if (isPPC64) 3460 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1, 3461 MVT::i32); 3462 else 3463 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1, 3464 MVT::i32); 3465} 3466