PPCISelLowering.cpp revision 6e0b2a0cb0d398f175a5294bf0ad5488c714e8c2
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "MCTargetDesc/PPCPredicates.h" 16#include "PPCMachineFunctionInfo.h" 17#include "PPCPerfectShuffle.h" 18#include "PPCTargetMachine.h" 19#include "PPCTargetObjectFile.h" 20#include "llvm/ADT/STLExtras.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/SelectionDAG.h" 27#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 28#include "llvm/IR/CallingConv.h" 29#include "llvm/IR/Constants.h" 30#include "llvm/IR/DerivedTypes.h" 31#include "llvm/IR/Function.h" 32#include "llvm/IR/Intrinsics.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include "llvm/Target/TargetOptions.h" 38using namespace llvm; 39 40static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 41 CCValAssign::LocInfo &LocInfo, 42 ISD::ArgFlagsTy &ArgFlags, 43 CCState &State); 44static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 45 MVT &LocVT, 46 CCValAssign::LocInfo &LocInfo, 47 ISD::ArgFlagsTy &ArgFlags, 48 CCState &State); 49static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 50 MVT &LocVT, 51 CCValAssign::LocInfo &LocInfo, 52 ISD::ArgFlagsTy &ArgFlags, 53 CCState &State); 54 55static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc", 56cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden); 57 58static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref", 59cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden); 60 61static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned", 62cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden); 63 64static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) { 65 if (TM.getSubtargetImpl()->isDarwin()) 66 return new TargetLoweringObjectFileMachO(); 67 68 if (TM.getSubtargetImpl()->isSVR4ABI()) 69 return new PPC64LinuxTargetObjectFile(); 70 71 return new TargetLoweringObjectFileELF(); 72} 73 74PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 75 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) { 76 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>(); 77 PPCRegInfo = TM.getRegisterInfo(); 78 PPCII = TM.getInstrInfo(); 79 80 setPow2DivIsCheap(); 81 82 // Use _setjmp/_longjmp instead of setjmp/longjmp. 83 setUseUnderscoreSetJmp(true); 84 setUseUnderscoreLongJmp(true); 85 86 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all 87 // arguments are at least 4/8 bytes aligned. 88 bool isPPC64 = Subtarget->isPPC64(); 89 setMinStackArgumentAlignment(isPPC64 ? 8:4); 90 91 // Set up the register classes. 92 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); 93 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); 94 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); 95 96 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 97 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 98 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 99 100 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 101 102 // PowerPC has pre-inc load and store's. 103 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 104 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 105 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 106 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 107 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 108 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 109 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 110 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 111 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 112 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 113 114 // This is used in the ppcf128->int sequence. Note it has different semantics 115 // from FP_ROUND: that rounds to nearest, this rounds to zero. 116 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 117 118 // We do not currently implement these libm ops for PowerPC. 119 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand); 120 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); 121 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand); 122 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand); 123 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand); 124 setOperationAction(ISD::FREM, MVT::ppcf128, Expand); 125 126 // PowerPC has no SREM/UREM instructions 127 setOperationAction(ISD::SREM, MVT::i32, Expand); 128 setOperationAction(ISD::UREM, MVT::i32, Expand); 129 setOperationAction(ISD::SREM, MVT::i64, Expand); 130 setOperationAction(ISD::UREM, MVT::i64, Expand); 131 132 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 133 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 134 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 135 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 136 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 137 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 138 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 139 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 140 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 141 142 // We don't support sin/cos/sqrt/fmod/pow 143 setOperationAction(ISD::FSIN , MVT::f64, Expand); 144 setOperationAction(ISD::FCOS , MVT::f64, Expand); 145 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 146 setOperationAction(ISD::FREM , MVT::f64, Expand); 147 setOperationAction(ISD::FPOW , MVT::f64, Expand); 148 setOperationAction(ISD::FMA , MVT::f64, Legal); 149 setOperationAction(ISD::FSIN , MVT::f32, Expand); 150 setOperationAction(ISD::FCOS , MVT::f32, Expand); 151 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 152 setOperationAction(ISD::FREM , MVT::f32, Expand); 153 setOperationAction(ISD::FPOW , MVT::f32, Expand); 154 setOperationAction(ISD::FMA , MVT::f32, Legal); 155 156 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 157 158 // If we're enabling GP optimizations, use hardware square root 159 if (!Subtarget->hasFSQRT() && 160 !(TM.Options.UnsafeFPMath && 161 Subtarget->hasFRSQRTE() && Subtarget->hasFRE())) 162 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 163 164 if (!Subtarget->hasFSQRT() && 165 !(TM.Options.UnsafeFPMath && 166 Subtarget->hasFRSQRTES() && Subtarget->hasFRES())) 167 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 168 169 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 170 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 171 172 if (Subtarget->hasFPRND()) { 173 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 174 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 175 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 176 177 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 178 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 179 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 180 181 // frin does not implement "ties to even." Thus, this is safe only in 182 // fast-math mode. 183 if (TM.Options.UnsafeFPMath) { 184 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 185 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 186 187 // These need to set FE_INEXACT, and use a custom inserter. 188 setOperationAction(ISD::FRINT, MVT::f64, Legal); 189 setOperationAction(ISD::FRINT, MVT::f32, Legal); 190 } 191 } 192 193 // PowerPC does not have BSWAP, CTPOP or CTTZ 194 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 195 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 196 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 197 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 198 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 199 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 200 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 201 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 202 203 if (Subtarget->hasPOPCNTD()) { 204 setOperationAction(ISD::CTPOP, MVT::i32 , Legal); 205 setOperationAction(ISD::CTPOP, MVT::i64 , Legal); 206 } else { 207 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 208 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 209 } 210 211 // PowerPC does not have ROTR 212 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 213 setOperationAction(ISD::ROTR, MVT::i64 , Expand); 214 215 // PowerPC does not have Select 216 setOperationAction(ISD::SELECT, MVT::i32, Expand); 217 setOperationAction(ISD::SELECT, MVT::i64, Expand); 218 setOperationAction(ISD::SELECT, MVT::f32, Expand); 219 setOperationAction(ISD::SELECT, MVT::f64, Expand); 220 221 // PowerPC wants to turn select_cc of FP into fsel when possible. 222 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 223 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 224 225 // PowerPC wants to optimize integer setcc a bit 226 setOperationAction(ISD::SETCC, MVT::i32, Custom); 227 228 // PowerPC does not have BRCOND which requires SetCC 229 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 230 231 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 232 233 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 234 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 235 236 // PowerPC does not have [U|S]INT_TO_FP 237 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 238 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 239 240 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 241 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 242 setOperationAction(ISD::BITCAST, MVT::i64, Expand); 243 setOperationAction(ISD::BITCAST, MVT::f64, Expand); 244 245 // We cannot sextinreg(i1). Expand to shifts. 246 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 247 248 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 249 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 250 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 251 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 252 253 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support 254 // SjLj exception handling but a light-weight setjmp/longjmp replacement to 255 // support continuation, user-level threading, and etc.. As a result, no 256 // other SjLj exception interfaces are implemented and please don't build 257 // your own exception handling based on them. 258 // LLVM/Clang supports zero-cost DWARF exception handling. 259 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); 260 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); 261 262 // We want to legalize GlobalAddress and ConstantPool nodes into the 263 // appropriate instructions to materialize the address. 264 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 265 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 266 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 267 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 268 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 269 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 270 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 271 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 272 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 273 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 274 275 // TRAP is legal. 276 setOperationAction(ISD::TRAP, MVT::Other, Legal); 277 278 // TRAMPOLINE is custom lowered. 279 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 280 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 281 282 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 283 setOperationAction(ISD::VASTART , MVT::Other, Custom); 284 285 if (Subtarget->isSVR4ABI()) { 286 if (isPPC64) { 287 // VAARG always uses double-word chunks, so promote anything smaller. 288 setOperationAction(ISD::VAARG, MVT::i1, Promote); 289 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64); 290 setOperationAction(ISD::VAARG, MVT::i8, Promote); 291 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64); 292 setOperationAction(ISD::VAARG, MVT::i16, Promote); 293 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64); 294 setOperationAction(ISD::VAARG, MVT::i32, Promote); 295 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64); 296 setOperationAction(ISD::VAARG, MVT::Other, Expand); 297 } else { 298 // VAARG is custom lowered with the 32-bit SVR4 ABI. 299 setOperationAction(ISD::VAARG, MVT::Other, Custom); 300 setOperationAction(ISD::VAARG, MVT::i64, Custom); 301 } 302 } else 303 setOperationAction(ISD::VAARG, MVT::Other, Expand); 304 305 // Use the default implementation. 306 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 307 setOperationAction(ISD::VAEND , MVT::Other, Expand); 308 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 309 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 310 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 311 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 312 313 // We want to custom lower some of our intrinsics. 314 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 315 316 // To handle counter-based loop conditions. 317 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom); 318 319 // Comparisons that require checking two conditions. 320 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 321 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); 322 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); 323 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); 324 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); 325 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); 326 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 327 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 328 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 329 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 330 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); 331 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); 332 333 if (Subtarget->has64BitSupport()) { 334 // They also have instructions for converting between i64 and fp. 335 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 336 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 337 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 338 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 339 // This is just the low 32 bits of a (signed) fp->i64 conversion. 340 // We cannot do this with Promote because i64 is not a legal type. 341 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 342 343 if (PPCSubTarget.hasLFIWAX() || Subtarget->isPPC64()) 344 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 345 } else { 346 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 347 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 348 } 349 350 // With the instructions enabled under FPCVT, we can do everything. 351 if (PPCSubTarget.hasFPCVT()) { 352 if (Subtarget->has64BitSupport()) { 353 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 354 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); 355 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 356 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); 357 } 358 359 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 361 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 362 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 363 } 364 365 if (Subtarget->use64BitRegs()) { 366 // 64-bit PowerPC implementations can support i64 types directly 367 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); 368 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 369 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 370 // 64-bit PowerPC wants to expand i128 shifts itself. 371 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 372 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 373 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 374 } else { 375 // 32-bit PowerPC wants to expand i64 shifts itself. 376 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 377 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 378 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 379 } 380 381 if (Subtarget->hasAltivec()) { 382 // First set operation action for all vector types to expand. Then we 383 // will selectively turn on ones that can be effectively codegen'd. 384 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 385 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 386 MVT::SimpleValueType VT = (MVT::SimpleValueType)i; 387 388 // add/sub are legal for all supported vector VT's. 389 setOperationAction(ISD::ADD , VT, Legal); 390 setOperationAction(ISD::SUB , VT, Legal); 391 392 // We promote all shuffles to v16i8. 393 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 394 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 395 396 // We promote all non-typed operations to v4i32. 397 setOperationAction(ISD::AND , VT, Promote); 398 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 399 setOperationAction(ISD::OR , VT, Promote); 400 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 401 setOperationAction(ISD::XOR , VT, Promote); 402 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 403 setOperationAction(ISD::LOAD , VT, Promote); 404 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 405 setOperationAction(ISD::SELECT, VT, Promote); 406 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 407 setOperationAction(ISD::STORE, VT, Promote); 408 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 409 410 // No other operations are legal. 411 setOperationAction(ISD::MUL , VT, Expand); 412 setOperationAction(ISD::SDIV, VT, Expand); 413 setOperationAction(ISD::SREM, VT, Expand); 414 setOperationAction(ISD::UDIV, VT, Expand); 415 setOperationAction(ISD::UREM, VT, Expand); 416 setOperationAction(ISD::FDIV, VT, Expand); 417 setOperationAction(ISD::FNEG, VT, Expand); 418 setOperationAction(ISD::FSQRT, VT, Expand); 419 setOperationAction(ISD::FLOG, VT, Expand); 420 setOperationAction(ISD::FLOG10, VT, Expand); 421 setOperationAction(ISD::FLOG2, VT, Expand); 422 setOperationAction(ISD::FEXP, VT, Expand); 423 setOperationAction(ISD::FEXP2, VT, Expand); 424 setOperationAction(ISD::FSIN, VT, Expand); 425 setOperationAction(ISD::FCOS, VT, Expand); 426 setOperationAction(ISD::FABS, VT, Expand); 427 setOperationAction(ISD::FPOWI, VT, Expand); 428 setOperationAction(ISD::FFLOOR, VT, Expand); 429 setOperationAction(ISD::FCEIL, VT, Expand); 430 setOperationAction(ISD::FTRUNC, VT, Expand); 431 setOperationAction(ISD::FRINT, VT, Expand); 432 setOperationAction(ISD::FNEARBYINT, VT, Expand); 433 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); 434 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 435 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); 436 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 437 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 438 setOperationAction(ISD::UDIVREM, VT, Expand); 439 setOperationAction(ISD::SDIVREM, VT, Expand); 440 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); 441 setOperationAction(ISD::FPOW, VT, Expand); 442 setOperationAction(ISD::CTPOP, VT, Expand); 443 setOperationAction(ISD::CTLZ, VT, Expand); 444 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); 445 setOperationAction(ISD::CTTZ, VT, Expand); 446 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); 447 setOperationAction(ISD::VSELECT, VT, Expand); 448 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); 449 450 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 451 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) { 452 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j; 453 setTruncStoreAction(VT, InnerVT, Expand); 454 } 455 setLoadExtAction(ISD::SEXTLOAD, VT, Expand); 456 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand); 457 setLoadExtAction(ISD::EXTLOAD, VT, Expand); 458 } 459 460 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 461 // with merges, splats, etc. 462 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 463 464 setOperationAction(ISD::AND , MVT::v4i32, Legal); 465 setOperationAction(ISD::OR , MVT::v4i32, Legal); 466 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 467 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 468 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 469 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 470 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 471 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal); 472 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 473 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); 474 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); 475 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); 476 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); 477 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); 478 479 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); 480 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); 481 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); 482 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass); 483 484 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 485 setOperationAction(ISD::FMA, MVT::v4f32, Legal); 486 487 if (TM.Options.UnsafeFPMath) { 488 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 489 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 490 } 491 492 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 493 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 494 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 495 496 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 497 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 498 499 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 500 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 501 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 502 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 503 504 // Altivec does not contain unordered floating-point compare instructions 505 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand); 506 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand); 507 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand); 508 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand); 509 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand); 510 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand); 511 } 512 513 if (Subtarget->has64BitSupport()) { 514 setOperationAction(ISD::PREFETCH, MVT::Other, Legal); 515 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal); 516 } 517 518 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 519 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 520 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 521 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 522 523 setBooleanContents(ZeroOrOneBooleanContent); 524 // Altivec instructions set fields to all zeros or all ones. 525 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 526 527 if (isPPC64) { 528 setStackPointerRegisterToSaveRestore(PPC::X1); 529 setExceptionPointerRegister(PPC::X3); 530 setExceptionSelectorRegister(PPC::X4); 531 } else { 532 setStackPointerRegisterToSaveRestore(PPC::R1); 533 setExceptionPointerRegister(PPC::R3); 534 setExceptionSelectorRegister(PPC::R4); 535 } 536 537 // We have target-specific dag combine patterns for the following nodes: 538 setTargetDAGCombine(ISD::SINT_TO_FP); 539 setTargetDAGCombine(ISD::LOAD); 540 setTargetDAGCombine(ISD::STORE); 541 setTargetDAGCombine(ISD::BR_CC); 542 setTargetDAGCombine(ISD::BSWAP); 543 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); 544 545 // Use reciprocal estimates. 546 if (TM.Options.UnsafeFPMath) { 547 setTargetDAGCombine(ISD::FDIV); 548 setTargetDAGCombine(ISD::FSQRT); 549 } 550 551 // Darwin long double math library functions have $LDBL128 appended. 552 if (Subtarget->isDarwin()) { 553 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 554 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 555 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 556 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 557 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 558 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128"); 559 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128"); 560 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128"); 561 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128"); 562 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128"); 563 } 564 565 setMinFunctionAlignment(2); 566 if (PPCSubTarget.isDarwin()) 567 setPrefFunctionAlignment(4); 568 569 if (isPPC64 && Subtarget->isJITCodeModel()) 570 // Temporary workaround for the inability of PPC64 JIT to handle jump 571 // tables. 572 setSupportJumpTables(false); 573 574 setInsertFencesForAtomic(true); 575 576 setSchedulingPreference(Sched::Hybrid); 577 578 computeRegisterProperties(); 579 580 // The Freescale cores does better with aggressive inlining of memcpy and 581 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores). 582 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc || 583 Subtarget->getDarwinDirective() == PPC::DIR_E5500) { 584 MaxStoresPerMemset = 32; 585 MaxStoresPerMemsetOptSize = 16; 586 MaxStoresPerMemcpy = 32; 587 MaxStoresPerMemcpyOptSize = 8; 588 MaxStoresPerMemmove = 32; 589 MaxStoresPerMemmoveOptSize = 8; 590 591 setPrefFunctionAlignment(4); 592 } 593} 594 595/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 596/// function arguments in the caller parameter area. 597unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const { 598 const TargetMachine &TM = getTargetMachine(); 599 // Darwin passes everything on 4 byte boundary. 600 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) 601 return 4; 602 603 // 16byte and wider vectors are passed on 16byte boundary. 604 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) 605 if (VTy->getBitWidth() >= 128) 606 return 16; 607 608 // The rest is 8 on PPC64 and 4 on PPC32 boundary. 609 if (PPCSubTarget.isPPC64()) 610 return 8; 611 612 return 4; 613} 614 615const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 616 switch (Opcode) { 617 default: return 0; 618 case PPCISD::FSEL: return "PPCISD::FSEL"; 619 case PPCISD::FCFID: return "PPCISD::FCFID"; 620 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 621 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 622 case PPCISD::FRE: return "PPCISD::FRE"; 623 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE"; 624 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 625 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 626 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 627 case PPCISD::VPERM: return "PPCISD::VPERM"; 628 case PPCISD::Hi: return "PPCISD::Hi"; 629 case PPCISD::Lo: return "PPCISD::Lo"; 630 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY"; 631 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE"; 632 case PPCISD::LOAD: return "PPCISD::LOAD"; 633 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC"; 634 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 635 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 636 case PPCISD::SRL: return "PPCISD::SRL"; 637 case PPCISD::SRA: return "PPCISD::SRA"; 638 case PPCISD::SHL: return "PPCISD::SHL"; 639 case PPCISD::CALL: return "PPCISD::CALL"; 640 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP"; 641 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 642 case PPCISD::BCTRL: return "PPCISD::BCTRL"; 643 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 644 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP"; 645 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP"; 646 case PPCISD::MFCR: return "PPCISD::MFCR"; 647 case PPCISD::VCMP: return "PPCISD::VCMP"; 648 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 649 case PPCISD::LBRX: return "PPCISD::LBRX"; 650 case PPCISD::STBRX: return "PPCISD::STBRX"; 651 case PPCISD::LARX: return "PPCISD::LARX"; 652 case PPCISD::STCX: return "PPCISD::STCX"; 653 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 654 case PPCISD::BDNZ: return "PPCISD::BDNZ"; 655 case PPCISD::BDZ: return "PPCISD::BDZ"; 656 case PPCISD::MFFS: return "PPCISD::MFFS"; 657 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 658 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; 659 case PPCISD::CR6SET: return "PPCISD::CR6SET"; 660 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET"; 661 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA"; 662 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L"; 663 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L"; 664 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA"; 665 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L"; 666 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS"; 667 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA"; 668 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L"; 669 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR"; 670 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA"; 671 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L"; 672 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR"; 673 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA"; 674 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L"; 675 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT"; 676 case PPCISD::SC: return "PPCISD::SC"; 677 } 678} 679 680EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { 681 if (!VT.isVector()) 682 return MVT::i32; 683 return VT.changeVectorElementTypeToInteger(); 684} 685 686//===----------------------------------------------------------------------===// 687// Node matching predicates, for use by the tblgen matching code. 688//===----------------------------------------------------------------------===// 689 690/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 691static bool isFloatingPointZero(SDValue Op) { 692 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 693 return CFP->getValueAPF().isZero(); 694 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 695 // Maybe this has already been legalized into the constant pool? 696 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 697 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 698 return CFP->getValueAPF().isZero(); 699 } 700 return false; 701} 702 703/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 704/// true if Op is undef or if it matches the specified value. 705static bool isConstantOrUndef(int Op, int Val) { 706 return Op < 0 || Op == Val; 707} 708 709/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 710/// VPKUHUM instruction. 711bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 712 if (!isUnary) { 713 for (unsigned i = 0; i != 16; ++i) 714 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1)) 715 return false; 716 } else { 717 for (unsigned i = 0; i != 8; ++i) 718 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) || 719 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1)) 720 return false; 721 } 722 return true; 723} 724 725/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 726/// VPKUWUM instruction. 727bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 728 if (!isUnary) { 729 for (unsigned i = 0; i != 16; i += 2) 730 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 731 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3)) 732 return false; 733 } else { 734 for (unsigned i = 0; i != 8; i += 2) 735 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 736 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) || 737 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) || 738 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3)) 739 return false; 740 } 741 return true; 742} 743 744/// isVMerge - Common function, used to match vmrg* shuffles. 745/// 746static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, 747 unsigned LHSStart, unsigned RHSStart) { 748 assert(N->getValueType(0) == MVT::v16i8 && 749 "PPC only supports shuffles by bytes!"); 750 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 751 "Unsupported merge size!"); 752 753 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 754 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 755 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j), 756 LHSStart+j+i*UnitSize) || 757 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j), 758 RHSStart+j+i*UnitSize)) 759 return false; 760 } 761 return true; 762} 763 764/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 765/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 766bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 767 bool isUnary) { 768 if (!isUnary) 769 return isVMerge(N, UnitSize, 8, 24); 770 return isVMerge(N, UnitSize, 8, 8); 771} 772 773/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 774/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 775bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 776 bool isUnary) { 777 if (!isUnary) 778 return isVMerge(N, UnitSize, 0, 16); 779 return isVMerge(N, UnitSize, 0, 0); 780} 781 782 783/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 784/// amount, otherwise return -1. 785int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 786 assert(N->getValueType(0) == MVT::v16i8 && 787 "PPC only supports shuffles by bytes!"); 788 789 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 790 791 // Find the first non-undef value in the shuffle mask. 792 unsigned i; 793 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i) 794 /*search*/; 795 796 if (i == 16) return -1; // all undef. 797 798 // Otherwise, check to see if the rest of the elements are consecutively 799 // numbered from this value. 800 unsigned ShiftAmt = SVOp->getMaskElt(i); 801 if (ShiftAmt < i) return -1; 802 ShiftAmt -= i; 803 804 if (!isUnary) { 805 // Check the rest of the elements to see if they are consecutive. 806 for (++i; i != 16; ++i) 807 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) 808 return -1; 809 } else { 810 // Check the rest of the elements to see if they are consecutive. 811 for (++i; i != 16; ++i) 812 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) 813 return -1; 814 } 815 return ShiftAmt; 816} 817 818/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 819/// specifies a splat of a single element that is suitable for input to 820/// VSPLTB/VSPLTH/VSPLTW. 821bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { 822 assert(N->getValueType(0) == MVT::v16i8 && 823 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 824 825 // This is a splat operation if each element of the permute is the same, and 826 // if the value doesn't reference the second vector. 827 unsigned ElementBase = N->getMaskElt(0); 828 829 // FIXME: Handle UNDEF elements too! 830 if (ElementBase >= 16) 831 return false; 832 833 // Check that the indices are consecutive, in the case of a multi-byte element 834 // splatted with a v16i8 mask. 835 for (unsigned i = 1; i != EltSize; ++i) 836 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase)) 837 return false; 838 839 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 840 if (N->getMaskElt(i) < 0) continue; 841 for (unsigned j = 0; j != EltSize; ++j) 842 if (N->getMaskElt(i+j) != N->getMaskElt(j)) 843 return false; 844 } 845 return true; 846} 847 848/// isAllNegativeZeroVector - Returns true if all elements of build_vector 849/// are -0.0. 850bool PPC::isAllNegativeZeroVector(SDNode *N) { 851 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N); 852 853 APInt APVal, APUndef; 854 unsigned BitSize; 855 bool HasAnyUndefs; 856 857 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true)) 858 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 859 return CFP->getValueAPF().isNegZero(); 860 861 return false; 862} 863 864/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 865/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 866unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 867 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 868 assert(isSplatShuffleMask(SVOp, EltSize)); 869 return SVOp->getMaskElt(0) / EltSize; 870} 871 872/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 873/// by using a vspltis[bhw] instruction of the specified element size, return 874/// the constant being splatted. The ByteSize field indicates the number of 875/// bytes of each element [124] -> [bhw]. 876SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 877 SDValue OpVal(0, 0); 878 879 // If ByteSize of the splat is bigger than the element size of the 880 // build_vector, then we have a case where we are checking for a splat where 881 // multiple elements of the buildvector are folded together into a single 882 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 883 unsigned EltSize = 16/N->getNumOperands(); 884 if (EltSize < ByteSize) { 885 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 886 SDValue UniquedVals[4]; 887 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 888 889 // See if all of the elements in the buildvector agree across. 890 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 891 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 892 // If the element isn't a constant, bail fully out. 893 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue(); 894 895 896 if (UniquedVals[i&(Multiple-1)].getNode() == 0) 897 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 898 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 899 return SDValue(); // no match. 900 } 901 902 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 903 // either constant or undef values that are identical for each chunk. See 904 // if these chunks can form into a larger vspltis*. 905 906 // Check to see if all of the leading entries are either 0 or -1. If 907 // neither, then this won't fit into the immediate field. 908 bool LeadingZero = true; 909 bool LeadingOnes = true; 910 for (unsigned i = 0; i != Multiple-1; ++i) { 911 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs. 912 913 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 914 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 915 } 916 // Finally, check the least significant entry. 917 if (LeadingZero) { 918 if (UniquedVals[Multiple-1].getNode() == 0) 919 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 920 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue(); 921 if (Val < 16) 922 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 923 } 924 if (LeadingOnes) { 925 if (UniquedVals[Multiple-1].getNode() == 0) 926 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 927 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue(); 928 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 929 return DAG.getTargetConstant(Val, MVT::i32); 930 } 931 932 return SDValue(); 933 } 934 935 // Check to see if this buildvec has a single non-undef value in its elements. 936 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 937 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 938 if (OpVal.getNode() == 0) 939 OpVal = N->getOperand(i); 940 else if (OpVal != N->getOperand(i)) 941 return SDValue(); 942 } 943 944 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def. 945 946 unsigned ValSizeInBytes = EltSize; 947 uint64_t Value = 0; 948 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 949 Value = CN->getZExtValue(); 950 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 951 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 952 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 953 } 954 955 // If the splat value is larger than the element value, then we can never do 956 // this splat. The only case that we could fit the replicated bits into our 957 // immediate field for would be zero, and we prefer to use vxor for it. 958 if (ValSizeInBytes < ByteSize) return SDValue(); 959 960 // If the element value is larger than the splat value, cut it in half and 961 // check to see if the two halves are equal. Continue doing this until we 962 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 963 while (ValSizeInBytes > ByteSize) { 964 ValSizeInBytes >>= 1; 965 966 // If the top half equals the bottom half, we're still ok. 967 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 968 (Value & ((1 << (8*ValSizeInBytes))-1))) 969 return SDValue(); 970 } 971 972 // Properly sign extend the value. 973 int MaskVal = SignExtend32(Value, ByteSize * 8); 974 975 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 976 if (MaskVal == 0) return SDValue(); 977 978 // Finally, if this value fits in a 5 bit sext field, return it 979 if (SignExtend32<5>(MaskVal) == MaskVal) 980 return DAG.getTargetConstant(MaskVal, MVT::i32); 981 return SDValue(); 982} 983 984//===----------------------------------------------------------------------===// 985// Addressing Mode Selection 986//===----------------------------------------------------------------------===// 987 988/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 989/// or 64-bit immediate, and if the value can be accurately represented as a 990/// sign extension from a 16-bit value. If so, this returns true and the 991/// immediate. 992static bool isIntS16Immediate(SDNode *N, short &Imm) { 993 if (N->getOpcode() != ISD::Constant) 994 return false; 995 996 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 997 if (N->getValueType(0) == MVT::i32) 998 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 999 else 1000 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 1001} 1002static bool isIntS16Immediate(SDValue Op, short &Imm) { 1003 return isIntS16Immediate(Op.getNode(), Imm); 1004} 1005 1006 1007/// SelectAddressRegReg - Given the specified addressed, check to see if it 1008/// can be represented as an indexed [r+r] operation. Returns false if it 1009/// can be more efficiently represented with [r+imm]. 1010bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, 1011 SDValue &Index, 1012 SelectionDAG &DAG) const { 1013 short imm = 0; 1014 if (N.getOpcode() == ISD::ADD) { 1015 if (isIntS16Immediate(N.getOperand(1), imm)) 1016 return false; // r+i 1017 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 1018 return false; // r+i 1019 1020 Base = N.getOperand(0); 1021 Index = N.getOperand(1); 1022 return true; 1023 } else if (N.getOpcode() == ISD::OR) { 1024 if (isIntS16Immediate(N.getOperand(1), imm)) 1025 return false; // r+i can fold it if we can. 1026 1027 // If this is an or of disjoint bitfields, we can codegen this as an add 1028 // (for better address arithmetic) if the LHS and RHS of the OR are provably 1029 // disjoint. 1030 APInt LHSKnownZero, LHSKnownOne; 1031 APInt RHSKnownZero, RHSKnownOne; 1032 DAG.ComputeMaskedBits(N.getOperand(0), 1033 LHSKnownZero, LHSKnownOne); 1034 1035 if (LHSKnownZero.getBoolValue()) { 1036 DAG.ComputeMaskedBits(N.getOperand(1), 1037 RHSKnownZero, RHSKnownOne); 1038 // If all of the bits are known zero on the LHS or RHS, the add won't 1039 // carry. 1040 if (~(LHSKnownZero | RHSKnownZero) == 0) { 1041 Base = N.getOperand(0); 1042 Index = N.getOperand(1); 1043 return true; 1044 } 1045 } 1046 } 1047 1048 return false; 1049} 1050 1051/// Returns true if the address N can be represented by a base register plus 1052/// a signed 16-bit displacement [r+imm], and if it is not better 1053/// represented as reg+reg. If Aligned is true, only accept displacements 1054/// suitable for STD and friends, i.e. multiples of 4. 1055bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, 1056 SDValue &Base, 1057 SelectionDAG &DAG, 1058 bool Aligned) const { 1059 // FIXME dl should come from parent load or store, not from address 1060 SDLoc dl(N); 1061 // If this can be more profitably realized as r+r, fail. 1062 if (SelectAddressRegReg(N, Disp, Base, DAG)) 1063 return false; 1064 1065 if (N.getOpcode() == ISD::ADD) { 1066 short imm = 0; 1067 if (isIntS16Immediate(N.getOperand(1), imm) && 1068 (!Aligned || (imm & 3) == 0)) { 1069 Disp = DAG.getTargetConstant(imm, N.getValueType()); 1070 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 1071 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1072 } else { 1073 Base = N.getOperand(0); 1074 } 1075 return true; // [r+i] 1076 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 1077 // Match LOAD (ADD (X, Lo(G))). 1078 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 1079 && "Cannot handle constant offsets yet!"); 1080 Disp = N.getOperand(1).getOperand(0); // The global address. 1081 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 1082 Disp.getOpcode() == ISD::TargetGlobalTLSAddress || 1083 Disp.getOpcode() == ISD::TargetConstantPool || 1084 Disp.getOpcode() == ISD::TargetJumpTable); 1085 Base = N.getOperand(0); 1086 return true; // [&g+r] 1087 } 1088 } else if (N.getOpcode() == ISD::OR) { 1089 short imm = 0; 1090 if (isIntS16Immediate(N.getOperand(1), imm) && 1091 (!Aligned || (imm & 3) == 0)) { 1092 // If this is an or of disjoint bitfields, we can codegen this as an add 1093 // (for better address arithmetic) if the LHS and RHS of the OR are 1094 // provably disjoint. 1095 APInt LHSKnownZero, LHSKnownOne; 1096 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne); 1097 1098 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 1099 // If all of the bits are known zero on the LHS or RHS, the add won't 1100 // carry. 1101 Base = N.getOperand(0); 1102 Disp = DAG.getTargetConstant(imm, N.getValueType()); 1103 return true; 1104 } 1105 } 1106 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 1107 // Loading from a constant address. 1108 1109 // If this address fits entirely in a 16-bit sext immediate field, codegen 1110 // this as "d, 0" 1111 short Imm; 1112 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) { 1113 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 1114 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, 1115 CN->getValueType(0)); 1116 return true; 1117 } 1118 1119 // Handle 32-bit sext immediates with LIS + addr mode. 1120 if ((CN->getValueType(0) == MVT::i32 || 1121 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) && 1122 (!Aligned || (CN->getZExtValue() & 3) == 0)) { 1123 int Addr = (int)CN->getZExtValue(); 1124 1125 // Otherwise, break this down into an LIS + disp. 1126 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 1127 1128 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 1129 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1130 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); 1131 return true; 1132 } 1133 } 1134 1135 Disp = DAG.getTargetConstant(0, getPointerTy()); 1136 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1137 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1138 else 1139 Base = N; 1140 return true; // [r+0] 1141} 1142 1143/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 1144/// represented as an indexed [r+r] operation. 1145bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, 1146 SDValue &Index, 1147 SelectionDAG &DAG) const { 1148 // Check to see if we can easily represent this as an [r+r] address. This 1149 // will fail if it thinks that the address is more profitably represented as 1150 // reg+imm, e.g. where imm = 0. 1151 if (SelectAddressRegReg(N, Base, Index, DAG)) 1152 return true; 1153 1154 // If the operand is an addition, always emit this as [r+r], since this is 1155 // better (for code size, and execution, as the memop does the add for free) 1156 // than emitting an explicit add. 1157 if (N.getOpcode() == ISD::ADD) { 1158 Base = N.getOperand(0); 1159 Index = N.getOperand(1); 1160 return true; 1161 } 1162 1163 // Otherwise, do it the hard way, using R0 as the base register. 1164 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, 1165 N.getValueType()); 1166 Index = N; 1167 return true; 1168} 1169 1170/// getPreIndexedAddressParts - returns true by value, base pointer and 1171/// offset pointer and addressing mode by reference if the node's address 1172/// can be legally represented as pre-indexed load / store address. 1173bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1174 SDValue &Offset, 1175 ISD::MemIndexedMode &AM, 1176 SelectionDAG &DAG) const { 1177 if (DisablePPCPreinc) return false; 1178 1179 bool isLoad = true; 1180 SDValue Ptr; 1181 EVT VT; 1182 unsigned Alignment; 1183 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1184 Ptr = LD->getBasePtr(); 1185 VT = LD->getMemoryVT(); 1186 Alignment = LD->getAlignment(); 1187 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1188 Ptr = ST->getBasePtr(); 1189 VT = ST->getMemoryVT(); 1190 Alignment = ST->getAlignment(); 1191 isLoad = false; 1192 } else 1193 return false; 1194 1195 // PowerPC doesn't have preinc load/store instructions for vectors. 1196 if (VT.isVector()) 1197 return false; 1198 1199 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) { 1200 1201 // Common code will reject creating a pre-inc form if the base pointer 1202 // is a frame index, or if N is a store and the base pointer is either 1203 // the same as or a predecessor of the value being stored. Check for 1204 // those situations here, and try with swapped Base/Offset instead. 1205 bool Swap = false; 1206 1207 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base)) 1208 Swap = true; 1209 else if (!isLoad) { 1210 SDValue Val = cast<StoreSDNode>(N)->getValue(); 1211 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode())) 1212 Swap = true; 1213 } 1214 1215 if (Swap) 1216 std::swap(Base, Offset); 1217 1218 AM = ISD::PRE_INC; 1219 return true; 1220 } 1221 1222 // LDU/STU can only handle immediates that are a multiple of 4. 1223 if (VT != MVT::i64) { 1224 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false)) 1225 return false; 1226 } else { 1227 // LDU/STU need an address with at least 4-byte alignment. 1228 if (Alignment < 4) 1229 return false; 1230 1231 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true)) 1232 return false; 1233 } 1234 1235 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1236 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 1237 // sext i32 to i64 when addr mode is r+i. 1238 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 1239 LD->getExtensionType() == ISD::SEXTLOAD && 1240 isa<ConstantSDNode>(Offset)) 1241 return false; 1242 } 1243 1244 AM = ISD::PRE_INC; 1245 return true; 1246} 1247 1248//===----------------------------------------------------------------------===// 1249// LowerOperation implementation 1250//===----------------------------------------------------------------------===// 1251 1252/// GetLabelAccessInfo - Return true if we should reference labels using a 1253/// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags. 1254static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags, 1255 unsigned &LoOpFlags, const GlobalValue *GV = 0) { 1256 HiOpFlags = PPCII::MO_HA16; 1257 LoOpFlags = PPCII::MO_LO16; 1258 1259 // Don't use the pic base if not in PIC relocation model. Or if we are on a 1260 // non-darwin platform. We don't support PIC on other platforms yet. 1261 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ && 1262 TM.getSubtarget<PPCSubtarget>().isDarwin(); 1263 if (isPIC) { 1264 HiOpFlags |= PPCII::MO_PIC_FLAG; 1265 LoOpFlags |= PPCII::MO_PIC_FLAG; 1266 } 1267 1268 // If this is a reference to a global value that requires a non-lazy-ptr, make 1269 // sure that instruction lowering adds it. 1270 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) { 1271 HiOpFlags |= PPCII::MO_NLP_FLAG; 1272 LoOpFlags |= PPCII::MO_NLP_FLAG; 1273 1274 if (GV->hasHiddenVisibility()) { 1275 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; 1276 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; 1277 } 1278 } 1279 1280 return isPIC; 1281} 1282 1283static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, 1284 SelectionDAG &DAG) { 1285 EVT PtrVT = HiPart.getValueType(); 1286 SDValue Zero = DAG.getConstant(0, PtrVT); 1287 SDLoc DL(HiPart); 1288 1289 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero); 1290 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero); 1291 1292 // With PIC, the first instruction is actually "GR+hi(&G)". 1293 if (isPIC) 1294 Hi = DAG.getNode(ISD::ADD, DL, PtrVT, 1295 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi); 1296 1297 // Generate non-pic code that has direct accesses to the constant pool. 1298 // The address of the global is just (hi(&g)+lo(&g)). 1299 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1300} 1301 1302SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, 1303 SelectionDAG &DAG) const { 1304 EVT PtrVT = Op.getValueType(); 1305 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1306 const Constant *C = CP->getConstVal(); 1307 1308 // 64-bit SVR4 ABI code is always position-independent. 1309 // The actual address of the GlobalValue is stored in the TOC. 1310 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1311 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0); 1312 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA, 1313 DAG.getRegister(PPC::X2, MVT::i64)); 1314 } 1315 1316 unsigned MOHiFlag, MOLoFlag; 1317 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1318 SDValue CPIHi = 1319 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag); 1320 SDValue CPILo = 1321 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag); 1322 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG); 1323} 1324 1325SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 1326 EVT PtrVT = Op.getValueType(); 1327 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1328 1329 // 64-bit SVR4 ABI code is always position-independent. 1330 // The actual address of the GlobalValue is stored in the TOC. 1331 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1332 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1333 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA, 1334 DAG.getRegister(PPC::X2, MVT::i64)); 1335 } 1336 1337 unsigned MOHiFlag, MOLoFlag; 1338 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1339 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag); 1340 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag); 1341 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG); 1342} 1343 1344SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, 1345 SelectionDAG &DAG) const { 1346 EVT PtrVT = Op.getValueType(); 1347 1348 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1349 1350 unsigned MOHiFlag, MOLoFlag; 1351 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1352 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag); 1353 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag); 1354 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG); 1355} 1356 1357SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, 1358 SelectionDAG &DAG) const { 1359 1360 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1361 SDLoc dl(GA); 1362 const GlobalValue *GV = GA->getGlobal(); 1363 EVT PtrVT = getPointerTy(); 1364 bool is64bit = PPCSubTarget.isPPC64(); 1365 1366 TLSModel::Model Model = getTargetMachine().getTLSModel(GV); 1367 1368 if (Model == TLSModel::LocalExec) { 1369 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1370 PPCII::MO_TPREL16_HA); 1371 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1372 PPCII::MO_TPREL16_LO); 1373 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2, 1374 is64bit ? MVT::i64 : MVT::i32); 1375 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg); 1376 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi); 1377 } 1378 1379 if (!is64bit) 1380 llvm_unreachable("only local-exec is currently supported for ppc32"); 1381 1382 if (Model == TLSModel::InitialExec) { 1383 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0); 1384 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); 1385 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl, 1386 PtrVT, GOTReg, TGA); 1387 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl, 1388 PtrVT, TGA, TPOffsetHi); 1389 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGA); 1390 } 1391 1392 if (Model == TLSModel::GeneralDynamic) { 1393 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0); 1394 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); 1395 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT, 1396 GOTReg, TGA); 1397 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT, 1398 GOTEntryHi, TGA); 1399 1400 // We need a chain node, and don't have one handy. The underlying 1401 // call has no side effects, so using the function entry node 1402 // suffices. 1403 SDValue Chain = DAG.getEntryNode(); 1404 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry); 1405 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64); 1406 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl, 1407 PtrVT, ParmReg, TGA); 1408 // The return value from GET_TLS_ADDR really is in X3 already, but 1409 // some hacks are needed here to tie everything together. The extra 1410 // copies dissolve during subsequent transforms. 1411 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr); 1412 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT); 1413 } 1414 1415 if (Model == TLSModel::LocalDynamic) { 1416 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0); 1417 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); 1418 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT, 1419 GOTReg, TGA); 1420 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT, 1421 GOTEntryHi, TGA); 1422 1423 // We need a chain node, and don't have one handy. The underlying 1424 // call has no side effects, so using the function entry node 1425 // suffices. 1426 SDValue Chain = DAG.getEntryNode(); 1427 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry); 1428 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64); 1429 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl, 1430 PtrVT, ParmReg, TGA); 1431 // The return value from GET_TLSLD_ADDR really is in X3 already, but 1432 // some hacks are needed here to tie everything together. The extra 1433 // copies dissolve during subsequent transforms. 1434 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr); 1435 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT, 1436 Chain, ParmReg, TGA); 1437 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA); 1438 } 1439 1440 llvm_unreachable("Unknown TLS model!"); 1441} 1442 1443SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, 1444 SelectionDAG &DAG) const { 1445 EVT PtrVT = Op.getValueType(); 1446 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1447 SDLoc DL(GSDN); 1448 const GlobalValue *GV = GSDN->getGlobal(); 1449 1450 // 64-bit SVR4 ABI code is always position-independent. 1451 // The actual address of the GlobalValue is stored in the TOC. 1452 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1453 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset()); 1454 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA, 1455 DAG.getRegister(PPC::X2, MVT::i64)); 1456 } 1457 1458 unsigned MOHiFlag, MOLoFlag; 1459 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV); 1460 1461 SDValue GAHi = 1462 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag); 1463 SDValue GALo = 1464 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag); 1465 1466 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG); 1467 1468 // If the global reference is actually to a non-lazy-pointer, we have to do an 1469 // extra load to get the address of the global. 1470 if (MOHiFlag & PPCII::MO_NLP_FLAG) 1471 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(), 1472 false, false, false, 0); 1473 return Ptr; 1474} 1475 1476SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1477 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1478 SDLoc dl(Op); 1479 1480 // If we're comparing for equality to zero, expose the fact that this is 1481 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1482 // fold the new nodes. 1483 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1484 if (C->isNullValue() && CC == ISD::SETEQ) { 1485 EVT VT = Op.getOperand(0).getValueType(); 1486 SDValue Zext = Op.getOperand(0); 1487 if (VT.bitsLT(MVT::i32)) { 1488 VT = MVT::i32; 1489 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); 1490 } 1491 unsigned Log2b = Log2_32(VT.getSizeInBits()); 1492 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); 1493 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, 1494 DAG.getConstant(Log2b, MVT::i32)); 1495 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); 1496 } 1497 // Leave comparisons against 0 and -1 alone for now, since they're usually 1498 // optimized. FIXME: revisit this when we can custom lower all setcc 1499 // optimizations. 1500 if (C->isAllOnesValue() || C->isNullValue()) 1501 return SDValue(); 1502 } 1503 1504 // If we have an integer seteq/setne, turn it into a compare against zero 1505 // by xor'ing the rhs with the lhs, which is faster than setting a 1506 // condition register, reading it back out, and masking the correct bit. The 1507 // normal approach here uses sub to do this instead of xor. Using xor exposes 1508 // the result to other bit-twiddling opportunities. 1509 EVT LHSVT = Op.getOperand(0).getValueType(); 1510 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1511 EVT VT = Op.getValueType(); 1512 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), 1513 Op.getOperand(1)); 1514 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); 1515 } 1516 return SDValue(); 1517} 1518 1519SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, 1520 const PPCSubtarget &Subtarget) const { 1521 SDNode *Node = Op.getNode(); 1522 EVT VT = Node->getValueType(0); 1523 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1524 SDValue InChain = Node->getOperand(0); 1525 SDValue VAListPtr = Node->getOperand(1); 1526 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1527 SDLoc dl(Node); 1528 1529 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); 1530 1531 // gpr_index 1532 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, 1533 VAListPtr, MachinePointerInfo(SV), MVT::i8, 1534 false, false, 0); 1535 InChain = GprIndex.getValue(1); 1536 1537 if (VT == MVT::i64) { 1538 // Check if GprIndex is even 1539 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex, 1540 DAG.getConstant(1, MVT::i32)); 1541 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd, 1542 DAG.getConstant(0, MVT::i32), ISD::SETNE); 1543 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex, 1544 DAG.getConstant(1, MVT::i32)); 1545 // Align GprIndex to be even if it isn't 1546 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne, 1547 GprIndex); 1548 } 1549 1550 // fpr index is 1 byte after gpr 1551 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1552 DAG.getConstant(1, MVT::i32)); 1553 1554 // fpr 1555 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, 1556 FprPtr, MachinePointerInfo(SV), MVT::i8, 1557 false, false, 0); 1558 InChain = FprIndex.getValue(1); 1559 1560 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1561 DAG.getConstant(8, MVT::i32)); 1562 1563 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1564 DAG.getConstant(4, MVT::i32)); 1565 1566 // areas 1567 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, 1568 MachinePointerInfo(), false, false, 1569 false, 0); 1570 InChain = OverflowArea.getValue(1); 1571 1572 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, 1573 MachinePointerInfo(), false, false, 1574 false, 0); 1575 InChain = RegSaveArea.getValue(1); 1576 1577 // select overflow_area if index > 8 1578 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, 1579 DAG.getConstant(8, MVT::i32), ISD::SETLT); 1580 1581 // adjustment constant gpr_index * 4/8 1582 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32, 1583 VT.isInteger() ? GprIndex : FprIndex, 1584 DAG.getConstant(VT.isInteger() ? 4 : 8, 1585 MVT::i32)); 1586 1587 // OurReg = RegSaveArea + RegConstant 1588 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea, 1589 RegConstant); 1590 1591 // Floating types are 32 bytes into RegSaveArea 1592 if (VT.isFloatingPoint()) 1593 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg, 1594 DAG.getConstant(32, MVT::i32)); 1595 1596 // increase {f,g}pr_index by 1 (or 2 if VT is i64) 1597 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32, 1598 VT.isInteger() ? GprIndex : FprIndex, 1599 DAG.getConstant(VT == MVT::i64 ? 2 : 1, 1600 MVT::i32)); 1601 1602 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1, 1603 VT.isInteger() ? VAListPtr : FprPtr, 1604 MachinePointerInfo(SV), 1605 MVT::i8, false, false, 0); 1606 1607 // determine if we should load from reg_save_area or overflow_area 1608 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea); 1609 1610 // increase overflow_area by 4/8 if gpr/fpr > 8 1611 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea, 1612 DAG.getConstant(VT.isInteger() ? 4 : 8, 1613 MVT::i32)); 1614 1615 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea, 1616 OverflowAreaPlusN); 1617 1618 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, 1619 OverflowAreaPtr, 1620 MachinePointerInfo(), 1621 MVT::i32, false, false, 0); 1622 1623 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(), 1624 false, false, false, 0); 1625} 1626 1627SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 1628 SelectionDAG &DAG) const { 1629 return Op.getOperand(0); 1630} 1631 1632SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 1633 SelectionDAG &DAG) const { 1634 SDValue Chain = Op.getOperand(0); 1635 SDValue Trmp = Op.getOperand(1); // trampoline 1636 SDValue FPtr = Op.getOperand(2); // nested function 1637 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 1638 SDLoc dl(Op); 1639 1640 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1641 bool isPPC64 = (PtrVT == MVT::i64); 1642 Type *IntPtrTy = 1643 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType( 1644 *DAG.getContext()); 1645 1646 TargetLowering::ArgListTy Args; 1647 TargetLowering::ArgListEntry Entry; 1648 1649 Entry.Ty = IntPtrTy; 1650 Entry.Node = Trmp; Args.push_back(Entry); 1651 1652 // TrampSize == (isPPC64 ? 48 : 40); 1653 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, 1654 isPPC64 ? MVT::i64 : MVT::i32); 1655 Args.push_back(Entry); 1656 1657 Entry.Node = FPtr; Args.push_back(Entry); 1658 Entry.Node = Nest; Args.push_back(Entry); 1659 1660 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) 1661 TargetLowering::CallLoweringInfo CLI(Chain, 1662 Type::getVoidTy(*DAG.getContext()), 1663 false, false, false, false, 0, 1664 CallingConv::C, 1665 /*isTailCall=*/false, 1666 /*doesNotRet=*/false, 1667 /*isReturnValueUsed=*/true, 1668 DAG.getExternalSymbol("__trampoline_setup", PtrVT), 1669 Args, DAG, dl); 1670 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1671 1672 return CallResult.second; 1673} 1674 1675SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, 1676 const PPCSubtarget &Subtarget) const { 1677 MachineFunction &MF = DAG.getMachineFunction(); 1678 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1679 1680 SDLoc dl(Op); 1681 1682 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) { 1683 // vastart just stores the address of the VarArgsFrameIndex slot into the 1684 // memory location argument. 1685 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1686 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1687 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1688 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 1689 MachinePointerInfo(SV), 1690 false, false, 0); 1691 } 1692 1693 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct. 1694 // We suppose the given va_list is already allocated. 1695 // 1696 // typedef struct { 1697 // char gpr; /* index into the array of 8 GPRs 1698 // * stored in the register save area 1699 // * gpr=0 corresponds to r3, 1700 // * gpr=1 to r4, etc. 1701 // */ 1702 // char fpr; /* index into the array of 8 FPRs 1703 // * stored in the register save area 1704 // * fpr=0 corresponds to f1, 1705 // * fpr=1 to f2, etc. 1706 // */ 1707 // char *overflow_arg_area; 1708 // /* location on stack that holds 1709 // * the next overflow argument 1710 // */ 1711 // char *reg_save_area; 1712 // /* where r3:r10 and f1:f8 (if saved) 1713 // * are stored 1714 // */ 1715 // } va_list[1]; 1716 1717 1718 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32); 1719 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32); 1720 1721 1722 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1723 1724 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(), 1725 PtrVT); 1726 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1727 PtrVT); 1728 1729 uint64_t FrameOffset = PtrVT.getSizeInBits()/8; 1730 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1731 1732 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; 1733 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1734 1735 uint64_t FPROffset = 1; 1736 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1737 1738 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1739 1740 // Store first byte : number of int regs 1741 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, 1742 Op.getOperand(1), 1743 MachinePointerInfo(SV), 1744 MVT::i8, false, false, 0); 1745 uint64_t nextOffset = FPROffset; 1746 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), 1747 ConstFPROffset); 1748 1749 // Store second byte : number of float regs 1750 SDValue secondStore = 1751 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, 1752 MachinePointerInfo(SV, nextOffset), MVT::i8, 1753 false, false, 0); 1754 nextOffset += StackOffset; 1755 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); 1756 1757 // Store second word : arguments given on stack 1758 SDValue thirdStore = 1759 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, 1760 MachinePointerInfo(SV, nextOffset), 1761 false, false, 0); 1762 nextOffset += FrameOffset; 1763 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset); 1764 1765 // Store third word : arguments given in registers 1766 return DAG.getStore(thirdStore, dl, FR, nextPtr, 1767 MachinePointerInfo(SV, nextOffset), 1768 false, false, 0); 1769 1770} 1771 1772#include "PPCGenCallingConv.inc" 1773 1774static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 1775 CCValAssign::LocInfo &LocInfo, 1776 ISD::ArgFlagsTy &ArgFlags, 1777 CCState &State) { 1778 return true; 1779} 1780 1781static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 1782 MVT &LocVT, 1783 CCValAssign::LocInfo &LocInfo, 1784 ISD::ArgFlagsTy &ArgFlags, 1785 CCState &State) { 1786 static const uint16_t ArgRegs[] = { 1787 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1788 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1789 }; 1790 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1791 1792 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1793 1794 // Skip one register if the first unallocated register has an even register 1795 // number and there are still argument registers available which have not been 1796 // allocated yet. RegNum is actually an index into ArgRegs, which means we 1797 // need to skip a register if RegNum is odd. 1798 if (RegNum != NumArgRegs && RegNum % 2 == 1) { 1799 State.AllocateReg(ArgRegs[RegNum]); 1800 } 1801 1802 // Always return false here, as this function only makes sure that the first 1803 // unallocated register has an odd register number and does not actually 1804 // allocate a register for the current argument. 1805 return false; 1806} 1807 1808static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 1809 MVT &LocVT, 1810 CCValAssign::LocInfo &LocInfo, 1811 ISD::ArgFlagsTy &ArgFlags, 1812 CCState &State) { 1813 static const uint16_t ArgRegs[] = { 1814 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1815 PPC::F8 1816 }; 1817 1818 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1819 1820 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1821 1822 // If there is only one Floating-point register left we need to put both f64 1823 // values of a split ppc_fp128 value on the stack. 1824 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { 1825 State.AllocateReg(ArgRegs[RegNum]); 1826 } 1827 1828 // Always return false here, as this function only makes sure that the two f64 1829 // values a ppc_fp128 value is split into are both passed in registers or both 1830 // passed on the stack and does not actually allocate a register for the 1831 // current argument. 1832 return false; 1833} 1834 1835/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1836/// on Darwin. 1837static const uint16_t *GetFPR() { 1838 static const uint16_t FPR[] = { 1839 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1840 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1841 }; 1842 1843 return FPR; 1844} 1845 1846/// CalculateStackSlotSize - Calculates the size reserved for this argument on 1847/// the stack. 1848static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, 1849 unsigned PtrByteSize) { 1850 unsigned ArgSize = ArgVT.getSizeInBits()/8; 1851 if (Flags.isByVal()) 1852 ArgSize = Flags.getByValSize(); 1853 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1854 1855 return ArgSize; 1856} 1857 1858SDValue 1859PPCTargetLowering::LowerFormalArguments(SDValue Chain, 1860 CallingConv::ID CallConv, bool isVarArg, 1861 const SmallVectorImpl<ISD::InputArg> 1862 &Ins, 1863 SDLoc dl, SelectionDAG &DAG, 1864 SmallVectorImpl<SDValue> &InVals) 1865 const { 1866 if (PPCSubTarget.isSVR4ABI()) { 1867 if (PPCSubTarget.isPPC64()) 1868 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins, 1869 dl, DAG, InVals); 1870 else 1871 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins, 1872 dl, DAG, InVals); 1873 } else { 1874 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, 1875 dl, DAG, InVals); 1876 } 1877} 1878 1879SDValue 1880PPCTargetLowering::LowerFormalArguments_32SVR4( 1881 SDValue Chain, 1882 CallingConv::ID CallConv, bool isVarArg, 1883 const SmallVectorImpl<ISD::InputArg> 1884 &Ins, 1885 SDLoc dl, SelectionDAG &DAG, 1886 SmallVectorImpl<SDValue> &InVals) const { 1887 1888 // 32-bit SVR4 ABI Stack Frame Layout: 1889 // +-----------------------------------+ 1890 // +--> | Back chain | 1891 // | +-----------------------------------+ 1892 // | | Floating-point register save area | 1893 // | +-----------------------------------+ 1894 // | | General register save area | 1895 // | +-----------------------------------+ 1896 // | | CR save word | 1897 // | +-----------------------------------+ 1898 // | | VRSAVE save word | 1899 // | +-----------------------------------+ 1900 // | | Alignment padding | 1901 // | +-----------------------------------+ 1902 // | | Vector register save area | 1903 // | +-----------------------------------+ 1904 // | | Local variable space | 1905 // | +-----------------------------------+ 1906 // | | Parameter list area | 1907 // | +-----------------------------------+ 1908 // | | LR save word | 1909 // | +-----------------------------------+ 1910 // SP--> +--- | Back chain | 1911 // +-----------------------------------+ 1912 // 1913 // Specifications: 1914 // System V Application Binary Interface PowerPC Processor Supplement 1915 // AltiVec Technology Programming Interface Manual 1916 1917 MachineFunction &MF = DAG.getMachineFunction(); 1918 MachineFrameInfo *MFI = MF.getFrameInfo(); 1919 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1920 1921 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1922 // Potential tail calls could cause overwriting of argument stack slots. 1923 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt && 1924 (CallConv == CallingConv::Fast)); 1925 unsigned PtrByteSize = 4; 1926 1927 // Assign locations to all of the incoming arguments. 1928 SmallVector<CCValAssign, 16> ArgLocs; 1929 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1930 getTargetMachine(), ArgLocs, *DAG.getContext()); 1931 1932 // Reserve space for the linkage area on the stack. 1933 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); 1934 1935 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4); 1936 1937 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1938 CCValAssign &VA = ArgLocs[i]; 1939 1940 // Arguments stored in registers. 1941 if (VA.isRegLoc()) { 1942 const TargetRegisterClass *RC; 1943 EVT ValVT = VA.getValVT(); 1944 1945 switch (ValVT.getSimpleVT().SimpleTy) { 1946 default: 1947 llvm_unreachable("ValVT not supported by formal arguments Lowering"); 1948 case MVT::i32: 1949 RC = &PPC::GPRCRegClass; 1950 break; 1951 case MVT::f32: 1952 RC = &PPC::F4RCRegClass; 1953 break; 1954 case MVT::f64: 1955 RC = &PPC::F8RCRegClass; 1956 break; 1957 case MVT::v16i8: 1958 case MVT::v8i16: 1959 case MVT::v4i32: 1960 case MVT::v4f32: 1961 RC = &PPC::VRRCRegClass; 1962 break; 1963 } 1964 1965 // Transform the arguments stored in physical registers into virtual ones. 1966 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1967 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT); 1968 1969 InVals.push_back(ArgValue); 1970 } else { 1971 // Argument stored in memory. 1972 assert(VA.isMemLoc()); 1973 1974 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; 1975 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), 1976 isImmutable); 1977 1978 // Create load nodes to retrieve arguments from the stack. 1979 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1980 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 1981 MachinePointerInfo(), 1982 false, false, false, 0)); 1983 } 1984 } 1985 1986 // Assign locations to all of the incoming aggregate by value arguments. 1987 // Aggregates passed by value are stored in the local variable space of the 1988 // caller's stack frame, right above the parameter list area. 1989 SmallVector<CCValAssign, 16> ByValArgLocs; 1990 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1991 getTargetMachine(), ByValArgLocs, *DAG.getContext()); 1992 1993 // Reserve stack space for the allocations in CCInfo. 1994 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 1995 1996 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal); 1997 1998 // Area that is at least reserved in the caller of this function. 1999 unsigned MinReservedArea = CCByValInfo.getNextStackOffset(); 2000 2001 // Set the size that is at least reserved in caller of this function. Tail 2002 // call optimized function's reserved stack space needs to be aligned so that 2003 // taking the difference between two stack areas will result in an aligned 2004 // stack. 2005 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2006 2007 MinReservedArea = 2008 std::max(MinReservedArea, 2009 PPCFrameLowering::getMinCallFrameSize(false, false)); 2010 2011 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> 2012 getStackAlignment(); 2013 unsigned AlignMask = TargetAlign-1; 2014 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 2015 2016 FI->setMinReservedArea(MinReservedArea); 2017 2018 SmallVector<SDValue, 8> MemOps; 2019 2020 // If the function takes variable number of arguments, make a frame index for 2021 // the start of the first vararg value... for expansion of llvm.va_start. 2022 if (isVarArg) { 2023 static const uint16_t GPArgRegs[] = { 2024 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 2025 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 2026 }; 2027 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs); 2028 2029 static const uint16_t FPArgRegs[] = { 2030 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 2031 PPC::F8 2032 }; 2033 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs); 2034 2035 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs, 2036 NumGPArgRegs)); 2037 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs, 2038 NumFPArgRegs)); 2039 2040 // Make room for NumGPArgRegs and NumFPArgRegs. 2041 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 + 2042 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8; 2043 2044 FuncInfo->setVarArgsStackOffset( 2045 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2046 CCInfo.getNextStackOffset(), true)); 2047 2048 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false)); 2049 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2050 2051 // The fixed integer arguments of a variadic function are stored to the 2052 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing 2053 // the result of va_next. 2054 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) { 2055 // Get an existing live-in vreg, or add a new one. 2056 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); 2057 if (!VReg) 2058 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); 2059 2060 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2061 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2062 MachinePointerInfo(), false, false, 0); 2063 MemOps.push_back(Store); 2064 // Increment the address by four for the next argument to store 2065 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2066 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2067 } 2068 2069 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6 2070 // is set. 2071 // The double arguments are stored to the VarArgsFrameIndex 2072 // on the stack. 2073 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) { 2074 // Get an existing live-in vreg, or add a new one. 2075 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); 2076 if (!VReg) 2077 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); 2078 2079 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); 2080 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2081 MachinePointerInfo(), false, false, 0); 2082 MemOps.push_back(Store); 2083 // Increment the address by eight for the next argument to store 2084 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8, 2085 PtrVT); 2086 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2087 } 2088 } 2089 2090 if (!MemOps.empty()) 2091 Chain = DAG.getNode(ISD::TokenFactor, dl, 2092 MVT::Other, &MemOps[0], MemOps.size()); 2093 2094 return Chain; 2095} 2096 2097// PPC64 passes i8, i16, and i32 values in i64 registers. Promote 2098// value to MVT::i64 and then truncate to the correct register size. 2099SDValue 2100PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, 2101 SelectionDAG &DAG, SDValue ArgVal, 2102 SDLoc dl) const { 2103 if (Flags.isSExt()) 2104 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, 2105 DAG.getValueType(ObjectVT)); 2106 else if (Flags.isZExt()) 2107 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, 2108 DAG.getValueType(ObjectVT)); 2109 2110 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); 2111} 2112 2113// Set the size that is at least reserved in caller of this function. Tail 2114// call optimized functions' reserved stack space needs to be aligned so that 2115// taking the difference between two stack areas will result in an aligned 2116// stack. 2117void 2118PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG, 2119 unsigned nAltivecParamsAtEnd, 2120 unsigned MinReservedArea, 2121 bool isPPC64) const { 2122 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2123 // Add the Altivec parameters at the end, if needed. 2124 if (nAltivecParamsAtEnd) { 2125 MinReservedArea = ((MinReservedArea+15)/16)*16; 2126 MinReservedArea += 16*nAltivecParamsAtEnd; 2127 } 2128 MinReservedArea = 2129 std::max(MinReservedArea, 2130 PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); 2131 unsigned TargetAlign 2132 = DAG.getMachineFunction().getTarget().getFrameLowering()-> 2133 getStackAlignment(); 2134 unsigned AlignMask = TargetAlign-1; 2135 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 2136 FI->setMinReservedArea(MinReservedArea); 2137} 2138 2139SDValue 2140PPCTargetLowering::LowerFormalArguments_64SVR4( 2141 SDValue Chain, 2142 CallingConv::ID CallConv, bool isVarArg, 2143 const SmallVectorImpl<ISD::InputArg> 2144 &Ins, 2145 SDLoc dl, SelectionDAG &DAG, 2146 SmallVectorImpl<SDValue> &InVals) const { 2147 // TODO: add description of PPC stack frame format, or at least some docs. 2148 // 2149 MachineFunction &MF = DAG.getMachineFunction(); 2150 MachineFrameInfo *MFI = MF.getFrameInfo(); 2151 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 2152 2153 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2154 // Potential tail calls could cause overwriting of argument stack slots. 2155 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt && 2156 (CallConv == CallingConv::Fast)); 2157 unsigned PtrByteSize = 8; 2158 2159 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true); 2160 // Area that is at least reserved in caller of this function. 2161 unsigned MinReservedArea = ArgOffset; 2162 2163 static const uint16_t GPR[] = { 2164 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 2165 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 2166 }; 2167 2168 static const uint16_t *FPR = GetFPR(); 2169 2170 static const uint16_t VR[] = { 2171 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 2172 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 2173 }; 2174 2175 const unsigned Num_GPR_Regs = array_lengthof(GPR); 2176 const unsigned Num_FPR_Regs = 13; 2177 const unsigned Num_VR_Regs = array_lengthof(VR); 2178 2179 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 2180 2181 // Add DAG nodes to load the arguments or copy them out of registers. On 2182 // entry to a function on PPC, the arguments start after the linkage area, 2183 // although the first ones are often in registers. 2184 2185 SmallVector<SDValue, 8> MemOps; 2186 unsigned nAltivecParamsAtEnd = 0; 2187 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin(); 2188 unsigned CurArgIdx = 0; 2189 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { 2190 SDValue ArgVal; 2191 bool needsLoad = false; 2192 EVT ObjectVT = Ins[ArgNo].VT; 2193 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 2194 unsigned ArgSize = ObjSize; 2195 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 2196 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx); 2197 CurArgIdx = Ins[ArgNo].OrigArgIndex; 2198 2199 unsigned CurArgOffset = ArgOffset; 2200 2201 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 2202 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 2203 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 2204 if (isVarArg) { 2205 MinReservedArea = ((MinReservedArea+15)/16)*16; 2206 MinReservedArea += CalculateStackSlotSize(ObjectVT, 2207 Flags, 2208 PtrByteSize); 2209 } else 2210 nAltivecParamsAtEnd++; 2211 } else 2212 // Calculate min reserved area. 2213 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 2214 Flags, 2215 PtrByteSize); 2216 2217 // FIXME the codegen can be much improved in some cases. 2218 // We do not have to keep everything in memory. 2219 if (Flags.isByVal()) { 2220 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 2221 ObjSize = Flags.getByValSize(); 2222 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 2223 // Empty aggregate parameters do not take up registers. Examples: 2224 // struct { } a; 2225 // union { } b; 2226 // int c[0]; 2227 // etc. However, we have to provide a place-holder in InVals, so 2228 // pretend we have an 8-byte item at the current address for that 2229 // purpose. 2230 if (!ObjSize) { 2231 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2232 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2233 InVals.push_back(FIN); 2234 continue; 2235 } 2236 // All aggregates smaller than 8 bytes must be passed right-justified. 2237 if (ObjSize < PtrByteSize) 2238 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize); 2239 // The value of the object is its address. 2240 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true); 2241 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2242 InVals.push_back(FIN); 2243 2244 if (ObjSize < 8) { 2245 if (GPR_idx != Num_GPR_Regs) { 2246 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2247 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2248 SDValue Store; 2249 2250 if (ObjSize==1 || ObjSize==2 || ObjSize==4) { 2251 EVT ObjType = (ObjSize == 1 ? MVT::i8 : 2252 (ObjSize == 2 ? MVT::i16 : MVT::i32)); 2253 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 2254 MachinePointerInfo(FuncArg, CurArgOffset), 2255 ObjType, false, false, 0); 2256 } else { 2257 // For sizes that don't fit a truncating store (3, 5, 6, 7), 2258 // store the whole register as-is to the parameter save area 2259 // slot. The address of the parameter was already calculated 2260 // above (InVals.push_back(FIN)) to be the right-justified 2261 // offset within the slot. For this store, we need a new 2262 // frame index that points at the beginning of the slot. 2263 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2264 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2265 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2266 MachinePointerInfo(FuncArg, ArgOffset), 2267 false, false, 0); 2268 } 2269 2270 MemOps.push_back(Store); 2271 ++GPR_idx; 2272 } 2273 // Whether we copied from a register or not, advance the offset 2274 // into the parameter save area by a full doubleword. 2275 ArgOffset += PtrByteSize; 2276 continue; 2277 } 2278 2279 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 2280 // Store whatever pieces of the object are in registers 2281 // to memory. ArgOffset will be the address of the beginning 2282 // of the object. 2283 if (GPR_idx != Num_GPR_Regs) { 2284 unsigned VReg; 2285 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2286 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2287 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2288 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2289 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2290 MachinePointerInfo(FuncArg, ArgOffset), 2291 false, false, 0); 2292 MemOps.push_back(Store); 2293 ++GPR_idx; 2294 ArgOffset += PtrByteSize; 2295 } else { 2296 ArgOffset += ArgSize - j; 2297 break; 2298 } 2299 } 2300 continue; 2301 } 2302 2303 switch (ObjectVT.getSimpleVT().SimpleTy) { 2304 default: llvm_unreachable("Unhandled argument type!"); 2305 case MVT::i32: 2306 case MVT::i64: 2307 if (GPR_idx != Num_GPR_Regs) { 2308 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2309 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2310 2311 if (ObjectVT == MVT::i32) 2312 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 2313 // value to MVT::i64 and then truncate to the correct register size. 2314 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl); 2315 2316 ++GPR_idx; 2317 } else { 2318 needsLoad = true; 2319 ArgSize = PtrByteSize; 2320 } 2321 ArgOffset += 8; 2322 break; 2323 2324 case MVT::f32: 2325 case MVT::f64: 2326 // Every 8 bytes of argument space consumes one of the GPRs available for 2327 // argument passing. 2328 if (GPR_idx != Num_GPR_Regs) { 2329 ++GPR_idx; 2330 } 2331 if (FPR_idx != Num_FPR_Regs) { 2332 unsigned VReg; 2333 2334 if (ObjectVT == MVT::f32) 2335 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 2336 else 2337 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 2338 2339 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2340 ++FPR_idx; 2341 } else { 2342 needsLoad = true; 2343 ArgSize = PtrByteSize; 2344 } 2345 2346 ArgOffset += 8; 2347 break; 2348 case MVT::v4f32: 2349 case MVT::v4i32: 2350 case MVT::v8i16: 2351 case MVT::v16i8: 2352 // Note that vector arguments in registers don't reserve stack space, 2353 // except in varargs functions. 2354 if (VR_idx != Num_VR_Regs) { 2355 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 2356 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2357 if (isVarArg) { 2358 while ((ArgOffset % 16) != 0) { 2359 ArgOffset += PtrByteSize; 2360 if (GPR_idx != Num_GPR_Regs) 2361 GPR_idx++; 2362 } 2363 ArgOffset += 16; 2364 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 2365 } 2366 ++VR_idx; 2367 } else { 2368 // Vectors are aligned. 2369 ArgOffset = ((ArgOffset+15)/16)*16; 2370 CurArgOffset = ArgOffset; 2371 ArgOffset += 16; 2372 needsLoad = true; 2373 } 2374 break; 2375 } 2376 2377 // We need to load the argument to a virtual register if we determined 2378 // above that we ran out of physical registers of the appropriate type. 2379 if (needsLoad) { 2380 int FI = MFI->CreateFixedObject(ObjSize, 2381 CurArgOffset + (ArgSize - ObjSize), 2382 isImmutable); 2383 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2384 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), 2385 false, false, false, 0); 2386 } 2387 2388 InVals.push_back(ArgVal); 2389 } 2390 2391 // Set the size that is at least reserved in caller of this function. Tail 2392 // call optimized functions' reserved stack space needs to be aligned so that 2393 // taking the difference between two stack areas will result in an aligned 2394 // stack. 2395 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true); 2396 2397 // If the function takes variable number of arguments, make a frame index for 2398 // the start of the first vararg value... for expansion of llvm.va_start. 2399 if (isVarArg) { 2400 int Depth = ArgOffset; 2401 2402 FuncInfo->setVarArgsFrameIndex( 2403 MFI->CreateFixedObject(PtrByteSize, Depth, true)); 2404 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2405 2406 // If this function is vararg, store any remaining integer argument regs 2407 // to their spots on the stack so that they may be loaded by deferencing the 2408 // result of va_next. 2409 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2410 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2411 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2412 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2413 MachinePointerInfo(), false, false, 0); 2414 MemOps.push_back(Store); 2415 // Increment the address by four for the next argument to store 2416 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT); 2417 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2418 } 2419 } 2420 2421 if (!MemOps.empty()) 2422 Chain = DAG.getNode(ISD::TokenFactor, dl, 2423 MVT::Other, &MemOps[0], MemOps.size()); 2424 2425 return Chain; 2426} 2427 2428SDValue 2429PPCTargetLowering::LowerFormalArguments_Darwin( 2430 SDValue Chain, 2431 CallingConv::ID CallConv, bool isVarArg, 2432 const SmallVectorImpl<ISD::InputArg> 2433 &Ins, 2434 SDLoc dl, SelectionDAG &DAG, 2435 SmallVectorImpl<SDValue> &InVals) const { 2436 // TODO: add description of PPC stack frame format, or at least some docs. 2437 // 2438 MachineFunction &MF = DAG.getMachineFunction(); 2439 MachineFrameInfo *MFI = MF.getFrameInfo(); 2440 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 2441 2442 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2443 bool isPPC64 = PtrVT == MVT::i64; 2444 // Potential tail calls could cause overwriting of argument stack slots. 2445 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt && 2446 (CallConv == CallingConv::Fast)); 2447 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2448 2449 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); 2450 // Area that is at least reserved in caller of this function. 2451 unsigned MinReservedArea = ArgOffset; 2452 2453 static const uint16_t GPR_32[] = { // 32-bit registers. 2454 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 2455 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 2456 }; 2457 static const uint16_t GPR_64[] = { // 64-bit registers. 2458 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 2459 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 2460 }; 2461 2462 static const uint16_t *FPR = GetFPR(); 2463 2464 static const uint16_t VR[] = { 2465 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 2466 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 2467 }; 2468 2469 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 2470 const unsigned Num_FPR_Regs = 13; 2471 const unsigned Num_VR_Regs = array_lengthof( VR); 2472 2473 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 2474 2475 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32; 2476 2477 // In 32-bit non-varargs functions, the stack space for vectors is after the 2478 // stack space for non-vectors. We do not use this space unless we have 2479 // too many vectors to fit in registers, something that only occurs in 2480 // constructed examples:), but we have to walk the arglist to figure 2481 // that out...for the pathological case, compute VecArgOffset as the 2482 // start of the vector parameter area. Computing VecArgOffset is the 2483 // entire point of the following loop. 2484 unsigned VecArgOffset = ArgOffset; 2485 if (!isVarArg && !isPPC64) { 2486 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; 2487 ++ArgNo) { 2488 EVT ObjectVT = Ins[ArgNo].VT; 2489 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 2490 2491 if (Flags.isByVal()) { 2492 // ObjSize is the true size, ArgSize rounded up to multiple of regs. 2493 unsigned ObjSize = Flags.getByValSize(); 2494 unsigned ArgSize = 2495 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 2496 VecArgOffset += ArgSize; 2497 continue; 2498 } 2499 2500 switch(ObjectVT.getSimpleVT().SimpleTy) { 2501 default: llvm_unreachable("Unhandled argument type!"); 2502 case MVT::i32: 2503 case MVT::f32: 2504 VecArgOffset += 4; 2505 break; 2506 case MVT::i64: // PPC64 2507 case MVT::f64: 2508 // FIXME: We are guaranteed to be !isPPC64 at this point. 2509 // Does MVT::i64 apply? 2510 VecArgOffset += 8; 2511 break; 2512 case MVT::v4f32: 2513 case MVT::v4i32: 2514 case MVT::v8i16: 2515 case MVT::v16i8: 2516 // Nothing to do, we're only looking at Nonvector args here. 2517 break; 2518 } 2519 } 2520 } 2521 // We've found where the vector parameter area in memory is. Skip the 2522 // first 12 parameters; these don't use that memory. 2523 VecArgOffset = ((VecArgOffset+15)/16)*16; 2524 VecArgOffset += 12*16; 2525 2526 // Add DAG nodes to load the arguments or copy them out of registers. On 2527 // entry to a function on PPC, the arguments start after the linkage area, 2528 // although the first ones are often in registers. 2529 2530 SmallVector<SDValue, 8> MemOps; 2531 unsigned nAltivecParamsAtEnd = 0; 2532 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin(); 2533 unsigned CurArgIdx = 0; 2534 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { 2535 SDValue ArgVal; 2536 bool needsLoad = false; 2537 EVT ObjectVT = Ins[ArgNo].VT; 2538 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 2539 unsigned ArgSize = ObjSize; 2540 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 2541 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx); 2542 CurArgIdx = Ins[ArgNo].OrigArgIndex; 2543 2544 unsigned CurArgOffset = ArgOffset; 2545 2546 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 2547 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 2548 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 2549 if (isVarArg || isPPC64) { 2550 MinReservedArea = ((MinReservedArea+15)/16)*16; 2551 MinReservedArea += CalculateStackSlotSize(ObjectVT, 2552 Flags, 2553 PtrByteSize); 2554 } else nAltivecParamsAtEnd++; 2555 } else 2556 // Calculate min reserved area. 2557 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 2558 Flags, 2559 PtrByteSize); 2560 2561 // FIXME the codegen can be much improved in some cases. 2562 // We do not have to keep everything in memory. 2563 if (Flags.isByVal()) { 2564 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 2565 ObjSize = Flags.getByValSize(); 2566 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 2567 // Objects of size 1 and 2 are right justified, everything else is 2568 // left justified. This means the memory address is adjusted forwards. 2569 if (ObjSize==1 || ObjSize==2) { 2570 CurArgOffset = CurArgOffset + (4 - ObjSize); 2571 } 2572 // The value of the object is its address. 2573 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true); 2574 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2575 InVals.push_back(FIN); 2576 if (ObjSize==1 || ObjSize==2) { 2577 if (GPR_idx != Num_GPR_Regs) { 2578 unsigned VReg; 2579 if (isPPC64) 2580 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2581 else 2582 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2583 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2584 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16; 2585 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 2586 MachinePointerInfo(FuncArg, 2587 CurArgOffset), 2588 ObjType, false, false, 0); 2589 MemOps.push_back(Store); 2590 ++GPR_idx; 2591 } 2592 2593 ArgOffset += PtrByteSize; 2594 2595 continue; 2596 } 2597 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 2598 // Store whatever pieces of the object are in registers 2599 // to memory. ArgOffset will be the address of the beginning 2600 // of the object. 2601 if (GPR_idx != Num_GPR_Regs) { 2602 unsigned VReg; 2603 if (isPPC64) 2604 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2605 else 2606 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2607 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2608 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2609 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2610 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2611 MachinePointerInfo(FuncArg, ArgOffset), 2612 false, false, 0); 2613 MemOps.push_back(Store); 2614 ++GPR_idx; 2615 ArgOffset += PtrByteSize; 2616 } else { 2617 ArgOffset += ArgSize - (ArgOffset-CurArgOffset); 2618 break; 2619 } 2620 } 2621 continue; 2622 } 2623 2624 switch (ObjectVT.getSimpleVT().SimpleTy) { 2625 default: llvm_unreachable("Unhandled argument type!"); 2626 case MVT::i32: 2627 if (!isPPC64) { 2628 if (GPR_idx != Num_GPR_Regs) { 2629 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2630 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2631 ++GPR_idx; 2632 } else { 2633 needsLoad = true; 2634 ArgSize = PtrByteSize; 2635 } 2636 // All int arguments reserve stack space in the Darwin ABI. 2637 ArgOffset += PtrByteSize; 2638 break; 2639 } 2640 // FALLTHROUGH 2641 case MVT::i64: // PPC64 2642 if (GPR_idx != Num_GPR_Regs) { 2643 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2644 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2645 2646 if (ObjectVT == MVT::i32) 2647 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 2648 // value to MVT::i64 and then truncate to the correct register size. 2649 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl); 2650 2651 ++GPR_idx; 2652 } else { 2653 needsLoad = true; 2654 ArgSize = PtrByteSize; 2655 } 2656 // All int arguments reserve stack space in the Darwin ABI. 2657 ArgOffset += 8; 2658 break; 2659 2660 case MVT::f32: 2661 case MVT::f64: 2662 // Every 4 bytes of argument space consumes one of the GPRs available for 2663 // argument passing. 2664 if (GPR_idx != Num_GPR_Regs) { 2665 ++GPR_idx; 2666 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 2667 ++GPR_idx; 2668 } 2669 if (FPR_idx != Num_FPR_Regs) { 2670 unsigned VReg; 2671 2672 if (ObjectVT == MVT::f32) 2673 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 2674 else 2675 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 2676 2677 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2678 ++FPR_idx; 2679 } else { 2680 needsLoad = true; 2681 } 2682 2683 // All FP arguments reserve stack space in the Darwin ABI. 2684 ArgOffset += isPPC64 ? 8 : ObjSize; 2685 break; 2686 case MVT::v4f32: 2687 case MVT::v4i32: 2688 case MVT::v8i16: 2689 case MVT::v16i8: 2690 // Note that vector arguments in registers don't reserve stack space, 2691 // except in varargs functions. 2692 if (VR_idx != Num_VR_Regs) { 2693 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 2694 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2695 if (isVarArg) { 2696 while ((ArgOffset % 16) != 0) { 2697 ArgOffset += PtrByteSize; 2698 if (GPR_idx != Num_GPR_Regs) 2699 GPR_idx++; 2700 } 2701 ArgOffset += 16; 2702 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 2703 } 2704 ++VR_idx; 2705 } else { 2706 if (!isVarArg && !isPPC64) { 2707 // Vectors go after all the nonvectors. 2708 CurArgOffset = VecArgOffset; 2709 VecArgOffset += 16; 2710 } else { 2711 // Vectors are aligned. 2712 ArgOffset = ((ArgOffset+15)/16)*16; 2713 CurArgOffset = ArgOffset; 2714 ArgOffset += 16; 2715 } 2716 needsLoad = true; 2717 } 2718 break; 2719 } 2720 2721 // We need to load the argument to a virtual register if we determined above 2722 // that we ran out of physical registers of the appropriate type. 2723 if (needsLoad) { 2724 int FI = MFI->CreateFixedObject(ObjSize, 2725 CurArgOffset + (ArgSize - ObjSize), 2726 isImmutable); 2727 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2728 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), 2729 false, false, false, 0); 2730 } 2731 2732 InVals.push_back(ArgVal); 2733 } 2734 2735 // Set the size that is at least reserved in caller of this function. Tail 2736 // call optimized functions' reserved stack space needs to be aligned so that 2737 // taking the difference between two stack areas will result in an aligned 2738 // stack. 2739 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64); 2740 2741 // If the function takes variable number of arguments, make a frame index for 2742 // the start of the first vararg value... for expansion of llvm.va_start. 2743 if (isVarArg) { 2744 int Depth = ArgOffset; 2745 2746 FuncInfo->setVarArgsFrameIndex( 2747 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2748 Depth, true)); 2749 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2750 2751 // If this function is vararg, store any remaining integer argument regs 2752 // to their spots on the stack so that they may be loaded by deferencing the 2753 // result of va_next. 2754 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2755 unsigned VReg; 2756 2757 if (isPPC64) 2758 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2759 else 2760 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2761 2762 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2763 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2764 MachinePointerInfo(), false, false, 0); 2765 MemOps.push_back(Store); 2766 // Increment the address by four for the next argument to store 2767 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2768 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2769 } 2770 } 2771 2772 if (!MemOps.empty()) 2773 Chain = DAG.getNode(ISD::TokenFactor, dl, 2774 MVT::Other, &MemOps[0], MemOps.size()); 2775 2776 return Chain; 2777} 2778 2779/// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus 2780/// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI. 2781static unsigned 2782CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, 2783 bool isPPC64, 2784 bool isVarArg, 2785 unsigned CC, 2786 const SmallVectorImpl<ISD::OutputArg> 2787 &Outs, 2788 const SmallVectorImpl<SDValue> &OutVals, 2789 unsigned &nAltivecParamsAtEnd) { 2790 // Count how many bytes are to be pushed on the stack, including the linkage 2791 // area, and parameter passing area. We start with 24/48 bytes, which is 2792 // prereserved space for [SP][CR][LR][3 x unused]. 2793 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true); 2794 unsigned NumOps = Outs.size(); 2795 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2796 2797 // Add up all the space actually used. 2798 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually 2799 // they all go in registers, but we must reserve stack space for them for 2800 // possible use by the caller. In varargs or 64-bit calls, parameters are 2801 // assigned stack space in order, with padding so Altivec parameters are 2802 // 16-byte aligned. 2803 nAltivecParamsAtEnd = 0; 2804 for (unsigned i = 0; i != NumOps; ++i) { 2805 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2806 EVT ArgVT = Outs[i].VT; 2807 // Varargs Altivec parameters are padded to a 16 byte boundary. 2808 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 2809 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { 2810 if (!isVarArg && !isPPC64) { 2811 // Non-varargs Altivec parameters go after all the non-Altivec 2812 // parameters; handle those later so we know how much padding we need. 2813 nAltivecParamsAtEnd++; 2814 continue; 2815 } 2816 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. 2817 NumBytes = ((NumBytes+15)/16)*16; 2818 } 2819 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); 2820 } 2821 2822 // Allow for Altivec parameters at the end, if needed. 2823 if (nAltivecParamsAtEnd) { 2824 NumBytes = ((NumBytes+15)/16)*16; 2825 NumBytes += 16*nAltivecParamsAtEnd; 2826 } 2827 2828 // The prolog code of the callee may store up to 8 GPR argument registers to 2829 // the stack, allowing va_start to index over them in memory if its varargs. 2830 // Because we cannot tell if this is needed on the caller side, we have to 2831 // conservatively assume that it is needed. As such, make sure we have at 2832 // least enough stack space for the caller to store the 8 GPRs. 2833 NumBytes = std::max(NumBytes, 2834 PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); 2835 2836 // Tail call needs the stack to be aligned. 2837 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){ 2838 unsigned TargetAlign = DAG.getMachineFunction().getTarget(). 2839 getFrameLowering()->getStackAlignment(); 2840 unsigned AlignMask = TargetAlign-1; 2841 NumBytes = (NumBytes + AlignMask) & ~AlignMask; 2842 } 2843 2844 return NumBytes; 2845} 2846 2847/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be 2848/// adjusted to accommodate the arguments for the tailcall. 2849static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, 2850 unsigned ParamSize) { 2851 2852 if (!isTailCall) return 0; 2853 2854 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>(); 2855 unsigned CallerMinReservedArea = FI->getMinReservedArea(); 2856 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize; 2857 // Remember only if the new adjustement is bigger. 2858 if (SPDiff < FI->getTailCallSPDelta()) 2859 FI->setTailCallSPDelta(SPDiff); 2860 2861 return SPDiff; 2862} 2863 2864/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2865/// for tail call optimization. Targets which want to do tail call 2866/// optimization should implement this function. 2867bool 2868PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2869 CallingConv::ID CalleeCC, 2870 bool isVarArg, 2871 const SmallVectorImpl<ISD::InputArg> &Ins, 2872 SelectionDAG& DAG) const { 2873 if (!getTargetMachine().Options.GuaranteedTailCallOpt) 2874 return false; 2875 2876 // Variable argument functions are not supported. 2877 if (isVarArg) 2878 return false; 2879 2880 MachineFunction &MF = DAG.getMachineFunction(); 2881 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv(); 2882 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 2883 // Functions containing by val parameters are not supported. 2884 for (unsigned i = 0; i != Ins.size(); i++) { 2885 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2886 if (Flags.isByVal()) return false; 2887 } 2888 2889 // Non PIC/GOT tail calls are supported. 2890 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 2891 return true; 2892 2893 // At the moment we can only do local tail calls (in same module, hidden 2894 // or protected) if we are generating PIC. 2895 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2896 return G->getGlobal()->hasHiddenVisibility() 2897 || G->getGlobal()->hasProtectedVisibility(); 2898 } 2899 2900 return false; 2901} 2902 2903/// isCallCompatibleAddress - Return the immediate to use if the specified 2904/// 32-bit value is representable in the immediate field of a BxA instruction. 2905static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { 2906 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2907 if (!C) return 0; 2908 2909 int Addr = C->getZExtValue(); 2910 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 2911 SignExtend32<26>(Addr) != Addr) 2912 return 0; // Top 6 bits have to be sext of immediate. 2913 2914 return DAG.getConstant((int)C->getZExtValue() >> 2, 2915 DAG.getTargetLoweringInfo().getPointerTy()).getNode(); 2916} 2917 2918namespace { 2919 2920struct TailCallArgumentInfo { 2921 SDValue Arg; 2922 SDValue FrameIdxOp; 2923 int FrameIdx; 2924 2925 TailCallArgumentInfo() : FrameIdx(0) {} 2926}; 2927 2928} 2929 2930/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. 2931static void 2932StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, 2933 SDValue Chain, 2934 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, 2935 SmallVector<SDValue, 8> &MemOpChains, 2936 SDLoc dl) { 2937 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { 2938 SDValue Arg = TailCallArgs[i].Arg; 2939 SDValue FIN = TailCallArgs[i].FrameIdxOp; 2940 int FI = TailCallArgs[i].FrameIdx; 2941 // Store relative to framepointer. 2942 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN, 2943 MachinePointerInfo::getFixedStack(FI), 2944 false, false, 0)); 2945 } 2946} 2947 2948/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to 2949/// the appropriate stack slot for the tail call optimized function call. 2950static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, 2951 MachineFunction &MF, 2952 SDValue Chain, 2953 SDValue OldRetAddr, 2954 SDValue OldFP, 2955 int SPDiff, 2956 bool isPPC64, 2957 bool isDarwinABI, 2958 SDLoc dl) { 2959 if (SPDiff) { 2960 // Calculate the new stack slot for the return address. 2961 int SlotSize = isPPC64 ? 8 : 4; 2962 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64, 2963 isDarwinABI); 2964 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, 2965 NewRetAddrLoc, true); 2966 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2967 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); 2968 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, 2969 MachinePointerInfo::getFixedStack(NewRetAddr), 2970 false, false, 0); 2971 2972 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack 2973 // slot as the FP is never overwritten. 2974 if (isDarwinABI) { 2975 int NewFPLoc = 2976 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 2977 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc, 2978 true); 2979 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); 2980 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, 2981 MachinePointerInfo::getFixedStack(NewFPIdx), 2982 false, false, 0); 2983 } 2984 } 2985 return Chain; 2986} 2987 2988/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate 2989/// the position of the argument. 2990static void 2991CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, 2992 SDValue Arg, int SPDiff, unsigned ArgOffset, 2993 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 2994 int Offset = ArgOffset + SPDiff; 2995 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; 2996 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2997 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2998 SDValue FIN = DAG.getFrameIndex(FI, VT); 2999 TailCallArgumentInfo Info; 3000 Info.Arg = Arg; 3001 Info.FrameIdxOp = FIN; 3002 Info.FrameIdx = FI; 3003 TailCallArguments.push_back(Info); 3004} 3005 3006/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address 3007/// stack slot. Returns the chain as result and the loaded frame pointers in 3008/// LROpOut/FPOpout. Used when tail calling. 3009SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 3010 int SPDiff, 3011 SDValue Chain, 3012 SDValue &LROpOut, 3013 SDValue &FPOpOut, 3014 bool isDarwinABI, 3015 SDLoc dl) const { 3016 if (SPDiff) { 3017 // Load the LR and FP stack slot for later adjusting. 3018 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; 3019 LROpOut = getReturnAddrFrameIndex(DAG); 3020 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(), 3021 false, false, false, 0); 3022 Chain = SDValue(LROpOut.getNode(), 1); 3023 3024 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack 3025 // slot as the FP is never overwritten. 3026 if (isDarwinABI) { 3027 FPOpOut = getFramePointerFrameIndex(DAG); 3028 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(), 3029 false, false, false, 0); 3030 Chain = SDValue(FPOpOut.getNode(), 1); 3031 } 3032 } 3033 return Chain; 3034} 3035 3036/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 3037/// by "Src" to address "Dst" of size "Size". Alignment information is 3038/// specified by the specific parameter attribute. The copy will be passed as 3039/// a byval function parameter. 3040/// Sometimes what we are copying is the end of a larger object, the part that 3041/// does not fit in registers. 3042static SDValue 3043CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 3044 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 3045 SDLoc dl) { 3046 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 3047 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 3048 false, false, MachinePointerInfo(0), 3049 MachinePointerInfo(0)); 3050} 3051 3052/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of 3053/// tail calls. 3054static void 3055LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, 3056 SDValue Arg, SDValue PtrOff, int SPDiff, 3057 unsigned ArgOffset, bool isPPC64, bool isTailCall, 3058 bool isVector, SmallVector<SDValue, 8> &MemOpChains, 3059 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments, 3060 SDLoc dl) { 3061 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3062 if (!isTailCall) { 3063 if (isVector) { 3064 SDValue StackPtr; 3065 if (isPPC64) 3066 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 3067 else 3068 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 3069 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 3070 DAG.getConstant(ArgOffset, PtrVT)); 3071 } 3072 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 3073 MachinePointerInfo(), false, false, 0)); 3074 // Calculate and remember argument location. 3075 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, 3076 TailCallArguments); 3077} 3078 3079static 3080void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, 3081 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, 3082 SDValue LROp, SDValue FPOp, bool isDarwinABI, 3083 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) { 3084 MachineFunction &MF = DAG.getMachineFunction(); 3085 3086 // Emit a sequence of copyto/copyfrom virtual registers for arguments that 3087 // might overwrite each other in case of tail call optimization. 3088 SmallVector<SDValue, 8> MemOpChains2; 3089 // Do not flag preceding copytoreg stuff together with the following stuff. 3090 InFlag = SDValue(); 3091 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, 3092 MemOpChains2, dl); 3093 if (!MemOpChains2.empty()) 3094 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3095 &MemOpChains2[0], MemOpChains2.size()); 3096 3097 // Store the return address to the appropriate stack slot. 3098 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, 3099 isPPC64, isDarwinABI, dl); 3100 3101 // Emit callseq_end just before tailcall node. 3102 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 3103 DAG.getIntPtrConstant(0, true), InFlag, dl); 3104 InFlag = Chain.getValue(1); 3105} 3106 3107static 3108unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, 3109 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall, 3110 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 3111 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys, 3112 const PPCSubtarget &PPCSubTarget) { 3113 3114 bool isPPC64 = PPCSubTarget.isPPC64(); 3115 bool isSVR4ABI = PPCSubTarget.isSVR4ABI(); 3116 3117 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3118 NodeTys.push_back(MVT::Other); // Returns a chain 3119 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use. 3120 3121 unsigned CallOpc = PPCISD::CALL; 3122 3123 bool needIndirectCall = true; 3124 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) { 3125 // If this is an absolute destination address, use the munged value. 3126 Callee = SDValue(Dest, 0); 3127 needIndirectCall = false; 3128 } 3129 3130 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3131 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201 3132 // Use indirect calls for ALL functions calls in JIT mode, since the 3133 // far-call stubs may be outside relocation limits for a BL instruction. 3134 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) { 3135 unsigned OpFlags = 0; 3136 if (DAG.getTarget().getRelocationModel() != Reloc::Static && 3137 (PPCSubTarget.getTargetTriple().isMacOSX() && 3138 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) && 3139 (G->getGlobal()->isDeclaration() || 3140 G->getGlobal()->isWeakForLinker())) { 3141 // PC-relative references to external symbols should go through $stub, 3142 // unless we're building with the leopard linker or later, which 3143 // automatically synthesizes these stubs. 3144 OpFlags = PPCII::MO_DARWIN_STUB; 3145 } 3146 3147 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, 3148 // every direct call is) turn it into a TargetGlobalAddress / 3149 // TargetExternalSymbol node so that legalize doesn't hack it. 3150 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 3151 Callee.getValueType(), 3152 0, OpFlags); 3153 needIndirectCall = false; 3154 } 3155 } 3156 3157 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3158 unsigned char OpFlags = 0; 3159 3160 if (DAG.getTarget().getRelocationModel() != Reloc::Static && 3161 (PPCSubTarget.getTargetTriple().isMacOSX() && 3162 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) { 3163 // PC-relative references to external symbols should go through $stub, 3164 // unless we're building with the leopard linker or later, which 3165 // automatically synthesizes these stubs. 3166 OpFlags = PPCII::MO_DARWIN_STUB; 3167 } 3168 3169 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(), 3170 OpFlags); 3171 needIndirectCall = false; 3172 } 3173 3174 if (needIndirectCall) { 3175 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 3176 // to do the call, we can't use PPCISD::CALL. 3177 SDValue MTCTROps[] = {Chain, Callee, InFlag}; 3178 3179 if (isSVR4ABI && isPPC64) { 3180 // Function pointers in the 64-bit SVR4 ABI do not point to the function 3181 // entry point, but to the function descriptor (the function entry point 3182 // address is part of the function descriptor though). 3183 // The function descriptor is a three doubleword structure with the 3184 // following fields: function entry point, TOC base address and 3185 // environment pointer. 3186 // Thus for a call through a function pointer, the following actions need 3187 // to be performed: 3188 // 1. Save the TOC of the caller in the TOC save area of its stack 3189 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()). 3190 // 2. Load the address of the function entry point from the function 3191 // descriptor. 3192 // 3. Load the TOC of the callee from the function descriptor into r2. 3193 // 4. Load the environment pointer from the function descriptor into 3194 // r11. 3195 // 5. Branch to the function entry point address. 3196 // 6. On return of the callee, the TOC of the caller needs to be 3197 // restored (this is done in FinishCall()). 3198 // 3199 // All those operations are flagged together to ensure that no other 3200 // operations can be scheduled in between. E.g. without flagging the 3201 // operations together, a TOC access in the caller could be scheduled 3202 // between the load of the callee TOC and the branch to the callee, which 3203 // results in the TOC access going through the TOC of the callee instead 3204 // of going through the TOC of the caller, which leads to incorrect code. 3205 3206 // Load the address of the function entry point from the function 3207 // descriptor. 3208 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue); 3209 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps, 3210 InFlag.getNode() ? 3 : 2); 3211 Chain = LoadFuncPtr.getValue(1); 3212 InFlag = LoadFuncPtr.getValue(2); 3213 3214 // Load environment pointer into r11. 3215 // Offset of the environment pointer within the function descriptor. 3216 SDValue PtrOff = DAG.getIntPtrConstant(16); 3217 3218 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff); 3219 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr, 3220 InFlag); 3221 Chain = LoadEnvPtr.getValue(1); 3222 InFlag = LoadEnvPtr.getValue(2); 3223 3224 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr, 3225 InFlag); 3226 Chain = EnvVal.getValue(0); 3227 InFlag = EnvVal.getValue(1); 3228 3229 // Load TOC of the callee into r2. We are using a target-specific load 3230 // with r2 hard coded, because the result of a target-independent load 3231 // would never go directly into r2, since r2 is a reserved register (which 3232 // prevents the register allocator from allocating it), resulting in an 3233 // additional register being allocated and an unnecessary move instruction 3234 // being generated. 3235 VTs = DAG.getVTList(MVT::Other, MVT::Glue); 3236 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, 3237 Callee, InFlag); 3238 Chain = LoadTOCPtr.getValue(0); 3239 InFlag = LoadTOCPtr.getValue(1); 3240 3241 MTCTROps[0] = Chain; 3242 MTCTROps[1] = LoadFuncPtr; 3243 MTCTROps[2] = InFlag; 3244 } 3245 3246 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps, 3247 2 + (InFlag.getNode() != 0)); 3248 InFlag = Chain.getValue(1); 3249 3250 NodeTys.clear(); 3251 NodeTys.push_back(MVT::Other); 3252 NodeTys.push_back(MVT::Glue); 3253 Ops.push_back(Chain); 3254 CallOpc = PPCISD::BCTRL; 3255 Callee.setNode(0); 3256 // Add use of X11 (holding environment pointer) 3257 if (isSVR4ABI && isPPC64) 3258 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT)); 3259 // Add CTR register as callee so a bctr can be emitted later. 3260 if (isTailCall) 3261 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT)); 3262 } 3263 3264 // If this is a direct call, pass the chain and the callee. 3265 if (Callee.getNode()) { 3266 Ops.push_back(Chain); 3267 Ops.push_back(Callee); 3268 } 3269 // If this is a tail call add stack pointer delta. 3270 if (isTailCall) 3271 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); 3272 3273 // Add argument registers to the end of the list so that they are known live 3274 // into the call. 3275 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 3276 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 3277 RegsToPass[i].second.getValueType())); 3278 3279 return CallOpc; 3280} 3281 3282static 3283bool isLocalCall(const SDValue &Callee) 3284{ 3285 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 3286 return !G->getGlobal()->isDeclaration() && 3287 !G->getGlobal()->isWeakForLinker(); 3288 return false; 3289} 3290 3291SDValue 3292PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 3293 CallingConv::ID CallConv, bool isVarArg, 3294 const SmallVectorImpl<ISD::InputArg> &Ins, 3295 SDLoc dl, SelectionDAG &DAG, 3296 SmallVectorImpl<SDValue> &InVals) const { 3297 3298 SmallVector<CCValAssign, 16> RVLocs; 3299 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3300 getTargetMachine(), RVLocs, *DAG.getContext()); 3301 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC); 3302 3303 // Copy all of the result registers out of their specified physreg. 3304 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 3305 CCValAssign &VA = RVLocs[i]; 3306 assert(VA.isRegLoc() && "Can only return in registers!"); 3307 3308 SDValue Val = DAG.getCopyFromReg(Chain, dl, 3309 VA.getLocReg(), VA.getLocVT(), InFlag); 3310 Chain = Val.getValue(1); 3311 InFlag = Val.getValue(2); 3312 3313 switch (VA.getLocInfo()) { 3314 default: llvm_unreachable("Unknown loc info!"); 3315 case CCValAssign::Full: break; 3316 case CCValAssign::AExt: 3317 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); 3318 break; 3319 case CCValAssign::ZExt: 3320 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val, 3321 DAG.getValueType(VA.getValVT())); 3322 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); 3323 break; 3324 case CCValAssign::SExt: 3325 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val, 3326 DAG.getValueType(VA.getValVT())); 3327 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); 3328 break; 3329 } 3330 3331 InVals.push_back(Val); 3332 } 3333 3334 return Chain; 3335} 3336 3337SDValue 3338PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl, 3339 bool isTailCall, bool isVarArg, 3340 SelectionDAG &DAG, 3341 SmallVector<std::pair<unsigned, SDValue>, 8> 3342 &RegsToPass, 3343 SDValue InFlag, SDValue Chain, 3344 SDValue &Callee, 3345 int SPDiff, unsigned NumBytes, 3346 const SmallVectorImpl<ISD::InputArg> &Ins, 3347 SmallVectorImpl<SDValue> &InVals) const { 3348 std::vector<EVT> NodeTys; 3349 SmallVector<SDValue, 8> Ops; 3350 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff, 3351 isTailCall, RegsToPass, Ops, NodeTys, 3352 PPCSubTarget); 3353 3354 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls 3355 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) 3356 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32)); 3357 3358 // When performing tail call optimization the callee pops its arguments off 3359 // the stack. Account for this here so these bytes can be pushed back on in 3360 // PPCFrameLowering::eliminateCallFramePseudoInstr. 3361 int BytesCalleePops = 3362 (CallConv == CallingConv::Fast && 3363 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0; 3364 3365 // Add a register mask operand representing the call-preserved registers. 3366 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 3367 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 3368 assert(Mask && "Missing call preserved mask for calling convention"); 3369 Ops.push_back(DAG.getRegisterMask(Mask)); 3370 3371 if (InFlag.getNode()) 3372 Ops.push_back(InFlag); 3373 3374 // Emit tail call. 3375 if (isTailCall) { 3376 assert(((Callee.getOpcode() == ISD::Register && 3377 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || 3378 Callee.getOpcode() == ISD::TargetExternalSymbol || 3379 Callee.getOpcode() == ISD::TargetGlobalAddress || 3380 isa<ConstantSDNode>(Callee)) && 3381 "Expecting an global address, external symbol, absolute value or register"); 3382 3383 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size()); 3384 } 3385 3386 // Add a NOP immediately after the branch instruction when using the 64-bit 3387 // SVR4 ABI. At link time, if caller and callee are in a different module and 3388 // thus have a different TOC, the call will be replaced with a call to a stub 3389 // function which saves the current TOC, loads the TOC of the callee and 3390 // branches to the callee. The NOP will be replaced with a load instruction 3391 // which restores the TOC of the caller from the TOC save slot of the current 3392 // stack frame. If caller and callee belong to the same module (and have the 3393 // same TOC), the NOP will remain unchanged. 3394 3395 bool needsTOCRestore = false; 3396 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) { 3397 if (CallOpc == PPCISD::BCTRL) { 3398 // This is a call through a function pointer. 3399 // Restore the caller TOC from the save area into R2. 3400 // See PrepareCall() for more information about calls through function 3401 // pointers in the 64-bit SVR4 ABI. 3402 // We are using a target-specific load with r2 hard coded, because the 3403 // result of a target-independent load would never go directly into r2, 3404 // since r2 is a reserved register (which prevents the register allocator 3405 // from allocating it), resulting in an additional register being 3406 // allocated and an unnecessary move instruction being generated. 3407 needsTOCRestore = true; 3408 } else if ((CallOpc == PPCISD::CALL) && !isLocalCall(Callee)) { 3409 // Otherwise insert NOP for non-local calls. 3410 CallOpc = PPCISD::CALL_NOP; 3411 } 3412 } 3413 3414 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 3415 InFlag = Chain.getValue(1); 3416 3417 if (needsTOCRestore) { 3418 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); 3419 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag); 3420 InFlag = Chain.getValue(1); 3421 } 3422 3423 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 3424 DAG.getIntPtrConstant(BytesCalleePops, true), 3425 InFlag, dl); 3426 if (!Ins.empty()) 3427 InFlag = Chain.getValue(1); 3428 3429 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 3430 Ins, dl, DAG, InVals); 3431} 3432 3433SDValue 3434PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 3435 SmallVectorImpl<SDValue> &InVals) const { 3436 SelectionDAG &DAG = CLI.DAG; 3437 SDLoc &dl = CLI.DL; 3438 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 3439 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 3440 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 3441 SDValue Chain = CLI.Chain; 3442 SDValue Callee = CLI.Callee; 3443 bool &isTailCall = CLI.IsTailCall; 3444 CallingConv::ID CallConv = CLI.CallConv; 3445 bool isVarArg = CLI.IsVarArg; 3446 3447 if (isTailCall) 3448 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, 3449 Ins, DAG); 3450 3451 if (PPCSubTarget.isSVR4ABI()) { 3452 if (PPCSubTarget.isPPC64()) 3453 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg, 3454 isTailCall, Outs, OutVals, Ins, 3455 dl, DAG, InVals); 3456 else 3457 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg, 3458 isTailCall, Outs, OutVals, Ins, 3459 dl, DAG, InVals); 3460 } 3461 3462 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg, 3463 isTailCall, Outs, OutVals, Ins, 3464 dl, DAG, InVals); 3465} 3466 3467SDValue 3468PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee, 3469 CallingConv::ID CallConv, bool isVarArg, 3470 bool isTailCall, 3471 const SmallVectorImpl<ISD::OutputArg> &Outs, 3472 const SmallVectorImpl<SDValue> &OutVals, 3473 const SmallVectorImpl<ISD::InputArg> &Ins, 3474 SDLoc dl, SelectionDAG &DAG, 3475 SmallVectorImpl<SDValue> &InVals) const { 3476 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description 3477 // of the 32-bit SVR4 ABI stack frame layout. 3478 3479 assert((CallConv == CallingConv::C || 3480 CallConv == CallingConv::Fast) && "Unknown calling convention!"); 3481 3482 unsigned PtrByteSize = 4; 3483 3484 MachineFunction &MF = DAG.getMachineFunction(); 3485 3486 // Mark this function as potentially containing a function that contains a 3487 // tail call. As a consequence the frame pointer will be used for dynamicalloc 3488 // and restoring the callers stack pointer in this functions epilog. This is 3489 // done because by tail calling the called function might overwrite the value 3490 // in this function's (MF) stack pointer stack slot 0(SP). 3491 if (getTargetMachine().Options.GuaranteedTailCallOpt && 3492 CallConv == CallingConv::Fast) 3493 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 3494 3495 // Count how many bytes are to be pushed on the stack, including the linkage 3496 // area, parameter list area and the part of the local variable space which 3497 // contains copies of aggregates which are passed by value. 3498 3499 // Assign locations to all of the outgoing arguments. 3500 SmallVector<CCValAssign, 16> ArgLocs; 3501 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3502 getTargetMachine(), ArgLocs, *DAG.getContext()); 3503 3504 // Reserve space for the linkage area on the stack. 3505 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); 3506 3507 if (isVarArg) { 3508 // Handle fixed and variable vector arguments differently. 3509 // Fixed vector arguments go into registers as long as registers are 3510 // available. Variable vector arguments always go into memory. 3511 unsigned NumArgs = Outs.size(); 3512 3513 for (unsigned i = 0; i != NumArgs; ++i) { 3514 MVT ArgVT = Outs[i].VT; 3515 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 3516 bool Result; 3517 3518 if (Outs[i].IsFixed) { 3519 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, 3520 CCInfo); 3521 } else { 3522 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, 3523 ArgFlags, CCInfo); 3524 } 3525 3526 if (Result) { 3527#ifndef NDEBUG 3528 errs() << "Call operand #" << i << " has unhandled type " 3529 << EVT(ArgVT).getEVTString() << "\n"; 3530#endif 3531 llvm_unreachable(0); 3532 } 3533 } 3534 } else { 3535 // All arguments are treated the same. 3536 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4); 3537 } 3538 3539 // Assign locations to all of the outgoing aggregate by value arguments. 3540 SmallVector<CCValAssign, 16> ByValArgLocs; 3541 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3542 getTargetMachine(), ByValArgLocs, *DAG.getContext()); 3543 3544 // Reserve stack space for the allocations in CCInfo. 3545 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 3546 3547 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal); 3548 3549 // Size of the linkage area, parameter list area and the part of the local 3550 // space variable where copies of aggregates which are passed by value are 3551 // stored. 3552 unsigned NumBytes = CCByValInfo.getNextStackOffset(); 3553 3554 // Calculate by how many bytes the stack has to be adjusted in case of tail 3555 // call optimization. 3556 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 3557 3558 // Adjust the stack pointer for the new arguments... 3559 // These operations are automatically eliminated by the prolog/epilog pass 3560 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), 3561 dl); 3562 SDValue CallSeqStart = Chain; 3563 3564 // Load the return address and frame pointer so it can be moved somewhere else 3565 // later. 3566 SDValue LROp, FPOp; 3567 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false, 3568 dl); 3569 3570 // Set up a copy of the stack pointer for use loading and storing any 3571 // arguments that may not fit in the registers available for argument 3572 // passing. 3573 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 3574 3575 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3576 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3577 SmallVector<SDValue, 8> MemOpChains; 3578 3579 bool seenFloatArg = false; 3580 // Walk the register/memloc assignments, inserting copies/loads. 3581 for (unsigned i = 0, j = 0, e = ArgLocs.size(); 3582 i != e; 3583 ++i) { 3584 CCValAssign &VA = ArgLocs[i]; 3585 SDValue Arg = OutVals[i]; 3586 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3587 3588 if (Flags.isByVal()) { 3589 // Argument is an aggregate which is passed by value, thus we need to 3590 // create a copy of it in the local variable space of the current stack 3591 // frame (which is the stack frame of the caller) and pass the address of 3592 // this copy to the callee. 3593 assert((j < ByValArgLocs.size()) && "Index out of bounds!"); 3594 CCValAssign &ByValVA = ByValArgLocs[j++]; 3595 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"); 3596 3597 // Memory reserved in the local variable space of the callers stack frame. 3598 unsigned LocMemOffset = ByValVA.getLocMemOffset(); 3599 3600 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 3601 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 3602 3603 // Create a copy of the argument in the local area of the current 3604 // stack frame. 3605 SDValue MemcpyCall = 3606 CreateCopyOfByValArgument(Arg, PtrOff, 3607 CallSeqStart.getNode()->getOperand(0), 3608 Flags, DAG, dl); 3609 3610 // This must go outside the CALLSEQ_START..END. 3611 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3612 CallSeqStart.getNode()->getOperand(1), 3613 SDLoc(MemcpyCall)); 3614 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3615 NewCallSeqStart.getNode()); 3616 Chain = CallSeqStart = NewCallSeqStart; 3617 3618 // Pass the address of the aggregate copy on the stack either in a 3619 // physical register or in the parameter list area of the current stack 3620 // frame to the callee. 3621 Arg = PtrOff; 3622 } 3623 3624 if (VA.isRegLoc()) { 3625 seenFloatArg |= VA.getLocVT().isFloatingPoint(); 3626 // Put argument in a physical register. 3627 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3628 } else { 3629 // Put argument in the parameter list area of the current stack frame. 3630 assert(VA.isMemLoc()); 3631 unsigned LocMemOffset = VA.getLocMemOffset(); 3632 3633 if (!isTailCall) { 3634 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 3635 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 3636 3637 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 3638 MachinePointerInfo(), 3639 false, false, 0)); 3640 } else { 3641 // Calculate and remember argument location. 3642 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset, 3643 TailCallArguments); 3644 } 3645 } 3646 } 3647 3648 if (!MemOpChains.empty()) 3649 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3650 &MemOpChains[0], MemOpChains.size()); 3651 3652 // Build a sequence of copy-to-reg nodes chained together with token chain 3653 // and flag operands which copy the outgoing args into the appropriate regs. 3654 SDValue InFlag; 3655 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3656 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3657 RegsToPass[i].second, InFlag); 3658 InFlag = Chain.getValue(1); 3659 } 3660 3661 // Set CR bit 6 to true if this is a vararg call with floating args passed in 3662 // registers. 3663 if (isVarArg) { 3664 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); 3665 SDValue Ops[] = { Chain, InFlag }; 3666 3667 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET, 3668 dl, VTs, Ops, InFlag.getNode() ? 2 : 1); 3669 3670 InFlag = Chain.getValue(1); 3671 } 3672 3673 if (isTailCall) 3674 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp, 3675 false, TailCallArguments); 3676 3677 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 3678 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 3679 Ins, InVals); 3680} 3681 3682// Copy an argument into memory, being careful to do this outside the 3683// call sequence for the call to which the argument belongs. 3684SDValue 3685PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 3686 SDValue CallSeqStart, 3687 ISD::ArgFlagsTy Flags, 3688 SelectionDAG &DAG, 3689 SDLoc dl) const { 3690 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, 3691 CallSeqStart.getNode()->getOperand(0), 3692 Flags, DAG, dl); 3693 // The MEMCPY must go outside the CALLSEQ_START..END. 3694 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3695 CallSeqStart.getNode()->getOperand(1), 3696 SDLoc(MemcpyCall)); 3697 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3698 NewCallSeqStart.getNode()); 3699 return NewCallSeqStart; 3700} 3701 3702SDValue 3703PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee, 3704 CallingConv::ID CallConv, bool isVarArg, 3705 bool isTailCall, 3706 const SmallVectorImpl<ISD::OutputArg> &Outs, 3707 const SmallVectorImpl<SDValue> &OutVals, 3708 const SmallVectorImpl<ISD::InputArg> &Ins, 3709 SDLoc dl, SelectionDAG &DAG, 3710 SmallVectorImpl<SDValue> &InVals) const { 3711 3712 unsigned NumOps = Outs.size(); 3713 3714 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3715 unsigned PtrByteSize = 8; 3716 3717 MachineFunction &MF = DAG.getMachineFunction(); 3718 3719 // Mark this function as potentially containing a function that contains a 3720 // tail call. As a consequence the frame pointer will be used for dynamicalloc 3721 // and restoring the callers stack pointer in this functions epilog. This is 3722 // done because by tail calling the called function might overwrite the value 3723 // in this function's (MF) stack pointer stack slot 0(SP). 3724 if (getTargetMachine().Options.GuaranteedTailCallOpt && 3725 CallConv == CallingConv::Fast) 3726 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 3727 3728 unsigned nAltivecParamsAtEnd = 0; 3729 3730 // Count how many bytes are to be pushed on the stack, including the linkage 3731 // area, and parameter passing area. We start with at least 48 bytes, which 3732 // is reserved space for [SP][CR][LR][3 x unused]. 3733 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result 3734 // of this call. 3735 unsigned NumBytes = 3736 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv, 3737 Outs, OutVals, nAltivecParamsAtEnd); 3738 3739 // Calculate by how many bytes the stack has to be adjusted in case of tail 3740 // call optimization. 3741 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 3742 3743 // To protect arguments on the stack from being clobbered in a tail call, 3744 // force all the loads to happen before doing any other lowering. 3745 if (isTailCall) 3746 Chain = DAG.getStackArgumentTokenFactor(Chain); 3747 3748 // Adjust the stack pointer for the new arguments... 3749 // These operations are automatically eliminated by the prolog/epilog pass 3750 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), 3751 dl); 3752 SDValue CallSeqStart = Chain; 3753 3754 // Load the return address and frame pointer so it can be move somewhere else 3755 // later. 3756 SDValue LROp, FPOp; 3757 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 3758 dl); 3759 3760 // Set up a copy of the stack pointer for use loading and storing any 3761 // arguments that may not fit in the registers available for argument 3762 // passing. 3763 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 3764 3765 // Figure out which arguments are going to go in registers, and which in 3766 // memory. Also, if this is a vararg function, floating point operations 3767 // must be stored to our stack, and loaded into integer regs as well, if 3768 // any integer regs are available for argument passing. 3769 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true); 3770 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 3771 3772 static const uint16_t GPR[] = { 3773 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 3774 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 3775 }; 3776 static const uint16_t *FPR = GetFPR(); 3777 3778 static const uint16_t VR[] = { 3779 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 3780 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 3781 }; 3782 const unsigned NumGPRs = array_lengthof(GPR); 3783 const unsigned NumFPRs = 13; 3784 const unsigned NumVRs = array_lengthof(VR); 3785 3786 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3787 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3788 3789 SmallVector<SDValue, 8> MemOpChains; 3790 for (unsigned i = 0; i != NumOps; ++i) { 3791 SDValue Arg = OutVals[i]; 3792 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3793 3794 // PtrOff will be used to store the current argument to the stack if a 3795 // register cannot be found for it. 3796 SDValue PtrOff; 3797 3798 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 3799 3800 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3801 3802 // Promote integers to 64-bit values. 3803 if (Arg.getValueType() == MVT::i32) { 3804 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 3805 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3806 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 3807 } 3808 3809 // FIXME memcpy is used way more than necessary. Correctness first. 3810 // Note: "by value" is code for passing a structure by value, not 3811 // basic types. 3812 if (Flags.isByVal()) { 3813 // Note: Size includes alignment padding, so 3814 // struct x { short a; char b; } 3815 // will have Size = 4. With #pragma pack(1), it will have Size = 3. 3816 // These are the proper values we need for right-justifying the 3817 // aggregate in a parameter register. 3818 unsigned Size = Flags.getByValSize(); 3819 3820 // An empty aggregate parameter takes up no storage and no 3821 // registers. 3822 if (Size == 0) 3823 continue; 3824 3825 // All aggregates smaller than 8 bytes must be passed right-justified. 3826 if (Size==1 || Size==2 || Size==4) { 3827 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32); 3828 if (GPR_idx != NumGPRs) { 3829 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, 3830 MachinePointerInfo(), VT, 3831 false, false, 0); 3832 MemOpChains.push_back(Load.getValue(1)); 3833 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3834 3835 ArgOffset += PtrByteSize; 3836 continue; 3837 } 3838 } 3839 3840 if (GPR_idx == NumGPRs && Size < 8) { 3841 SDValue Const = DAG.getConstant(PtrByteSize - Size, 3842 PtrOff.getValueType()); 3843 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3844 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, 3845 CallSeqStart, 3846 Flags, DAG, dl); 3847 ArgOffset += PtrByteSize; 3848 continue; 3849 } 3850 // Copy entire object into memory. There are cases where gcc-generated 3851 // code assumes it is there, even if it could be put entirely into 3852 // registers. (This is not what the doc says.) 3853 3854 // FIXME: The above statement is likely due to a misunderstanding of the 3855 // documents. All arguments must be copied into the parameter area BY 3856 // THE CALLEE in the event that the callee takes the address of any 3857 // formal argument. That has not yet been implemented. However, it is 3858 // reasonable to use the stack area as a staging area for the register 3859 // load. 3860 3861 // Skip this for small aggregates, as we will use the same slot for a 3862 // right-justified copy, below. 3863 if (Size >= 8) 3864 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff, 3865 CallSeqStart, 3866 Flags, DAG, dl); 3867 3868 // When a register is available, pass a small aggregate right-justified. 3869 if (Size < 8 && GPR_idx != NumGPRs) { 3870 // The easiest way to get this right-justified in a register 3871 // is to copy the structure into the rightmost portion of a 3872 // local variable slot, then load the whole slot into the 3873 // register. 3874 // FIXME: The memcpy seems to produce pretty awful code for 3875 // small aggregates, particularly for packed ones. 3876 // FIXME: It would be preferable to use the slot in the 3877 // parameter save area instead of a new local variable. 3878 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType()); 3879 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3880 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, 3881 CallSeqStart, 3882 Flags, DAG, dl); 3883 3884 // Load the slot into the register. 3885 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff, 3886 MachinePointerInfo(), 3887 false, false, false, 0); 3888 MemOpChains.push_back(Load.getValue(1)); 3889 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3890 3891 // Done with this argument. 3892 ArgOffset += PtrByteSize; 3893 continue; 3894 } 3895 3896 // For aggregates larger than PtrByteSize, copy the pieces of the 3897 // object that fit into registers from the parameter save area. 3898 for (unsigned j=0; j<Size; j+=PtrByteSize) { 3899 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 3900 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 3901 if (GPR_idx != NumGPRs) { 3902 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 3903 MachinePointerInfo(), 3904 false, false, false, 0); 3905 MemOpChains.push_back(Load.getValue(1)); 3906 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3907 ArgOffset += PtrByteSize; 3908 } else { 3909 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 3910 break; 3911 } 3912 } 3913 continue; 3914 } 3915 3916 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 3917 default: llvm_unreachable("Unexpected ValueType for argument!"); 3918 case MVT::i32: 3919 case MVT::i64: 3920 if (GPR_idx != NumGPRs) { 3921 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 3922 } else { 3923 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3924 true, isTailCall, false, MemOpChains, 3925 TailCallArguments, dl); 3926 } 3927 ArgOffset += PtrByteSize; 3928 break; 3929 case MVT::f32: 3930 case MVT::f64: 3931 if (FPR_idx != NumFPRs) { 3932 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 3933 3934 if (isVarArg) { 3935 // A single float or an aggregate containing only a single float 3936 // must be passed right-justified in the stack doubleword, and 3937 // in the GPR, if one is available. 3938 SDValue StoreOff; 3939 if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) { 3940 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3941 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 3942 } else 3943 StoreOff = PtrOff; 3944 3945 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff, 3946 MachinePointerInfo(), false, false, 0); 3947 MemOpChains.push_back(Store); 3948 3949 // Float varargs are always shadowed in available integer registers 3950 if (GPR_idx != NumGPRs) { 3951 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 3952 MachinePointerInfo(), false, false, 3953 false, 0); 3954 MemOpChains.push_back(Load.getValue(1)); 3955 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3956 } 3957 } else if (GPR_idx != NumGPRs) 3958 // If we have any FPRs remaining, we may also have GPRs remaining. 3959 ++GPR_idx; 3960 } else { 3961 // Single-precision floating-point values are mapped to the 3962 // second (rightmost) word of the stack doubleword. 3963 if (Arg.getValueType() == MVT::f32) { 3964 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3965 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 3966 } 3967 3968 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3969 true, isTailCall, false, MemOpChains, 3970 TailCallArguments, dl); 3971 } 3972 ArgOffset += 8; 3973 break; 3974 case MVT::v4f32: 3975 case MVT::v4i32: 3976 case MVT::v8i16: 3977 case MVT::v16i8: 3978 if (isVarArg) { 3979 // These go aligned on the stack, or in the corresponding R registers 3980 // when within range. The Darwin PPC ABI doc claims they also go in 3981 // V registers; in fact gcc does this only for arguments that are 3982 // prototyped, not for those that match the ... We do it for all 3983 // arguments, seems to work. 3984 while (ArgOffset % 16 !=0) { 3985 ArgOffset += PtrByteSize; 3986 if (GPR_idx != NumGPRs) 3987 GPR_idx++; 3988 } 3989 // We could elide this store in the case where the object fits 3990 // entirely in R registers. Maybe later. 3991 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 3992 DAG.getConstant(ArgOffset, PtrVT)); 3993 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 3994 MachinePointerInfo(), false, false, 0); 3995 MemOpChains.push_back(Store); 3996 if (VR_idx != NumVRs) { 3997 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, 3998 MachinePointerInfo(), 3999 false, false, false, 0); 4000 MemOpChains.push_back(Load.getValue(1)); 4001 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 4002 } 4003 ArgOffset += 16; 4004 for (unsigned i=0; i<16; i+=PtrByteSize) { 4005 if (GPR_idx == NumGPRs) 4006 break; 4007 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 4008 DAG.getConstant(i, PtrVT)); 4009 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(), 4010 false, false, false, 0); 4011 MemOpChains.push_back(Load.getValue(1)); 4012 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4013 } 4014 break; 4015 } 4016 4017 // Non-varargs Altivec params generally go in registers, but have 4018 // stack space allocated at the end. 4019 if (VR_idx != NumVRs) { 4020 // Doesn't have GPR space allocated. 4021 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 4022 } else { 4023 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4024 true, isTailCall, true, MemOpChains, 4025 TailCallArguments, dl); 4026 ArgOffset += 16; 4027 } 4028 break; 4029 } 4030 } 4031 4032 if (!MemOpChains.empty()) 4033 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 4034 &MemOpChains[0], MemOpChains.size()); 4035 4036 // Check if this is an indirect call (MTCTR/BCTRL). 4037 // See PrepareCall() for more information about calls through function 4038 // pointers in the 64-bit SVR4 ABI. 4039 if (!isTailCall && 4040 !dyn_cast<GlobalAddressSDNode>(Callee) && 4041 !dyn_cast<ExternalSymbolSDNode>(Callee) && 4042 !isBLACompatibleAddress(Callee, DAG)) { 4043 // Load r2 into a virtual register and store it to the TOC save area. 4044 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); 4045 // TOC save area offset. 4046 SDValue PtrOff = DAG.getIntPtrConstant(40); 4047 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 4048 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(), 4049 false, false, 0); 4050 // R12 must contain the address of an indirect callee. This does not 4051 // mean the MTCTR instruction must use R12; it's easier to model this 4052 // as an extra parameter, so do that. 4053 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee)); 4054 } 4055 4056 // Build a sequence of copy-to-reg nodes chained together with token chain 4057 // and flag operands which copy the outgoing args into the appropriate regs. 4058 SDValue InFlag; 4059 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 4060 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 4061 RegsToPass[i].second, InFlag); 4062 InFlag = Chain.getValue(1); 4063 } 4064 4065 if (isTailCall) 4066 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp, 4067 FPOp, true, TailCallArguments); 4068 4069 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 4070 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 4071 Ins, InVals); 4072} 4073 4074SDValue 4075PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, 4076 CallingConv::ID CallConv, bool isVarArg, 4077 bool isTailCall, 4078 const SmallVectorImpl<ISD::OutputArg> &Outs, 4079 const SmallVectorImpl<SDValue> &OutVals, 4080 const SmallVectorImpl<ISD::InputArg> &Ins, 4081 SDLoc dl, SelectionDAG &DAG, 4082 SmallVectorImpl<SDValue> &InVals) const { 4083 4084 unsigned NumOps = Outs.size(); 4085 4086 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4087 bool isPPC64 = PtrVT == MVT::i64; 4088 unsigned PtrByteSize = isPPC64 ? 8 : 4; 4089 4090 MachineFunction &MF = DAG.getMachineFunction(); 4091 4092 // Mark this function as potentially containing a function that contains a 4093 // tail call. As a consequence the frame pointer will be used for dynamicalloc 4094 // and restoring the callers stack pointer in this functions epilog. This is 4095 // done because by tail calling the called function might overwrite the value 4096 // in this function's (MF) stack pointer stack slot 0(SP). 4097 if (getTargetMachine().Options.GuaranteedTailCallOpt && 4098 CallConv == CallingConv::Fast) 4099 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 4100 4101 unsigned nAltivecParamsAtEnd = 0; 4102 4103 // Count how many bytes are to be pushed on the stack, including the linkage 4104 // area, and parameter passing area. We start with 24/48 bytes, which is 4105 // prereserved space for [SP][CR][LR][3 x unused]. 4106 unsigned NumBytes = 4107 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv, 4108 Outs, OutVals, 4109 nAltivecParamsAtEnd); 4110 4111 // Calculate by how many bytes the stack has to be adjusted in case of tail 4112 // call optimization. 4113 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 4114 4115 // To protect arguments on the stack from being clobbered in a tail call, 4116 // force all the loads to happen before doing any other lowering. 4117 if (isTailCall) 4118 Chain = DAG.getStackArgumentTokenFactor(Chain); 4119 4120 // Adjust the stack pointer for the new arguments... 4121 // These operations are automatically eliminated by the prolog/epilog pass 4122 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), 4123 dl); 4124 SDValue CallSeqStart = Chain; 4125 4126 // Load the return address and frame pointer so it can be move somewhere else 4127 // later. 4128 SDValue LROp, FPOp; 4129 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 4130 dl); 4131 4132 // Set up a copy of the stack pointer for use loading and storing any 4133 // arguments that may not fit in the registers available for argument 4134 // passing. 4135 SDValue StackPtr; 4136 if (isPPC64) 4137 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 4138 else 4139 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 4140 4141 // Figure out which arguments are going to go in registers, and which in 4142 // memory. Also, if this is a vararg function, floating point operations 4143 // must be stored to our stack, and loaded into integer regs as well, if 4144 // any integer regs are available for argument passing. 4145 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); 4146 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 4147 4148 static const uint16_t GPR_32[] = { // 32-bit registers. 4149 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 4150 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 4151 }; 4152 static const uint16_t GPR_64[] = { // 64-bit registers. 4153 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 4154 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 4155 }; 4156 static const uint16_t *FPR = GetFPR(); 4157 4158 static const uint16_t VR[] = { 4159 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 4160 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 4161 }; 4162 const unsigned NumGPRs = array_lengthof(GPR_32); 4163 const unsigned NumFPRs = 13; 4164 const unsigned NumVRs = array_lengthof(VR); 4165 4166 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32; 4167 4168 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 4169 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 4170 4171 SmallVector<SDValue, 8> MemOpChains; 4172 for (unsigned i = 0; i != NumOps; ++i) { 4173 SDValue Arg = OutVals[i]; 4174 ISD::ArgFlagsTy Flags = Outs[i].Flags; 4175 4176 // PtrOff will be used to store the current argument to the stack if a 4177 // register cannot be found for it. 4178 SDValue PtrOff; 4179 4180 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 4181 4182 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 4183 4184 // On PPC64, promote integers to 64-bit values. 4185 if (isPPC64 && Arg.getValueType() == MVT::i32) { 4186 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 4187 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 4188 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 4189 } 4190 4191 // FIXME memcpy is used way more than necessary. Correctness first. 4192 // Note: "by value" is code for passing a structure by value, not 4193 // basic types. 4194 if (Flags.isByVal()) { 4195 unsigned Size = Flags.getByValSize(); 4196 // Very small objects are passed right-justified. Everything else is 4197 // passed left-justified. 4198 if (Size==1 || Size==2) { 4199 EVT VT = (Size==1) ? MVT::i8 : MVT::i16; 4200 if (GPR_idx != NumGPRs) { 4201 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, 4202 MachinePointerInfo(), VT, 4203 false, false, 0); 4204 MemOpChains.push_back(Load.getValue(1)); 4205 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4206 4207 ArgOffset += PtrByteSize; 4208 } else { 4209 SDValue Const = DAG.getConstant(PtrByteSize - Size, 4210 PtrOff.getValueType()); 4211 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 4212 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, 4213 CallSeqStart, 4214 Flags, DAG, dl); 4215 ArgOffset += PtrByteSize; 4216 } 4217 continue; 4218 } 4219 // Copy entire object into memory. There are cases where gcc-generated 4220 // code assumes it is there, even if it could be put entirely into 4221 // registers. (This is not what the doc says.) 4222 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff, 4223 CallSeqStart, 4224 Flags, DAG, dl); 4225 4226 // For small aggregates (Darwin only) and aggregates >= PtrByteSize, 4227 // copy the pieces of the object that fit into registers from the 4228 // parameter save area. 4229 for (unsigned j=0; j<Size; j+=PtrByteSize) { 4230 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 4231 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 4232 if (GPR_idx != NumGPRs) { 4233 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 4234 MachinePointerInfo(), 4235 false, false, false, 0); 4236 MemOpChains.push_back(Load.getValue(1)); 4237 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4238 ArgOffset += PtrByteSize; 4239 } else { 4240 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 4241 break; 4242 } 4243 } 4244 continue; 4245 } 4246 4247 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 4248 default: llvm_unreachable("Unexpected ValueType for argument!"); 4249 case MVT::i32: 4250 case MVT::i64: 4251 if (GPR_idx != NumGPRs) { 4252 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 4253 } else { 4254 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4255 isPPC64, isTailCall, false, MemOpChains, 4256 TailCallArguments, dl); 4257 } 4258 ArgOffset += PtrByteSize; 4259 break; 4260 case MVT::f32: 4261 case MVT::f64: 4262 if (FPR_idx != NumFPRs) { 4263 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 4264 4265 if (isVarArg) { 4266 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 4267 MachinePointerInfo(), false, false, 0); 4268 MemOpChains.push_back(Store); 4269 4270 // Float varargs are always shadowed in available integer registers 4271 if (GPR_idx != NumGPRs) { 4272 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 4273 MachinePointerInfo(), false, false, 4274 false, 0); 4275 MemOpChains.push_back(Load.getValue(1)); 4276 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4277 } 4278 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 4279 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 4280 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 4281 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 4282 MachinePointerInfo(), 4283 false, false, false, 0); 4284 MemOpChains.push_back(Load.getValue(1)); 4285 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4286 } 4287 } else { 4288 // If we have any FPRs remaining, we may also have GPRs remaining. 4289 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 4290 // GPRs. 4291 if (GPR_idx != NumGPRs) 4292 ++GPR_idx; 4293 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 4294 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 4295 ++GPR_idx; 4296 } 4297 } else 4298 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4299 isPPC64, isTailCall, false, MemOpChains, 4300 TailCallArguments, dl); 4301 if (isPPC64) 4302 ArgOffset += 8; 4303 else 4304 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 4305 break; 4306 case MVT::v4f32: 4307 case MVT::v4i32: 4308 case MVT::v8i16: 4309 case MVT::v16i8: 4310 if (isVarArg) { 4311 // These go aligned on the stack, or in the corresponding R registers 4312 // when within range. The Darwin PPC ABI doc claims they also go in 4313 // V registers; in fact gcc does this only for arguments that are 4314 // prototyped, not for those that match the ... We do it for all 4315 // arguments, seems to work. 4316 while (ArgOffset % 16 !=0) { 4317 ArgOffset += PtrByteSize; 4318 if (GPR_idx != NumGPRs) 4319 GPR_idx++; 4320 } 4321 // We could elide this store in the case where the object fits 4322 // entirely in R registers. Maybe later. 4323 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 4324 DAG.getConstant(ArgOffset, PtrVT)); 4325 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 4326 MachinePointerInfo(), false, false, 0); 4327 MemOpChains.push_back(Store); 4328 if (VR_idx != NumVRs) { 4329 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, 4330 MachinePointerInfo(), 4331 false, false, false, 0); 4332 MemOpChains.push_back(Load.getValue(1)); 4333 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 4334 } 4335 ArgOffset += 16; 4336 for (unsigned i=0; i<16; i+=PtrByteSize) { 4337 if (GPR_idx == NumGPRs) 4338 break; 4339 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 4340 DAG.getConstant(i, PtrVT)); 4341 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(), 4342 false, false, false, 0); 4343 MemOpChains.push_back(Load.getValue(1)); 4344 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4345 } 4346 break; 4347 } 4348 4349 // Non-varargs Altivec params generally go in registers, but have 4350 // stack space allocated at the end. 4351 if (VR_idx != NumVRs) { 4352 // Doesn't have GPR space allocated. 4353 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 4354 } else if (nAltivecParamsAtEnd==0) { 4355 // We are emitting Altivec params in order. 4356 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4357 isPPC64, isTailCall, true, MemOpChains, 4358 TailCallArguments, dl); 4359 ArgOffset += 16; 4360 } 4361 break; 4362 } 4363 } 4364 // If all Altivec parameters fit in registers, as they usually do, 4365 // they get stack space following the non-Altivec parameters. We 4366 // don't track this here because nobody below needs it. 4367 // If there are more Altivec parameters than fit in registers emit 4368 // the stores here. 4369 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) { 4370 unsigned j = 0; 4371 // Offset is aligned; skip 1st 12 params which go in V registers. 4372 ArgOffset = ((ArgOffset+15)/16)*16; 4373 ArgOffset += 12*16; 4374 for (unsigned i = 0; i != NumOps; ++i) { 4375 SDValue Arg = OutVals[i]; 4376 EVT ArgType = Outs[i].VT; 4377 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || 4378 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { 4379 if (++j > NumVRs) { 4380 SDValue PtrOff; 4381 // We are emitting Altivec params in order. 4382 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4383 isPPC64, isTailCall, true, MemOpChains, 4384 TailCallArguments, dl); 4385 ArgOffset += 16; 4386 } 4387 } 4388 } 4389 } 4390 4391 if (!MemOpChains.empty()) 4392 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 4393 &MemOpChains[0], MemOpChains.size()); 4394 4395 // On Darwin, R12 must contain the address of an indirect callee. This does 4396 // not mean the MTCTR instruction must use R12; it's easier to model this as 4397 // an extra parameter, so do that. 4398 if (!isTailCall && 4399 !dyn_cast<GlobalAddressSDNode>(Callee) && 4400 !dyn_cast<ExternalSymbolSDNode>(Callee) && 4401 !isBLACompatibleAddress(Callee, DAG)) 4402 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 : 4403 PPC::R12), Callee)); 4404 4405 // Build a sequence of copy-to-reg nodes chained together with token chain 4406 // and flag operands which copy the outgoing args into the appropriate regs. 4407 SDValue InFlag; 4408 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 4409 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 4410 RegsToPass[i].second, InFlag); 4411 InFlag = Chain.getValue(1); 4412 } 4413 4414 if (isTailCall) 4415 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp, 4416 FPOp, true, TailCallArguments); 4417 4418 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 4419 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 4420 Ins, InVals); 4421} 4422 4423bool 4424PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 4425 MachineFunction &MF, bool isVarArg, 4426 const SmallVectorImpl<ISD::OutputArg> &Outs, 4427 LLVMContext &Context) const { 4428 SmallVector<CCValAssign, 16> RVLocs; 4429 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 4430 RVLocs, Context); 4431 return CCInfo.CheckReturn(Outs, RetCC_PPC); 4432} 4433 4434SDValue 4435PPCTargetLowering::LowerReturn(SDValue Chain, 4436 CallingConv::ID CallConv, bool isVarArg, 4437 const SmallVectorImpl<ISD::OutputArg> &Outs, 4438 const SmallVectorImpl<SDValue> &OutVals, 4439 SDLoc dl, SelectionDAG &DAG) const { 4440 4441 SmallVector<CCValAssign, 16> RVLocs; 4442 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 4443 getTargetMachine(), RVLocs, *DAG.getContext()); 4444 CCInfo.AnalyzeReturn(Outs, RetCC_PPC); 4445 4446 SDValue Flag; 4447 SmallVector<SDValue, 4> RetOps(1, Chain); 4448 4449 // Copy the result values into the output registers. 4450 for (unsigned i = 0; i != RVLocs.size(); ++i) { 4451 CCValAssign &VA = RVLocs[i]; 4452 assert(VA.isRegLoc() && "Can only return in registers!"); 4453 4454 SDValue Arg = OutVals[i]; 4455 4456 switch (VA.getLocInfo()) { 4457 default: llvm_unreachable("Unknown loc info!"); 4458 case CCValAssign::Full: break; 4459 case CCValAssign::AExt: 4460 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 4461 break; 4462 case CCValAssign::ZExt: 4463 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 4464 break; 4465 case CCValAssign::SExt: 4466 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 4467 break; 4468 } 4469 4470 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 4471 Flag = Chain.getValue(1); 4472 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 4473 } 4474 4475 RetOps[0] = Chain; // Update chain. 4476 4477 // Add the flag if we have it. 4478 if (Flag.getNode()) 4479 RetOps.push_back(Flag); 4480 4481 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, 4482 &RetOps[0], RetOps.size()); 4483} 4484 4485SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 4486 const PPCSubtarget &Subtarget) const { 4487 // When we pop the dynamic allocation we need to restore the SP link. 4488 SDLoc dl(Op); 4489 4490 // Get the corect type for pointers. 4491 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4492 4493 // Construct the stack pointer operand. 4494 bool isPPC64 = Subtarget.isPPC64(); 4495 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; 4496 SDValue StackPtr = DAG.getRegister(SP, PtrVT); 4497 4498 // Get the operands for the STACKRESTORE. 4499 SDValue Chain = Op.getOperand(0); 4500 SDValue SaveSP = Op.getOperand(1); 4501 4502 // Load the old link SP. 4503 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, 4504 MachinePointerInfo(), 4505 false, false, false, 0); 4506 4507 // Restore the stack pointer. 4508 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); 4509 4510 // Store the old link SP. 4511 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(), 4512 false, false, 0); 4513} 4514 4515 4516 4517SDValue 4518PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { 4519 MachineFunction &MF = DAG.getMachineFunction(); 4520 bool isPPC64 = PPCSubTarget.isPPC64(); 4521 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 4522 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4523 4524 // Get current frame pointer save index. The users of this index will be 4525 // primarily DYNALLOC instructions. 4526 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 4527 int RASI = FI->getReturnAddrSaveIndex(); 4528 4529 // If the frame pointer save index hasn't been defined yet. 4530 if (!RASI) { 4531 // Find out what the fix offset of the frame pointer save area. 4532 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 4533 // Allocate the frame index for frame pointer save area. 4534 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true); 4535 // Save the result. 4536 FI->setReturnAddrSaveIndex(RASI); 4537 } 4538 return DAG.getFrameIndex(RASI, PtrVT); 4539} 4540 4541SDValue 4542PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { 4543 MachineFunction &MF = DAG.getMachineFunction(); 4544 bool isPPC64 = PPCSubTarget.isPPC64(); 4545 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 4546 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4547 4548 // Get current frame pointer save index. The users of this index will be 4549 // primarily DYNALLOC instructions. 4550 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 4551 int FPSI = FI->getFramePointerSaveIndex(); 4552 4553 // If the frame pointer save index hasn't been defined yet. 4554 if (!FPSI) { 4555 // Find out what the fix offset of the frame pointer save area. 4556 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, 4557 isDarwinABI); 4558 4559 // Allocate the frame index for frame pointer save area. 4560 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 4561 // Save the result. 4562 FI->setFramePointerSaveIndex(FPSI); 4563 } 4564 return DAG.getFrameIndex(FPSI, PtrVT); 4565} 4566 4567SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 4568 SelectionDAG &DAG, 4569 const PPCSubtarget &Subtarget) const { 4570 // Get the inputs. 4571 SDValue Chain = Op.getOperand(0); 4572 SDValue Size = Op.getOperand(1); 4573 SDLoc dl(Op); 4574 4575 // Get the corect type for pointers. 4576 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4577 // Negate the size. 4578 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, 4579 DAG.getConstant(0, PtrVT), Size); 4580 // Construct a node for the frame pointer save index. 4581 SDValue FPSIdx = getFramePointerFrameIndex(DAG); 4582 // Build a DYNALLOC node. 4583 SDValue Ops[3] = { Chain, NegSize, FPSIdx }; 4584 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 4585 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3); 4586} 4587 4588SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op, 4589 SelectionDAG &DAG) const { 4590 SDLoc DL(Op); 4591 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL, 4592 DAG.getVTList(MVT::i32, MVT::Other), 4593 Op.getOperand(0), Op.getOperand(1)); 4594} 4595 4596SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op, 4597 SelectionDAG &DAG) const { 4598 SDLoc DL(Op); 4599 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other, 4600 Op.getOperand(0), Op.getOperand(1)); 4601} 4602 4603/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 4604/// possible. 4605SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 4606 // Not FP? Not a fsel. 4607 if (!Op.getOperand(0).getValueType().isFloatingPoint() || 4608 !Op.getOperand(2).getValueType().isFloatingPoint()) 4609 return Op; 4610 4611 // We might be able to do better than this under some circumstances, but in 4612 // general, fsel-based lowering of select is a finite-math-only optimization. 4613 // For more information, see section F.3 of the 2.06 ISA specification. 4614 if (!DAG.getTarget().Options.NoInfsFPMath || 4615 !DAG.getTarget().Options.NoNaNsFPMath) 4616 return Op; 4617 4618 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 4619 4620 EVT ResVT = Op.getValueType(); 4621 EVT CmpVT = Op.getOperand(0).getValueType(); 4622 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4623 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); 4624 SDLoc dl(Op); 4625 4626 // If the RHS of the comparison is a 0.0, we don't need to do the 4627 // subtraction at all. 4628 SDValue Sel1; 4629 if (isFloatingPointZero(RHS)) 4630 switch (CC) { 4631 default: break; // SETUO etc aren't handled by fsel. 4632 case ISD::SETNE: 4633 std::swap(TV, FV); 4634 case ISD::SETEQ: 4635 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 4636 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 4637 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); 4638 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits 4639 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); 4640 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 4641 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV); 4642 case ISD::SETULT: 4643 case ISD::SETLT: 4644 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 4645 case ISD::SETOGE: 4646 case ISD::SETGE: 4647 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 4648 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 4649 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); 4650 case ISD::SETUGT: 4651 case ISD::SETGT: 4652 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 4653 case ISD::SETOLE: 4654 case ISD::SETLE: 4655 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 4656 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 4657 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 4658 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); 4659 } 4660 4661 SDValue Cmp; 4662 switch (CC) { 4663 default: break; // SETUO etc aren't handled by fsel. 4664 case ISD::SETNE: 4665 std::swap(TV, FV); 4666 case ISD::SETEQ: 4667 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 4668 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4669 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4670 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 4671 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits 4672 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); 4673 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 4674 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV); 4675 case ISD::SETULT: 4676 case ISD::SETLT: 4677 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 4678 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4679 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4680 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 4681 case ISD::SETOGE: 4682 case ISD::SETGE: 4683 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 4684 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4685 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4686 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 4687 case ISD::SETUGT: 4688 case ISD::SETGT: 4689 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 4690 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4691 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4692 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 4693 case ISD::SETOLE: 4694 case ISD::SETLE: 4695 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 4696 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4697 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4698 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 4699 } 4700 return Op; 4701} 4702 4703// FIXME: Split this code up when LegalizeDAGTypes lands. 4704SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 4705 SDLoc dl) const { 4706 assert(Op.getOperand(0).getValueType().isFloatingPoint()); 4707 SDValue Src = Op.getOperand(0); 4708 if (Src.getValueType() == MVT::f32) 4709 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); 4710 4711 SDValue Tmp; 4712 switch (Op.getValueType().getSimpleVT().SimpleTy) { 4713 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); 4714 case MVT::i32: 4715 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : 4716 (PPCSubTarget.hasFPCVT() ? PPCISD::FCTIWUZ : 4717 PPCISD::FCTIDZ), 4718 dl, MVT::f64, Src); 4719 break; 4720 case MVT::i64: 4721 assert((Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()) && 4722 "i64 FP_TO_UINT is supported only with FPCVT"); 4723 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ : 4724 PPCISD::FCTIDUZ, 4725 dl, MVT::f64, Src); 4726 break; 4727 } 4728 4729 // Convert the FP value to an int value through memory. 4730 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() && 4731 (Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()); 4732 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64); 4733 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex(); 4734 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI); 4735 4736 // Emit a store to the stack slot. 4737 SDValue Chain; 4738 if (i32Stack) { 4739 MachineFunction &MF = DAG.getMachineFunction(); 4740 MachineMemOperand *MMO = 4741 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4); 4742 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr }; 4743 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl, 4744 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops), 4745 MVT::i32, MMO); 4746 } else 4747 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, 4748 MPI, false, false, 0); 4749 4750 // Result is a load from the stack slot. If loading 4 bytes, make sure to 4751 // add in a bias. 4752 if (Op.getValueType() == MVT::i32 && !i32Stack) { 4753 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, 4754 DAG.getConstant(4, FIPtr.getValueType())); 4755 MPI = MachinePointerInfo(); 4756 } 4757 4758 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI, 4759 false, false, false, 0); 4760} 4761 4762SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op, 4763 SelectionDAG &DAG) const { 4764 SDLoc dl(Op); 4765 // Don't handle ppc_fp128 here; let it be lowered to a libcall. 4766 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) 4767 return SDValue(); 4768 4769 assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) && 4770 "UINT_TO_FP is supported only with FPCVT"); 4771 4772 // If we have FCFIDS, then use it when converting to single-precision. 4773 // Otherwise, convert to double-precision and then round. 4774 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ? 4775 (Op.getOpcode() == ISD::UINT_TO_FP ? 4776 PPCISD::FCFIDUS : PPCISD::FCFIDS) : 4777 (Op.getOpcode() == ISD::UINT_TO_FP ? 4778 PPCISD::FCFIDU : PPCISD::FCFID); 4779 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ? 4780 MVT::f32 : MVT::f64; 4781 4782 if (Op.getOperand(0).getValueType() == MVT::i64) { 4783 SDValue SINT = Op.getOperand(0); 4784 // When converting to single-precision, we actually need to convert 4785 // to double-precision first and then round to single-precision. 4786 // To avoid double-rounding effects during that operation, we have 4787 // to prepare the input operand. Bits that might be truncated when 4788 // converting to double-precision are replaced by a bit that won't 4789 // be lost at this stage, but is below the single-precision rounding 4790 // position. 4791 // 4792 // However, if -enable-unsafe-fp-math is in effect, accept double 4793 // rounding to avoid the extra overhead. 4794 if (Op.getValueType() == MVT::f32 && 4795 !PPCSubTarget.hasFPCVT() && 4796 !DAG.getTarget().Options.UnsafeFPMath) { 4797 4798 // Twiddle input to make sure the low 11 bits are zero. (If this 4799 // is the case, we are guaranteed the value will fit into the 53 bit 4800 // mantissa of an IEEE double-precision value without rounding.) 4801 // If any of those low 11 bits were not zero originally, make sure 4802 // bit 12 (value 2048) is set instead, so that the final rounding 4803 // to single-precision gets the correct result. 4804 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64, 4805 SINT, DAG.getConstant(2047, MVT::i64)); 4806 Round = DAG.getNode(ISD::ADD, dl, MVT::i64, 4807 Round, DAG.getConstant(2047, MVT::i64)); 4808 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT); 4809 Round = DAG.getNode(ISD::AND, dl, MVT::i64, 4810 Round, DAG.getConstant(-2048, MVT::i64)); 4811 4812 // However, we cannot use that value unconditionally: if the magnitude 4813 // of the input value is small, the bit-twiddling we did above might 4814 // end up visibly changing the output. Fortunately, in that case, we 4815 // don't need to twiddle bits since the original input will convert 4816 // exactly to double-precision floating-point already. Therefore, 4817 // construct a conditional to use the original value if the top 11 4818 // bits are all sign-bit copies, and use the rounded value computed 4819 // above otherwise. 4820 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64, 4821 SINT, DAG.getConstant(53, MVT::i32)); 4822 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64, 4823 Cond, DAG.getConstant(1, MVT::i64)); 4824 Cond = DAG.getSetCC(dl, MVT::i32, 4825 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT); 4826 4827 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT); 4828 } 4829 4830 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT); 4831 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits); 4832 4833 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT()) 4834 FP = DAG.getNode(ISD::FP_ROUND, dl, 4835 MVT::f32, FP, DAG.getIntPtrConstant(0)); 4836 return FP; 4837 } 4838 4839 assert(Op.getOperand(0).getValueType() == MVT::i32 && 4840 "Unhandled INT_TO_FP type in custom expander!"); 4841 // Since we only generate this in 64-bit mode, we can take advantage of 4842 // 64-bit registers. In particular, sign extend the input value into the 4843 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 4844 // then lfd it and fcfid it. 4845 MachineFunction &MF = DAG.getMachineFunction(); 4846 MachineFrameInfo *FrameInfo = MF.getFrameInfo(); 4847 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4848 4849 SDValue Ld; 4850 if (PPCSubTarget.hasLFIWAX() || PPCSubTarget.hasFPCVT()) { 4851 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false); 4852 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 4853 4854 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx, 4855 MachinePointerInfo::getFixedStack(FrameIdx), 4856 false, false, 0); 4857 4858 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 && 4859 "Expected an i32 store"); 4860 MachineMemOperand *MMO = 4861 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 4862 MachineMemOperand::MOLoad, 4, 4); 4863 SDValue Ops[] = { Store, FIdx }; 4864 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ? 4865 PPCISD::LFIWZX : PPCISD::LFIWAX, 4866 dl, DAG.getVTList(MVT::f64, MVT::Other), 4867 Ops, 2, MVT::i32, MMO); 4868 } else { 4869 assert(PPCSubTarget.isPPC64() && 4870 "i32->FP without LFIWAX supported only on PPC64"); 4871 4872 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false); 4873 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 4874 4875 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64, 4876 Op.getOperand(0)); 4877 4878 // STD the extended value into the stack slot. 4879 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx, 4880 MachinePointerInfo::getFixedStack(FrameIdx), 4881 false, false, 0); 4882 4883 // Load the value as a double. 4884 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, 4885 MachinePointerInfo::getFixedStack(FrameIdx), 4886 false, false, false, 0); 4887 } 4888 4889 // FCFID it and return it. 4890 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld); 4891 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT()) 4892 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); 4893 return FP; 4894} 4895 4896SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 4897 SelectionDAG &DAG) const { 4898 SDLoc dl(Op); 4899 /* 4900 The rounding mode is in bits 30:31 of FPSR, and has the following 4901 settings: 4902 00 Round to nearest 4903 01 Round to 0 4904 10 Round to +inf 4905 11 Round to -inf 4906 4907 FLT_ROUNDS, on the other hand, expects the following: 4908 -1 Undefined 4909 0 Round to 0 4910 1 Round to nearest 4911 2 Round to +inf 4912 3 Round to -inf 4913 4914 To perform the conversion, we do: 4915 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 4916 */ 4917 4918 MachineFunction &MF = DAG.getMachineFunction(); 4919 EVT VT = Op.getValueType(); 4920 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4921 SDValue MFFSreg, InFlag; 4922 4923 // Save FP Control Word to register 4924 EVT NodeTys[] = { 4925 MVT::f64, // return register 4926 MVT::Glue // unused in this context 4927 }; 4928 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 4929 4930 // Save FP register to stack slot 4931 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 4932 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 4933 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, 4934 StackSlot, MachinePointerInfo(), false, false,0); 4935 4936 // Load FP Control Word from low 32 bits of stack slot. 4937 SDValue Four = DAG.getConstant(4, PtrVT); 4938 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); 4939 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(), 4940 false, false, false, 0); 4941 4942 // Transform as necessary 4943 SDValue CWD1 = 4944 DAG.getNode(ISD::AND, dl, MVT::i32, 4945 CWD, DAG.getConstant(3, MVT::i32)); 4946 SDValue CWD2 = 4947 DAG.getNode(ISD::SRL, dl, MVT::i32, 4948 DAG.getNode(ISD::AND, dl, MVT::i32, 4949 DAG.getNode(ISD::XOR, dl, MVT::i32, 4950 CWD, DAG.getConstant(3, MVT::i32)), 4951 DAG.getConstant(3, MVT::i32)), 4952 DAG.getConstant(1, MVT::i32)); 4953 4954 SDValue RetVal = 4955 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); 4956 4957 return DAG.getNode((VT.getSizeInBits() < 16 ? 4958 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 4959} 4960 4961SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const { 4962 EVT VT = Op.getValueType(); 4963 unsigned BitWidth = VT.getSizeInBits(); 4964 SDLoc dl(Op); 4965 assert(Op.getNumOperands() == 3 && 4966 VT == Op.getOperand(1).getValueType() && 4967 "Unexpected SHL!"); 4968 4969 // Expand into a bunch of logical ops. Note that these ops 4970 // depend on the PPC behavior for oversized shift amounts. 4971 SDValue Lo = Op.getOperand(0); 4972 SDValue Hi = Op.getOperand(1); 4973 SDValue Amt = Op.getOperand(2); 4974 EVT AmtVT = Amt.getValueType(); 4975 4976 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 4977 DAG.getConstant(BitWidth, AmtVT), Amt); 4978 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); 4979 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); 4980 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); 4981 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 4982 DAG.getConstant(-BitWidth, AmtVT)); 4983 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); 4984 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 4985 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); 4986 SDValue OutOps[] = { OutLo, OutHi }; 4987 return DAG.getMergeValues(OutOps, 2, dl); 4988} 4989 4990SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const { 4991 EVT VT = Op.getValueType(); 4992 SDLoc dl(Op); 4993 unsigned BitWidth = VT.getSizeInBits(); 4994 assert(Op.getNumOperands() == 3 && 4995 VT == Op.getOperand(1).getValueType() && 4996 "Unexpected SRL!"); 4997 4998 // Expand into a bunch of logical ops. Note that these ops 4999 // depend on the PPC behavior for oversized shift amounts. 5000 SDValue Lo = Op.getOperand(0); 5001 SDValue Hi = Op.getOperand(1); 5002 SDValue Amt = Op.getOperand(2); 5003 EVT AmtVT = Amt.getValueType(); 5004 5005 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 5006 DAG.getConstant(BitWidth, AmtVT), Amt); 5007 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 5008 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 5009 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 5010 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 5011 DAG.getConstant(-BitWidth, AmtVT)); 5012 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); 5013 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 5014 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); 5015 SDValue OutOps[] = { OutLo, OutHi }; 5016 return DAG.getMergeValues(OutOps, 2, dl); 5017} 5018 5019SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const { 5020 SDLoc dl(Op); 5021 EVT VT = Op.getValueType(); 5022 unsigned BitWidth = VT.getSizeInBits(); 5023 assert(Op.getNumOperands() == 3 && 5024 VT == Op.getOperand(1).getValueType() && 5025 "Unexpected SRA!"); 5026 5027 // Expand into a bunch of logical ops, followed by a select_cc. 5028 SDValue Lo = Op.getOperand(0); 5029 SDValue Hi = Op.getOperand(1); 5030 SDValue Amt = Op.getOperand(2); 5031 EVT AmtVT = Amt.getValueType(); 5032 5033 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 5034 DAG.getConstant(BitWidth, AmtVT), Amt); 5035 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 5036 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 5037 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 5038 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 5039 DAG.getConstant(-BitWidth, AmtVT)); 5040 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); 5041 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); 5042 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), 5043 Tmp4, Tmp6, ISD::SETLE); 5044 SDValue OutOps[] = { OutLo, OutHi }; 5045 return DAG.getMergeValues(OutOps, 2, dl); 5046} 5047 5048//===----------------------------------------------------------------------===// 5049// Vector related lowering. 5050// 5051 5052/// BuildSplatI - Build a canonical splati of Val with an element size of 5053/// SplatSize. Cast the result to VT. 5054static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT, 5055 SelectionDAG &DAG, SDLoc dl) { 5056 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 5057 5058 static const EVT VTys[] = { // canonical VT to use for each size. 5059 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 5060 }; 5061 5062 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 5063 5064 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 5065 if (Val == -1) 5066 SplatSize = 1; 5067 5068 EVT CanonicalVT = VTys[SplatSize-1]; 5069 5070 // Build a canonical splat for this value. 5071 SDValue Elt = DAG.getConstant(Val, MVT::i32); 5072 SmallVector<SDValue, 8> Ops; 5073 Ops.assign(CanonicalVT.getVectorNumElements(), Elt); 5074 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, 5075 &Ops[0], Ops.size()); 5076 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res); 5077} 5078 5079/// BuildIntrinsicOp - Return a unary operator intrinsic node with the 5080/// specified intrinsic ID. 5081static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op, 5082 SelectionDAG &DAG, SDLoc dl, 5083 EVT DestVT = MVT::Other) { 5084 if (DestVT == MVT::Other) DestVT = Op.getValueType(); 5085 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 5086 DAG.getConstant(IID, MVT::i32), Op); 5087} 5088 5089/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 5090/// specified intrinsic ID. 5091static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, 5092 SelectionDAG &DAG, SDLoc dl, 5093 EVT DestVT = MVT::Other) { 5094 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 5095 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 5096 DAG.getConstant(IID, MVT::i32), LHS, RHS); 5097} 5098 5099/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 5100/// specified intrinsic ID. 5101static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, 5102 SDValue Op2, SelectionDAG &DAG, 5103 SDLoc dl, EVT DestVT = MVT::Other) { 5104 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 5105 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 5106 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 5107} 5108 5109 5110/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 5111/// amount. The result has the specified value type. 5112static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, 5113 EVT VT, SelectionDAG &DAG, SDLoc dl) { 5114 // Force LHS/RHS to be the right type. 5115 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS); 5116 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS); 5117 5118 int Ops[16]; 5119 for (unsigned i = 0; i != 16; ++i) 5120 Ops[i] = i + Amt; 5121 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); 5122 return DAG.getNode(ISD::BITCAST, dl, VT, T); 5123} 5124 5125// If this is a case we can't handle, return null and let the default 5126// expansion code take care of it. If we CAN select this case, and if it 5127// selects to a single instruction, return Op. Otherwise, if we can codegen 5128// this case more efficiently than a constant pool load, lower it to the 5129// sequence of ops that should be used. 5130SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, 5131 SelectionDAG &DAG) const { 5132 SDLoc dl(Op); 5133 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 5134 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR"); 5135 5136 // Check if this is a splat of a constant value. 5137 APInt APSplatBits, APSplatUndef; 5138 unsigned SplatBitSize; 5139 bool HasAnyUndefs; 5140 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize, 5141 HasAnyUndefs, 0, true) || SplatBitSize > 32) 5142 return SDValue(); 5143 5144 unsigned SplatBits = APSplatBits.getZExtValue(); 5145 unsigned SplatUndef = APSplatUndef.getZExtValue(); 5146 unsigned SplatSize = SplatBitSize / 8; 5147 5148 // First, handle single instruction cases. 5149 5150 // All zeros? 5151 if (SplatBits == 0) { 5152 // Canonicalize all zero vectors to be v4i32. 5153 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 5154 SDValue Z = DAG.getConstant(0, MVT::i32); 5155 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); 5156 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z); 5157 } 5158 return Op; 5159 } 5160 5161 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 5162 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >> 5163 (32-SplatBitSize)); 5164 if (SextVal >= -16 && SextVal <= 15) 5165 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl); 5166 5167 5168 // Two instruction sequences. 5169 5170 // If this value is in the range [-32,30] and is even, use: 5171 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2) 5172 // If this value is in the range [17,31] and is odd, use: 5173 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16) 5174 // If this value is in the range [-31,-17] and is odd, use: 5175 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16) 5176 // Note the last two are three-instruction sequences. 5177 if (SextVal >= -32 && SextVal <= 31) { 5178 // To avoid having these optimizations undone by constant folding, 5179 // we convert to a pseudo that will be expanded later into one of 5180 // the above forms. 5181 SDValue Elt = DAG.getConstant(SextVal, MVT::i32); 5182 EVT VT = Op.getValueType(); 5183 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4); 5184 SDValue EltSize = DAG.getConstant(Size, MVT::i32); 5185 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize); 5186 } 5187 5188 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 5189 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 5190 // for fneg/fabs. 5191 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 5192 // Make -1 and vspltisw -1: 5193 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); 5194 5195 // Make the VSLW intrinsic, computing 0x8000_0000. 5196 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 5197 OnesV, DAG, dl); 5198 5199 // xor by OnesV to invert it. 5200 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); 5201 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5202 } 5203 5204 // Check to see if this is a wide variety of vsplti*, binop self cases. 5205 static const signed char SplatCsts[] = { 5206 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 5207 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 5208 }; 5209 5210 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 5211 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 5212 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 5213 int i = SplatCsts[idx]; 5214 5215 // Figure out what shift amount will be used by altivec if shifted by i in 5216 // this splat size. 5217 unsigned TypeShiftAmt = i & (SplatBitSize-1); 5218 5219 // vsplti + shl self. 5220 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) { 5221 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5222 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5223 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 5224 Intrinsic::ppc_altivec_vslw 5225 }; 5226 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5227 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5228 } 5229 5230 // vsplti + srl self. 5231 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 5232 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5233 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5234 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 5235 Intrinsic::ppc_altivec_vsrw 5236 }; 5237 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5238 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5239 } 5240 5241 // vsplti + sra self. 5242 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 5243 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5244 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5245 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 5246 Intrinsic::ppc_altivec_vsraw 5247 }; 5248 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5249 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5250 } 5251 5252 // vsplti + rol self. 5253 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 5254 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 5255 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5256 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5257 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 5258 Intrinsic::ppc_altivec_vrlw 5259 }; 5260 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5261 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5262 } 5263 5264 // t = vsplti c, result = vsldoi t, t, 1 5265 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) { 5266 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 5267 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); 5268 } 5269 // t = vsplti c, result = vsldoi t, t, 2 5270 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) { 5271 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 5272 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); 5273 } 5274 // t = vsplti c, result = vsldoi t, t, 3 5275 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) { 5276 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 5277 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); 5278 } 5279 } 5280 5281 return SDValue(); 5282} 5283 5284/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 5285/// the specified operations to build the shuffle. 5286static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 5287 SDValue RHS, SelectionDAG &DAG, 5288 SDLoc dl) { 5289 unsigned OpNum = (PFEntry >> 26) & 0x0F; 5290 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 5291 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 5292 5293 enum { 5294 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 5295 OP_VMRGHW, 5296 OP_VMRGLW, 5297 OP_VSPLTISW0, 5298 OP_VSPLTISW1, 5299 OP_VSPLTISW2, 5300 OP_VSPLTISW3, 5301 OP_VSLDOI4, 5302 OP_VSLDOI8, 5303 OP_VSLDOI12 5304 }; 5305 5306 if (OpNum == OP_COPY) { 5307 if (LHSID == (1*9+2)*9+3) return LHS; 5308 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 5309 return RHS; 5310 } 5311 5312 SDValue OpLHS, OpRHS; 5313 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 5314 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 5315 5316 int ShufIdxs[16]; 5317 switch (OpNum) { 5318 default: llvm_unreachable("Unknown i32 permute!"); 5319 case OP_VMRGHW: 5320 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 5321 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 5322 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 5323 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 5324 break; 5325 case OP_VMRGLW: 5326 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 5327 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 5328 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 5329 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 5330 break; 5331 case OP_VSPLTISW0: 5332 for (unsigned i = 0; i != 16; ++i) 5333 ShufIdxs[i] = (i&3)+0; 5334 break; 5335 case OP_VSPLTISW1: 5336 for (unsigned i = 0; i != 16; ++i) 5337 ShufIdxs[i] = (i&3)+4; 5338 break; 5339 case OP_VSPLTISW2: 5340 for (unsigned i = 0; i != 16; ++i) 5341 ShufIdxs[i] = (i&3)+8; 5342 break; 5343 case OP_VSPLTISW3: 5344 for (unsigned i = 0; i != 16; ++i) 5345 ShufIdxs[i] = (i&3)+12; 5346 break; 5347 case OP_VSLDOI4: 5348 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl); 5349 case OP_VSLDOI8: 5350 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl); 5351 case OP_VSLDOI12: 5352 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl); 5353 } 5354 EVT VT = OpLHS.getValueType(); 5355 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS); 5356 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS); 5357 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); 5358 return DAG.getNode(ISD::BITCAST, dl, VT, T); 5359} 5360 5361/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 5362/// is a shuffle we can handle in a single instruction, return it. Otherwise, 5363/// return the code it can be lowered into. Worst case, it can always be 5364/// lowered into a vperm. 5365SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 5366 SelectionDAG &DAG) const { 5367 SDLoc dl(Op); 5368 SDValue V1 = Op.getOperand(0); 5369 SDValue V2 = Op.getOperand(1); 5370 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5371 EVT VT = Op.getValueType(); 5372 5373 // Cases that are handled by instructions that take permute immediates 5374 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 5375 // selected by the instruction selector. 5376 if (V2.getOpcode() == ISD::UNDEF) { 5377 if (PPC::isSplatShuffleMask(SVOp, 1) || 5378 PPC::isSplatShuffleMask(SVOp, 2) || 5379 PPC::isSplatShuffleMask(SVOp, 4) || 5380 PPC::isVPKUWUMShuffleMask(SVOp, true) || 5381 PPC::isVPKUHUMShuffleMask(SVOp, true) || 5382 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 || 5383 PPC::isVMRGLShuffleMask(SVOp, 1, true) || 5384 PPC::isVMRGLShuffleMask(SVOp, 2, true) || 5385 PPC::isVMRGLShuffleMask(SVOp, 4, true) || 5386 PPC::isVMRGHShuffleMask(SVOp, 1, true) || 5387 PPC::isVMRGHShuffleMask(SVOp, 2, true) || 5388 PPC::isVMRGHShuffleMask(SVOp, 4, true)) { 5389 return Op; 5390 } 5391 } 5392 5393 // Altivec has a variety of "shuffle immediates" that take two vector inputs 5394 // and produce a fixed permutation. If any of these match, do not lower to 5395 // VPERM. 5396 if (PPC::isVPKUWUMShuffleMask(SVOp, false) || 5397 PPC::isVPKUHUMShuffleMask(SVOp, false) || 5398 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 || 5399 PPC::isVMRGLShuffleMask(SVOp, 1, false) || 5400 PPC::isVMRGLShuffleMask(SVOp, 2, false) || 5401 PPC::isVMRGLShuffleMask(SVOp, 4, false) || 5402 PPC::isVMRGHShuffleMask(SVOp, 1, false) || 5403 PPC::isVMRGHShuffleMask(SVOp, 2, false) || 5404 PPC::isVMRGHShuffleMask(SVOp, 4, false)) 5405 return Op; 5406 5407 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 5408 // perfect shuffle table to emit an optimal matching sequence. 5409 ArrayRef<int> PermMask = SVOp->getMask(); 5410 5411 unsigned PFIndexes[4]; 5412 bool isFourElementShuffle = true; 5413 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 5414 unsigned EltNo = 8; // Start out undef. 5415 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 5416 if (PermMask[i*4+j] < 0) 5417 continue; // Undef, ignore it. 5418 5419 unsigned ByteSource = PermMask[i*4+j]; 5420 if ((ByteSource & 3) != j) { 5421 isFourElementShuffle = false; 5422 break; 5423 } 5424 5425 if (EltNo == 8) { 5426 EltNo = ByteSource/4; 5427 } else if (EltNo != ByteSource/4) { 5428 isFourElementShuffle = false; 5429 break; 5430 } 5431 } 5432 PFIndexes[i] = EltNo; 5433 } 5434 5435 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 5436 // perfect shuffle vector to determine if it is cost effective to do this as 5437 // discrete instructions, or whether we should use a vperm. 5438 if (isFourElementShuffle) { 5439 // Compute the index in the perfect shuffle table. 5440 unsigned PFTableIndex = 5441 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 5442 5443 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 5444 unsigned Cost = (PFEntry >> 30); 5445 5446 // Determining when to avoid vperm is tricky. Many things affect the cost 5447 // of vperm, particularly how many times the perm mask needs to be computed. 5448 // For example, if the perm mask can be hoisted out of a loop or is already 5449 // used (perhaps because there are multiple permutes with the same shuffle 5450 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 5451 // the loop requires an extra register. 5452 // 5453 // As a compromise, we only emit discrete instructions if the shuffle can be 5454 // generated in 3 or fewer operations. When we have loop information 5455 // available, if this block is within a loop, we should avoid using vperm 5456 // for 3-operation perms and use a constant pool load instead. 5457 if (Cost < 3) 5458 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 5459 } 5460 5461 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 5462 // vector that will get spilled to the constant pool. 5463 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 5464 5465 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 5466 // that it is in input element units, not in bytes. Convert now. 5467 EVT EltVT = V1.getValueType().getVectorElementType(); 5468 unsigned BytesPerElement = EltVT.getSizeInBits()/8; 5469 5470 SmallVector<SDValue, 16> ResultMask; 5471 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { 5472 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i]; 5473 5474 for (unsigned j = 0; j != BytesPerElement; ++j) 5475 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 5476 MVT::i32)); 5477 } 5478 5479 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, 5480 &ResultMask[0], ResultMask.size()); 5481 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); 5482} 5483 5484/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 5485/// altivec comparison. If it is, return true and fill in Opc/isDot with 5486/// information about the intrinsic. 5487static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, 5488 bool &isDot) { 5489 unsigned IntrinsicID = 5490 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue(); 5491 CompareOpc = -1; 5492 isDot = false; 5493 switch (IntrinsicID) { 5494 default: return false; 5495 // Comparison predicates. 5496 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 5497 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 5498 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 5499 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 5500 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 5501 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 5502 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 5503 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 5504 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 5505 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 5506 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 5507 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 5508 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 5509 5510 // Normal Comparisons. 5511 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 5512 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 5513 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 5514 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 5515 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 5516 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 5517 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 5518 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 5519 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 5520 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 5521 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 5522 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 5523 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 5524 } 5525 return true; 5526} 5527 5528/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 5529/// lower, do it, otherwise return null. 5530SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 5531 SelectionDAG &DAG) const { 5532 // If this is a lowered altivec predicate compare, CompareOpc is set to the 5533 // opcode number of the comparison. 5534 SDLoc dl(Op); 5535 int CompareOpc; 5536 bool isDot; 5537 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 5538 return SDValue(); // Don't custom lower most intrinsics. 5539 5540 // If this is a non-dot comparison, make the VCMP node and we are done. 5541 if (!isDot) { 5542 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), 5543 Op.getOperand(1), Op.getOperand(2), 5544 DAG.getConstant(CompareOpc, MVT::i32)); 5545 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp); 5546 } 5547 5548 // Create the PPCISD altivec 'dot' comparison node. 5549 SDValue Ops[] = { 5550 Op.getOperand(2), // LHS 5551 Op.getOperand(3), // RHS 5552 DAG.getConstant(CompareOpc, MVT::i32) 5553 }; 5554 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue }; 5555 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 5556 5557 // Now that we have the comparison, emit a copy from the CR to a GPR. 5558 // This is flagged to the above dot comparison. 5559 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32, 5560 DAG.getRegister(PPC::CR6, MVT::i32), 5561 CompNode.getValue(1)); 5562 5563 // Unpack the result based on how the target uses it. 5564 unsigned BitNo; // Bit # of CR6. 5565 bool InvertBit; // Invert result? 5566 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) { 5567 default: // Can't happen, don't crash on invalid number though. 5568 case 0: // Return the value of the EQ bit of CR6. 5569 BitNo = 0; InvertBit = false; 5570 break; 5571 case 1: // Return the inverted value of the EQ bit of CR6. 5572 BitNo = 0; InvertBit = true; 5573 break; 5574 case 2: // Return the value of the LT bit of CR6. 5575 BitNo = 2; InvertBit = false; 5576 break; 5577 case 3: // Return the inverted value of the LT bit of CR6. 5578 BitNo = 2; InvertBit = true; 5579 break; 5580 } 5581 5582 // Shift the bit into the low position. 5583 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, 5584 DAG.getConstant(8-(3-BitNo), MVT::i32)); 5585 // Isolate the bit. 5586 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, 5587 DAG.getConstant(1, MVT::i32)); 5588 5589 // If we are supposed to, toggle the bit. 5590 if (InvertBit) 5591 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, 5592 DAG.getConstant(1, MVT::i32)); 5593 return Flags; 5594} 5595 5596SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, 5597 SelectionDAG &DAG) const { 5598 SDLoc dl(Op); 5599 // Create a stack slot that is 16-byte aligned. 5600 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 5601 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false); 5602 EVT PtrVT = getPointerTy(); 5603 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 5604 5605 // Store the input value into Value#0 of the stack slot. 5606 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 5607 Op.getOperand(0), FIdx, MachinePointerInfo(), 5608 false, false, 0); 5609 // Load it out. 5610 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(), 5611 false, false, false, 0); 5612} 5613 5614SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 5615 SDLoc dl(Op); 5616 if (Op.getValueType() == MVT::v4i32) { 5617 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 5618 5619 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); 5620 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. 5621 5622 SDValue RHSSwap = // = vrlw RHS, 16 5623 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); 5624 5625 // Shrinkify inputs to v8i16. 5626 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS); 5627 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS); 5628 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap); 5629 5630 // Low parts multiplied together, generating 32-bit results (we ignore the 5631 // top parts). 5632 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 5633 LHS, RHS, DAG, dl, MVT::v4i32); 5634 5635 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 5636 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); 5637 // Shift the high parts up 16 bits. 5638 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, 5639 Neg16, DAG, dl); 5640 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); 5641 } else if (Op.getValueType() == MVT::v8i16) { 5642 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 5643 5644 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); 5645 5646 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 5647 LHS, RHS, Zero, DAG, dl); 5648 } else if (Op.getValueType() == MVT::v16i8) { 5649 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 5650 5651 // Multiply the even 8-bit parts, producing 16-bit sums. 5652 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 5653 LHS, RHS, DAG, dl, MVT::v8i16); 5654 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts); 5655 5656 // Multiply the odd 8-bit parts, producing 16-bit sums. 5657 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 5658 LHS, RHS, DAG, dl, MVT::v8i16); 5659 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts); 5660 5661 // Merge the results together. 5662 int Ops[16]; 5663 for (unsigned i = 0; i != 8; ++i) { 5664 Ops[i*2 ] = 2*i+1; 5665 Ops[i*2+1] = 2*i+1+16; 5666 } 5667 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); 5668 } else { 5669 llvm_unreachable("Unknown mul to lower!"); 5670 } 5671} 5672 5673/// LowerOperation - Provide custom lowering hooks for some operations. 5674/// 5675SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 5676 switch (Op.getOpcode()) { 5677 default: llvm_unreachable("Wasn't expecting to be able to lower this!"); 5678 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 5679 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 5680 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 5681 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 5682 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 5683 case ISD::SETCC: return LowerSETCC(Op, DAG); 5684 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 5685 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 5686 case ISD::VASTART: 5687 return LowerVASTART(Op, DAG, PPCSubTarget); 5688 5689 case ISD::VAARG: 5690 return LowerVAARG(Op, DAG, PPCSubTarget); 5691 5692 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 5693 case ISD::DYNAMIC_STACKALLOC: 5694 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 5695 5696 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG); 5697 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG); 5698 5699 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 5700 case ISD::FP_TO_UINT: 5701 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, 5702 SDLoc(Op)); 5703 case ISD::UINT_TO_FP: 5704 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 5705 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 5706 5707 // Lower 64-bit shifts. 5708 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 5709 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 5710 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 5711 5712 // Vector-related lowering. 5713 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 5714 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 5715 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 5716 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 5717 case ISD::MUL: return LowerMUL(Op, DAG); 5718 5719 // For counter-based loop handling. 5720 case ISD::INTRINSIC_W_CHAIN: return SDValue(); 5721 5722 // Frame & Return address. 5723 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 5724 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 5725 } 5726} 5727 5728void PPCTargetLowering::ReplaceNodeResults(SDNode *N, 5729 SmallVectorImpl<SDValue>&Results, 5730 SelectionDAG &DAG) const { 5731 const TargetMachine &TM = getTargetMachine(); 5732 SDLoc dl(N); 5733 switch (N->getOpcode()) { 5734 default: 5735 llvm_unreachable("Do not know how to custom type legalize this operation!"); 5736 case ISD::INTRINSIC_W_CHAIN: { 5737 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 5738 Intrinsic::ppc_is_decremented_ctr_nonzero) 5739 break; 5740 5741 assert(N->getValueType(0) == MVT::i1 && 5742 "Unexpected result type for CTR decrement intrinsic"); 5743 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0)); 5744 SDVTList VTs = DAG.getVTList(SVT, MVT::Other); 5745 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0), 5746 N->getOperand(1)); 5747 5748 Results.push_back(NewInt); 5749 Results.push_back(NewInt.getValue(1)); 5750 break; 5751 } 5752 case ISD::VAARG: { 5753 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI() 5754 || TM.getSubtarget<PPCSubtarget>().isPPC64()) 5755 return; 5756 5757 EVT VT = N->getValueType(0); 5758 5759 if (VT == MVT::i64) { 5760 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget); 5761 5762 Results.push_back(NewNode); 5763 Results.push_back(NewNode.getValue(1)); 5764 } 5765 return; 5766 } 5767 case ISD::FP_ROUND_INREG: { 5768 assert(N->getValueType(0) == MVT::ppcf128); 5769 assert(N->getOperand(0).getValueType() == MVT::ppcf128); 5770 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 5771 MVT::f64, N->getOperand(0), 5772 DAG.getIntPtrConstant(0)); 5773 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 5774 MVT::f64, N->getOperand(0), 5775 DAG.getIntPtrConstant(1)); 5776 5777 // Add the two halves of the long double in round-to-zero mode. 5778 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi); 5779 5780 // We know the low half is about to be thrown away, so just use something 5781 // convenient. 5782 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, 5783 FPreg, FPreg)); 5784 return; 5785 } 5786 case ISD::FP_TO_SINT: 5787 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl)); 5788 return; 5789 } 5790} 5791 5792 5793//===----------------------------------------------------------------------===// 5794// Other Lowering Code 5795//===----------------------------------------------------------------------===// 5796 5797MachineBasicBlock * 5798PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 5799 bool is64bit, unsigned BinOpcode) const { 5800 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 5801 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5802 5803 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5804 MachineFunction *F = BB->getParent(); 5805 MachineFunction::iterator It = BB; 5806 ++It; 5807 5808 unsigned dest = MI->getOperand(0).getReg(); 5809 unsigned ptrA = MI->getOperand(1).getReg(); 5810 unsigned ptrB = MI->getOperand(2).getReg(); 5811 unsigned incr = MI->getOperand(3).getReg(); 5812 DebugLoc dl = MI->getDebugLoc(); 5813 5814 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 5815 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 5816 F->insert(It, loopMBB); 5817 F->insert(It, exitMBB); 5818 exitMBB->splice(exitMBB->begin(), BB, 5819 llvm::next(MachineBasicBlock::iterator(MI)), 5820 BB->end()); 5821 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5822 5823 MachineRegisterInfo &RegInfo = F->getRegInfo(); 5824 unsigned TmpReg = (!BinOpcode) ? incr : 5825 RegInfo.createVirtualRegister( 5826 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 5827 (const TargetRegisterClass *) &PPC::GPRCRegClass); 5828 5829 // thisMBB: 5830 // ... 5831 // fallthrough --> loopMBB 5832 BB->addSuccessor(loopMBB); 5833 5834 // loopMBB: 5835 // l[wd]arx dest, ptr 5836 // add r0, dest, incr 5837 // st[wd]cx. r0, ptr 5838 // bne- loopMBB 5839 // fallthrough --> exitMBB 5840 BB = loopMBB; 5841 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 5842 .addReg(ptrA).addReg(ptrB); 5843 if (BinOpcode) 5844 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); 5845 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 5846 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); 5847 BuildMI(BB, dl, TII->get(PPC::BCC)) 5848 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 5849 BB->addSuccessor(loopMBB); 5850 BB->addSuccessor(exitMBB); 5851 5852 // exitMBB: 5853 // ... 5854 BB = exitMBB; 5855 return BB; 5856} 5857 5858MachineBasicBlock * 5859PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, 5860 MachineBasicBlock *BB, 5861 bool is8bit, // operation 5862 unsigned BinOpcode) const { 5863 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 5864 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5865 // In 64 bit mode we have to use 64 bits for addresses, even though the 5866 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address 5867 // registers without caring whether they're 32 or 64, but here we're 5868 // doing actual arithmetic on the addresses. 5869 bool is64bit = PPCSubTarget.isPPC64(); 5870 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; 5871 5872 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5873 MachineFunction *F = BB->getParent(); 5874 MachineFunction::iterator It = BB; 5875 ++It; 5876 5877 unsigned dest = MI->getOperand(0).getReg(); 5878 unsigned ptrA = MI->getOperand(1).getReg(); 5879 unsigned ptrB = MI->getOperand(2).getReg(); 5880 unsigned incr = MI->getOperand(3).getReg(); 5881 DebugLoc dl = MI->getDebugLoc(); 5882 5883 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 5884 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 5885 F->insert(It, loopMBB); 5886 F->insert(It, exitMBB); 5887 exitMBB->splice(exitMBB->begin(), BB, 5888 llvm::next(MachineBasicBlock::iterator(MI)), 5889 BB->end()); 5890 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5891 5892 MachineRegisterInfo &RegInfo = F->getRegInfo(); 5893 const TargetRegisterClass *RC = 5894 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 5895 (const TargetRegisterClass *) &PPC::GPRCRegClass; 5896 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 5897 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 5898 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 5899 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC); 5900 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 5901 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 5902 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 5903 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 5904 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC); 5905 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 5906 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 5907 unsigned Ptr1Reg; 5908 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); 5909 5910 // thisMBB: 5911 // ... 5912 // fallthrough --> loopMBB 5913 BB->addSuccessor(loopMBB); 5914 5915 // The 4-byte load must be aligned, while a char or short may be 5916 // anywhere in the word. Hence all this nasty bookkeeping code. 5917 // add ptr1, ptrA, ptrB [copy if ptrA==0] 5918 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 5919 // xori shift, shift1, 24 [16] 5920 // rlwinm ptr, ptr1, 0, 0, 29 5921 // slw incr2, incr, shift 5922 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 5923 // slw mask, mask2, shift 5924 // loopMBB: 5925 // lwarx tmpDest, ptr 5926 // add tmp, tmpDest, incr2 5927 // andc tmp2, tmpDest, mask 5928 // and tmp3, tmp, mask 5929 // or tmp4, tmp3, tmp2 5930 // stwcx. tmp4, ptr 5931 // bne- loopMBB 5932 // fallthrough --> exitMBB 5933 // srw dest, tmpDest, shift 5934 if (ptrA != ZeroReg) { 5935 Ptr1Reg = RegInfo.createVirtualRegister(RC); 5936 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 5937 .addReg(ptrA).addReg(ptrB); 5938 } else { 5939 Ptr1Reg = ptrB; 5940 } 5941 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 5942 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 5943 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 5944 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 5945 if (is64bit) 5946 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 5947 .addReg(Ptr1Reg).addImm(0).addImm(61); 5948 else 5949 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 5950 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 5951 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg) 5952 .addReg(incr).addReg(ShiftReg); 5953 if (is8bit) 5954 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 5955 else { 5956 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 5957 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535); 5958 } 5959 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 5960 .addReg(Mask2Reg).addReg(ShiftReg); 5961 5962 BB = loopMBB; 5963 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 5964 .addReg(ZeroReg).addReg(PtrReg); 5965 if (BinOpcode) 5966 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) 5967 .addReg(Incr2Reg).addReg(TmpDestReg); 5968 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) 5969 .addReg(TmpDestReg).addReg(MaskReg); 5970 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) 5971 .addReg(TmpReg).addReg(MaskReg); 5972 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) 5973 .addReg(Tmp3Reg).addReg(Tmp2Reg); 5974 BuildMI(BB, dl, TII->get(PPC::STWCX)) 5975 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg); 5976 BuildMI(BB, dl, TII->get(PPC::BCC)) 5977 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 5978 BB->addSuccessor(loopMBB); 5979 BB->addSuccessor(exitMBB); 5980 5981 // exitMBB: 5982 // ... 5983 BB = exitMBB; 5984 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg) 5985 .addReg(ShiftReg); 5986 return BB; 5987} 5988 5989llvm::MachineBasicBlock* 5990PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI, 5991 MachineBasicBlock *MBB) const { 5992 DebugLoc DL = MI->getDebugLoc(); 5993 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5994 5995 MachineFunction *MF = MBB->getParent(); 5996 MachineRegisterInfo &MRI = MF->getRegInfo(); 5997 5998 const BasicBlock *BB = MBB->getBasicBlock(); 5999 MachineFunction::iterator I = MBB; 6000 ++I; 6001 6002 // Memory Reference 6003 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 6004 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 6005 6006 unsigned DstReg = MI->getOperand(0).getReg(); 6007 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); 6008 assert(RC->hasType(MVT::i32) && "Invalid destination!"); 6009 unsigned mainDstReg = MRI.createVirtualRegister(RC); 6010 unsigned restoreDstReg = MRI.createVirtualRegister(RC); 6011 6012 MVT PVT = getPointerTy(); 6013 assert((PVT == MVT::i64 || PVT == MVT::i32) && 6014 "Invalid Pointer Size!"); 6015 // For v = setjmp(buf), we generate 6016 // 6017 // thisMBB: 6018 // SjLjSetup mainMBB 6019 // bl mainMBB 6020 // v_restore = 1 6021 // b sinkMBB 6022 // 6023 // mainMBB: 6024 // buf[LabelOffset] = LR 6025 // v_main = 0 6026 // 6027 // sinkMBB: 6028 // v = phi(main, restore) 6029 // 6030 6031 MachineBasicBlock *thisMBB = MBB; 6032 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB); 6033 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB); 6034 MF->insert(I, mainMBB); 6035 MF->insert(I, sinkMBB); 6036 6037 MachineInstrBuilder MIB; 6038 6039 // Transfer the remainder of BB and its successor edges to sinkMBB. 6040 sinkMBB->splice(sinkMBB->begin(), MBB, 6041 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end()); 6042 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB); 6043 6044 // Note that the structure of the jmp_buf used here is not compatible 6045 // with that used by libc, and is not designed to be. Specifically, it 6046 // stores only those 'reserved' registers that LLVM does not otherwise 6047 // understand how to spill. Also, by convention, by the time this 6048 // intrinsic is called, Clang has already stored the frame address in the 6049 // first slot of the buffer and stack address in the third. Following the 6050 // X86 target code, we'll store the jump address in the second slot. We also 6051 // need to save the TOC pointer (R2) to handle jumps between shared 6052 // libraries, and that will be stored in the fourth slot. The thread 6053 // identifier (R13) is not affected. 6054 6055 // thisMBB: 6056 const int64_t LabelOffset = 1 * PVT.getStoreSize(); 6057 const int64_t TOCOffset = 3 * PVT.getStoreSize(); 6058 6059 // Prepare IP either in reg. 6060 const TargetRegisterClass *PtrRC = getRegClassFor(PVT); 6061 unsigned LabelReg = MRI.createVirtualRegister(PtrRC); 6062 unsigned BufReg = MI->getOperand(1).getReg(); 6063 6064 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) { 6065 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD)) 6066 .addReg(PPC::X2) 6067 .addImm(TOCOffset) 6068 .addReg(BufReg); 6069 6070 MIB.setMemRefs(MMOBegin, MMOEnd); 6071 } 6072 6073 // Setup 6074 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB); 6075 MIB.addRegMask(PPCRegInfo->getNoPreservedMask()); 6076 6077 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1); 6078 6079 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup)) 6080 .addMBB(mainMBB); 6081 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB); 6082 6083 thisMBB->addSuccessor(mainMBB, /* weight */ 0); 6084 thisMBB->addSuccessor(sinkMBB, /* weight */ 1); 6085 6086 // mainMBB: 6087 // mainDstReg = 0 6088 MIB = BuildMI(mainMBB, DL, 6089 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg); 6090 6091 // Store IP 6092 if (PPCSubTarget.isPPC64()) { 6093 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD)) 6094 .addReg(LabelReg) 6095 .addImm(LabelOffset) 6096 .addReg(BufReg); 6097 } else { 6098 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW)) 6099 .addReg(LabelReg) 6100 .addImm(LabelOffset) 6101 .addReg(BufReg); 6102 } 6103 6104 MIB.setMemRefs(MMOBegin, MMOEnd); 6105 6106 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0); 6107 mainMBB->addSuccessor(sinkMBB); 6108 6109 // sinkMBB: 6110 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 6111 TII->get(PPC::PHI), DstReg) 6112 .addReg(mainDstReg).addMBB(mainMBB) 6113 .addReg(restoreDstReg).addMBB(thisMBB); 6114 6115 MI->eraseFromParent(); 6116 return sinkMBB; 6117} 6118 6119MachineBasicBlock * 6120PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI, 6121 MachineBasicBlock *MBB) const { 6122 DebugLoc DL = MI->getDebugLoc(); 6123 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 6124 6125 MachineFunction *MF = MBB->getParent(); 6126 MachineRegisterInfo &MRI = MF->getRegInfo(); 6127 6128 // Memory Reference 6129 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 6130 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 6131 6132 MVT PVT = getPointerTy(); 6133 assert((PVT == MVT::i64 || PVT == MVT::i32) && 6134 "Invalid Pointer Size!"); 6135 6136 const TargetRegisterClass *RC = 6137 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; 6138 unsigned Tmp = MRI.createVirtualRegister(RC); 6139 // Since FP is only updated here but NOT referenced, it's treated as GPR. 6140 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31; 6141 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1; 6142 6143 MachineInstrBuilder MIB; 6144 6145 const int64_t LabelOffset = 1 * PVT.getStoreSize(); 6146 const int64_t SPOffset = 2 * PVT.getStoreSize(); 6147 const int64_t TOCOffset = 3 * PVT.getStoreSize(); 6148 6149 unsigned BufReg = MI->getOperand(0).getReg(); 6150 6151 // Reload FP (the jumped-to function may not have had a 6152 // frame pointer, and if so, then its r31 will be restored 6153 // as necessary). 6154 if (PVT == MVT::i64) { 6155 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP) 6156 .addImm(0) 6157 .addReg(BufReg); 6158 } else { 6159 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP) 6160 .addImm(0) 6161 .addReg(BufReg); 6162 } 6163 MIB.setMemRefs(MMOBegin, MMOEnd); 6164 6165 // Reload IP 6166 if (PVT == MVT::i64) { 6167 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp) 6168 .addImm(LabelOffset) 6169 .addReg(BufReg); 6170 } else { 6171 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp) 6172 .addImm(LabelOffset) 6173 .addReg(BufReg); 6174 } 6175 MIB.setMemRefs(MMOBegin, MMOEnd); 6176 6177 // Reload SP 6178 if (PVT == MVT::i64) { 6179 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP) 6180 .addImm(SPOffset) 6181 .addReg(BufReg); 6182 } else { 6183 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP) 6184 .addImm(SPOffset) 6185 .addReg(BufReg); 6186 } 6187 MIB.setMemRefs(MMOBegin, MMOEnd); 6188 6189 // FIXME: When we also support base pointers, that register must also be 6190 // restored here. 6191 6192 // Reload TOC 6193 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) { 6194 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2) 6195 .addImm(TOCOffset) 6196 .addReg(BufReg); 6197 6198 MIB.setMemRefs(MMOBegin, MMOEnd); 6199 } 6200 6201 // Jump 6202 BuildMI(*MBB, MI, DL, 6203 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp); 6204 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR)); 6205 6206 MI->eraseFromParent(); 6207 return MBB; 6208} 6209 6210MachineBasicBlock * 6211PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 6212 MachineBasicBlock *BB) const { 6213 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 || 6214 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) { 6215 return emitEHSjLjSetJmp(MI, BB); 6216 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 || 6217 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) { 6218 return emitEHSjLjLongJmp(MI, BB); 6219 } 6220 6221 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 6222 6223 // To "insert" these instructions we actually have to insert their 6224 // control-flow patterns. 6225 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 6226 MachineFunction::iterator It = BB; 6227 ++It; 6228 6229 MachineFunction *F = BB->getParent(); 6230 6231 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 || 6232 MI->getOpcode() == PPC::SELECT_CC_I8)) { 6233 SmallVector<MachineOperand, 2> Cond; 6234 Cond.push_back(MI->getOperand(4)); 6235 Cond.push_back(MI->getOperand(1)); 6236 6237 DebugLoc dl = MI->getDebugLoc(); 6238 PPCII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(), Cond, 6239 MI->getOperand(2).getReg(), MI->getOperand(3).getReg()); 6240 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 || 6241 MI->getOpcode() == PPC::SELECT_CC_I8 || 6242 MI->getOpcode() == PPC::SELECT_CC_F4 || 6243 MI->getOpcode() == PPC::SELECT_CC_F8 || 6244 MI->getOpcode() == PPC::SELECT_CC_VRRC) { 6245 6246 6247 // The incoming instruction knows the destination vreg to set, the 6248 // condition code register to branch on, the true/false values to 6249 // select between, and a branch opcode to use. 6250 6251 // thisMBB: 6252 // ... 6253 // TrueVal = ... 6254 // cmpTY ccX, r1, r2 6255 // bCC copy1MBB 6256 // fallthrough --> copy0MBB 6257 MachineBasicBlock *thisMBB = BB; 6258 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 6259 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 6260 unsigned SelectPred = MI->getOperand(4).getImm(); 6261 DebugLoc dl = MI->getDebugLoc(); 6262 F->insert(It, copy0MBB); 6263 F->insert(It, sinkMBB); 6264 6265 // Transfer the remainder of BB and its successor edges to sinkMBB. 6266 sinkMBB->splice(sinkMBB->begin(), BB, 6267 llvm::next(MachineBasicBlock::iterator(MI)), 6268 BB->end()); 6269 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 6270 6271 // Next, add the true and fallthrough blocks as its successors. 6272 BB->addSuccessor(copy0MBB); 6273 BB->addSuccessor(sinkMBB); 6274 6275 BuildMI(BB, dl, TII->get(PPC::BCC)) 6276 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 6277 6278 // copy0MBB: 6279 // %FalseValue = ... 6280 // # fallthrough to sinkMBB 6281 BB = copy0MBB; 6282 6283 // Update machine-CFG edges 6284 BB->addSuccessor(sinkMBB); 6285 6286 // sinkMBB: 6287 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 6288 // ... 6289 BB = sinkMBB; 6290 BuildMI(*BB, BB->begin(), dl, 6291 TII->get(PPC::PHI), MI->getOperand(0).getReg()) 6292 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 6293 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 6294 } 6295 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) 6296 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); 6297 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) 6298 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); 6299 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) 6300 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4); 6301 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) 6302 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8); 6303 6304 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8) 6305 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); 6306 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16) 6307 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); 6308 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32) 6309 BB = EmitAtomicBinary(MI, BB, false, PPC::AND); 6310 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64) 6311 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8); 6312 6313 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8) 6314 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); 6315 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16) 6316 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); 6317 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32) 6318 BB = EmitAtomicBinary(MI, BB, false, PPC::OR); 6319 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64) 6320 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8); 6321 6322 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) 6323 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); 6324 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) 6325 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); 6326 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) 6327 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR); 6328 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) 6329 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8); 6330 6331 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) 6332 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC); 6333 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) 6334 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC); 6335 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) 6336 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC); 6337 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) 6338 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8); 6339 6340 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) 6341 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); 6342 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) 6343 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); 6344 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) 6345 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF); 6346 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) 6347 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8); 6348 6349 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8) 6350 BB = EmitPartwordAtomicBinary(MI, BB, true, 0); 6351 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16) 6352 BB = EmitPartwordAtomicBinary(MI, BB, false, 0); 6353 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32) 6354 BB = EmitAtomicBinary(MI, BB, false, 0); 6355 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64) 6356 BB = EmitAtomicBinary(MI, BB, true, 0); 6357 6358 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || 6359 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) { 6360 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; 6361 6362 unsigned dest = MI->getOperand(0).getReg(); 6363 unsigned ptrA = MI->getOperand(1).getReg(); 6364 unsigned ptrB = MI->getOperand(2).getReg(); 6365 unsigned oldval = MI->getOperand(3).getReg(); 6366 unsigned newval = MI->getOperand(4).getReg(); 6367 DebugLoc dl = MI->getDebugLoc(); 6368 6369 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 6370 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 6371 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 6372 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 6373 F->insert(It, loop1MBB); 6374 F->insert(It, loop2MBB); 6375 F->insert(It, midMBB); 6376 F->insert(It, exitMBB); 6377 exitMBB->splice(exitMBB->begin(), BB, 6378 llvm::next(MachineBasicBlock::iterator(MI)), 6379 BB->end()); 6380 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 6381 6382 // thisMBB: 6383 // ... 6384 // fallthrough --> loopMBB 6385 BB->addSuccessor(loop1MBB); 6386 6387 // loop1MBB: 6388 // l[wd]arx dest, ptr 6389 // cmp[wd] dest, oldval 6390 // bne- midMBB 6391 // loop2MBB: 6392 // st[wd]cx. newval, ptr 6393 // bne- loopMBB 6394 // b exitBB 6395 // midMBB: 6396 // st[wd]cx. dest, ptr 6397 // exitBB: 6398 BB = loop1MBB; 6399 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 6400 .addReg(ptrA).addReg(ptrB); 6401 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) 6402 .addReg(oldval).addReg(dest); 6403 BuildMI(BB, dl, TII->get(PPC::BCC)) 6404 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 6405 BB->addSuccessor(loop2MBB); 6406 BB->addSuccessor(midMBB); 6407 6408 BB = loop2MBB; 6409 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 6410 .addReg(newval).addReg(ptrA).addReg(ptrB); 6411 BuildMI(BB, dl, TII->get(PPC::BCC)) 6412 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 6413 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 6414 BB->addSuccessor(loop1MBB); 6415 BB->addSuccessor(exitMBB); 6416 6417 BB = midMBB; 6418 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 6419 .addReg(dest).addReg(ptrA).addReg(ptrB); 6420 BB->addSuccessor(exitMBB); 6421 6422 // exitMBB: 6423 // ... 6424 BB = exitMBB; 6425 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || 6426 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { 6427 // We must use 64-bit registers for addresses when targeting 64-bit, 6428 // since we're actually doing arithmetic on them. Other registers 6429 // can be 32-bit. 6430 bool is64bit = PPCSubTarget.isPPC64(); 6431 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; 6432 6433 unsigned dest = MI->getOperand(0).getReg(); 6434 unsigned ptrA = MI->getOperand(1).getReg(); 6435 unsigned ptrB = MI->getOperand(2).getReg(); 6436 unsigned oldval = MI->getOperand(3).getReg(); 6437 unsigned newval = MI->getOperand(4).getReg(); 6438 DebugLoc dl = MI->getDebugLoc(); 6439 6440 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 6441 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 6442 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 6443 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 6444 F->insert(It, loop1MBB); 6445 F->insert(It, loop2MBB); 6446 F->insert(It, midMBB); 6447 F->insert(It, exitMBB); 6448 exitMBB->splice(exitMBB->begin(), BB, 6449 llvm::next(MachineBasicBlock::iterator(MI)), 6450 BB->end()); 6451 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 6452 6453 MachineRegisterInfo &RegInfo = F->getRegInfo(); 6454 const TargetRegisterClass *RC = 6455 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 6456 (const TargetRegisterClass *) &PPC::GPRCRegClass; 6457 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 6458 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 6459 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 6460 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC); 6461 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC); 6462 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC); 6463 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC); 6464 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 6465 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 6466 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 6467 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 6468 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 6469 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 6470 unsigned Ptr1Reg; 6471 unsigned TmpReg = RegInfo.createVirtualRegister(RC); 6472 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; 6473 // thisMBB: 6474 // ... 6475 // fallthrough --> loopMBB 6476 BB->addSuccessor(loop1MBB); 6477 6478 // The 4-byte load must be aligned, while a char or short may be 6479 // anywhere in the word. Hence all this nasty bookkeeping code. 6480 // add ptr1, ptrA, ptrB [copy if ptrA==0] 6481 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 6482 // xori shift, shift1, 24 [16] 6483 // rlwinm ptr, ptr1, 0, 0, 29 6484 // slw newval2, newval, shift 6485 // slw oldval2, oldval,shift 6486 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 6487 // slw mask, mask2, shift 6488 // and newval3, newval2, mask 6489 // and oldval3, oldval2, mask 6490 // loop1MBB: 6491 // lwarx tmpDest, ptr 6492 // and tmp, tmpDest, mask 6493 // cmpw tmp, oldval3 6494 // bne- midMBB 6495 // loop2MBB: 6496 // andc tmp2, tmpDest, mask 6497 // or tmp4, tmp2, newval3 6498 // stwcx. tmp4, ptr 6499 // bne- loop1MBB 6500 // b exitBB 6501 // midMBB: 6502 // stwcx. tmpDest, ptr 6503 // exitBB: 6504 // srw dest, tmpDest, shift 6505 if (ptrA != ZeroReg) { 6506 Ptr1Reg = RegInfo.createVirtualRegister(RC); 6507 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 6508 .addReg(ptrA).addReg(ptrB); 6509 } else { 6510 Ptr1Reg = ptrB; 6511 } 6512 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 6513 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 6514 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 6515 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 6516 if (is64bit) 6517 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 6518 .addReg(Ptr1Reg).addImm(0).addImm(61); 6519 else 6520 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 6521 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 6522 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) 6523 .addReg(newval).addReg(ShiftReg); 6524 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) 6525 .addReg(oldval).addReg(ShiftReg); 6526 if (is8bit) 6527 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 6528 else { 6529 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 6530 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) 6531 .addReg(Mask3Reg).addImm(65535); 6532 } 6533 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 6534 .addReg(Mask2Reg).addReg(ShiftReg); 6535 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg) 6536 .addReg(NewVal2Reg).addReg(MaskReg); 6537 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg) 6538 .addReg(OldVal2Reg).addReg(MaskReg); 6539 6540 BB = loop1MBB; 6541 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 6542 .addReg(ZeroReg).addReg(PtrReg); 6543 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) 6544 .addReg(TmpDestReg).addReg(MaskReg); 6545 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0) 6546 .addReg(TmpReg).addReg(OldVal3Reg); 6547 BuildMI(BB, dl, TII->get(PPC::BCC)) 6548 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 6549 BB->addSuccessor(loop2MBB); 6550 BB->addSuccessor(midMBB); 6551 6552 BB = loop2MBB; 6553 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg) 6554 .addReg(TmpDestReg).addReg(MaskReg); 6555 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg) 6556 .addReg(Tmp2Reg).addReg(NewVal3Reg); 6557 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg) 6558 .addReg(ZeroReg).addReg(PtrReg); 6559 BuildMI(BB, dl, TII->get(PPC::BCC)) 6560 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 6561 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 6562 BB->addSuccessor(loop1MBB); 6563 BB->addSuccessor(exitMBB); 6564 6565 BB = midMBB; 6566 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg) 6567 .addReg(ZeroReg).addReg(PtrReg); 6568 BB->addSuccessor(exitMBB); 6569 6570 // exitMBB: 6571 // ... 6572 BB = exitMBB; 6573 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg) 6574 .addReg(ShiftReg); 6575 } else if (MI->getOpcode() == PPC::FADDrtz) { 6576 // This pseudo performs an FADD with rounding mode temporarily forced 6577 // to round-to-zero. We emit this via custom inserter since the FPSCR 6578 // is not modeled at the SelectionDAG level. 6579 unsigned Dest = MI->getOperand(0).getReg(); 6580 unsigned Src1 = MI->getOperand(1).getReg(); 6581 unsigned Src2 = MI->getOperand(2).getReg(); 6582 DebugLoc dl = MI->getDebugLoc(); 6583 6584 MachineRegisterInfo &RegInfo = F->getRegInfo(); 6585 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); 6586 6587 // Save FPSCR value. 6588 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg); 6589 6590 // Set rounding mode to round-to-zero. 6591 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31); 6592 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30); 6593 6594 // Perform addition. 6595 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2); 6596 6597 // Restore FPSCR value. 6598 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg); 6599 } else if (MI->getOpcode() == PPC::FRINDrint || 6600 MI->getOpcode() == PPC::FRINSrint) { 6601 bool isf32 = MI->getOpcode() == PPC::FRINSrint; 6602 unsigned Dest = MI->getOperand(0).getReg(); 6603 unsigned Src = MI->getOperand(1).getReg(); 6604 DebugLoc dl = MI->getDebugLoc(); 6605 6606 MachineRegisterInfo &RegInfo = F->getRegInfo(); 6607 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass); 6608 6609 // Perform the rounding. 6610 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FRINS : PPC::FRIND), Dest) 6611 .addReg(Src); 6612 6613 // Compare the results. 6614 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FCMPUS : PPC::FCMPUD), CRReg) 6615 .addReg(Dest).addReg(Src); 6616 6617 // If the results were not equal, then set the FPSCR XX bit. 6618 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 6619 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 6620 F->insert(It, midMBB); 6621 F->insert(It, exitMBB); 6622 exitMBB->splice(exitMBB->begin(), BB, 6623 llvm::next(MachineBasicBlock::iterator(MI)), 6624 BB->end()); 6625 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 6626 6627 BuildMI(*BB, MI, dl, TII->get(PPC::BCC)) 6628 .addImm(PPC::PRED_EQ).addReg(CRReg).addMBB(exitMBB); 6629 6630 BB->addSuccessor(midMBB); 6631 BB->addSuccessor(exitMBB); 6632 6633 BB = midMBB; 6634 6635 // Set the FPSCR XX bit (FE_INEXACT). Note that we cannot just set 6636 // the FI bit here because that will not automatically set XX also, 6637 // and XX is what libm interprets as the FE_INEXACT flag. 6638 BuildMI(BB, dl, TII->get(PPC::MTFSB1)).addImm(/* 38 - 32 = */ 6); 6639 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 6640 6641 BB->addSuccessor(exitMBB); 6642 6643 BB = exitMBB; 6644 } else { 6645 llvm_unreachable("Unexpected instr type to insert"); 6646 } 6647 6648 MI->eraseFromParent(); // The pseudo instruction is gone now. 6649 return BB; 6650} 6651 6652//===----------------------------------------------------------------------===// 6653// Target Optimization Hooks 6654//===----------------------------------------------------------------------===// 6655 6656SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op, 6657 DAGCombinerInfo &DCI) const { 6658 if (DCI.isAfterLegalizeVectorOps()) 6659 return SDValue(); 6660 6661 EVT VT = Op.getValueType(); 6662 6663 if ((VT == MVT::f32 && PPCSubTarget.hasFRES()) || 6664 (VT == MVT::f64 && PPCSubTarget.hasFRE()) || 6665 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) { 6666 6667 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i) 6668 // For the reciprocal, we need to find the zero of the function: 6669 // F(X) = A X - 1 [which has a zero at X = 1/A] 6670 // => 6671 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form 6672 // does not require additional intermediate precision] 6673 6674 // Convergence is quadratic, so we essentially double the number of digits 6675 // correct after every iteration. The minimum architected relative 6676 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has 6677 // 23 digits and double has 52 digits. 6678 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3; 6679 if (VT.getScalarType() == MVT::f64) 6680 ++Iterations; 6681 6682 SelectionDAG &DAG = DCI.DAG; 6683 SDLoc dl(Op); 6684 6685 SDValue FPOne = 6686 DAG.getConstantFP(1.0, VT.getScalarType()); 6687 if (VT.isVector()) { 6688 assert(VT.getVectorNumElements() == 4 && 6689 "Unknown vector type"); 6690 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, 6691 FPOne, FPOne, FPOne, FPOne); 6692 } 6693 6694 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op); 6695 DCI.AddToWorklist(Est.getNode()); 6696 6697 // Newton iterations: Est = Est + Est (1 - Arg * Est) 6698 for (int i = 0; i < Iterations; ++i) { 6699 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est); 6700 DCI.AddToWorklist(NewEst.getNode()); 6701 6702 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst); 6703 DCI.AddToWorklist(NewEst.getNode()); 6704 6705 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst); 6706 DCI.AddToWorklist(NewEst.getNode()); 6707 6708 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst); 6709 DCI.AddToWorklist(Est.getNode()); 6710 } 6711 6712 return Est; 6713 } 6714 6715 return SDValue(); 6716} 6717 6718SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op, 6719 DAGCombinerInfo &DCI) const { 6720 if (DCI.isAfterLegalizeVectorOps()) 6721 return SDValue(); 6722 6723 EVT VT = Op.getValueType(); 6724 6725 if ((VT == MVT::f32 && PPCSubTarget.hasFRSQRTES()) || 6726 (VT == MVT::f64 && PPCSubTarget.hasFRSQRTE()) || 6727 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) { 6728 6729 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i) 6730 // For the reciprocal sqrt, we need to find the zero of the function: 6731 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)] 6732 // => 6733 // X_{i+1} = X_i (1.5 - A X_i^2 / 2) 6734 // As a result, we precompute A/2 prior to the iteration loop. 6735 6736 // Convergence is quadratic, so we essentially double the number of digits 6737 // correct after every iteration. The minimum architected relative 6738 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has 6739 // 23 digits and double has 52 digits. 6740 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3; 6741 if (VT.getScalarType() == MVT::f64) 6742 ++Iterations; 6743 6744 SelectionDAG &DAG = DCI.DAG; 6745 SDLoc dl(Op); 6746 6747 SDValue FPThreeHalves = 6748 DAG.getConstantFP(1.5, VT.getScalarType()); 6749 if (VT.isVector()) { 6750 assert(VT.getVectorNumElements() == 4 && 6751 "Unknown vector type"); 6752 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, 6753 FPThreeHalves, FPThreeHalves, 6754 FPThreeHalves, FPThreeHalves); 6755 } 6756 6757 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op); 6758 DCI.AddToWorklist(Est.getNode()); 6759 6760 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that 6761 // this entire sequence requires only one FP constant. 6762 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op); 6763 DCI.AddToWorklist(HalfArg.getNode()); 6764 6765 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op); 6766 DCI.AddToWorklist(HalfArg.getNode()); 6767 6768 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est) 6769 for (int i = 0; i < Iterations; ++i) { 6770 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est); 6771 DCI.AddToWorklist(NewEst.getNode()); 6772 6773 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst); 6774 DCI.AddToWorklist(NewEst.getNode()); 6775 6776 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst); 6777 DCI.AddToWorklist(NewEst.getNode()); 6778 6779 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst); 6780 DCI.AddToWorklist(Est.getNode()); 6781 } 6782 6783 return Est; 6784 } 6785 6786 return SDValue(); 6787} 6788 6789// Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does 6790// not enforce equality of the chain operands. 6791static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base, 6792 unsigned Bytes, int Dist, 6793 SelectionDAG &DAG) { 6794 EVT VT = LS->getMemoryVT(); 6795 if (VT.getSizeInBits() / 8 != Bytes) 6796 return false; 6797 6798 SDValue Loc = LS->getBasePtr(); 6799 SDValue BaseLoc = Base->getBasePtr(); 6800 if (Loc.getOpcode() == ISD::FrameIndex) { 6801 if (BaseLoc.getOpcode() != ISD::FrameIndex) 6802 return false; 6803 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 6804 int FI = cast<FrameIndexSDNode>(Loc)->getIndex(); 6805 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex(); 6806 int FS = MFI->getObjectSize(FI); 6807 int BFS = MFI->getObjectSize(BFI); 6808 if (FS != BFS || FS != (int)Bytes) return false; 6809 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes); 6810 } 6811 6812 // Handle X+C 6813 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc && 6814 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes) 6815 return true; 6816 6817 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6818 const GlobalValue *GV1 = NULL; 6819 const GlobalValue *GV2 = NULL; 6820 int64_t Offset1 = 0; 6821 int64_t Offset2 = 0; 6822 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1); 6823 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2); 6824 if (isGA1 && isGA2 && GV1 == GV2) 6825 return Offset1 == (Offset2 + Dist*Bytes); 6826 return false; 6827} 6828 6829// Return true is there is a nearyby consecutive load to the one provided 6830// (regardless of alignment). We search up and down the chain, looking though 6831// token factors and other loads (but nothing else). As a result, a true 6832// results indicates that it is safe to create a new consecutive load adjacent 6833// to the load provided. 6834static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) { 6835 SDValue Chain = LD->getChain(); 6836 EVT VT = LD->getMemoryVT(); 6837 6838 SmallSet<SDNode *, 16> LoadRoots; 6839 SmallVector<SDNode *, 8> Queue(1, Chain.getNode()); 6840 SmallSet<SDNode *, 16> Visited; 6841 6842 // First, search up the chain, branching to follow all token-factor operands. 6843 // If we find a consecutive load, then we're done, otherwise, record all 6844 // nodes just above the top-level loads and token factors. 6845 while (!Queue.empty()) { 6846 SDNode *ChainNext = Queue.pop_back_val(); 6847 if (!Visited.insert(ChainNext)) 6848 continue; 6849 6850 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) { 6851 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG)) 6852 return true; 6853 6854 if (!Visited.count(ChainLD->getChain().getNode())) 6855 Queue.push_back(ChainLD->getChain().getNode()); 6856 } else if (ChainNext->getOpcode() == ISD::TokenFactor) { 6857 for (SDNode::op_iterator O = ChainNext->op_begin(), 6858 OE = ChainNext->op_end(); O != OE; ++O) 6859 if (!Visited.count(O->getNode())) 6860 Queue.push_back(O->getNode()); 6861 } else 6862 LoadRoots.insert(ChainNext); 6863 } 6864 6865 // Second, search down the chain, starting from the top-level nodes recorded 6866 // in the first phase. These top-level nodes are the nodes just above all 6867 // loads and token factors. Starting with their uses, recursively look though 6868 // all loads (just the chain uses) and token factors to find a consecutive 6869 // load. 6870 Visited.clear(); 6871 Queue.clear(); 6872 6873 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(), 6874 IE = LoadRoots.end(); I != IE; ++I) { 6875 Queue.push_back(*I); 6876 6877 while (!Queue.empty()) { 6878 SDNode *LoadRoot = Queue.pop_back_val(); 6879 if (!Visited.insert(LoadRoot)) 6880 continue; 6881 6882 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot)) 6883 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG)) 6884 return true; 6885 6886 for (SDNode::use_iterator UI = LoadRoot->use_begin(), 6887 UE = LoadRoot->use_end(); UI != UE; ++UI) 6888 if (((isa<LoadSDNode>(*UI) && 6889 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) || 6890 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI)) 6891 Queue.push_back(*UI); 6892 } 6893 } 6894 6895 return false; 6896} 6897 6898SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, 6899 DAGCombinerInfo &DCI) const { 6900 const TargetMachine &TM = getTargetMachine(); 6901 SelectionDAG &DAG = DCI.DAG; 6902 SDLoc dl(N); 6903 switch (N->getOpcode()) { 6904 default: break; 6905 case PPCISD::SHL: 6906 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 6907 if (C->isNullValue()) // 0 << V -> 0. 6908 return N->getOperand(0); 6909 } 6910 break; 6911 case PPCISD::SRL: 6912 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 6913 if (C->isNullValue()) // 0 >>u V -> 0. 6914 return N->getOperand(0); 6915 } 6916 break; 6917 case PPCISD::SRA: 6918 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 6919 if (C->isNullValue() || // 0 >>s V -> 0. 6920 C->isAllOnesValue()) // -1 >>s V -> -1. 6921 return N->getOperand(0); 6922 } 6923 break; 6924 case ISD::FDIV: { 6925 assert(TM.Options.UnsafeFPMath && 6926 "Reciprocal estimates require UnsafeFPMath"); 6927 6928 if (N->getOperand(1).getOpcode() == ISD::FSQRT) { 6929 SDValue RV = 6930 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI); 6931 if (RV.getNode() != 0) { 6932 DCI.AddToWorklist(RV.getNode()); 6933 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0), 6934 N->getOperand(0), RV); 6935 } 6936 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND && 6937 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) { 6938 SDValue RV = 6939 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0), 6940 DCI); 6941 if (RV.getNode() != 0) { 6942 DCI.AddToWorklist(RV.getNode()); 6943 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)), 6944 N->getValueType(0), RV); 6945 DCI.AddToWorklist(RV.getNode()); 6946 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0), 6947 N->getOperand(0), RV); 6948 } 6949 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND && 6950 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) { 6951 SDValue RV = 6952 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0), 6953 DCI); 6954 if (RV.getNode() != 0) { 6955 DCI.AddToWorklist(RV.getNode()); 6956 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)), 6957 N->getValueType(0), RV, 6958 N->getOperand(1).getOperand(1)); 6959 DCI.AddToWorklist(RV.getNode()); 6960 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0), 6961 N->getOperand(0), RV); 6962 } 6963 } 6964 6965 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI); 6966 if (RV.getNode() != 0) { 6967 DCI.AddToWorklist(RV.getNode()); 6968 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0), 6969 N->getOperand(0), RV); 6970 } 6971 6972 } 6973 break; 6974 case ISD::FSQRT: { 6975 assert(TM.Options.UnsafeFPMath && 6976 "Reciprocal estimates require UnsafeFPMath"); 6977 6978 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the 6979 // reciprocal sqrt. 6980 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI); 6981 if (RV.getNode() != 0) { 6982 DCI.AddToWorklist(RV.getNode()); 6983 RV = DAGCombineFastRecip(RV, DCI); 6984 if (RV.getNode() != 0) 6985 return RV; 6986 } 6987 6988 } 6989 break; 6990 case ISD::SINT_TO_FP: 6991 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 6992 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 6993 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 6994 // We allow the src/dst to be either f32/f64, but the intermediate 6995 // type must be i64. 6996 if (N->getOperand(0).getValueType() == MVT::i64 && 6997 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 6998 SDValue Val = N->getOperand(0).getOperand(0); 6999 if (Val.getValueType() == MVT::f32) { 7000 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 7001 DCI.AddToWorklist(Val.getNode()); 7002 } 7003 7004 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val); 7005 DCI.AddToWorklist(Val.getNode()); 7006 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val); 7007 DCI.AddToWorklist(Val.getNode()); 7008 if (N->getValueType(0) == MVT::f32) { 7009 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val, 7010 DAG.getIntPtrConstant(0)); 7011 DCI.AddToWorklist(Val.getNode()); 7012 } 7013 return Val; 7014 } else if (N->getOperand(0).getValueType() == MVT::i32) { 7015 // If the intermediate type is i32, we can avoid the load/store here 7016 // too. 7017 } 7018 } 7019 } 7020 break; 7021 case ISD::STORE: 7022 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 7023 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 7024 !cast<StoreSDNode>(N)->isTruncatingStore() && 7025 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 7026 N->getOperand(1).getValueType() == MVT::i32 && 7027 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 7028 SDValue Val = N->getOperand(1).getOperand(0); 7029 if (Val.getValueType() == MVT::f32) { 7030 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 7031 DCI.AddToWorklist(Val.getNode()); 7032 } 7033 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); 7034 DCI.AddToWorklist(Val.getNode()); 7035 7036 SDValue Ops[] = { 7037 N->getOperand(0), Val, N->getOperand(2), 7038 DAG.getValueType(N->getOperand(1).getValueType()) 7039 }; 7040 7041 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl, 7042 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops), 7043 cast<StoreSDNode>(N)->getMemoryVT(), 7044 cast<StoreSDNode>(N)->getMemOperand()); 7045 DCI.AddToWorklist(Val.getNode()); 7046 return Val; 7047 } 7048 7049 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 7050 if (cast<StoreSDNode>(N)->isUnindexed() && 7051 N->getOperand(1).getOpcode() == ISD::BSWAP && 7052 N->getOperand(1).getNode()->hasOneUse() && 7053 (N->getOperand(1).getValueType() == MVT::i32 || 7054 N->getOperand(1).getValueType() == MVT::i16 || 7055 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() && 7056 TM.getSubtarget<PPCSubtarget>().isPPC64() && 7057 N->getOperand(1).getValueType() == MVT::i64))) { 7058 SDValue BSwapOp = N->getOperand(1).getOperand(0); 7059 // Do an any-extend to 32-bits if this is a half-word input. 7060 if (BSwapOp.getValueType() == MVT::i16) 7061 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); 7062 7063 SDValue Ops[] = { 7064 N->getOperand(0), BSwapOp, N->getOperand(2), 7065 DAG.getValueType(N->getOperand(1).getValueType()) 7066 }; 7067 return 7068 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), 7069 Ops, array_lengthof(Ops), 7070 cast<StoreSDNode>(N)->getMemoryVT(), 7071 cast<StoreSDNode>(N)->getMemOperand()); 7072 } 7073 break; 7074 case ISD::LOAD: { 7075 LoadSDNode *LD = cast<LoadSDNode>(N); 7076 EVT VT = LD->getValueType(0); 7077 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 7078 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty); 7079 if (ISD::isNON_EXTLoad(N) && VT.isVector() && 7080 TM.getSubtarget<PPCSubtarget>().hasAltivec() && 7081 DCI.getDAGCombineLevel() == AfterLegalizeTypes && 7082 LD->getAlignment() < ABIAlignment) { 7083 // This is a type-legal unaligned Altivec load. 7084 SDValue Chain = LD->getChain(); 7085 SDValue Ptr = LD->getBasePtr(); 7086 7087 // This implements the loading of unaligned vectors as described in 7088 // the venerable Apple Velocity Engine overview. Specifically: 7089 // https://developer.apple.com/hardwaredrivers/ve/alignment.html 7090 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html 7091 // 7092 // The general idea is to expand a sequence of one or more unaligned 7093 // loads into a alignment-based permutation-control instruction (lvsl), 7094 // a series of regular vector loads (which always truncate their 7095 // input address to an aligned address), and a series of permutations. 7096 // The results of these permutations are the requested loaded values. 7097 // The trick is that the last "extra" load is not taken from the address 7098 // you might suspect (sizeof(vector) bytes after the last requested 7099 // load), but rather sizeof(vector) - 1 bytes after the last 7100 // requested vector. The point of this is to avoid a page fault if the 7101 // base address happend to be aligned. This works because if the base 7102 // address is aligned, then adding less than a full vector length will 7103 // cause the last vector in the sequence to be (re)loaded. Otherwise, 7104 // the next vector will be fetched as you might suspect was necessary. 7105 7106 // We might be able to reuse the permutation generation from 7107 // a different base address offset from this one by an aligned amount. 7108 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this 7109 // optimization later. 7110 SDValue PermCntl = BuildIntrinsicOp(Intrinsic::ppc_altivec_lvsl, Ptr, 7111 DAG, dl, MVT::v16i8); 7112 7113 // Refine the alignment of the original load (a "new" load created here 7114 // which was identical to the first except for the alignment would be 7115 // merged with the existing node regardless). 7116 MachineFunction &MF = DAG.getMachineFunction(); 7117 MachineMemOperand *MMO = 7118 MF.getMachineMemOperand(LD->getPointerInfo(), 7119 LD->getMemOperand()->getFlags(), 7120 LD->getMemoryVT().getStoreSize(), 7121 ABIAlignment); 7122 LD->refineAlignment(MMO); 7123 SDValue BaseLoad = SDValue(LD, 0); 7124 7125 // Note that the value of IncOffset (which is provided to the next 7126 // load's pointer info offset value, and thus used to calculate the 7127 // alignment), and the value of IncValue (which is actually used to 7128 // increment the pointer value) are different! This is because we 7129 // require the next load to appear to be aligned, even though it 7130 // is actually offset from the base pointer by a lesser amount. 7131 int IncOffset = VT.getSizeInBits() / 8; 7132 int IncValue = IncOffset; 7133 7134 // Walk (both up and down) the chain looking for another load at the real 7135 // (aligned) offset (the alignment of the other load does not matter in 7136 // this case). If found, then do not use the offset reduction trick, as 7137 // that will prevent the loads from being later combined (as they would 7138 // otherwise be duplicates). 7139 if (!findConsecutiveLoad(LD, DAG)) 7140 --IncValue; 7141 7142 SDValue Increment = DAG.getConstant(IncValue, getPointerTy()); 7143 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 7144 7145 SDValue ExtraLoad = 7146 DAG.getLoad(VT, dl, Chain, Ptr, 7147 LD->getPointerInfo().getWithOffset(IncOffset), 7148 LD->isVolatile(), LD->isNonTemporal(), 7149 LD->isInvariant(), ABIAlignment); 7150 7151 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 7152 BaseLoad.getValue(1), ExtraLoad.getValue(1)); 7153 7154 if (BaseLoad.getValueType() != MVT::v4i32) 7155 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad); 7156 7157 if (ExtraLoad.getValueType() != MVT::v4i32) 7158 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad); 7159 7160 SDValue Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm, 7161 BaseLoad, ExtraLoad, PermCntl, DAG, dl); 7162 7163 if (VT != MVT::v4i32) 7164 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm); 7165 7166 // Now we need to be really careful about how we update the users of the 7167 // original load. We cannot just call DCI.CombineTo (or 7168 // DAG.ReplaceAllUsesWith for that matter), because the load still has 7169 // uses created here (the permutation for example) that need to stay. 7170 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 7171 while (UI != UE) { 7172 SDUse &Use = UI.getUse(); 7173 SDNode *User = *UI; 7174 // Note: BaseLoad is checked here because it might not be N, but a 7175 // bitcast of N. 7176 if (User == Perm.getNode() || User == BaseLoad.getNode() || 7177 User == TF.getNode() || Use.getResNo() > 1) { 7178 ++UI; 7179 continue; 7180 } 7181 7182 SDValue To = Use.getResNo() ? TF : Perm; 7183 ++UI; 7184 7185 SmallVector<SDValue, 8> Ops; 7186 for (SDNode::op_iterator O = User->op_begin(), 7187 OE = User->op_end(); O != OE; ++O) { 7188 if (*O == Use) 7189 Ops.push_back(To); 7190 else 7191 Ops.push_back(*O); 7192 } 7193 7194 DAG.UpdateNodeOperands(User, Ops.data(), Ops.size()); 7195 } 7196 7197 return SDValue(N, 0); 7198 } 7199 } 7200 break; 7201 case ISD::INTRINSIC_WO_CHAIN: 7202 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == 7203 Intrinsic::ppc_altivec_lvsl && 7204 N->getOperand(1)->getOpcode() == ISD::ADD) { 7205 SDValue Add = N->getOperand(1); 7206 7207 if (DAG.MaskedValueIsZero(Add->getOperand(1), 7208 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext( 7209 Add.getValueType().getScalarType().getSizeInBits()))) { 7210 SDNode *BasePtr = Add->getOperand(0).getNode(); 7211 for (SDNode::use_iterator UI = BasePtr->use_begin(), 7212 UE = BasePtr->use_end(); UI != UE; ++UI) { 7213 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN && 7214 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() == 7215 Intrinsic::ppc_altivec_lvsl) { 7216 // We've found another LVSL, and this address if an aligned 7217 // multiple of that one. The results will be the same, so use the 7218 // one we've just found instead. 7219 7220 return SDValue(*UI, 0); 7221 } 7222 } 7223 } 7224 } 7225 case ISD::BSWAP: 7226 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 7227 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) && 7228 N->getOperand(0).hasOneUse() && 7229 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 || 7230 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() && 7231 TM.getSubtarget<PPCSubtarget>().isPPC64() && 7232 N->getValueType(0) == MVT::i64))) { 7233 SDValue Load = N->getOperand(0); 7234 LoadSDNode *LD = cast<LoadSDNode>(Load); 7235 // Create the byte-swapping load. 7236 SDValue Ops[] = { 7237 LD->getChain(), // Chain 7238 LD->getBasePtr(), // Ptr 7239 DAG.getValueType(N->getValueType(0)) // VT 7240 }; 7241 SDValue BSLoad = 7242 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl, 7243 DAG.getVTList(N->getValueType(0) == MVT::i64 ? 7244 MVT::i64 : MVT::i32, MVT::Other), 7245 Ops, 3, LD->getMemoryVT(), LD->getMemOperand()); 7246 7247 // If this is an i16 load, insert the truncate. 7248 SDValue ResVal = BSLoad; 7249 if (N->getValueType(0) == MVT::i16) 7250 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); 7251 7252 // First, combine the bswap away. This makes the value produced by the 7253 // load dead. 7254 DCI.CombineTo(N, ResVal); 7255 7256 // Next, combine the load away, we give it a bogus result value but a real 7257 // chain result. The result value is dead because the bswap is dead. 7258 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1)); 7259 7260 // Return N so it doesn't get rechecked! 7261 return SDValue(N, 0); 7262 } 7263 7264 break; 7265 case PPCISD::VCMP: { 7266 // If a VCMPo node already exists with exactly the same operands as this 7267 // node, use its result instead of this node (VCMPo computes both a CR6 and 7268 // a normal output). 7269 // 7270 if (!N->getOperand(0).hasOneUse() && 7271 !N->getOperand(1).hasOneUse() && 7272 !N->getOperand(2).hasOneUse()) { 7273 7274 // Scan all of the users of the LHS, looking for VCMPo's that match. 7275 SDNode *VCMPoNode = 0; 7276 7277 SDNode *LHSN = N->getOperand(0).getNode(); 7278 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 7279 UI != E; ++UI) 7280 if (UI->getOpcode() == PPCISD::VCMPo && 7281 UI->getOperand(1) == N->getOperand(1) && 7282 UI->getOperand(2) == N->getOperand(2) && 7283 UI->getOperand(0) == N->getOperand(0)) { 7284 VCMPoNode = *UI; 7285 break; 7286 } 7287 7288 // If there is no VCMPo node, or if the flag value has a single use, don't 7289 // transform this. 7290 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 7291 break; 7292 7293 // Look at the (necessarily single) use of the flag value. If it has a 7294 // chain, this transformation is more complex. Note that multiple things 7295 // could use the value result, which we should ignore. 7296 SDNode *FlagUser = 0; 7297 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 7298 FlagUser == 0; ++UI) { 7299 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 7300 SDNode *User = *UI; 7301 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 7302 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) { 7303 FlagUser = User; 7304 break; 7305 } 7306 } 7307 } 7308 7309 // If the user is a MFCR instruction, we know this is safe. Otherwise we 7310 // give up for right now. 7311 if (FlagUser->getOpcode() == PPCISD::MFCR) 7312 return SDValue(VCMPoNode, 0); 7313 } 7314 break; 7315 } 7316 case ISD::BR_CC: { 7317 // If this is a branch on an altivec predicate comparison, lower this so 7318 // that we don't have to do a MFCR: instead, branch directly on CR6. This 7319 // lowering is done pre-legalize, because the legalizer lowers the predicate 7320 // compare down to code that is difficult to reassemble. 7321 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 7322 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 7323 7324 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero 7325 // value. If so, pass-through the AND to get to the intrinsic. 7326 if (LHS.getOpcode() == ISD::AND && 7327 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN && 7328 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() == 7329 Intrinsic::ppc_is_decremented_ctr_nonzero && 7330 isa<ConstantSDNode>(LHS.getOperand(1)) && 7331 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()-> 7332 isZero()) 7333 LHS = LHS.getOperand(0); 7334 7335 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN && 7336 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 7337 Intrinsic::ppc_is_decremented_ctr_nonzero && 7338 isa<ConstantSDNode>(RHS)) { 7339 assert((CC == ISD::SETEQ || CC == ISD::SETNE) && 7340 "Counter decrement comparison is not EQ or NE"); 7341 7342 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue(); 7343 bool isBDNZ = (CC == ISD::SETEQ && Val) || 7344 (CC == ISD::SETNE && !Val); 7345 7346 // We now need to make the intrinsic dead (it cannot be instruction 7347 // selected). 7348 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0)); 7349 assert(LHS.getNode()->hasOneUse() && 7350 "Counter decrement has more than one use"); 7351 7352 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other, 7353 N->getOperand(0), N->getOperand(4)); 7354 } 7355 7356 int CompareOpc; 7357 bool isDot; 7358 7359 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 7360 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 7361 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 7362 assert(isDot && "Can't compare against a vector result!"); 7363 7364 // If this is a comparison against something other than 0/1, then we know 7365 // that the condition is never/always true. 7366 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue(); 7367 if (Val != 0 && Val != 1) { 7368 if (CC == ISD::SETEQ) // Cond never true, remove branch. 7369 return N->getOperand(0); 7370 // Always !=, turn it into an unconditional branch. 7371 return DAG.getNode(ISD::BR, dl, MVT::Other, 7372 N->getOperand(0), N->getOperand(4)); 7373 } 7374 7375 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 7376 7377 // Create the PPCISD altivec 'dot' comparison node. 7378 SDValue Ops[] = { 7379 LHS.getOperand(2), // LHS of compare 7380 LHS.getOperand(3), // RHS of compare 7381 DAG.getConstant(CompareOpc, MVT::i32) 7382 }; 7383 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue }; 7384 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 7385 7386 // Unpack the result based on how the target uses it. 7387 PPC::Predicate CompOpc; 7388 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) { 7389 default: // Can't happen, don't crash on invalid number though. 7390 case 0: // Branch on the value of the EQ bit of CR6. 7391 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 7392 break; 7393 case 1: // Branch on the inverted value of the EQ bit of CR6. 7394 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 7395 break; 7396 case 2: // Branch on the value of the LT bit of CR6. 7397 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 7398 break; 7399 case 3: // Branch on the inverted value of the LT bit of CR6. 7400 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 7401 break; 7402 } 7403 7404 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), 7405 DAG.getConstant(CompOpc, MVT::i32), 7406 DAG.getRegister(PPC::CR6, MVT::i32), 7407 N->getOperand(4), CompNode.getValue(1)); 7408 } 7409 break; 7410 } 7411 } 7412 7413 return SDValue(); 7414} 7415 7416//===----------------------------------------------------------------------===// 7417// Inline Assembly Support 7418//===----------------------------------------------------------------------===// 7419 7420void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 7421 APInt &KnownZero, 7422 APInt &KnownOne, 7423 const SelectionDAG &DAG, 7424 unsigned Depth) const { 7425 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); 7426 switch (Op.getOpcode()) { 7427 default: break; 7428 case PPCISD::LBRX: { 7429 // lhbrx is known to have the top bits cleared out. 7430 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) 7431 KnownZero = 0xFFFF0000; 7432 break; 7433 } 7434 case ISD::INTRINSIC_WO_CHAIN: { 7435 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) { 7436 default: break; 7437 case Intrinsic::ppc_altivec_vcmpbfp_p: 7438 case Intrinsic::ppc_altivec_vcmpeqfp_p: 7439 case Intrinsic::ppc_altivec_vcmpequb_p: 7440 case Intrinsic::ppc_altivec_vcmpequh_p: 7441 case Intrinsic::ppc_altivec_vcmpequw_p: 7442 case Intrinsic::ppc_altivec_vcmpgefp_p: 7443 case Intrinsic::ppc_altivec_vcmpgtfp_p: 7444 case Intrinsic::ppc_altivec_vcmpgtsb_p: 7445 case Intrinsic::ppc_altivec_vcmpgtsh_p: 7446 case Intrinsic::ppc_altivec_vcmpgtsw_p: 7447 case Intrinsic::ppc_altivec_vcmpgtub_p: 7448 case Intrinsic::ppc_altivec_vcmpgtuh_p: 7449 case Intrinsic::ppc_altivec_vcmpgtuw_p: 7450 KnownZero = ~1U; // All bits but the low one are known to be zero. 7451 break; 7452 } 7453 } 7454 } 7455} 7456 7457 7458/// getConstraintType - Given a constraint, return the type of 7459/// constraint it is for this target. 7460PPCTargetLowering::ConstraintType 7461PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 7462 if (Constraint.size() == 1) { 7463 switch (Constraint[0]) { 7464 default: break; 7465 case 'b': 7466 case 'r': 7467 case 'f': 7468 case 'v': 7469 case 'y': 7470 return C_RegisterClass; 7471 case 'Z': 7472 // FIXME: While Z does indicate a memory constraint, it specifically 7473 // indicates an r+r address (used in conjunction with the 'y' modifier 7474 // in the replacement string). Currently, we're forcing the base 7475 // register to be r0 in the asm printer (which is interpreted as zero) 7476 // and forming the complete address in the second register. This is 7477 // suboptimal. 7478 return C_Memory; 7479 } 7480 } 7481 return TargetLowering::getConstraintType(Constraint); 7482} 7483 7484/// Examine constraint type and operand type and determine a weight value. 7485/// This object must already have been set up with the operand type 7486/// and the current alternative constraint selected. 7487TargetLowering::ConstraintWeight 7488PPCTargetLowering::getSingleConstraintMatchWeight( 7489 AsmOperandInfo &info, const char *constraint) const { 7490 ConstraintWeight weight = CW_Invalid; 7491 Value *CallOperandVal = info.CallOperandVal; 7492 // If we don't have a value, we can't do a match, 7493 // but allow it at the lowest weight. 7494 if (CallOperandVal == NULL) 7495 return CW_Default; 7496 Type *type = CallOperandVal->getType(); 7497 // Look at the constraint type. 7498 switch (*constraint) { 7499 default: 7500 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 7501 break; 7502 case 'b': 7503 if (type->isIntegerTy()) 7504 weight = CW_Register; 7505 break; 7506 case 'f': 7507 if (type->isFloatTy()) 7508 weight = CW_Register; 7509 break; 7510 case 'd': 7511 if (type->isDoubleTy()) 7512 weight = CW_Register; 7513 break; 7514 case 'v': 7515 if (type->isVectorTy()) 7516 weight = CW_Register; 7517 break; 7518 case 'y': 7519 weight = CW_Register; 7520 break; 7521 case 'Z': 7522 weight = CW_Memory; 7523 break; 7524 } 7525 return weight; 7526} 7527 7528std::pair<unsigned, const TargetRegisterClass*> 7529PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 7530 EVT VT) const { 7531 if (Constraint.size() == 1) { 7532 // GCC RS6000 Constraint Letters 7533 switch (Constraint[0]) { 7534 case 'b': // R1-R31 7535 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 7536 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass); 7537 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass); 7538 case 'r': // R0-R31 7539 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 7540 return std::make_pair(0U, &PPC::G8RCRegClass); 7541 return std::make_pair(0U, &PPC::GPRCRegClass); 7542 case 'f': 7543 if (VT == MVT::f32 || VT == MVT::i32) 7544 return std::make_pair(0U, &PPC::F4RCRegClass); 7545 if (VT == MVT::f64 || VT == MVT::i64) 7546 return std::make_pair(0U, &PPC::F8RCRegClass); 7547 break; 7548 case 'v': 7549 return std::make_pair(0U, &PPC::VRRCRegClass); 7550 case 'y': // crrc 7551 return std::make_pair(0U, &PPC::CRRCRegClass); 7552 } 7553 } 7554 7555 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 7556} 7557 7558 7559/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 7560/// vector. If it is invalid, don't add anything to Ops. 7561void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 7562 std::string &Constraint, 7563 std::vector<SDValue>&Ops, 7564 SelectionDAG &DAG) const { 7565 SDValue Result(0,0); 7566 7567 // Only support length 1 constraints. 7568 if (Constraint.length() > 1) return; 7569 7570 char Letter = Constraint[0]; 7571 switch (Letter) { 7572 default: break; 7573 case 'I': 7574 case 'J': 7575 case 'K': 7576 case 'L': 7577 case 'M': 7578 case 'N': 7579 case 'O': 7580 case 'P': { 7581 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 7582 if (!CST) return; // Must be an immediate to match. 7583 unsigned Value = CST->getZExtValue(); 7584 switch (Letter) { 7585 default: llvm_unreachable("Unknown constraint letter!"); 7586 case 'I': // "I" is a signed 16-bit constant. 7587 if ((short)Value == (int)Value) 7588 Result = DAG.getTargetConstant(Value, Op.getValueType()); 7589 break; 7590 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 7591 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 7592 if ((short)Value == 0) 7593 Result = DAG.getTargetConstant(Value, Op.getValueType()); 7594 break; 7595 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 7596 if ((Value >> 16) == 0) 7597 Result = DAG.getTargetConstant(Value, Op.getValueType()); 7598 break; 7599 case 'M': // "M" is a constant that is greater than 31. 7600 if (Value > 31) 7601 Result = DAG.getTargetConstant(Value, Op.getValueType()); 7602 break; 7603 case 'N': // "N" is a positive constant that is an exact power of two. 7604 if ((int)Value > 0 && isPowerOf2_32(Value)) 7605 Result = DAG.getTargetConstant(Value, Op.getValueType()); 7606 break; 7607 case 'O': // "O" is the constant zero. 7608 if (Value == 0) 7609 Result = DAG.getTargetConstant(Value, Op.getValueType()); 7610 break; 7611 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 7612 if ((short)-Value == (int)-Value) 7613 Result = DAG.getTargetConstant(Value, Op.getValueType()); 7614 break; 7615 } 7616 break; 7617 } 7618 } 7619 7620 if (Result.getNode()) { 7621 Ops.push_back(Result); 7622 return; 7623 } 7624 7625 // Handle standard constraint letters. 7626 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 7627} 7628 7629// isLegalAddressingMode - Return true if the addressing mode represented 7630// by AM is legal for this target, for a load/store of the specified type. 7631bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 7632 Type *Ty) const { 7633 // FIXME: PPC does not allow r+i addressing modes for vectors! 7634 7635 // PPC allows a sign-extended 16-bit immediate field. 7636 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 7637 return false; 7638 7639 // No global is ever allowed as a base. 7640 if (AM.BaseGV) 7641 return false; 7642 7643 // PPC only support r+r, 7644 switch (AM.Scale) { 7645 case 0: // "r+i" or just "i", depending on HasBaseReg. 7646 break; 7647 case 1: 7648 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 7649 return false; 7650 // Otherwise we have r+r or r+i. 7651 break; 7652 case 2: 7653 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 7654 return false; 7655 // Allow 2*r as r+r. 7656 break; 7657 default: 7658 // No other scales are supported. 7659 return false; 7660 } 7661 7662 return true; 7663} 7664 7665SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, 7666 SelectionDAG &DAG) const { 7667 MachineFunction &MF = DAG.getMachineFunction(); 7668 MachineFrameInfo *MFI = MF.getFrameInfo(); 7669 MFI->setReturnAddressIsTaken(true); 7670 7671 SDLoc dl(Op); 7672 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7673 7674 // Make sure the function does not optimize away the store of the RA to 7675 // the stack. 7676 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 7677 FuncInfo->setLRStoreRequired(); 7678 bool isPPC64 = PPCSubTarget.isPPC64(); 7679 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 7680 7681 if (Depth > 0) { 7682 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 7683 SDValue Offset = 7684 7685 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI), 7686 isPPC64? MVT::i64 : MVT::i32); 7687 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 7688 DAG.getNode(ISD::ADD, dl, getPointerTy(), 7689 FrameAddr, Offset), 7690 MachinePointerInfo(), false, false, false, 0); 7691 } 7692 7693 // Just load the return address off the stack. 7694 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); 7695 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 7696 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 7697} 7698 7699SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, 7700 SelectionDAG &DAG) const { 7701 SDLoc dl(Op); 7702 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7703 7704 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 7705 bool isPPC64 = PtrVT == MVT::i64; 7706 7707 MachineFunction &MF = DAG.getMachineFunction(); 7708 MachineFrameInfo *MFI = MF.getFrameInfo(); 7709 MFI->setFrameAddressIsTaken(true); 7710 7711 // Naked functions never have a frame pointer, and so we use r1. For all 7712 // other functions, this decision must be delayed until during PEI. 7713 unsigned FrameReg; 7714 if (MF.getFunction()->getAttributes().hasAttribute( 7715 AttributeSet::FunctionIndex, Attribute::Naked)) 7716 FrameReg = isPPC64 ? PPC::X1 : PPC::R1; 7717 else 7718 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP; 7719 7720 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, 7721 PtrVT); 7722 while (Depth--) 7723 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(), 7724 FrameAddr, MachinePointerInfo(), false, false, 7725 false, 0); 7726 return FrameAddr; 7727} 7728 7729bool 7730PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 7731 // The PowerPC target isn't yet aware of offsets. 7732 return false; 7733} 7734 7735/// getOptimalMemOpType - Returns the target specific optimal type for load 7736/// and store operations as a result of memset, memcpy, and memmove 7737/// lowering. If DstAlign is zero that means it's safe to destination 7738/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 7739/// means there isn't a need to check it against alignment requirement, 7740/// probably because the source does not need to be loaded. If 'IsMemset' is 7741/// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 7742/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 7743/// source is constant so it does not need to be loaded. 7744/// It returns EVT::Other if the type should be determined using generic 7745/// target-independent logic. 7746EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, 7747 unsigned DstAlign, unsigned SrcAlign, 7748 bool IsMemset, bool ZeroMemset, 7749 bool MemcpyStrSrc, 7750 MachineFunction &MF) const { 7751 if (this->PPCSubTarget.isPPC64()) { 7752 return MVT::i64; 7753 } else { 7754 return MVT::i32; 7755 } 7756} 7757 7758bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT, 7759 bool *Fast) const { 7760 if (DisablePPCUnaligned) 7761 return false; 7762 7763 // PowerPC supports unaligned memory access for simple non-vector types. 7764 // Although accessing unaligned addresses is not as efficient as accessing 7765 // aligned addresses, it is generally more efficient than manual expansion, 7766 // and generally only traps for software emulation when crossing page 7767 // boundaries. 7768 7769 if (!VT.isSimple()) 7770 return false; 7771 7772 if (VT.getSimpleVT().isVector()) 7773 return false; 7774 7775 if (VT == MVT::ppcf128) 7776 return false; 7777 7778 if (Fast) 7779 *Fast = true; 7780 7781 return true; 7782} 7783 7784/// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than 7785/// a pair of mul and add instructions. fmuladd intrinsics will be expanded to 7786/// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd 7787/// is expanded to mul + add. 7788bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const { 7789 if (!VT.isSimple()) 7790 return false; 7791 7792 switch (VT.getSimpleVT().SimpleTy) { 7793 case MVT::f32: 7794 case MVT::f64: 7795 case MVT::v4f32: 7796 return true; 7797 default: 7798 break; 7799 } 7800 7801 return false; 7802} 7803 7804Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const { 7805 if (DisableILPPref) 7806 return TargetLowering::getSchedulingPreference(N); 7807 7808 return Sched::ILP; 7809} 7810 7811