PPCISelLowering.cpp revision 700ed80d3da5e98e05ceb90e9bfb66058581a6db
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "MCTargetDesc/PPCPredicates.h" 16#include "PPCMachineFunctionInfo.h" 17#include "PPCPerfectShuffle.h" 18#include "PPCTargetMachine.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/CodeGen/CallingConvLower.h" 21#include "llvm/CodeGen/MachineFrameInfo.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineInstrBuilder.h" 24#include "llvm/CodeGen/MachineRegisterInfo.h" 25#include "llvm/CodeGen/SelectionDAG.h" 26#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 27#include "llvm/IR/CallingConv.h" 28#include "llvm/IR/Constants.h" 29#include "llvm/IR/DerivedTypes.h" 30#include "llvm/IR/Function.h" 31#include "llvm/IR/Intrinsics.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/Target/TargetOptions.h" 37using namespace llvm; 38 39static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 40 CCValAssign::LocInfo &LocInfo, 41 ISD::ArgFlagsTy &ArgFlags, 42 CCState &State); 43static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 44 MVT &LocVT, 45 CCValAssign::LocInfo &LocInfo, 46 ISD::ArgFlagsTy &ArgFlags, 47 CCState &State); 48static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 49 MVT &LocVT, 50 CCValAssign::LocInfo &LocInfo, 51 ISD::ArgFlagsTy &ArgFlags, 52 CCState &State); 53 54static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc", 55cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden); 56 57static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref", 58cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden); 59 60static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) { 61 if (TM.getSubtargetImpl()->isDarwin()) 62 return new TargetLoweringObjectFileMachO(); 63 64 return new TargetLoweringObjectFileELF(); 65} 66 67PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) { 69 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>(); 70 71 setPow2DivIsCheap(); 72 73 // Use _setjmp/_longjmp instead of setjmp/longjmp. 74 setUseUnderscoreSetJmp(true); 75 setUseUnderscoreLongJmp(true); 76 77 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all 78 // arguments are at least 4/8 bytes aligned. 79 bool isPPC64 = Subtarget->isPPC64(); 80 setMinStackArgumentAlignment(isPPC64 ? 8:4); 81 82 // Set up the register classes. 83 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); 84 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); 85 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); 86 87 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 88 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 90 91 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 92 93 // PowerPC has pre-inc load and store's. 94 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 95 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 96 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 97 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 98 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 99 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 100 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 101 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 102 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 103 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 104 105 // This is used in the ppcf128->int sequence. Note it has different semantics 106 // from FP_ROUND: that rounds to nearest, this rounds to zero. 107 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 108 109 // We do not currently implement these libm ops for PowerPC. 110 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand); 111 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); 112 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand); 113 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand); 114 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand); 115 116 // PowerPC has no SREM/UREM instructions 117 setOperationAction(ISD::SREM, MVT::i32, Expand); 118 setOperationAction(ISD::UREM, MVT::i32, Expand); 119 setOperationAction(ISD::SREM, MVT::i64, Expand); 120 setOperationAction(ISD::UREM, MVT::i64, Expand); 121 122 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 123 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 124 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 125 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 126 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 127 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 128 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 129 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 130 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 131 132 // We don't support sin/cos/sqrt/fmod/pow 133 setOperationAction(ISD::FSIN , MVT::f64, Expand); 134 setOperationAction(ISD::FCOS , MVT::f64, Expand); 135 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 136 setOperationAction(ISD::FREM , MVT::f64, Expand); 137 setOperationAction(ISD::FPOW , MVT::f64, Expand); 138 setOperationAction(ISD::FMA , MVT::f64, Legal); 139 setOperationAction(ISD::FSIN , MVT::f32, Expand); 140 setOperationAction(ISD::FCOS , MVT::f32, Expand); 141 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 142 setOperationAction(ISD::FREM , MVT::f32, Expand); 143 setOperationAction(ISD::FPOW , MVT::f32, Expand); 144 setOperationAction(ISD::FMA , MVT::f32, Legal); 145 146 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 147 148 // If we're enabling GP optimizations, use hardware square root 149 if (!Subtarget->hasFSQRT()) { 150 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 151 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 152 } 153 154 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 155 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 156 157 // PowerPC does not have BSWAP, CTPOP or CTTZ 158 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 159 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 160 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 161 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 162 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 163 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 164 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 165 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 166 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 167 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 168 169 // PowerPC does not have ROTR 170 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 171 setOperationAction(ISD::ROTR, MVT::i64 , Expand); 172 173 // PowerPC does not have Select 174 setOperationAction(ISD::SELECT, MVT::i32, Expand); 175 setOperationAction(ISD::SELECT, MVT::i64, Expand); 176 setOperationAction(ISD::SELECT, MVT::f32, Expand); 177 setOperationAction(ISD::SELECT, MVT::f64, Expand); 178 179 // PowerPC wants to turn select_cc of FP into fsel when possible. 180 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 181 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 182 183 // PowerPC wants to optimize integer setcc a bit 184 setOperationAction(ISD::SETCC, MVT::i32, Custom); 185 186 // PowerPC does not have BRCOND which requires SetCC 187 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 188 189 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 190 191 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 192 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 193 194 // PowerPC does not have [U|S]INT_TO_FP 195 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 196 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 197 198 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 199 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 200 setOperationAction(ISD::BITCAST, MVT::i64, Expand); 201 setOperationAction(ISD::BITCAST, MVT::f64, Expand); 202 203 // We cannot sextinreg(i1). Expand to shifts. 204 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 205 206 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 207 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 208 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 209 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 210 211 212 // We want to legalize GlobalAddress and ConstantPool nodes into the 213 // appropriate instructions to materialize the address. 214 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 215 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 216 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 217 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 218 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 219 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 220 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 221 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 222 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 223 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 224 225 // TRAP is legal. 226 setOperationAction(ISD::TRAP, MVT::Other, Legal); 227 228 // TRAMPOLINE is custom lowered. 229 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 230 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 231 232 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 233 setOperationAction(ISD::VASTART , MVT::Other, Custom); 234 235 if (Subtarget->isSVR4ABI()) { 236 if (isPPC64) { 237 // VAARG always uses double-word chunks, so promote anything smaller. 238 setOperationAction(ISD::VAARG, MVT::i1, Promote); 239 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64); 240 setOperationAction(ISD::VAARG, MVT::i8, Promote); 241 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64); 242 setOperationAction(ISD::VAARG, MVT::i16, Promote); 243 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64); 244 setOperationAction(ISD::VAARG, MVT::i32, Promote); 245 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64); 246 setOperationAction(ISD::VAARG, MVT::Other, Expand); 247 } else { 248 // VAARG is custom lowered with the 32-bit SVR4 ABI. 249 setOperationAction(ISD::VAARG, MVT::Other, Custom); 250 setOperationAction(ISD::VAARG, MVT::i64, Custom); 251 } 252 } else 253 setOperationAction(ISD::VAARG, MVT::Other, Expand); 254 255 // Use the default implementation. 256 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 257 setOperationAction(ISD::VAEND , MVT::Other, Expand); 258 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 259 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 260 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 261 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 262 263 // We want to custom lower some of our intrinsics. 264 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 265 266 // Comparisons that require checking two conditions. 267 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 268 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); 269 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); 270 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); 271 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); 272 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); 273 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 274 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 275 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 276 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 277 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); 278 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); 279 280 if (Subtarget->has64BitSupport()) { 281 // They also have instructions for converting between i64 and fp. 282 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 283 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 284 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 285 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 286 // This is just the low 32 bits of a (signed) fp->i64 conversion. 287 // We cannot do this with Promote because i64 is not a legal type. 288 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 289 290 // FIXME: disable this lowered code. This generates 64-bit register values, 291 // and we don't model the fact that the top part is clobbered by calls. We 292 // need to flag these together so that the value isn't live across a call. 293 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 294 } else { 295 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 296 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 297 } 298 299 if (Subtarget->use64BitRegs()) { 300 // 64-bit PowerPC implementations can support i64 types directly 301 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); 302 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 303 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 304 // 64-bit PowerPC wants to expand i128 shifts itself. 305 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 306 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 307 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 308 } else { 309 // 32-bit PowerPC wants to expand i64 shifts itself. 310 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 311 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 312 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 313 } 314 315 if (Subtarget->hasAltivec()) { 316 // First set operation action for all vector types to expand. Then we 317 // will selectively turn on ones that can be effectively codegen'd. 318 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 319 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 320 MVT::SimpleValueType VT = (MVT::SimpleValueType)i; 321 322 // add/sub are legal for all supported vector VT's. 323 setOperationAction(ISD::ADD , VT, Legal); 324 setOperationAction(ISD::SUB , VT, Legal); 325 326 // We promote all shuffles to v16i8. 327 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 328 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 329 330 // We promote all non-typed operations to v4i32. 331 setOperationAction(ISD::AND , VT, Promote); 332 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 333 setOperationAction(ISD::OR , VT, Promote); 334 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 335 setOperationAction(ISD::XOR , VT, Promote); 336 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 337 setOperationAction(ISD::LOAD , VT, Promote); 338 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 339 setOperationAction(ISD::SELECT, VT, Promote); 340 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 341 setOperationAction(ISD::STORE, VT, Promote); 342 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 343 344 // No other operations are legal. 345 setOperationAction(ISD::MUL , VT, Expand); 346 setOperationAction(ISD::SDIV, VT, Expand); 347 setOperationAction(ISD::SREM, VT, Expand); 348 setOperationAction(ISD::UDIV, VT, Expand); 349 setOperationAction(ISD::UREM, VT, Expand); 350 setOperationAction(ISD::FDIV, VT, Expand); 351 setOperationAction(ISD::FNEG, VT, Expand); 352 setOperationAction(ISD::FSQRT, VT, Expand); 353 setOperationAction(ISD::FLOG, VT, Expand); 354 setOperationAction(ISD::FLOG10, VT, Expand); 355 setOperationAction(ISD::FLOG2, VT, Expand); 356 setOperationAction(ISD::FEXP, VT, Expand); 357 setOperationAction(ISD::FEXP2, VT, Expand); 358 setOperationAction(ISD::FSIN, VT, Expand); 359 setOperationAction(ISD::FCOS, VT, Expand); 360 setOperationAction(ISD::FABS, VT, Expand); 361 setOperationAction(ISD::FPOWI, VT, Expand); 362 setOperationAction(ISD::FFLOOR, VT, Expand); 363 setOperationAction(ISD::FCEIL, VT, Expand); 364 setOperationAction(ISD::FTRUNC, VT, Expand); 365 setOperationAction(ISD::FRINT, VT, Expand); 366 setOperationAction(ISD::FNEARBYINT, VT, Expand); 367 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); 368 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 369 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); 370 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 371 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 372 setOperationAction(ISD::UDIVREM, VT, Expand); 373 setOperationAction(ISD::SDIVREM, VT, Expand); 374 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); 375 setOperationAction(ISD::FPOW, VT, Expand); 376 setOperationAction(ISD::CTPOP, VT, Expand); 377 setOperationAction(ISD::CTLZ, VT, Expand); 378 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); 379 setOperationAction(ISD::CTTZ, VT, Expand); 380 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); 381 setOperationAction(ISD::VSELECT, VT, Expand); 382 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); 383 384 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 385 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) { 386 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j; 387 setTruncStoreAction(VT, InnerVT, Expand); 388 } 389 setLoadExtAction(ISD::SEXTLOAD, VT, Expand); 390 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand); 391 setLoadExtAction(ISD::EXTLOAD, VT, Expand); 392 } 393 394 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 395 // with merges, splats, etc. 396 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 397 398 setOperationAction(ISD::AND , MVT::v4i32, Legal); 399 setOperationAction(ISD::OR , MVT::v4i32, Legal); 400 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 401 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 402 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 403 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 404 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 405 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal); 406 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 407 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); 408 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); 409 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); 410 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); 411 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); 412 413 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); 414 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); 415 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); 416 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass); 417 418 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 419 setOperationAction(ISD::FMA, MVT::v4f32, Legal); 420 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 421 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 422 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 423 424 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 425 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 426 427 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 428 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 429 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 430 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 431 432 // Altivec does not contain unordered floating-point compare instructions 433 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand); 434 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand); 435 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand); 436 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand); 437 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand); 438 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand); 439 } 440 441 if (Subtarget->has64BitSupport()) { 442 setOperationAction(ISD::PREFETCH, MVT::Other, Legal); 443 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal); 444 } 445 446 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 447 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 448 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 449 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 450 451 setBooleanContents(ZeroOrOneBooleanContent); 452 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 453 454 if (isPPC64) { 455 setStackPointerRegisterToSaveRestore(PPC::X1); 456 setExceptionPointerRegister(PPC::X3); 457 setExceptionSelectorRegister(PPC::X4); 458 } else { 459 setStackPointerRegisterToSaveRestore(PPC::R1); 460 setExceptionPointerRegister(PPC::R3); 461 setExceptionSelectorRegister(PPC::R4); 462 } 463 464 // We have target-specific dag combine patterns for the following nodes: 465 setTargetDAGCombine(ISD::SINT_TO_FP); 466 setTargetDAGCombine(ISD::STORE); 467 setTargetDAGCombine(ISD::BR_CC); 468 setTargetDAGCombine(ISD::BSWAP); 469 470 // Darwin long double math library functions have $LDBL128 appended. 471 if (Subtarget->isDarwin()) { 472 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 473 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 474 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 475 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 476 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 477 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128"); 478 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128"); 479 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128"); 480 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128"); 481 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128"); 482 } 483 484 setMinFunctionAlignment(2); 485 if (PPCSubTarget.isDarwin()) 486 setPrefFunctionAlignment(4); 487 488 if (isPPC64 && Subtarget->isJITCodeModel()) 489 // Temporary workaround for the inability of PPC64 JIT to handle jump 490 // tables. 491 setSupportJumpTables(false); 492 493 setInsertFencesForAtomic(true); 494 495 setSchedulingPreference(Sched::Hybrid); 496 497 computeRegisterProperties(); 498 499 // The Freescale cores does better with aggressive inlining of memcpy and 500 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores). 501 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc || 502 Subtarget->getDarwinDirective() == PPC::DIR_E5500) { 503 MaxStoresPerMemset = 32; 504 MaxStoresPerMemsetOptSize = 16; 505 MaxStoresPerMemcpy = 32; 506 MaxStoresPerMemcpyOptSize = 8; 507 MaxStoresPerMemmove = 32; 508 MaxStoresPerMemmoveOptSize = 8; 509 510 setPrefFunctionAlignment(4); 511 BenefitFromCodePlacementOpt = true; 512 } 513} 514 515/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 516/// function arguments in the caller parameter area. 517unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const { 518 const TargetMachine &TM = getTargetMachine(); 519 // Darwin passes everything on 4 byte boundary. 520 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) 521 return 4; 522 523 // 16byte and wider vectors are passed on 16byte boundary. 524 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) 525 if (VTy->getBitWidth() >= 128) 526 return 16; 527 528 // The rest is 8 on PPC64 and 4 on PPC32 boundary. 529 if (PPCSubTarget.isPPC64()) 530 return 8; 531 532 return 4; 533} 534 535const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 536 switch (Opcode) { 537 default: return 0; 538 case PPCISD::FSEL: return "PPCISD::FSEL"; 539 case PPCISD::FCFID: return "PPCISD::FCFID"; 540 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 541 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 542 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 543 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 544 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 545 case PPCISD::VPERM: return "PPCISD::VPERM"; 546 case PPCISD::Hi: return "PPCISD::Hi"; 547 case PPCISD::Lo: return "PPCISD::Lo"; 548 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY"; 549 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE"; 550 case PPCISD::LOAD: return "PPCISD::LOAD"; 551 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC"; 552 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 553 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 554 case PPCISD::SRL: return "PPCISD::SRL"; 555 case PPCISD::SRA: return "PPCISD::SRA"; 556 case PPCISD::SHL: return "PPCISD::SHL"; 557 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 558 case PPCISD::STD_32: return "PPCISD::STD_32"; 559 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4"; 560 case PPCISD::CALL_NOP_SVR4: return "PPCISD::CALL_NOP_SVR4"; 561 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin"; 562 case PPCISD::NOP: return "PPCISD::NOP"; 563 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 564 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin"; 565 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4"; 566 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 567 case PPCISD::MFCR: return "PPCISD::MFCR"; 568 case PPCISD::VCMP: return "PPCISD::VCMP"; 569 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 570 case PPCISD::LBRX: return "PPCISD::LBRX"; 571 case PPCISD::STBRX: return "PPCISD::STBRX"; 572 case PPCISD::LARX: return "PPCISD::LARX"; 573 case PPCISD::STCX: return "PPCISD::STCX"; 574 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 575 case PPCISD::MFFS: return "PPCISD::MFFS"; 576 case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; 577 case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; 578 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 579 case PPCISD::MTFSF: return "PPCISD::MTFSF"; 580 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; 581 case PPCISD::CR6SET: return "PPCISD::CR6SET"; 582 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET"; 583 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA"; 584 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L"; 585 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L"; 586 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA"; 587 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L"; 588 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS"; 589 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA"; 590 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L"; 591 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR"; 592 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA"; 593 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L"; 594 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR"; 595 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA"; 596 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L"; 597 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT"; 598 } 599} 600 601EVT PPCTargetLowering::getSetCCResultType(EVT VT) const { 602 if (!VT.isVector()) 603 return MVT::i32; 604 return VT.changeVectorElementTypeToInteger(); 605} 606 607//===----------------------------------------------------------------------===// 608// Node matching predicates, for use by the tblgen matching code. 609//===----------------------------------------------------------------------===// 610 611/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 612static bool isFloatingPointZero(SDValue Op) { 613 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 614 return CFP->getValueAPF().isZero(); 615 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 616 // Maybe this has already been legalized into the constant pool? 617 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 618 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 619 return CFP->getValueAPF().isZero(); 620 } 621 return false; 622} 623 624/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 625/// true if Op is undef or if it matches the specified value. 626static bool isConstantOrUndef(int Op, int Val) { 627 return Op < 0 || Op == Val; 628} 629 630/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 631/// VPKUHUM instruction. 632bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 633 if (!isUnary) { 634 for (unsigned i = 0; i != 16; ++i) 635 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1)) 636 return false; 637 } else { 638 for (unsigned i = 0; i != 8; ++i) 639 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) || 640 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1)) 641 return false; 642 } 643 return true; 644} 645 646/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 647/// VPKUWUM instruction. 648bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 649 if (!isUnary) { 650 for (unsigned i = 0; i != 16; i += 2) 651 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 652 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3)) 653 return false; 654 } else { 655 for (unsigned i = 0; i != 8; i += 2) 656 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 657 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) || 658 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) || 659 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3)) 660 return false; 661 } 662 return true; 663} 664 665/// isVMerge - Common function, used to match vmrg* shuffles. 666/// 667static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, 668 unsigned LHSStart, unsigned RHSStart) { 669 assert(N->getValueType(0) == MVT::v16i8 && 670 "PPC only supports shuffles by bytes!"); 671 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 672 "Unsupported merge size!"); 673 674 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 675 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 676 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j), 677 LHSStart+j+i*UnitSize) || 678 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j), 679 RHSStart+j+i*UnitSize)) 680 return false; 681 } 682 return true; 683} 684 685/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 686/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 687bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 688 bool isUnary) { 689 if (!isUnary) 690 return isVMerge(N, UnitSize, 8, 24); 691 return isVMerge(N, UnitSize, 8, 8); 692} 693 694/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 695/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 696bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 697 bool isUnary) { 698 if (!isUnary) 699 return isVMerge(N, UnitSize, 0, 16); 700 return isVMerge(N, UnitSize, 0, 0); 701} 702 703 704/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 705/// amount, otherwise return -1. 706int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 707 assert(N->getValueType(0) == MVT::v16i8 && 708 "PPC only supports shuffles by bytes!"); 709 710 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 711 712 // Find the first non-undef value in the shuffle mask. 713 unsigned i; 714 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i) 715 /*search*/; 716 717 if (i == 16) return -1; // all undef. 718 719 // Otherwise, check to see if the rest of the elements are consecutively 720 // numbered from this value. 721 unsigned ShiftAmt = SVOp->getMaskElt(i); 722 if (ShiftAmt < i) return -1; 723 ShiftAmt -= i; 724 725 if (!isUnary) { 726 // Check the rest of the elements to see if they are consecutive. 727 for (++i; i != 16; ++i) 728 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) 729 return -1; 730 } else { 731 // Check the rest of the elements to see if they are consecutive. 732 for (++i; i != 16; ++i) 733 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) 734 return -1; 735 } 736 return ShiftAmt; 737} 738 739/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 740/// specifies a splat of a single element that is suitable for input to 741/// VSPLTB/VSPLTH/VSPLTW. 742bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { 743 assert(N->getValueType(0) == MVT::v16i8 && 744 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 745 746 // This is a splat operation if each element of the permute is the same, and 747 // if the value doesn't reference the second vector. 748 unsigned ElementBase = N->getMaskElt(0); 749 750 // FIXME: Handle UNDEF elements too! 751 if (ElementBase >= 16) 752 return false; 753 754 // Check that the indices are consecutive, in the case of a multi-byte element 755 // splatted with a v16i8 mask. 756 for (unsigned i = 1; i != EltSize; ++i) 757 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase)) 758 return false; 759 760 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 761 if (N->getMaskElt(i) < 0) continue; 762 for (unsigned j = 0; j != EltSize; ++j) 763 if (N->getMaskElt(i+j) != N->getMaskElt(j)) 764 return false; 765 } 766 return true; 767} 768 769/// isAllNegativeZeroVector - Returns true if all elements of build_vector 770/// are -0.0. 771bool PPC::isAllNegativeZeroVector(SDNode *N) { 772 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N); 773 774 APInt APVal, APUndef; 775 unsigned BitSize; 776 bool HasAnyUndefs; 777 778 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true)) 779 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 780 return CFP->getValueAPF().isNegZero(); 781 782 return false; 783} 784 785/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 786/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 787unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 788 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 789 assert(isSplatShuffleMask(SVOp, EltSize)); 790 return SVOp->getMaskElt(0) / EltSize; 791} 792 793/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 794/// by using a vspltis[bhw] instruction of the specified element size, return 795/// the constant being splatted. The ByteSize field indicates the number of 796/// bytes of each element [124] -> [bhw]. 797SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 798 SDValue OpVal(0, 0); 799 800 // If ByteSize of the splat is bigger than the element size of the 801 // build_vector, then we have a case where we are checking for a splat where 802 // multiple elements of the buildvector are folded together into a single 803 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 804 unsigned EltSize = 16/N->getNumOperands(); 805 if (EltSize < ByteSize) { 806 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 807 SDValue UniquedVals[4]; 808 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 809 810 // See if all of the elements in the buildvector agree across. 811 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 812 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 813 // If the element isn't a constant, bail fully out. 814 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue(); 815 816 817 if (UniquedVals[i&(Multiple-1)].getNode() == 0) 818 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 819 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 820 return SDValue(); // no match. 821 } 822 823 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 824 // either constant or undef values that are identical for each chunk. See 825 // if these chunks can form into a larger vspltis*. 826 827 // Check to see if all of the leading entries are either 0 or -1. If 828 // neither, then this won't fit into the immediate field. 829 bool LeadingZero = true; 830 bool LeadingOnes = true; 831 for (unsigned i = 0; i != Multiple-1; ++i) { 832 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs. 833 834 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 835 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 836 } 837 // Finally, check the least significant entry. 838 if (LeadingZero) { 839 if (UniquedVals[Multiple-1].getNode() == 0) 840 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 841 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue(); 842 if (Val < 16) 843 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 844 } 845 if (LeadingOnes) { 846 if (UniquedVals[Multiple-1].getNode() == 0) 847 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 848 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue(); 849 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 850 return DAG.getTargetConstant(Val, MVT::i32); 851 } 852 853 return SDValue(); 854 } 855 856 // Check to see if this buildvec has a single non-undef value in its elements. 857 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 858 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 859 if (OpVal.getNode() == 0) 860 OpVal = N->getOperand(i); 861 else if (OpVal != N->getOperand(i)) 862 return SDValue(); 863 } 864 865 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def. 866 867 unsigned ValSizeInBytes = EltSize; 868 uint64_t Value = 0; 869 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 870 Value = CN->getZExtValue(); 871 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 872 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 873 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 874 } 875 876 // If the splat value is larger than the element value, then we can never do 877 // this splat. The only case that we could fit the replicated bits into our 878 // immediate field for would be zero, and we prefer to use vxor for it. 879 if (ValSizeInBytes < ByteSize) return SDValue(); 880 881 // If the element value is larger than the splat value, cut it in half and 882 // check to see if the two halves are equal. Continue doing this until we 883 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 884 while (ValSizeInBytes > ByteSize) { 885 ValSizeInBytes >>= 1; 886 887 // If the top half equals the bottom half, we're still ok. 888 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 889 (Value & ((1 << (8*ValSizeInBytes))-1))) 890 return SDValue(); 891 } 892 893 // Properly sign extend the value. 894 int MaskVal = SignExtend32(Value, ByteSize * 8); 895 896 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 897 if (MaskVal == 0) return SDValue(); 898 899 // Finally, if this value fits in a 5 bit sext field, return it 900 if (SignExtend32<5>(MaskVal) == MaskVal) 901 return DAG.getTargetConstant(MaskVal, MVT::i32); 902 return SDValue(); 903} 904 905//===----------------------------------------------------------------------===// 906// Addressing Mode Selection 907//===----------------------------------------------------------------------===// 908 909/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 910/// or 64-bit immediate, and if the value can be accurately represented as a 911/// sign extension from a 16-bit value. If so, this returns true and the 912/// immediate. 913static bool isIntS16Immediate(SDNode *N, short &Imm) { 914 if (N->getOpcode() != ISD::Constant) 915 return false; 916 917 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 918 if (N->getValueType(0) == MVT::i32) 919 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 920 else 921 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 922} 923static bool isIntS16Immediate(SDValue Op, short &Imm) { 924 return isIntS16Immediate(Op.getNode(), Imm); 925} 926 927 928/// SelectAddressRegReg - Given the specified addressed, check to see if it 929/// can be represented as an indexed [r+r] operation. Returns false if it 930/// can be more efficiently represented with [r+imm]. 931bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, 932 SDValue &Index, 933 SelectionDAG &DAG) const { 934 short imm = 0; 935 if (N.getOpcode() == ISD::ADD) { 936 if (isIntS16Immediate(N.getOperand(1), imm)) 937 return false; // r+i 938 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 939 return false; // r+i 940 941 Base = N.getOperand(0); 942 Index = N.getOperand(1); 943 return true; 944 } else if (N.getOpcode() == ISD::OR) { 945 if (isIntS16Immediate(N.getOperand(1), imm)) 946 return false; // r+i can fold it if we can. 947 948 // If this is an or of disjoint bitfields, we can codegen this as an add 949 // (for better address arithmetic) if the LHS and RHS of the OR are provably 950 // disjoint. 951 APInt LHSKnownZero, LHSKnownOne; 952 APInt RHSKnownZero, RHSKnownOne; 953 DAG.ComputeMaskedBits(N.getOperand(0), 954 LHSKnownZero, LHSKnownOne); 955 956 if (LHSKnownZero.getBoolValue()) { 957 DAG.ComputeMaskedBits(N.getOperand(1), 958 RHSKnownZero, RHSKnownOne); 959 // If all of the bits are known zero on the LHS or RHS, the add won't 960 // carry. 961 if (~(LHSKnownZero | RHSKnownZero) == 0) { 962 Base = N.getOperand(0); 963 Index = N.getOperand(1); 964 return true; 965 } 966 } 967 } 968 969 return false; 970} 971 972/// Returns true if the address N can be represented by a base register plus 973/// a signed 16-bit displacement [r+imm], and if it is not better 974/// represented as reg+reg. 975bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, 976 SDValue &Base, 977 SelectionDAG &DAG) const { 978 // FIXME dl should come from parent load or store, not from address 979 DebugLoc dl = N.getDebugLoc(); 980 // If this can be more profitably realized as r+r, fail. 981 if (SelectAddressRegReg(N, Disp, Base, DAG)) 982 return false; 983 984 if (N.getOpcode() == ISD::ADD) { 985 short imm = 0; 986 if (isIntS16Immediate(N.getOperand(1), imm)) { 987 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 988 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 989 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 990 } else { 991 Base = N.getOperand(0); 992 } 993 return true; // [r+i] 994 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 995 // Match LOAD (ADD (X, Lo(G))). 996 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 997 && "Cannot handle constant offsets yet!"); 998 Disp = N.getOperand(1).getOperand(0); // The global address. 999 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 1000 Disp.getOpcode() == ISD::TargetGlobalTLSAddress || 1001 Disp.getOpcode() == ISD::TargetConstantPool || 1002 Disp.getOpcode() == ISD::TargetJumpTable); 1003 Base = N.getOperand(0); 1004 return true; // [&g+r] 1005 } 1006 } else if (N.getOpcode() == ISD::OR) { 1007 short imm = 0; 1008 if (isIntS16Immediate(N.getOperand(1), imm)) { 1009 // If this is an or of disjoint bitfields, we can codegen this as an add 1010 // (for better address arithmetic) if the LHS and RHS of the OR are 1011 // provably disjoint. 1012 APInt LHSKnownZero, LHSKnownOne; 1013 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne); 1014 1015 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 1016 // If all of the bits are known zero on the LHS or RHS, the add won't 1017 // carry. 1018 Base = N.getOperand(0); 1019 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 1020 return true; 1021 } 1022 } 1023 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 1024 // Loading from a constant address. 1025 1026 // If this address fits entirely in a 16-bit sext immediate field, codegen 1027 // this as "d, 0" 1028 short Imm; 1029 if (isIntS16Immediate(CN, Imm)) { 1030 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 1031 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 1032 CN->getValueType(0)); 1033 return true; 1034 } 1035 1036 // Handle 32-bit sext immediates with LIS + addr mode. 1037 if (CN->getValueType(0) == MVT::i32 || 1038 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 1039 int Addr = (int)CN->getZExtValue(); 1040 1041 // Otherwise, break this down into an LIS + disp. 1042 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 1043 1044 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 1045 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1046 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); 1047 return true; 1048 } 1049 } 1050 1051 Disp = DAG.getTargetConstant(0, getPointerTy()); 1052 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1053 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1054 else 1055 Base = N; 1056 return true; // [r+0] 1057} 1058 1059/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 1060/// represented as an indexed [r+r] operation. 1061bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, 1062 SDValue &Index, 1063 SelectionDAG &DAG) const { 1064 // Check to see if we can easily represent this as an [r+r] address. This 1065 // will fail if it thinks that the address is more profitably represented as 1066 // reg+imm, e.g. where imm = 0. 1067 if (SelectAddressRegReg(N, Base, Index, DAG)) 1068 return true; 1069 1070 // If the operand is an addition, always emit this as [r+r], since this is 1071 // better (for code size, and execution, as the memop does the add for free) 1072 // than emitting an explicit add. 1073 if (N.getOpcode() == ISD::ADD) { 1074 Base = N.getOperand(0); 1075 Index = N.getOperand(1); 1076 return true; 1077 } 1078 1079 // Otherwise, do it the hard way, using R0 as the base register. 1080 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 1081 N.getValueType()); 1082 Index = N; 1083 return true; 1084} 1085 1086/// SelectAddressRegImmShift - Returns true if the address N can be 1087/// represented by a base register plus a signed 14-bit displacement 1088/// [r+imm*4]. Suitable for use by STD and friends. 1089bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, 1090 SDValue &Base, 1091 SelectionDAG &DAG) const { 1092 // FIXME dl should come from the parent load or store, not the address 1093 DebugLoc dl = N.getDebugLoc(); 1094 // If this can be more profitably realized as r+r, fail. 1095 if (SelectAddressRegReg(N, Disp, Base, DAG)) 1096 return false; 1097 1098 if (N.getOpcode() == ISD::ADD) { 1099 short imm = 0; 1100 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 1101 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 1102 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 1103 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1104 } else { 1105 Base = N.getOperand(0); 1106 } 1107 return true; // [r+i] 1108 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 1109 // Match LOAD (ADD (X, Lo(G))). 1110 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 1111 && "Cannot handle constant offsets yet!"); 1112 Disp = N.getOperand(1).getOperand(0); // The global address. 1113 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 1114 Disp.getOpcode() == ISD::TargetConstantPool || 1115 Disp.getOpcode() == ISD::TargetJumpTable); 1116 Base = N.getOperand(0); 1117 return true; // [&g+r] 1118 } 1119 } else if (N.getOpcode() == ISD::OR) { 1120 short imm = 0; 1121 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 1122 // If this is an or of disjoint bitfields, we can codegen this as an add 1123 // (for better address arithmetic) if the LHS and RHS of the OR are 1124 // provably disjoint. 1125 APInt LHSKnownZero, LHSKnownOne; 1126 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne); 1127 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 1128 // If all of the bits are known zero on the LHS or RHS, the add won't 1129 // carry. 1130 Base = N.getOperand(0); 1131 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 1132 return true; 1133 } 1134 } 1135 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 1136 // Loading from a constant address. Verify low two bits are clear. 1137 if ((CN->getZExtValue() & 3) == 0) { 1138 // If this address fits entirely in a 14-bit sext immediate field, codegen 1139 // this as "d, 0" 1140 short Imm; 1141 if (isIntS16Immediate(CN, Imm)) { 1142 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 1143 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 1144 CN->getValueType(0)); 1145 return true; 1146 } 1147 1148 // Fold the low-part of 32-bit absolute addresses into addr mode. 1149 if (CN->getValueType(0) == MVT::i32 || 1150 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 1151 int Addr = (int)CN->getZExtValue(); 1152 1153 // Otherwise, break this down into an LIS + disp. 1154 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 1155 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 1156 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1157 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0); 1158 return true; 1159 } 1160 } 1161 } 1162 1163 Disp = DAG.getTargetConstant(0, getPointerTy()); 1164 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1165 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1166 else 1167 Base = N; 1168 return true; // [r+0] 1169} 1170 1171 1172/// getPreIndexedAddressParts - returns true by value, base pointer and 1173/// offset pointer and addressing mode by reference if the node's address 1174/// can be legally represented as pre-indexed load / store address. 1175bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1176 SDValue &Offset, 1177 ISD::MemIndexedMode &AM, 1178 SelectionDAG &DAG) const { 1179 if (DisablePPCPreinc) return false; 1180 1181 SDValue Ptr; 1182 EVT VT; 1183 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1184 Ptr = LD->getBasePtr(); 1185 VT = LD->getMemoryVT(); 1186 1187 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1188 Ptr = ST->getBasePtr(); 1189 VT = ST->getMemoryVT(); 1190 } else 1191 return false; 1192 1193 // PowerPC doesn't have preinc load/store instructions for vectors. 1194 if (VT.isVector()) 1195 return false; 1196 1197 if (SelectAddressRegReg(Ptr, Offset, Base, DAG)) { 1198 AM = ISD::PRE_INC; 1199 return true; 1200 } 1201 1202 // LDU/STU use reg+imm*4, others use reg+imm. 1203 if (VT != MVT::i64) { 1204 // reg + imm 1205 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 1206 return false; 1207 } else { 1208 // reg + imm * 4. 1209 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 1210 return false; 1211 } 1212 1213 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1214 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 1215 // sext i32 to i64 when addr mode is r+i. 1216 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 1217 LD->getExtensionType() == ISD::SEXTLOAD && 1218 isa<ConstantSDNode>(Offset)) 1219 return false; 1220 } 1221 1222 AM = ISD::PRE_INC; 1223 return true; 1224} 1225 1226//===----------------------------------------------------------------------===// 1227// LowerOperation implementation 1228//===----------------------------------------------------------------------===// 1229 1230/// GetLabelAccessInfo - Return true if we should reference labels using a 1231/// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags. 1232static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags, 1233 unsigned &LoOpFlags, const GlobalValue *GV = 0) { 1234 HiOpFlags = PPCII::MO_HA16; 1235 LoOpFlags = PPCII::MO_LO16; 1236 1237 // Don't use the pic base if not in PIC relocation model. Or if we are on a 1238 // non-darwin platform. We don't support PIC on other platforms yet. 1239 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ && 1240 TM.getSubtarget<PPCSubtarget>().isDarwin(); 1241 if (isPIC) { 1242 HiOpFlags |= PPCII::MO_PIC_FLAG; 1243 LoOpFlags |= PPCII::MO_PIC_FLAG; 1244 } 1245 1246 // If this is a reference to a global value that requires a non-lazy-ptr, make 1247 // sure that instruction lowering adds it. 1248 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) { 1249 HiOpFlags |= PPCII::MO_NLP_FLAG; 1250 LoOpFlags |= PPCII::MO_NLP_FLAG; 1251 1252 if (GV->hasHiddenVisibility()) { 1253 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; 1254 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; 1255 } 1256 } 1257 1258 return isPIC; 1259} 1260 1261static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, 1262 SelectionDAG &DAG) { 1263 EVT PtrVT = HiPart.getValueType(); 1264 SDValue Zero = DAG.getConstant(0, PtrVT); 1265 DebugLoc DL = HiPart.getDebugLoc(); 1266 1267 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero); 1268 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero); 1269 1270 // With PIC, the first instruction is actually "GR+hi(&G)". 1271 if (isPIC) 1272 Hi = DAG.getNode(ISD::ADD, DL, PtrVT, 1273 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi); 1274 1275 // Generate non-pic code that has direct accesses to the constant pool. 1276 // The address of the global is just (hi(&g)+lo(&g)). 1277 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1278} 1279 1280SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, 1281 SelectionDAG &DAG) const { 1282 EVT PtrVT = Op.getValueType(); 1283 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1284 const Constant *C = CP->getConstVal(); 1285 1286 // 64-bit SVR4 ABI code is always position-independent. 1287 // The actual address of the GlobalValue is stored in the TOC. 1288 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1289 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0); 1290 return DAG.getNode(PPCISD::TOC_ENTRY, CP->getDebugLoc(), MVT::i64, GA, 1291 DAG.getRegister(PPC::X2, MVT::i64)); 1292 } 1293 1294 unsigned MOHiFlag, MOLoFlag; 1295 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1296 SDValue CPIHi = 1297 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag); 1298 SDValue CPILo = 1299 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag); 1300 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG); 1301} 1302 1303SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 1304 EVT PtrVT = Op.getValueType(); 1305 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1306 1307 // 64-bit SVR4 ABI code is always position-independent. 1308 // The actual address of the GlobalValue is stored in the TOC. 1309 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1310 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1311 return DAG.getNode(PPCISD::TOC_ENTRY, JT->getDebugLoc(), MVT::i64, GA, 1312 DAG.getRegister(PPC::X2, MVT::i64)); 1313 } 1314 1315 unsigned MOHiFlag, MOLoFlag; 1316 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1317 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag); 1318 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag); 1319 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG); 1320} 1321 1322SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, 1323 SelectionDAG &DAG) const { 1324 EVT PtrVT = Op.getValueType(); 1325 1326 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1327 1328 unsigned MOHiFlag, MOLoFlag; 1329 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1330 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag); 1331 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag); 1332 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG); 1333} 1334 1335SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, 1336 SelectionDAG &DAG) const { 1337 1338 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1339 DebugLoc dl = GA->getDebugLoc(); 1340 const GlobalValue *GV = GA->getGlobal(); 1341 EVT PtrVT = getPointerTy(); 1342 bool is64bit = PPCSubTarget.isPPC64(); 1343 1344 TLSModel::Model Model = getTargetMachine().getTLSModel(GV); 1345 1346 if (Model == TLSModel::LocalExec) { 1347 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1348 PPCII::MO_TPREL16_HA); 1349 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1350 PPCII::MO_TPREL16_LO); 1351 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2, 1352 is64bit ? MVT::i64 : MVT::i32); 1353 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg); 1354 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi); 1355 } 1356 1357 if (!is64bit) 1358 llvm_unreachable("only local-exec is currently supported for ppc32"); 1359 1360 if (Model == TLSModel::InitialExec) { 1361 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0); 1362 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); 1363 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl, 1364 PtrVT, GOTReg, TGA); 1365 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl, 1366 PtrVT, TGA, TPOffsetHi); 1367 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGA); 1368 } 1369 1370 if (Model == TLSModel::GeneralDynamic) { 1371 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0); 1372 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); 1373 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT, 1374 GOTReg, TGA); 1375 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT, 1376 GOTEntryHi, TGA); 1377 1378 // We need a chain node, and don't have one handy. The underlying 1379 // call has no side effects, so using the function entry node 1380 // suffices. 1381 SDValue Chain = DAG.getEntryNode(); 1382 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry); 1383 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64); 1384 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl, 1385 PtrVT, ParmReg, TGA); 1386 // The return value from GET_TLS_ADDR really is in X3 already, but 1387 // some hacks are needed here to tie everything together. The extra 1388 // copies dissolve during subsequent transforms. 1389 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr); 1390 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT); 1391 } 1392 1393 if (Model == TLSModel::LocalDynamic) { 1394 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0); 1395 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); 1396 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT, 1397 GOTReg, TGA); 1398 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT, 1399 GOTEntryHi, TGA); 1400 1401 // We need a chain node, and don't have one handy. The underlying 1402 // call has no side effects, so using the function entry node 1403 // suffices. 1404 SDValue Chain = DAG.getEntryNode(); 1405 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry); 1406 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64); 1407 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl, 1408 PtrVT, ParmReg, TGA); 1409 // The return value from GET_TLSLD_ADDR really is in X3 already, but 1410 // some hacks are needed here to tie everything together. The extra 1411 // copies dissolve during subsequent transforms. 1412 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr); 1413 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT, 1414 Chain, ParmReg, TGA); 1415 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA); 1416 } 1417 1418 llvm_unreachable("Unknown TLS model!"); 1419} 1420 1421SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, 1422 SelectionDAG &DAG) const { 1423 EVT PtrVT = Op.getValueType(); 1424 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1425 DebugLoc DL = GSDN->getDebugLoc(); 1426 const GlobalValue *GV = GSDN->getGlobal(); 1427 1428 // 64-bit SVR4 ABI code is always position-independent. 1429 // The actual address of the GlobalValue is stored in the TOC. 1430 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1431 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset()); 1432 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA, 1433 DAG.getRegister(PPC::X2, MVT::i64)); 1434 } 1435 1436 unsigned MOHiFlag, MOLoFlag; 1437 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV); 1438 1439 SDValue GAHi = 1440 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag); 1441 SDValue GALo = 1442 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag); 1443 1444 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG); 1445 1446 // If the global reference is actually to a non-lazy-pointer, we have to do an 1447 // extra load to get the address of the global. 1448 if (MOHiFlag & PPCII::MO_NLP_FLAG) 1449 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(), 1450 false, false, false, 0); 1451 return Ptr; 1452} 1453 1454SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1455 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1456 DebugLoc dl = Op.getDebugLoc(); 1457 1458 // If we're comparing for equality to zero, expose the fact that this is 1459 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1460 // fold the new nodes. 1461 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1462 if (C->isNullValue() && CC == ISD::SETEQ) { 1463 EVT VT = Op.getOperand(0).getValueType(); 1464 SDValue Zext = Op.getOperand(0); 1465 if (VT.bitsLT(MVT::i32)) { 1466 VT = MVT::i32; 1467 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); 1468 } 1469 unsigned Log2b = Log2_32(VT.getSizeInBits()); 1470 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); 1471 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, 1472 DAG.getConstant(Log2b, MVT::i32)); 1473 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); 1474 } 1475 // Leave comparisons against 0 and -1 alone for now, since they're usually 1476 // optimized. FIXME: revisit this when we can custom lower all setcc 1477 // optimizations. 1478 if (C->isAllOnesValue() || C->isNullValue()) 1479 return SDValue(); 1480 } 1481 1482 // If we have an integer seteq/setne, turn it into a compare against zero 1483 // by xor'ing the rhs with the lhs, which is faster than setting a 1484 // condition register, reading it back out, and masking the correct bit. The 1485 // normal approach here uses sub to do this instead of xor. Using xor exposes 1486 // the result to other bit-twiddling opportunities. 1487 EVT LHSVT = Op.getOperand(0).getValueType(); 1488 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1489 EVT VT = Op.getValueType(); 1490 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), 1491 Op.getOperand(1)); 1492 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); 1493 } 1494 return SDValue(); 1495} 1496 1497SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, 1498 const PPCSubtarget &Subtarget) const { 1499 SDNode *Node = Op.getNode(); 1500 EVT VT = Node->getValueType(0); 1501 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1502 SDValue InChain = Node->getOperand(0); 1503 SDValue VAListPtr = Node->getOperand(1); 1504 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1505 DebugLoc dl = Node->getDebugLoc(); 1506 1507 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); 1508 1509 // gpr_index 1510 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, 1511 VAListPtr, MachinePointerInfo(SV), MVT::i8, 1512 false, false, 0); 1513 InChain = GprIndex.getValue(1); 1514 1515 if (VT == MVT::i64) { 1516 // Check if GprIndex is even 1517 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex, 1518 DAG.getConstant(1, MVT::i32)); 1519 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd, 1520 DAG.getConstant(0, MVT::i32), ISD::SETNE); 1521 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex, 1522 DAG.getConstant(1, MVT::i32)); 1523 // Align GprIndex to be even if it isn't 1524 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne, 1525 GprIndex); 1526 } 1527 1528 // fpr index is 1 byte after gpr 1529 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1530 DAG.getConstant(1, MVT::i32)); 1531 1532 // fpr 1533 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, 1534 FprPtr, MachinePointerInfo(SV), MVT::i8, 1535 false, false, 0); 1536 InChain = FprIndex.getValue(1); 1537 1538 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1539 DAG.getConstant(8, MVT::i32)); 1540 1541 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1542 DAG.getConstant(4, MVT::i32)); 1543 1544 // areas 1545 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, 1546 MachinePointerInfo(), false, false, 1547 false, 0); 1548 InChain = OverflowArea.getValue(1); 1549 1550 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, 1551 MachinePointerInfo(), false, false, 1552 false, 0); 1553 InChain = RegSaveArea.getValue(1); 1554 1555 // select overflow_area if index > 8 1556 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, 1557 DAG.getConstant(8, MVT::i32), ISD::SETLT); 1558 1559 // adjustment constant gpr_index * 4/8 1560 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32, 1561 VT.isInteger() ? GprIndex : FprIndex, 1562 DAG.getConstant(VT.isInteger() ? 4 : 8, 1563 MVT::i32)); 1564 1565 // OurReg = RegSaveArea + RegConstant 1566 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea, 1567 RegConstant); 1568 1569 // Floating types are 32 bytes into RegSaveArea 1570 if (VT.isFloatingPoint()) 1571 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg, 1572 DAG.getConstant(32, MVT::i32)); 1573 1574 // increase {f,g}pr_index by 1 (or 2 if VT is i64) 1575 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32, 1576 VT.isInteger() ? GprIndex : FprIndex, 1577 DAG.getConstant(VT == MVT::i64 ? 2 : 1, 1578 MVT::i32)); 1579 1580 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1, 1581 VT.isInteger() ? VAListPtr : FprPtr, 1582 MachinePointerInfo(SV), 1583 MVT::i8, false, false, 0); 1584 1585 // determine if we should load from reg_save_area or overflow_area 1586 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea); 1587 1588 // increase overflow_area by 4/8 if gpr/fpr > 8 1589 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea, 1590 DAG.getConstant(VT.isInteger() ? 4 : 8, 1591 MVT::i32)); 1592 1593 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea, 1594 OverflowAreaPlusN); 1595 1596 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, 1597 OverflowAreaPtr, 1598 MachinePointerInfo(), 1599 MVT::i32, false, false, 0); 1600 1601 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(), 1602 false, false, false, 0); 1603} 1604 1605SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 1606 SelectionDAG &DAG) const { 1607 return Op.getOperand(0); 1608} 1609 1610SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 1611 SelectionDAG &DAG) const { 1612 SDValue Chain = Op.getOperand(0); 1613 SDValue Trmp = Op.getOperand(1); // trampoline 1614 SDValue FPtr = Op.getOperand(2); // nested function 1615 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 1616 DebugLoc dl = Op.getDebugLoc(); 1617 1618 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1619 bool isPPC64 = (PtrVT == MVT::i64); 1620 Type *IntPtrTy = 1621 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType( 1622 *DAG.getContext()); 1623 1624 TargetLowering::ArgListTy Args; 1625 TargetLowering::ArgListEntry Entry; 1626 1627 Entry.Ty = IntPtrTy; 1628 Entry.Node = Trmp; Args.push_back(Entry); 1629 1630 // TrampSize == (isPPC64 ? 48 : 40); 1631 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, 1632 isPPC64 ? MVT::i64 : MVT::i32); 1633 Args.push_back(Entry); 1634 1635 Entry.Node = FPtr; Args.push_back(Entry); 1636 Entry.Node = Nest; Args.push_back(Entry); 1637 1638 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) 1639 TargetLowering::CallLoweringInfo CLI(Chain, 1640 Type::getVoidTy(*DAG.getContext()), 1641 false, false, false, false, 0, 1642 CallingConv::C, 1643 /*isTailCall=*/false, 1644 /*doesNotRet=*/false, 1645 /*isReturnValueUsed=*/true, 1646 DAG.getExternalSymbol("__trampoline_setup", PtrVT), 1647 Args, DAG, dl); 1648 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1649 1650 return CallResult.second; 1651} 1652 1653SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, 1654 const PPCSubtarget &Subtarget) const { 1655 MachineFunction &MF = DAG.getMachineFunction(); 1656 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1657 1658 DebugLoc dl = Op.getDebugLoc(); 1659 1660 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) { 1661 // vastart just stores the address of the VarArgsFrameIndex slot into the 1662 // memory location argument. 1663 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1664 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1665 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1666 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 1667 MachinePointerInfo(SV), 1668 false, false, 0); 1669 } 1670 1671 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct. 1672 // We suppose the given va_list is already allocated. 1673 // 1674 // typedef struct { 1675 // char gpr; /* index into the array of 8 GPRs 1676 // * stored in the register save area 1677 // * gpr=0 corresponds to r3, 1678 // * gpr=1 to r4, etc. 1679 // */ 1680 // char fpr; /* index into the array of 8 FPRs 1681 // * stored in the register save area 1682 // * fpr=0 corresponds to f1, 1683 // * fpr=1 to f2, etc. 1684 // */ 1685 // char *overflow_arg_area; 1686 // /* location on stack that holds 1687 // * the next overflow argument 1688 // */ 1689 // char *reg_save_area; 1690 // /* where r3:r10 and f1:f8 (if saved) 1691 // * are stored 1692 // */ 1693 // } va_list[1]; 1694 1695 1696 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32); 1697 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32); 1698 1699 1700 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1701 1702 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(), 1703 PtrVT); 1704 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1705 PtrVT); 1706 1707 uint64_t FrameOffset = PtrVT.getSizeInBits()/8; 1708 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1709 1710 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; 1711 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1712 1713 uint64_t FPROffset = 1; 1714 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1715 1716 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1717 1718 // Store first byte : number of int regs 1719 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, 1720 Op.getOperand(1), 1721 MachinePointerInfo(SV), 1722 MVT::i8, false, false, 0); 1723 uint64_t nextOffset = FPROffset; 1724 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), 1725 ConstFPROffset); 1726 1727 // Store second byte : number of float regs 1728 SDValue secondStore = 1729 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, 1730 MachinePointerInfo(SV, nextOffset), MVT::i8, 1731 false, false, 0); 1732 nextOffset += StackOffset; 1733 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); 1734 1735 // Store second word : arguments given on stack 1736 SDValue thirdStore = 1737 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, 1738 MachinePointerInfo(SV, nextOffset), 1739 false, false, 0); 1740 nextOffset += FrameOffset; 1741 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset); 1742 1743 // Store third word : arguments given in registers 1744 return DAG.getStore(thirdStore, dl, FR, nextPtr, 1745 MachinePointerInfo(SV, nextOffset), 1746 false, false, 0); 1747 1748} 1749 1750#include "PPCGenCallingConv.inc" 1751 1752static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 1753 CCValAssign::LocInfo &LocInfo, 1754 ISD::ArgFlagsTy &ArgFlags, 1755 CCState &State) { 1756 return true; 1757} 1758 1759static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 1760 MVT &LocVT, 1761 CCValAssign::LocInfo &LocInfo, 1762 ISD::ArgFlagsTy &ArgFlags, 1763 CCState &State) { 1764 static const uint16_t ArgRegs[] = { 1765 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1766 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1767 }; 1768 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1769 1770 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1771 1772 // Skip one register if the first unallocated register has an even register 1773 // number and there are still argument registers available which have not been 1774 // allocated yet. RegNum is actually an index into ArgRegs, which means we 1775 // need to skip a register if RegNum is odd. 1776 if (RegNum != NumArgRegs && RegNum % 2 == 1) { 1777 State.AllocateReg(ArgRegs[RegNum]); 1778 } 1779 1780 // Always return false here, as this function only makes sure that the first 1781 // unallocated register has an odd register number and does not actually 1782 // allocate a register for the current argument. 1783 return false; 1784} 1785 1786static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 1787 MVT &LocVT, 1788 CCValAssign::LocInfo &LocInfo, 1789 ISD::ArgFlagsTy &ArgFlags, 1790 CCState &State) { 1791 static const uint16_t ArgRegs[] = { 1792 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1793 PPC::F8 1794 }; 1795 1796 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1797 1798 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1799 1800 // If there is only one Floating-point register left we need to put both f64 1801 // values of a split ppc_fp128 value on the stack. 1802 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { 1803 State.AllocateReg(ArgRegs[RegNum]); 1804 } 1805 1806 // Always return false here, as this function only makes sure that the two f64 1807 // values a ppc_fp128 value is split into are both passed in registers or both 1808 // passed on the stack and does not actually allocate a register for the 1809 // current argument. 1810 return false; 1811} 1812 1813/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1814/// on Darwin. 1815static const uint16_t *GetFPR() { 1816 static const uint16_t FPR[] = { 1817 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1818 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1819 }; 1820 1821 return FPR; 1822} 1823 1824/// CalculateStackSlotSize - Calculates the size reserved for this argument on 1825/// the stack. 1826static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, 1827 unsigned PtrByteSize) { 1828 unsigned ArgSize = ArgVT.getSizeInBits()/8; 1829 if (Flags.isByVal()) 1830 ArgSize = Flags.getByValSize(); 1831 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1832 1833 return ArgSize; 1834} 1835 1836SDValue 1837PPCTargetLowering::LowerFormalArguments(SDValue Chain, 1838 CallingConv::ID CallConv, bool isVarArg, 1839 const SmallVectorImpl<ISD::InputArg> 1840 &Ins, 1841 DebugLoc dl, SelectionDAG &DAG, 1842 SmallVectorImpl<SDValue> &InVals) 1843 const { 1844 if (PPCSubTarget.isSVR4ABI()) { 1845 if (PPCSubTarget.isPPC64()) 1846 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins, 1847 dl, DAG, InVals); 1848 else 1849 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins, 1850 dl, DAG, InVals); 1851 } else { 1852 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, 1853 dl, DAG, InVals); 1854 } 1855} 1856 1857SDValue 1858PPCTargetLowering::LowerFormalArguments_32SVR4( 1859 SDValue Chain, 1860 CallingConv::ID CallConv, bool isVarArg, 1861 const SmallVectorImpl<ISD::InputArg> 1862 &Ins, 1863 DebugLoc dl, SelectionDAG &DAG, 1864 SmallVectorImpl<SDValue> &InVals) const { 1865 1866 // 32-bit SVR4 ABI Stack Frame Layout: 1867 // +-----------------------------------+ 1868 // +--> | Back chain | 1869 // | +-----------------------------------+ 1870 // | | Floating-point register save area | 1871 // | +-----------------------------------+ 1872 // | | General register save area | 1873 // | +-----------------------------------+ 1874 // | | CR save word | 1875 // | +-----------------------------------+ 1876 // | | VRSAVE save word | 1877 // | +-----------------------------------+ 1878 // | | Alignment padding | 1879 // | +-----------------------------------+ 1880 // | | Vector register save area | 1881 // | +-----------------------------------+ 1882 // | | Local variable space | 1883 // | +-----------------------------------+ 1884 // | | Parameter list area | 1885 // | +-----------------------------------+ 1886 // | | LR save word | 1887 // | +-----------------------------------+ 1888 // SP--> +--- | Back chain | 1889 // +-----------------------------------+ 1890 // 1891 // Specifications: 1892 // System V Application Binary Interface PowerPC Processor Supplement 1893 // AltiVec Technology Programming Interface Manual 1894 1895 MachineFunction &MF = DAG.getMachineFunction(); 1896 MachineFrameInfo *MFI = MF.getFrameInfo(); 1897 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1898 1899 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1900 // Potential tail calls could cause overwriting of argument stack slots. 1901 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt && 1902 (CallConv == CallingConv::Fast)); 1903 unsigned PtrByteSize = 4; 1904 1905 // Assign locations to all of the incoming arguments. 1906 SmallVector<CCValAssign, 16> ArgLocs; 1907 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1908 getTargetMachine(), ArgLocs, *DAG.getContext()); 1909 1910 // Reserve space for the linkage area on the stack. 1911 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); 1912 1913 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4); 1914 1915 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1916 CCValAssign &VA = ArgLocs[i]; 1917 1918 // Arguments stored in registers. 1919 if (VA.isRegLoc()) { 1920 const TargetRegisterClass *RC; 1921 EVT ValVT = VA.getValVT(); 1922 1923 switch (ValVT.getSimpleVT().SimpleTy) { 1924 default: 1925 llvm_unreachable("ValVT not supported by formal arguments Lowering"); 1926 case MVT::i32: 1927 RC = &PPC::GPRCRegClass; 1928 break; 1929 case MVT::f32: 1930 RC = &PPC::F4RCRegClass; 1931 break; 1932 case MVT::f64: 1933 RC = &PPC::F8RCRegClass; 1934 break; 1935 case MVT::v16i8: 1936 case MVT::v8i16: 1937 case MVT::v4i32: 1938 case MVT::v4f32: 1939 RC = &PPC::VRRCRegClass; 1940 break; 1941 } 1942 1943 // Transform the arguments stored in physical registers into virtual ones. 1944 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1945 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT); 1946 1947 InVals.push_back(ArgValue); 1948 } else { 1949 // Argument stored in memory. 1950 assert(VA.isMemLoc()); 1951 1952 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; 1953 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), 1954 isImmutable); 1955 1956 // Create load nodes to retrieve arguments from the stack. 1957 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1958 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 1959 MachinePointerInfo(), 1960 false, false, false, 0)); 1961 } 1962 } 1963 1964 // Assign locations to all of the incoming aggregate by value arguments. 1965 // Aggregates passed by value are stored in the local variable space of the 1966 // caller's stack frame, right above the parameter list area. 1967 SmallVector<CCValAssign, 16> ByValArgLocs; 1968 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1969 getTargetMachine(), ByValArgLocs, *DAG.getContext()); 1970 1971 // Reserve stack space for the allocations in CCInfo. 1972 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 1973 1974 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal); 1975 1976 // Area that is at least reserved in the caller of this function. 1977 unsigned MinReservedArea = CCByValInfo.getNextStackOffset(); 1978 1979 // Set the size that is at least reserved in caller of this function. Tail 1980 // call optimized function's reserved stack space needs to be aligned so that 1981 // taking the difference between two stack areas will result in an aligned 1982 // stack. 1983 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1984 1985 MinReservedArea = 1986 std::max(MinReservedArea, 1987 PPCFrameLowering::getMinCallFrameSize(false, false)); 1988 1989 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> 1990 getStackAlignment(); 1991 unsigned AlignMask = TargetAlign-1; 1992 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 1993 1994 FI->setMinReservedArea(MinReservedArea); 1995 1996 SmallVector<SDValue, 8> MemOps; 1997 1998 // If the function takes variable number of arguments, make a frame index for 1999 // the start of the first vararg value... for expansion of llvm.va_start. 2000 if (isVarArg) { 2001 static const uint16_t GPArgRegs[] = { 2002 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 2003 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 2004 }; 2005 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs); 2006 2007 static const uint16_t FPArgRegs[] = { 2008 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 2009 PPC::F8 2010 }; 2011 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs); 2012 2013 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs, 2014 NumGPArgRegs)); 2015 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs, 2016 NumFPArgRegs)); 2017 2018 // Make room for NumGPArgRegs and NumFPArgRegs. 2019 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 + 2020 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8; 2021 2022 FuncInfo->setVarArgsStackOffset( 2023 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2024 CCInfo.getNextStackOffset(), true)); 2025 2026 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false)); 2027 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2028 2029 // The fixed integer arguments of a variadic function are stored to the 2030 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing 2031 // the result of va_next. 2032 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) { 2033 // Get an existing live-in vreg, or add a new one. 2034 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); 2035 if (!VReg) 2036 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); 2037 2038 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2039 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2040 MachinePointerInfo(), false, false, 0); 2041 MemOps.push_back(Store); 2042 // Increment the address by four for the next argument to store 2043 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2044 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2045 } 2046 2047 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6 2048 // is set. 2049 // The double arguments are stored to the VarArgsFrameIndex 2050 // on the stack. 2051 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) { 2052 // Get an existing live-in vreg, or add a new one. 2053 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); 2054 if (!VReg) 2055 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); 2056 2057 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); 2058 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2059 MachinePointerInfo(), false, false, 0); 2060 MemOps.push_back(Store); 2061 // Increment the address by eight for the next argument to store 2062 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8, 2063 PtrVT); 2064 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2065 } 2066 } 2067 2068 if (!MemOps.empty()) 2069 Chain = DAG.getNode(ISD::TokenFactor, dl, 2070 MVT::Other, &MemOps[0], MemOps.size()); 2071 2072 return Chain; 2073} 2074 2075// PPC64 passes i8, i16, and i32 values in i64 registers. Promote 2076// value to MVT::i64 and then truncate to the correct register size. 2077SDValue 2078PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, 2079 SelectionDAG &DAG, SDValue ArgVal, 2080 DebugLoc dl) const { 2081 if (Flags.isSExt()) 2082 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, 2083 DAG.getValueType(ObjectVT)); 2084 else if (Flags.isZExt()) 2085 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, 2086 DAG.getValueType(ObjectVT)); 2087 2088 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); 2089} 2090 2091// Set the size that is at least reserved in caller of this function. Tail 2092// call optimized functions' reserved stack space needs to be aligned so that 2093// taking the difference between two stack areas will result in an aligned 2094// stack. 2095void 2096PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG, 2097 unsigned nAltivecParamsAtEnd, 2098 unsigned MinReservedArea, 2099 bool isPPC64) const { 2100 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2101 // Add the Altivec parameters at the end, if needed. 2102 if (nAltivecParamsAtEnd) { 2103 MinReservedArea = ((MinReservedArea+15)/16)*16; 2104 MinReservedArea += 16*nAltivecParamsAtEnd; 2105 } 2106 MinReservedArea = 2107 std::max(MinReservedArea, 2108 PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); 2109 unsigned TargetAlign 2110 = DAG.getMachineFunction().getTarget().getFrameLowering()-> 2111 getStackAlignment(); 2112 unsigned AlignMask = TargetAlign-1; 2113 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 2114 FI->setMinReservedArea(MinReservedArea); 2115} 2116 2117SDValue 2118PPCTargetLowering::LowerFormalArguments_64SVR4( 2119 SDValue Chain, 2120 CallingConv::ID CallConv, bool isVarArg, 2121 const SmallVectorImpl<ISD::InputArg> 2122 &Ins, 2123 DebugLoc dl, SelectionDAG &DAG, 2124 SmallVectorImpl<SDValue> &InVals) const { 2125 // TODO: add description of PPC stack frame format, or at least some docs. 2126 // 2127 MachineFunction &MF = DAG.getMachineFunction(); 2128 MachineFrameInfo *MFI = MF.getFrameInfo(); 2129 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 2130 2131 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2132 // Potential tail calls could cause overwriting of argument stack slots. 2133 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt && 2134 (CallConv == CallingConv::Fast)); 2135 unsigned PtrByteSize = 8; 2136 2137 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true); 2138 // Area that is at least reserved in caller of this function. 2139 unsigned MinReservedArea = ArgOffset; 2140 2141 static const uint16_t GPR[] = { 2142 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 2143 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 2144 }; 2145 2146 static const uint16_t *FPR = GetFPR(); 2147 2148 static const uint16_t VR[] = { 2149 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 2150 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 2151 }; 2152 2153 const unsigned Num_GPR_Regs = array_lengthof(GPR); 2154 const unsigned Num_FPR_Regs = 13; 2155 const unsigned Num_VR_Regs = array_lengthof(VR); 2156 2157 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 2158 2159 // Add DAG nodes to load the arguments or copy them out of registers. On 2160 // entry to a function on PPC, the arguments start after the linkage area, 2161 // although the first ones are often in registers. 2162 2163 SmallVector<SDValue, 8> MemOps; 2164 unsigned nAltivecParamsAtEnd = 0; 2165 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin(); 2166 unsigned CurArgIdx = 0; 2167 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { 2168 SDValue ArgVal; 2169 bool needsLoad = false; 2170 EVT ObjectVT = Ins[ArgNo].VT; 2171 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 2172 unsigned ArgSize = ObjSize; 2173 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 2174 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx); 2175 CurArgIdx = Ins[ArgNo].OrigArgIndex; 2176 2177 unsigned CurArgOffset = ArgOffset; 2178 2179 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 2180 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 2181 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 2182 if (isVarArg) { 2183 MinReservedArea = ((MinReservedArea+15)/16)*16; 2184 MinReservedArea += CalculateStackSlotSize(ObjectVT, 2185 Flags, 2186 PtrByteSize); 2187 } else 2188 nAltivecParamsAtEnd++; 2189 } else 2190 // Calculate min reserved area. 2191 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 2192 Flags, 2193 PtrByteSize); 2194 2195 // FIXME the codegen can be much improved in some cases. 2196 // We do not have to keep everything in memory. 2197 if (Flags.isByVal()) { 2198 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 2199 ObjSize = Flags.getByValSize(); 2200 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 2201 // Empty aggregate parameters do not take up registers. Examples: 2202 // struct { } a; 2203 // union { } b; 2204 // int c[0]; 2205 // etc. However, we have to provide a place-holder in InVals, so 2206 // pretend we have an 8-byte item at the current address for that 2207 // purpose. 2208 if (!ObjSize) { 2209 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2210 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2211 InVals.push_back(FIN); 2212 continue; 2213 } 2214 // All aggregates smaller than 8 bytes must be passed right-justified. 2215 if (ObjSize < PtrByteSize) 2216 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize); 2217 // The value of the object is its address. 2218 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true); 2219 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2220 InVals.push_back(FIN); 2221 2222 if (ObjSize < 8) { 2223 if (GPR_idx != Num_GPR_Regs) { 2224 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2225 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2226 SDValue Store; 2227 2228 if (ObjSize==1 || ObjSize==2 || ObjSize==4) { 2229 EVT ObjType = (ObjSize == 1 ? MVT::i8 : 2230 (ObjSize == 2 ? MVT::i16 : MVT::i32)); 2231 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 2232 MachinePointerInfo(FuncArg, CurArgOffset), 2233 ObjType, false, false, 0); 2234 } else { 2235 // For sizes that don't fit a truncating store (3, 5, 6, 7), 2236 // store the whole register as-is to the parameter save area 2237 // slot. The address of the parameter was already calculated 2238 // above (InVals.push_back(FIN)) to be the right-justified 2239 // offset within the slot. For this store, we need a new 2240 // frame index that points at the beginning of the slot. 2241 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2242 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2243 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2244 MachinePointerInfo(FuncArg, ArgOffset), 2245 false, false, 0); 2246 } 2247 2248 MemOps.push_back(Store); 2249 ++GPR_idx; 2250 } 2251 // Whether we copied from a register or not, advance the offset 2252 // into the parameter save area by a full doubleword. 2253 ArgOffset += PtrByteSize; 2254 continue; 2255 } 2256 2257 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 2258 // Store whatever pieces of the object are in registers 2259 // to memory. ArgOffset will be the address of the beginning 2260 // of the object. 2261 if (GPR_idx != Num_GPR_Regs) { 2262 unsigned VReg; 2263 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2264 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2265 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2266 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2267 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2268 MachinePointerInfo(FuncArg, ArgOffset), 2269 false, false, 0); 2270 MemOps.push_back(Store); 2271 ++GPR_idx; 2272 ArgOffset += PtrByteSize; 2273 } else { 2274 ArgOffset += ArgSize - j; 2275 break; 2276 } 2277 } 2278 continue; 2279 } 2280 2281 switch (ObjectVT.getSimpleVT().SimpleTy) { 2282 default: llvm_unreachable("Unhandled argument type!"); 2283 case MVT::i32: 2284 case MVT::i64: 2285 if (GPR_idx != Num_GPR_Regs) { 2286 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2287 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2288 2289 if (ObjectVT == MVT::i32) 2290 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 2291 // value to MVT::i64 and then truncate to the correct register size. 2292 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl); 2293 2294 ++GPR_idx; 2295 } else { 2296 needsLoad = true; 2297 ArgSize = PtrByteSize; 2298 } 2299 ArgOffset += 8; 2300 break; 2301 2302 case MVT::f32: 2303 case MVT::f64: 2304 // Every 8 bytes of argument space consumes one of the GPRs available for 2305 // argument passing. 2306 if (GPR_idx != Num_GPR_Regs) { 2307 ++GPR_idx; 2308 } 2309 if (FPR_idx != Num_FPR_Regs) { 2310 unsigned VReg; 2311 2312 if (ObjectVT == MVT::f32) 2313 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 2314 else 2315 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 2316 2317 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2318 ++FPR_idx; 2319 } else { 2320 needsLoad = true; 2321 ArgSize = PtrByteSize; 2322 } 2323 2324 ArgOffset += 8; 2325 break; 2326 case MVT::v4f32: 2327 case MVT::v4i32: 2328 case MVT::v8i16: 2329 case MVT::v16i8: 2330 // Note that vector arguments in registers don't reserve stack space, 2331 // except in varargs functions. 2332 if (VR_idx != Num_VR_Regs) { 2333 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 2334 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2335 if (isVarArg) { 2336 while ((ArgOffset % 16) != 0) { 2337 ArgOffset += PtrByteSize; 2338 if (GPR_idx != Num_GPR_Regs) 2339 GPR_idx++; 2340 } 2341 ArgOffset += 16; 2342 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 2343 } 2344 ++VR_idx; 2345 } else { 2346 // Vectors are aligned. 2347 ArgOffset = ((ArgOffset+15)/16)*16; 2348 CurArgOffset = ArgOffset; 2349 ArgOffset += 16; 2350 needsLoad = true; 2351 } 2352 break; 2353 } 2354 2355 // We need to load the argument to a virtual register if we determined 2356 // above that we ran out of physical registers of the appropriate type. 2357 if (needsLoad) { 2358 int FI = MFI->CreateFixedObject(ObjSize, 2359 CurArgOffset + (ArgSize - ObjSize), 2360 isImmutable); 2361 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2362 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), 2363 false, false, false, 0); 2364 } 2365 2366 InVals.push_back(ArgVal); 2367 } 2368 2369 // Set the size that is at least reserved in caller of this function. Tail 2370 // call optimized functions' reserved stack space needs to be aligned so that 2371 // taking the difference between two stack areas will result in an aligned 2372 // stack. 2373 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true); 2374 2375 // If the function takes variable number of arguments, make a frame index for 2376 // the start of the first vararg value... for expansion of llvm.va_start. 2377 if (isVarArg) { 2378 int Depth = ArgOffset; 2379 2380 FuncInfo->setVarArgsFrameIndex( 2381 MFI->CreateFixedObject(PtrByteSize, Depth, true)); 2382 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2383 2384 // If this function is vararg, store any remaining integer argument regs 2385 // to their spots on the stack so that they may be loaded by deferencing the 2386 // result of va_next. 2387 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2388 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2389 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2390 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2391 MachinePointerInfo(), false, false, 0); 2392 MemOps.push_back(Store); 2393 // Increment the address by four for the next argument to store 2394 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT); 2395 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2396 } 2397 } 2398 2399 if (!MemOps.empty()) 2400 Chain = DAG.getNode(ISD::TokenFactor, dl, 2401 MVT::Other, &MemOps[0], MemOps.size()); 2402 2403 return Chain; 2404} 2405 2406SDValue 2407PPCTargetLowering::LowerFormalArguments_Darwin( 2408 SDValue Chain, 2409 CallingConv::ID CallConv, bool isVarArg, 2410 const SmallVectorImpl<ISD::InputArg> 2411 &Ins, 2412 DebugLoc dl, SelectionDAG &DAG, 2413 SmallVectorImpl<SDValue> &InVals) const { 2414 // TODO: add description of PPC stack frame format, or at least some docs. 2415 // 2416 MachineFunction &MF = DAG.getMachineFunction(); 2417 MachineFrameInfo *MFI = MF.getFrameInfo(); 2418 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 2419 2420 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2421 bool isPPC64 = PtrVT == MVT::i64; 2422 // Potential tail calls could cause overwriting of argument stack slots. 2423 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt && 2424 (CallConv == CallingConv::Fast)); 2425 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2426 2427 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); 2428 // Area that is at least reserved in caller of this function. 2429 unsigned MinReservedArea = ArgOffset; 2430 2431 static const uint16_t GPR_32[] = { // 32-bit registers. 2432 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 2433 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 2434 }; 2435 static const uint16_t GPR_64[] = { // 64-bit registers. 2436 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 2437 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 2438 }; 2439 2440 static const uint16_t *FPR = GetFPR(); 2441 2442 static const uint16_t VR[] = { 2443 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 2444 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 2445 }; 2446 2447 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 2448 const unsigned Num_FPR_Regs = 13; 2449 const unsigned Num_VR_Regs = array_lengthof( VR); 2450 2451 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 2452 2453 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32; 2454 2455 // In 32-bit non-varargs functions, the stack space for vectors is after the 2456 // stack space for non-vectors. We do not use this space unless we have 2457 // too many vectors to fit in registers, something that only occurs in 2458 // constructed examples:), but we have to walk the arglist to figure 2459 // that out...for the pathological case, compute VecArgOffset as the 2460 // start of the vector parameter area. Computing VecArgOffset is the 2461 // entire point of the following loop. 2462 unsigned VecArgOffset = ArgOffset; 2463 if (!isVarArg && !isPPC64) { 2464 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; 2465 ++ArgNo) { 2466 EVT ObjectVT = Ins[ArgNo].VT; 2467 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 2468 2469 if (Flags.isByVal()) { 2470 // ObjSize is the true size, ArgSize rounded up to multiple of regs. 2471 unsigned ObjSize = Flags.getByValSize(); 2472 unsigned ArgSize = 2473 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 2474 VecArgOffset += ArgSize; 2475 continue; 2476 } 2477 2478 switch(ObjectVT.getSimpleVT().SimpleTy) { 2479 default: llvm_unreachable("Unhandled argument type!"); 2480 case MVT::i32: 2481 case MVT::f32: 2482 VecArgOffset += 4; 2483 break; 2484 case MVT::i64: // PPC64 2485 case MVT::f64: 2486 // FIXME: We are guaranteed to be !isPPC64 at this point. 2487 // Does MVT::i64 apply? 2488 VecArgOffset += 8; 2489 break; 2490 case MVT::v4f32: 2491 case MVT::v4i32: 2492 case MVT::v8i16: 2493 case MVT::v16i8: 2494 // Nothing to do, we're only looking at Nonvector args here. 2495 break; 2496 } 2497 } 2498 } 2499 // We've found where the vector parameter area in memory is. Skip the 2500 // first 12 parameters; these don't use that memory. 2501 VecArgOffset = ((VecArgOffset+15)/16)*16; 2502 VecArgOffset += 12*16; 2503 2504 // Add DAG nodes to load the arguments or copy them out of registers. On 2505 // entry to a function on PPC, the arguments start after the linkage area, 2506 // although the first ones are often in registers. 2507 2508 SmallVector<SDValue, 8> MemOps; 2509 unsigned nAltivecParamsAtEnd = 0; 2510 // FIXME: FuncArg and Ins[ArgNo] must reference the same argument. 2511 // When passing anonymous aggregates, this is currently not true. 2512 // See LowerFormalArguments_64SVR4 for a fix. 2513 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin(); 2514 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo, ++FuncArg) { 2515 SDValue ArgVal; 2516 bool needsLoad = false; 2517 EVT ObjectVT = Ins[ArgNo].VT; 2518 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 2519 unsigned ArgSize = ObjSize; 2520 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 2521 2522 unsigned CurArgOffset = ArgOffset; 2523 2524 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 2525 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 2526 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 2527 if (isVarArg || isPPC64) { 2528 MinReservedArea = ((MinReservedArea+15)/16)*16; 2529 MinReservedArea += CalculateStackSlotSize(ObjectVT, 2530 Flags, 2531 PtrByteSize); 2532 } else nAltivecParamsAtEnd++; 2533 } else 2534 // Calculate min reserved area. 2535 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 2536 Flags, 2537 PtrByteSize); 2538 2539 // FIXME the codegen can be much improved in some cases. 2540 // We do not have to keep everything in memory. 2541 if (Flags.isByVal()) { 2542 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 2543 ObjSize = Flags.getByValSize(); 2544 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 2545 // Objects of size 1 and 2 are right justified, everything else is 2546 // left justified. This means the memory address is adjusted forwards. 2547 if (ObjSize==1 || ObjSize==2) { 2548 CurArgOffset = CurArgOffset + (4 - ObjSize); 2549 } 2550 // The value of the object is its address. 2551 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true); 2552 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2553 InVals.push_back(FIN); 2554 if (ObjSize==1 || ObjSize==2) { 2555 if (GPR_idx != Num_GPR_Regs) { 2556 unsigned VReg; 2557 if (isPPC64) 2558 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2559 else 2560 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2561 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2562 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16; 2563 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 2564 MachinePointerInfo(FuncArg, 2565 CurArgOffset), 2566 ObjType, false, false, 0); 2567 MemOps.push_back(Store); 2568 ++GPR_idx; 2569 } 2570 2571 ArgOffset += PtrByteSize; 2572 2573 continue; 2574 } 2575 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 2576 // Store whatever pieces of the object are in registers 2577 // to memory. ArgOffset will be the address of the beginning 2578 // of the object. 2579 if (GPR_idx != Num_GPR_Regs) { 2580 unsigned VReg; 2581 if (isPPC64) 2582 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2583 else 2584 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2585 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2586 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2587 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2588 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2589 MachinePointerInfo(FuncArg, ArgOffset), 2590 false, false, 0); 2591 MemOps.push_back(Store); 2592 ++GPR_idx; 2593 ArgOffset += PtrByteSize; 2594 } else { 2595 ArgOffset += ArgSize - (ArgOffset-CurArgOffset); 2596 break; 2597 } 2598 } 2599 continue; 2600 } 2601 2602 switch (ObjectVT.getSimpleVT().SimpleTy) { 2603 default: llvm_unreachable("Unhandled argument type!"); 2604 case MVT::i32: 2605 if (!isPPC64) { 2606 if (GPR_idx != Num_GPR_Regs) { 2607 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2608 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2609 ++GPR_idx; 2610 } else { 2611 needsLoad = true; 2612 ArgSize = PtrByteSize; 2613 } 2614 // All int arguments reserve stack space in the Darwin ABI. 2615 ArgOffset += PtrByteSize; 2616 break; 2617 } 2618 // FALLTHROUGH 2619 case MVT::i64: // PPC64 2620 if (GPR_idx != Num_GPR_Regs) { 2621 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2622 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2623 2624 if (ObjectVT == MVT::i32) 2625 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 2626 // value to MVT::i64 and then truncate to the correct register size. 2627 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl); 2628 2629 ++GPR_idx; 2630 } else { 2631 needsLoad = true; 2632 ArgSize = PtrByteSize; 2633 } 2634 // All int arguments reserve stack space in the Darwin ABI. 2635 ArgOffset += 8; 2636 break; 2637 2638 case MVT::f32: 2639 case MVT::f64: 2640 // Every 4 bytes of argument space consumes one of the GPRs available for 2641 // argument passing. 2642 if (GPR_idx != Num_GPR_Regs) { 2643 ++GPR_idx; 2644 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 2645 ++GPR_idx; 2646 } 2647 if (FPR_idx != Num_FPR_Regs) { 2648 unsigned VReg; 2649 2650 if (ObjectVT == MVT::f32) 2651 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 2652 else 2653 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 2654 2655 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2656 ++FPR_idx; 2657 } else { 2658 needsLoad = true; 2659 } 2660 2661 // All FP arguments reserve stack space in the Darwin ABI. 2662 ArgOffset += isPPC64 ? 8 : ObjSize; 2663 break; 2664 case MVT::v4f32: 2665 case MVT::v4i32: 2666 case MVT::v8i16: 2667 case MVT::v16i8: 2668 // Note that vector arguments in registers don't reserve stack space, 2669 // except in varargs functions. 2670 if (VR_idx != Num_VR_Regs) { 2671 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 2672 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2673 if (isVarArg) { 2674 while ((ArgOffset % 16) != 0) { 2675 ArgOffset += PtrByteSize; 2676 if (GPR_idx != Num_GPR_Regs) 2677 GPR_idx++; 2678 } 2679 ArgOffset += 16; 2680 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 2681 } 2682 ++VR_idx; 2683 } else { 2684 if (!isVarArg && !isPPC64) { 2685 // Vectors go after all the nonvectors. 2686 CurArgOffset = VecArgOffset; 2687 VecArgOffset += 16; 2688 } else { 2689 // Vectors are aligned. 2690 ArgOffset = ((ArgOffset+15)/16)*16; 2691 CurArgOffset = ArgOffset; 2692 ArgOffset += 16; 2693 } 2694 needsLoad = true; 2695 } 2696 break; 2697 } 2698 2699 // We need to load the argument to a virtual register if we determined above 2700 // that we ran out of physical registers of the appropriate type. 2701 if (needsLoad) { 2702 int FI = MFI->CreateFixedObject(ObjSize, 2703 CurArgOffset + (ArgSize - ObjSize), 2704 isImmutable); 2705 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2706 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), 2707 false, false, false, 0); 2708 } 2709 2710 InVals.push_back(ArgVal); 2711 } 2712 2713 // Set the size that is at least reserved in caller of this function. Tail 2714 // call optimized functions' reserved stack space needs to be aligned so that 2715 // taking the difference between two stack areas will result in an aligned 2716 // stack. 2717 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64); 2718 2719 // If the function takes variable number of arguments, make a frame index for 2720 // the start of the first vararg value... for expansion of llvm.va_start. 2721 if (isVarArg) { 2722 int Depth = ArgOffset; 2723 2724 FuncInfo->setVarArgsFrameIndex( 2725 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2726 Depth, true)); 2727 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2728 2729 // If this function is vararg, store any remaining integer argument regs 2730 // to their spots on the stack so that they may be loaded by deferencing the 2731 // result of va_next. 2732 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2733 unsigned VReg; 2734 2735 if (isPPC64) 2736 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2737 else 2738 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2739 2740 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2741 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2742 MachinePointerInfo(), false, false, 0); 2743 MemOps.push_back(Store); 2744 // Increment the address by four for the next argument to store 2745 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2746 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2747 } 2748 } 2749 2750 if (!MemOps.empty()) 2751 Chain = DAG.getNode(ISD::TokenFactor, dl, 2752 MVT::Other, &MemOps[0], MemOps.size()); 2753 2754 return Chain; 2755} 2756 2757/// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus 2758/// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI. 2759static unsigned 2760CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, 2761 bool isPPC64, 2762 bool isVarArg, 2763 unsigned CC, 2764 const SmallVectorImpl<ISD::OutputArg> 2765 &Outs, 2766 const SmallVectorImpl<SDValue> &OutVals, 2767 unsigned &nAltivecParamsAtEnd) { 2768 // Count how many bytes are to be pushed on the stack, including the linkage 2769 // area, and parameter passing area. We start with 24/48 bytes, which is 2770 // prereserved space for [SP][CR][LR][3 x unused]. 2771 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true); 2772 unsigned NumOps = Outs.size(); 2773 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2774 2775 // Add up all the space actually used. 2776 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually 2777 // they all go in registers, but we must reserve stack space for them for 2778 // possible use by the caller. In varargs or 64-bit calls, parameters are 2779 // assigned stack space in order, with padding so Altivec parameters are 2780 // 16-byte aligned. 2781 nAltivecParamsAtEnd = 0; 2782 for (unsigned i = 0; i != NumOps; ++i) { 2783 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2784 EVT ArgVT = Outs[i].VT; 2785 // Varargs Altivec parameters are padded to a 16 byte boundary. 2786 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 2787 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { 2788 if (!isVarArg && !isPPC64) { 2789 // Non-varargs Altivec parameters go after all the non-Altivec 2790 // parameters; handle those later so we know how much padding we need. 2791 nAltivecParamsAtEnd++; 2792 continue; 2793 } 2794 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. 2795 NumBytes = ((NumBytes+15)/16)*16; 2796 } 2797 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); 2798 } 2799 2800 // Allow for Altivec parameters at the end, if needed. 2801 if (nAltivecParamsAtEnd) { 2802 NumBytes = ((NumBytes+15)/16)*16; 2803 NumBytes += 16*nAltivecParamsAtEnd; 2804 } 2805 2806 // The prolog code of the callee may store up to 8 GPR argument registers to 2807 // the stack, allowing va_start to index over them in memory if its varargs. 2808 // Because we cannot tell if this is needed on the caller side, we have to 2809 // conservatively assume that it is needed. As such, make sure we have at 2810 // least enough stack space for the caller to store the 8 GPRs. 2811 NumBytes = std::max(NumBytes, 2812 PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); 2813 2814 // Tail call needs the stack to be aligned. 2815 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){ 2816 unsigned TargetAlign = DAG.getMachineFunction().getTarget(). 2817 getFrameLowering()->getStackAlignment(); 2818 unsigned AlignMask = TargetAlign-1; 2819 NumBytes = (NumBytes + AlignMask) & ~AlignMask; 2820 } 2821 2822 return NumBytes; 2823} 2824 2825/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be 2826/// adjusted to accommodate the arguments for the tailcall. 2827static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, 2828 unsigned ParamSize) { 2829 2830 if (!isTailCall) return 0; 2831 2832 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>(); 2833 unsigned CallerMinReservedArea = FI->getMinReservedArea(); 2834 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize; 2835 // Remember only if the new adjustement is bigger. 2836 if (SPDiff < FI->getTailCallSPDelta()) 2837 FI->setTailCallSPDelta(SPDiff); 2838 2839 return SPDiff; 2840} 2841 2842/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2843/// for tail call optimization. Targets which want to do tail call 2844/// optimization should implement this function. 2845bool 2846PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2847 CallingConv::ID CalleeCC, 2848 bool isVarArg, 2849 const SmallVectorImpl<ISD::InputArg> &Ins, 2850 SelectionDAG& DAG) const { 2851 if (!getTargetMachine().Options.GuaranteedTailCallOpt) 2852 return false; 2853 2854 // Variable argument functions are not supported. 2855 if (isVarArg) 2856 return false; 2857 2858 MachineFunction &MF = DAG.getMachineFunction(); 2859 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv(); 2860 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 2861 // Functions containing by val parameters are not supported. 2862 for (unsigned i = 0; i != Ins.size(); i++) { 2863 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2864 if (Flags.isByVal()) return false; 2865 } 2866 2867 // Non PIC/GOT tail calls are supported. 2868 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 2869 return true; 2870 2871 // At the moment we can only do local tail calls (in same module, hidden 2872 // or protected) if we are generating PIC. 2873 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2874 return G->getGlobal()->hasHiddenVisibility() 2875 || G->getGlobal()->hasProtectedVisibility(); 2876 } 2877 2878 return false; 2879} 2880 2881/// isCallCompatibleAddress - Return the immediate to use if the specified 2882/// 32-bit value is representable in the immediate field of a BxA instruction. 2883static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { 2884 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2885 if (!C) return 0; 2886 2887 int Addr = C->getZExtValue(); 2888 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 2889 SignExtend32<26>(Addr) != Addr) 2890 return 0; // Top 6 bits have to be sext of immediate. 2891 2892 return DAG.getConstant((int)C->getZExtValue() >> 2, 2893 DAG.getTargetLoweringInfo().getPointerTy()).getNode(); 2894} 2895 2896namespace { 2897 2898struct TailCallArgumentInfo { 2899 SDValue Arg; 2900 SDValue FrameIdxOp; 2901 int FrameIdx; 2902 2903 TailCallArgumentInfo() : FrameIdx(0) {} 2904}; 2905 2906} 2907 2908/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. 2909static void 2910StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, 2911 SDValue Chain, 2912 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, 2913 SmallVector<SDValue, 8> &MemOpChains, 2914 DebugLoc dl) { 2915 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { 2916 SDValue Arg = TailCallArgs[i].Arg; 2917 SDValue FIN = TailCallArgs[i].FrameIdxOp; 2918 int FI = TailCallArgs[i].FrameIdx; 2919 // Store relative to framepointer. 2920 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN, 2921 MachinePointerInfo::getFixedStack(FI), 2922 false, false, 0)); 2923 } 2924} 2925 2926/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to 2927/// the appropriate stack slot for the tail call optimized function call. 2928static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, 2929 MachineFunction &MF, 2930 SDValue Chain, 2931 SDValue OldRetAddr, 2932 SDValue OldFP, 2933 int SPDiff, 2934 bool isPPC64, 2935 bool isDarwinABI, 2936 DebugLoc dl) { 2937 if (SPDiff) { 2938 // Calculate the new stack slot for the return address. 2939 int SlotSize = isPPC64 ? 8 : 4; 2940 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64, 2941 isDarwinABI); 2942 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, 2943 NewRetAddrLoc, true); 2944 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2945 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); 2946 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, 2947 MachinePointerInfo::getFixedStack(NewRetAddr), 2948 false, false, 0); 2949 2950 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack 2951 // slot as the FP is never overwritten. 2952 if (isDarwinABI) { 2953 int NewFPLoc = 2954 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 2955 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc, 2956 true); 2957 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); 2958 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, 2959 MachinePointerInfo::getFixedStack(NewFPIdx), 2960 false, false, 0); 2961 } 2962 } 2963 return Chain; 2964} 2965 2966/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate 2967/// the position of the argument. 2968static void 2969CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, 2970 SDValue Arg, int SPDiff, unsigned ArgOffset, 2971 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 2972 int Offset = ArgOffset + SPDiff; 2973 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; 2974 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2975 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2976 SDValue FIN = DAG.getFrameIndex(FI, VT); 2977 TailCallArgumentInfo Info; 2978 Info.Arg = Arg; 2979 Info.FrameIdxOp = FIN; 2980 Info.FrameIdx = FI; 2981 TailCallArguments.push_back(Info); 2982} 2983 2984/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address 2985/// stack slot. Returns the chain as result and the loaded frame pointers in 2986/// LROpOut/FPOpout. Used when tail calling. 2987SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 2988 int SPDiff, 2989 SDValue Chain, 2990 SDValue &LROpOut, 2991 SDValue &FPOpOut, 2992 bool isDarwinABI, 2993 DebugLoc dl) const { 2994 if (SPDiff) { 2995 // Load the LR and FP stack slot for later adjusting. 2996 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; 2997 LROpOut = getReturnAddrFrameIndex(DAG); 2998 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(), 2999 false, false, false, 0); 3000 Chain = SDValue(LROpOut.getNode(), 1); 3001 3002 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack 3003 // slot as the FP is never overwritten. 3004 if (isDarwinABI) { 3005 FPOpOut = getFramePointerFrameIndex(DAG); 3006 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(), 3007 false, false, false, 0); 3008 Chain = SDValue(FPOpOut.getNode(), 1); 3009 } 3010 } 3011 return Chain; 3012} 3013 3014/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 3015/// by "Src" to address "Dst" of size "Size". Alignment information is 3016/// specified by the specific parameter attribute. The copy will be passed as 3017/// a byval function parameter. 3018/// Sometimes what we are copying is the end of a larger object, the part that 3019/// does not fit in registers. 3020static SDValue 3021CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 3022 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 3023 DebugLoc dl) { 3024 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 3025 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 3026 false, false, MachinePointerInfo(0), 3027 MachinePointerInfo(0)); 3028} 3029 3030/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of 3031/// tail calls. 3032static void 3033LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, 3034 SDValue Arg, SDValue PtrOff, int SPDiff, 3035 unsigned ArgOffset, bool isPPC64, bool isTailCall, 3036 bool isVector, SmallVector<SDValue, 8> &MemOpChains, 3037 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments, 3038 DebugLoc dl) { 3039 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3040 if (!isTailCall) { 3041 if (isVector) { 3042 SDValue StackPtr; 3043 if (isPPC64) 3044 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 3045 else 3046 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 3047 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 3048 DAG.getConstant(ArgOffset, PtrVT)); 3049 } 3050 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 3051 MachinePointerInfo(), false, false, 0)); 3052 // Calculate and remember argument location. 3053 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, 3054 TailCallArguments); 3055} 3056 3057static 3058void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, 3059 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, 3060 SDValue LROp, SDValue FPOp, bool isDarwinABI, 3061 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) { 3062 MachineFunction &MF = DAG.getMachineFunction(); 3063 3064 // Emit a sequence of copyto/copyfrom virtual registers for arguments that 3065 // might overwrite each other in case of tail call optimization. 3066 SmallVector<SDValue, 8> MemOpChains2; 3067 // Do not flag preceding copytoreg stuff together with the following stuff. 3068 InFlag = SDValue(); 3069 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, 3070 MemOpChains2, dl); 3071 if (!MemOpChains2.empty()) 3072 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3073 &MemOpChains2[0], MemOpChains2.size()); 3074 3075 // Store the return address to the appropriate stack slot. 3076 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, 3077 isPPC64, isDarwinABI, dl); 3078 3079 // Emit callseq_end just before tailcall node. 3080 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 3081 DAG.getIntPtrConstant(0, true), InFlag); 3082 InFlag = Chain.getValue(1); 3083} 3084 3085static 3086unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, 3087 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall, 3088 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 3089 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys, 3090 const PPCSubtarget &PPCSubTarget) { 3091 3092 bool isPPC64 = PPCSubTarget.isPPC64(); 3093 bool isSVR4ABI = PPCSubTarget.isSVR4ABI(); 3094 3095 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3096 NodeTys.push_back(MVT::Other); // Returns a chain 3097 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use. 3098 3099 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin; 3100 3101 bool needIndirectCall = true; 3102 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) { 3103 // If this is an absolute destination address, use the munged value. 3104 Callee = SDValue(Dest, 0); 3105 needIndirectCall = false; 3106 } 3107 3108 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3109 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201 3110 // Use indirect calls for ALL functions calls in JIT mode, since the 3111 // far-call stubs may be outside relocation limits for a BL instruction. 3112 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) { 3113 unsigned OpFlags = 0; 3114 if (DAG.getTarget().getRelocationModel() != Reloc::Static && 3115 (PPCSubTarget.getTargetTriple().isMacOSX() && 3116 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) && 3117 (G->getGlobal()->isDeclaration() || 3118 G->getGlobal()->isWeakForLinker())) { 3119 // PC-relative references to external symbols should go through $stub, 3120 // unless we're building with the leopard linker or later, which 3121 // automatically synthesizes these stubs. 3122 OpFlags = PPCII::MO_DARWIN_STUB; 3123 } 3124 3125 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, 3126 // every direct call is) turn it into a TargetGlobalAddress / 3127 // TargetExternalSymbol node so that legalize doesn't hack it. 3128 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 3129 Callee.getValueType(), 3130 0, OpFlags); 3131 needIndirectCall = false; 3132 } 3133 } 3134 3135 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3136 unsigned char OpFlags = 0; 3137 3138 if (DAG.getTarget().getRelocationModel() != Reloc::Static && 3139 (PPCSubTarget.getTargetTriple().isMacOSX() && 3140 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) { 3141 // PC-relative references to external symbols should go through $stub, 3142 // unless we're building with the leopard linker or later, which 3143 // automatically synthesizes these stubs. 3144 OpFlags = PPCII::MO_DARWIN_STUB; 3145 } 3146 3147 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(), 3148 OpFlags); 3149 needIndirectCall = false; 3150 } 3151 3152 if (needIndirectCall) { 3153 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 3154 // to do the call, we can't use PPCISD::CALL. 3155 SDValue MTCTROps[] = {Chain, Callee, InFlag}; 3156 3157 if (isSVR4ABI && isPPC64) { 3158 // Function pointers in the 64-bit SVR4 ABI do not point to the function 3159 // entry point, but to the function descriptor (the function entry point 3160 // address is part of the function descriptor though). 3161 // The function descriptor is a three doubleword structure with the 3162 // following fields: function entry point, TOC base address and 3163 // environment pointer. 3164 // Thus for a call through a function pointer, the following actions need 3165 // to be performed: 3166 // 1. Save the TOC of the caller in the TOC save area of its stack 3167 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()). 3168 // 2. Load the address of the function entry point from the function 3169 // descriptor. 3170 // 3. Load the TOC of the callee from the function descriptor into r2. 3171 // 4. Load the environment pointer from the function descriptor into 3172 // r11. 3173 // 5. Branch to the function entry point address. 3174 // 6. On return of the callee, the TOC of the caller needs to be 3175 // restored (this is done in FinishCall()). 3176 // 3177 // All those operations are flagged together to ensure that no other 3178 // operations can be scheduled in between. E.g. without flagging the 3179 // operations together, a TOC access in the caller could be scheduled 3180 // between the load of the callee TOC and the branch to the callee, which 3181 // results in the TOC access going through the TOC of the callee instead 3182 // of going through the TOC of the caller, which leads to incorrect code. 3183 3184 // Load the address of the function entry point from the function 3185 // descriptor. 3186 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue); 3187 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps, 3188 InFlag.getNode() ? 3 : 2); 3189 Chain = LoadFuncPtr.getValue(1); 3190 InFlag = LoadFuncPtr.getValue(2); 3191 3192 // Load environment pointer into r11. 3193 // Offset of the environment pointer within the function descriptor. 3194 SDValue PtrOff = DAG.getIntPtrConstant(16); 3195 3196 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff); 3197 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr, 3198 InFlag); 3199 Chain = LoadEnvPtr.getValue(1); 3200 InFlag = LoadEnvPtr.getValue(2); 3201 3202 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr, 3203 InFlag); 3204 Chain = EnvVal.getValue(0); 3205 InFlag = EnvVal.getValue(1); 3206 3207 // Load TOC of the callee into r2. We are using a target-specific load 3208 // with r2 hard coded, because the result of a target-independent load 3209 // would never go directly into r2, since r2 is a reserved register (which 3210 // prevents the register allocator from allocating it), resulting in an 3211 // additional register being allocated and an unnecessary move instruction 3212 // being generated. 3213 VTs = DAG.getVTList(MVT::Other, MVT::Glue); 3214 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, 3215 Callee, InFlag); 3216 Chain = LoadTOCPtr.getValue(0); 3217 InFlag = LoadTOCPtr.getValue(1); 3218 3219 MTCTROps[0] = Chain; 3220 MTCTROps[1] = LoadFuncPtr; 3221 MTCTROps[2] = InFlag; 3222 } 3223 3224 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps, 3225 2 + (InFlag.getNode() != 0)); 3226 InFlag = Chain.getValue(1); 3227 3228 NodeTys.clear(); 3229 NodeTys.push_back(MVT::Other); 3230 NodeTys.push_back(MVT::Glue); 3231 Ops.push_back(Chain); 3232 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin; 3233 Callee.setNode(0); 3234 // Add CTR register as callee so a bctr can be emitted later. 3235 if (isTailCall) 3236 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT)); 3237 } 3238 3239 // If this is a direct call, pass the chain and the callee. 3240 if (Callee.getNode()) { 3241 Ops.push_back(Chain); 3242 Ops.push_back(Callee); 3243 } 3244 // If this is a tail call add stack pointer delta. 3245 if (isTailCall) 3246 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); 3247 3248 // Add argument registers to the end of the list so that they are known live 3249 // into the call. 3250 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 3251 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 3252 RegsToPass[i].second.getValueType())); 3253 3254 return CallOpc; 3255} 3256 3257static 3258bool isLocalCall(const SDValue &Callee) 3259{ 3260 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 3261 return !G->getGlobal()->isDeclaration() && 3262 !G->getGlobal()->isWeakForLinker(); 3263 return false; 3264} 3265 3266SDValue 3267PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 3268 CallingConv::ID CallConv, bool isVarArg, 3269 const SmallVectorImpl<ISD::InputArg> &Ins, 3270 DebugLoc dl, SelectionDAG &DAG, 3271 SmallVectorImpl<SDValue> &InVals) const { 3272 3273 SmallVector<CCValAssign, 16> RVLocs; 3274 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3275 getTargetMachine(), RVLocs, *DAG.getContext()); 3276 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC); 3277 3278 // Copy all of the result registers out of their specified physreg. 3279 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 3280 CCValAssign &VA = RVLocs[i]; 3281 assert(VA.isRegLoc() && "Can only return in registers!"); 3282 3283 SDValue Val = DAG.getCopyFromReg(Chain, dl, 3284 VA.getLocReg(), VA.getLocVT(), InFlag); 3285 Chain = Val.getValue(1); 3286 InFlag = Val.getValue(2); 3287 3288 switch (VA.getLocInfo()) { 3289 default: llvm_unreachable("Unknown loc info!"); 3290 case CCValAssign::Full: break; 3291 case CCValAssign::AExt: 3292 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); 3293 break; 3294 case CCValAssign::ZExt: 3295 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val, 3296 DAG.getValueType(VA.getValVT())); 3297 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); 3298 break; 3299 case CCValAssign::SExt: 3300 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val, 3301 DAG.getValueType(VA.getValVT())); 3302 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); 3303 break; 3304 } 3305 3306 InVals.push_back(Val); 3307 } 3308 3309 return Chain; 3310} 3311 3312SDValue 3313PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl, 3314 bool isTailCall, bool isVarArg, 3315 SelectionDAG &DAG, 3316 SmallVector<std::pair<unsigned, SDValue>, 8> 3317 &RegsToPass, 3318 SDValue InFlag, SDValue Chain, 3319 SDValue &Callee, 3320 int SPDiff, unsigned NumBytes, 3321 const SmallVectorImpl<ISD::InputArg> &Ins, 3322 SmallVectorImpl<SDValue> &InVals) const { 3323 std::vector<EVT> NodeTys; 3324 SmallVector<SDValue, 8> Ops; 3325 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff, 3326 isTailCall, RegsToPass, Ops, NodeTys, 3327 PPCSubTarget); 3328 3329 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls 3330 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) 3331 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32)); 3332 3333 // When performing tail call optimization the callee pops its arguments off 3334 // the stack. Account for this here so these bytes can be pushed back on in 3335 // PPCFrameLowering::eliminateCallFramePseudoInstr. 3336 int BytesCalleePops = 3337 (CallConv == CallingConv::Fast && 3338 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0; 3339 3340 // Add a register mask operand representing the call-preserved registers. 3341 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 3342 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 3343 assert(Mask && "Missing call preserved mask for calling convention"); 3344 Ops.push_back(DAG.getRegisterMask(Mask)); 3345 3346 if (InFlag.getNode()) 3347 Ops.push_back(InFlag); 3348 3349 // Emit tail call. 3350 if (isTailCall) { 3351 assert(((Callee.getOpcode() == ISD::Register && 3352 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || 3353 Callee.getOpcode() == ISD::TargetExternalSymbol || 3354 Callee.getOpcode() == ISD::TargetGlobalAddress || 3355 isa<ConstantSDNode>(Callee)) && 3356 "Expecting an global address, external symbol, absolute value or register"); 3357 3358 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size()); 3359 } 3360 3361 // Add a NOP immediately after the branch instruction when using the 64-bit 3362 // SVR4 ABI. At link time, if caller and callee are in a different module and 3363 // thus have a different TOC, the call will be replaced with a call to a stub 3364 // function which saves the current TOC, loads the TOC of the callee and 3365 // branches to the callee. The NOP will be replaced with a load instruction 3366 // which restores the TOC of the caller from the TOC save slot of the current 3367 // stack frame. If caller and callee belong to the same module (and have the 3368 // same TOC), the NOP will remain unchanged. 3369 3370 bool needsTOCRestore = false; 3371 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) { 3372 if (CallOpc == PPCISD::BCTRL_SVR4) { 3373 // This is a call through a function pointer. 3374 // Restore the caller TOC from the save area into R2. 3375 // See PrepareCall() for more information about calls through function 3376 // pointers in the 64-bit SVR4 ABI. 3377 // We are using a target-specific load with r2 hard coded, because the 3378 // result of a target-independent load would never go directly into r2, 3379 // since r2 is a reserved register (which prevents the register allocator 3380 // from allocating it), resulting in an additional register being 3381 // allocated and an unnecessary move instruction being generated. 3382 needsTOCRestore = true; 3383 } else if ((CallOpc == PPCISD::CALL_SVR4) && !isLocalCall(Callee)) { 3384 // Otherwise insert NOP for non-local calls. 3385 CallOpc = PPCISD::CALL_NOP_SVR4; 3386 } 3387 } 3388 3389 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 3390 InFlag = Chain.getValue(1); 3391 3392 if (needsTOCRestore) { 3393 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); 3394 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag); 3395 InFlag = Chain.getValue(1); 3396 } 3397 3398 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 3399 DAG.getIntPtrConstant(BytesCalleePops, true), 3400 InFlag); 3401 if (!Ins.empty()) 3402 InFlag = Chain.getValue(1); 3403 3404 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 3405 Ins, dl, DAG, InVals); 3406} 3407 3408SDValue 3409PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 3410 SmallVectorImpl<SDValue> &InVals) const { 3411 SelectionDAG &DAG = CLI.DAG; 3412 DebugLoc &dl = CLI.DL; 3413 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 3414 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 3415 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 3416 SDValue Chain = CLI.Chain; 3417 SDValue Callee = CLI.Callee; 3418 bool &isTailCall = CLI.IsTailCall; 3419 CallingConv::ID CallConv = CLI.CallConv; 3420 bool isVarArg = CLI.IsVarArg; 3421 3422 if (isTailCall) 3423 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, 3424 Ins, DAG); 3425 3426 if (PPCSubTarget.isSVR4ABI()) { 3427 if (PPCSubTarget.isPPC64()) 3428 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg, 3429 isTailCall, Outs, OutVals, Ins, 3430 dl, DAG, InVals); 3431 else 3432 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg, 3433 isTailCall, Outs, OutVals, Ins, 3434 dl, DAG, InVals); 3435 } 3436 3437 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg, 3438 isTailCall, Outs, OutVals, Ins, 3439 dl, DAG, InVals); 3440} 3441 3442SDValue 3443PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee, 3444 CallingConv::ID CallConv, bool isVarArg, 3445 bool isTailCall, 3446 const SmallVectorImpl<ISD::OutputArg> &Outs, 3447 const SmallVectorImpl<SDValue> &OutVals, 3448 const SmallVectorImpl<ISD::InputArg> &Ins, 3449 DebugLoc dl, SelectionDAG &DAG, 3450 SmallVectorImpl<SDValue> &InVals) const { 3451 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description 3452 // of the 32-bit SVR4 ABI stack frame layout. 3453 3454 assert((CallConv == CallingConv::C || 3455 CallConv == CallingConv::Fast) && "Unknown calling convention!"); 3456 3457 unsigned PtrByteSize = 4; 3458 3459 MachineFunction &MF = DAG.getMachineFunction(); 3460 3461 // Mark this function as potentially containing a function that contains a 3462 // tail call. As a consequence the frame pointer will be used for dynamicalloc 3463 // and restoring the callers stack pointer in this functions epilog. This is 3464 // done because by tail calling the called function might overwrite the value 3465 // in this function's (MF) stack pointer stack slot 0(SP). 3466 if (getTargetMachine().Options.GuaranteedTailCallOpt && 3467 CallConv == CallingConv::Fast) 3468 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 3469 3470 // Count how many bytes are to be pushed on the stack, including the linkage 3471 // area, parameter list area and the part of the local variable space which 3472 // contains copies of aggregates which are passed by value. 3473 3474 // Assign locations to all of the outgoing arguments. 3475 SmallVector<CCValAssign, 16> ArgLocs; 3476 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3477 getTargetMachine(), ArgLocs, *DAG.getContext()); 3478 3479 // Reserve space for the linkage area on the stack. 3480 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); 3481 3482 if (isVarArg) { 3483 // Handle fixed and variable vector arguments differently. 3484 // Fixed vector arguments go into registers as long as registers are 3485 // available. Variable vector arguments always go into memory. 3486 unsigned NumArgs = Outs.size(); 3487 3488 for (unsigned i = 0; i != NumArgs; ++i) { 3489 MVT ArgVT = Outs[i].VT; 3490 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 3491 bool Result; 3492 3493 if (Outs[i].IsFixed) { 3494 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, 3495 CCInfo); 3496 } else { 3497 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, 3498 ArgFlags, CCInfo); 3499 } 3500 3501 if (Result) { 3502#ifndef NDEBUG 3503 errs() << "Call operand #" << i << " has unhandled type " 3504 << EVT(ArgVT).getEVTString() << "\n"; 3505#endif 3506 llvm_unreachable(0); 3507 } 3508 } 3509 } else { 3510 // All arguments are treated the same. 3511 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4); 3512 } 3513 3514 // Assign locations to all of the outgoing aggregate by value arguments. 3515 SmallVector<CCValAssign, 16> ByValArgLocs; 3516 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3517 getTargetMachine(), ByValArgLocs, *DAG.getContext()); 3518 3519 // Reserve stack space for the allocations in CCInfo. 3520 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 3521 3522 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal); 3523 3524 // Size of the linkage area, parameter list area and the part of the local 3525 // space variable where copies of aggregates which are passed by value are 3526 // stored. 3527 unsigned NumBytes = CCByValInfo.getNextStackOffset(); 3528 3529 // Calculate by how many bytes the stack has to be adjusted in case of tail 3530 // call optimization. 3531 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 3532 3533 // Adjust the stack pointer for the new arguments... 3534 // These operations are automatically eliminated by the prolog/epilog pass 3535 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 3536 SDValue CallSeqStart = Chain; 3537 3538 // Load the return address and frame pointer so it can be moved somewhere else 3539 // later. 3540 SDValue LROp, FPOp; 3541 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false, 3542 dl); 3543 3544 // Set up a copy of the stack pointer for use loading and storing any 3545 // arguments that may not fit in the registers available for argument 3546 // passing. 3547 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 3548 3549 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3550 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3551 SmallVector<SDValue, 8> MemOpChains; 3552 3553 bool seenFloatArg = false; 3554 // Walk the register/memloc assignments, inserting copies/loads. 3555 for (unsigned i = 0, j = 0, e = ArgLocs.size(); 3556 i != e; 3557 ++i) { 3558 CCValAssign &VA = ArgLocs[i]; 3559 SDValue Arg = OutVals[i]; 3560 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3561 3562 if (Flags.isByVal()) { 3563 // Argument is an aggregate which is passed by value, thus we need to 3564 // create a copy of it in the local variable space of the current stack 3565 // frame (which is the stack frame of the caller) and pass the address of 3566 // this copy to the callee. 3567 assert((j < ByValArgLocs.size()) && "Index out of bounds!"); 3568 CCValAssign &ByValVA = ByValArgLocs[j++]; 3569 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"); 3570 3571 // Memory reserved in the local variable space of the callers stack frame. 3572 unsigned LocMemOffset = ByValVA.getLocMemOffset(); 3573 3574 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 3575 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 3576 3577 // Create a copy of the argument in the local area of the current 3578 // stack frame. 3579 SDValue MemcpyCall = 3580 CreateCopyOfByValArgument(Arg, PtrOff, 3581 CallSeqStart.getNode()->getOperand(0), 3582 Flags, DAG, dl); 3583 3584 // This must go outside the CALLSEQ_START..END. 3585 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3586 CallSeqStart.getNode()->getOperand(1)); 3587 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3588 NewCallSeqStart.getNode()); 3589 Chain = CallSeqStart = NewCallSeqStart; 3590 3591 // Pass the address of the aggregate copy on the stack either in a 3592 // physical register or in the parameter list area of the current stack 3593 // frame to the callee. 3594 Arg = PtrOff; 3595 } 3596 3597 if (VA.isRegLoc()) { 3598 seenFloatArg |= VA.getLocVT().isFloatingPoint(); 3599 // Put argument in a physical register. 3600 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3601 } else { 3602 // Put argument in the parameter list area of the current stack frame. 3603 assert(VA.isMemLoc()); 3604 unsigned LocMemOffset = VA.getLocMemOffset(); 3605 3606 if (!isTailCall) { 3607 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 3608 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 3609 3610 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 3611 MachinePointerInfo(), 3612 false, false, 0)); 3613 } else { 3614 // Calculate and remember argument location. 3615 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset, 3616 TailCallArguments); 3617 } 3618 } 3619 } 3620 3621 if (!MemOpChains.empty()) 3622 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3623 &MemOpChains[0], MemOpChains.size()); 3624 3625 // Build a sequence of copy-to-reg nodes chained together with token chain 3626 // and flag operands which copy the outgoing args into the appropriate regs. 3627 SDValue InFlag; 3628 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3629 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3630 RegsToPass[i].second, InFlag); 3631 InFlag = Chain.getValue(1); 3632 } 3633 3634 // Set CR bit 6 to true if this is a vararg call with floating args passed in 3635 // registers. 3636 if (isVarArg) { 3637 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); 3638 SDValue Ops[] = { Chain, InFlag }; 3639 3640 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET, 3641 dl, VTs, Ops, InFlag.getNode() ? 2 : 1); 3642 3643 InFlag = Chain.getValue(1); 3644 } 3645 3646 if (isTailCall) 3647 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp, 3648 false, TailCallArguments); 3649 3650 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 3651 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 3652 Ins, InVals); 3653} 3654 3655// Copy an argument into memory, being careful to do this outside the 3656// call sequence for the call to which the argument belongs. 3657SDValue 3658PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 3659 SDValue CallSeqStart, 3660 ISD::ArgFlagsTy Flags, 3661 SelectionDAG &DAG, 3662 DebugLoc dl) const { 3663 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, 3664 CallSeqStart.getNode()->getOperand(0), 3665 Flags, DAG, dl); 3666 // The MEMCPY must go outside the CALLSEQ_START..END. 3667 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3668 CallSeqStart.getNode()->getOperand(1)); 3669 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3670 NewCallSeqStart.getNode()); 3671 return NewCallSeqStart; 3672} 3673 3674SDValue 3675PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee, 3676 CallingConv::ID CallConv, bool isVarArg, 3677 bool isTailCall, 3678 const SmallVectorImpl<ISD::OutputArg> &Outs, 3679 const SmallVectorImpl<SDValue> &OutVals, 3680 const SmallVectorImpl<ISD::InputArg> &Ins, 3681 DebugLoc dl, SelectionDAG &DAG, 3682 SmallVectorImpl<SDValue> &InVals) const { 3683 3684 unsigned NumOps = Outs.size(); 3685 3686 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3687 unsigned PtrByteSize = 8; 3688 3689 MachineFunction &MF = DAG.getMachineFunction(); 3690 3691 // Mark this function as potentially containing a function that contains a 3692 // tail call. As a consequence the frame pointer will be used for dynamicalloc 3693 // and restoring the callers stack pointer in this functions epilog. This is 3694 // done because by tail calling the called function might overwrite the value 3695 // in this function's (MF) stack pointer stack slot 0(SP). 3696 if (getTargetMachine().Options.GuaranteedTailCallOpt && 3697 CallConv == CallingConv::Fast) 3698 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 3699 3700 unsigned nAltivecParamsAtEnd = 0; 3701 3702 // Count how many bytes are to be pushed on the stack, including the linkage 3703 // area, and parameter passing area. We start with at least 48 bytes, which 3704 // is reserved space for [SP][CR][LR][3 x unused]. 3705 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result 3706 // of this call. 3707 unsigned NumBytes = 3708 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv, 3709 Outs, OutVals, nAltivecParamsAtEnd); 3710 3711 // Calculate by how many bytes the stack has to be adjusted in case of tail 3712 // call optimization. 3713 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 3714 3715 // To protect arguments on the stack from being clobbered in a tail call, 3716 // force all the loads to happen before doing any other lowering. 3717 if (isTailCall) 3718 Chain = DAG.getStackArgumentTokenFactor(Chain); 3719 3720 // Adjust the stack pointer for the new arguments... 3721 // These operations are automatically eliminated by the prolog/epilog pass 3722 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 3723 SDValue CallSeqStart = Chain; 3724 3725 // Load the return address and frame pointer so it can be move somewhere else 3726 // later. 3727 SDValue LROp, FPOp; 3728 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 3729 dl); 3730 3731 // Set up a copy of the stack pointer for use loading and storing any 3732 // arguments that may not fit in the registers available for argument 3733 // passing. 3734 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 3735 3736 // Figure out which arguments are going to go in registers, and which in 3737 // memory. Also, if this is a vararg function, floating point operations 3738 // must be stored to our stack, and loaded into integer regs as well, if 3739 // any integer regs are available for argument passing. 3740 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true); 3741 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 3742 3743 static const uint16_t GPR[] = { 3744 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 3745 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 3746 }; 3747 static const uint16_t *FPR = GetFPR(); 3748 3749 static const uint16_t VR[] = { 3750 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 3751 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 3752 }; 3753 const unsigned NumGPRs = array_lengthof(GPR); 3754 const unsigned NumFPRs = 13; 3755 const unsigned NumVRs = array_lengthof(VR); 3756 3757 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3758 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3759 3760 SmallVector<SDValue, 8> MemOpChains; 3761 for (unsigned i = 0; i != NumOps; ++i) { 3762 SDValue Arg = OutVals[i]; 3763 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3764 3765 // PtrOff will be used to store the current argument to the stack if a 3766 // register cannot be found for it. 3767 SDValue PtrOff; 3768 3769 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 3770 3771 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3772 3773 // Promote integers to 64-bit values. 3774 if (Arg.getValueType() == MVT::i32) { 3775 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 3776 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3777 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 3778 } 3779 3780 // FIXME memcpy is used way more than necessary. Correctness first. 3781 // Note: "by value" is code for passing a structure by value, not 3782 // basic types. 3783 if (Flags.isByVal()) { 3784 // Note: Size includes alignment padding, so 3785 // struct x { short a; char b; } 3786 // will have Size = 4. With #pragma pack(1), it will have Size = 3. 3787 // These are the proper values we need for right-justifying the 3788 // aggregate in a parameter register. 3789 unsigned Size = Flags.getByValSize(); 3790 3791 // An empty aggregate parameter takes up no storage and no 3792 // registers. 3793 if (Size == 0) 3794 continue; 3795 3796 // All aggregates smaller than 8 bytes must be passed right-justified. 3797 if (Size==1 || Size==2 || Size==4) { 3798 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32); 3799 if (GPR_idx != NumGPRs) { 3800 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, 3801 MachinePointerInfo(), VT, 3802 false, false, 0); 3803 MemOpChains.push_back(Load.getValue(1)); 3804 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3805 3806 ArgOffset += PtrByteSize; 3807 continue; 3808 } 3809 } 3810 3811 if (GPR_idx == NumGPRs && Size < 8) { 3812 SDValue Const = DAG.getConstant(PtrByteSize - Size, 3813 PtrOff.getValueType()); 3814 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3815 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, 3816 CallSeqStart, 3817 Flags, DAG, dl); 3818 ArgOffset += PtrByteSize; 3819 continue; 3820 } 3821 // Copy entire object into memory. There are cases where gcc-generated 3822 // code assumes it is there, even if it could be put entirely into 3823 // registers. (This is not what the doc says.) 3824 3825 // FIXME: The above statement is likely due to a misunderstanding of the 3826 // documents. All arguments must be copied into the parameter area BY 3827 // THE CALLEE in the event that the callee takes the address of any 3828 // formal argument. That has not yet been implemented. However, it is 3829 // reasonable to use the stack area as a staging area for the register 3830 // load. 3831 3832 // Skip this for small aggregates, as we will use the same slot for a 3833 // right-justified copy, below. 3834 if (Size >= 8) 3835 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff, 3836 CallSeqStart, 3837 Flags, DAG, dl); 3838 3839 // When a register is available, pass a small aggregate right-justified. 3840 if (Size < 8 && GPR_idx != NumGPRs) { 3841 // The easiest way to get this right-justified in a register 3842 // is to copy the structure into the rightmost portion of a 3843 // local variable slot, then load the whole slot into the 3844 // register. 3845 // FIXME: The memcpy seems to produce pretty awful code for 3846 // small aggregates, particularly for packed ones. 3847 // FIXME: It would be preferable to use the slot in the 3848 // parameter save area instead of a new local variable. 3849 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType()); 3850 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3851 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, 3852 CallSeqStart, 3853 Flags, DAG, dl); 3854 3855 // Load the slot into the register. 3856 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff, 3857 MachinePointerInfo(), 3858 false, false, false, 0); 3859 MemOpChains.push_back(Load.getValue(1)); 3860 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3861 3862 // Done with this argument. 3863 ArgOffset += PtrByteSize; 3864 continue; 3865 } 3866 3867 // For aggregates larger than PtrByteSize, copy the pieces of the 3868 // object that fit into registers from the parameter save area. 3869 for (unsigned j=0; j<Size; j+=PtrByteSize) { 3870 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 3871 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 3872 if (GPR_idx != NumGPRs) { 3873 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 3874 MachinePointerInfo(), 3875 false, false, false, 0); 3876 MemOpChains.push_back(Load.getValue(1)); 3877 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3878 ArgOffset += PtrByteSize; 3879 } else { 3880 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 3881 break; 3882 } 3883 } 3884 continue; 3885 } 3886 3887 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 3888 default: llvm_unreachable("Unexpected ValueType for argument!"); 3889 case MVT::i32: 3890 case MVT::i64: 3891 if (GPR_idx != NumGPRs) { 3892 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 3893 } else { 3894 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3895 true, isTailCall, false, MemOpChains, 3896 TailCallArguments, dl); 3897 } 3898 ArgOffset += PtrByteSize; 3899 break; 3900 case MVT::f32: 3901 case MVT::f64: 3902 if (FPR_idx != NumFPRs) { 3903 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 3904 3905 if (isVarArg) { 3906 // A single float or an aggregate containing only a single float 3907 // must be passed right-justified in the stack doubleword, and 3908 // in the GPR, if one is available. 3909 SDValue StoreOff; 3910 if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) { 3911 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3912 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 3913 } else 3914 StoreOff = PtrOff; 3915 3916 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff, 3917 MachinePointerInfo(), false, false, 0); 3918 MemOpChains.push_back(Store); 3919 3920 // Float varargs are always shadowed in available integer registers 3921 if (GPR_idx != NumGPRs) { 3922 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 3923 MachinePointerInfo(), false, false, 3924 false, 0); 3925 MemOpChains.push_back(Load.getValue(1)); 3926 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3927 } 3928 } else if (GPR_idx != NumGPRs) 3929 // If we have any FPRs remaining, we may also have GPRs remaining. 3930 ++GPR_idx; 3931 } else { 3932 // Single-precision floating-point values are mapped to the 3933 // second (rightmost) word of the stack doubleword. 3934 if (Arg.getValueType() == MVT::f32) { 3935 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3936 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 3937 } 3938 3939 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3940 true, isTailCall, false, MemOpChains, 3941 TailCallArguments, dl); 3942 } 3943 ArgOffset += 8; 3944 break; 3945 case MVT::v4f32: 3946 case MVT::v4i32: 3947 case MVT::v8i16: 3948 case MVT::v16i8: 3949 if (isVarArg) { 3950 // These go aligned on the stack, or in the corresponding R registers 3951 // when within range. The Darwin PPC ABI doc claims they also go in 3952 // V registers; in fact gcc does this only for arguments that are 3953 // prototyped, not for those that match the ... We do it for all 3954 // arguments, seems to work. 3955 while (ArgOffset % 16 !=0) { 3956 ArgOffset += PtrByteSize; 3957 if (GPR_idx != NumGPRs) 3958 GPR_idx++; 3959 } 3960 // We could elide this store in the case where the object fits 3961 // entirely in R registers. Maybe later. 3962 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 3963 DAG.getConstant(ArgOffset, PtrVT)); 3964 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 3965 MachinePointerInfo(), false, false, 0); 3966 MemOpChains.push_back(Store); 3967 if (VR_idx != NumVRs) { 3968 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, 3969 MachinePointerInfo(), 3970 false, false, false, 0); 3971 MemOpChains.push_back(Load.getValue(1)); 3972 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 3973 } 3974 ArgOffset += 16; 3975 for (unsigned i=0; i<16; i+=PtrByteSize) { 3976 if (GPR_idx == NumGPRs) 3977 break; 3978 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 3979 DAG.getConstant(i, PtrVT)); 3980 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(), 3981 false, false, false, 0); 3982 MemOpChains.push_back(Load.getValue(1)); 3983 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3984 } 3985 break; 3986 } 3987 3988 // Non-varargs Altivec params generally go in registers, but have 3989 // stack space allocated at the end. 3990 if (VR_idx != NumVRs) { 3991 // Doesn't have GPR space allocated. 3992 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 3993 } else { 3994 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3995 true, isTailCall, true, MemOpChains, 3996 TailCallArguments, dl); 3997 ArgOffset += 16; 3998 } 3999 break; 4000 } 4001 } 4002 4003 if (!MemOpChains.empty()) 4004 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 4005 &MemOpChains[0], MemOpChains.size()); 4006 4007 // Check if this is an indirect call (MTCTR/BCTRL). 4008 // See PrepareCall() for more information about calls through function 4009 // pointers in the 64-bit SVR4 ABI. 4010 if (!isTailCall && 4011 !dyn_cast<GlobalAddressSDNode>(Callee) && 4012 !dyn_cast<ExternalSymbolSDNode>(Callee) && 4013 !isBLACompatibleAddress(Callee, DAG)) { 4014 // Load r2 into a virtual register and store it to the TOC save area. 4015 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); 4016 // TOC save area offset. 4017 SDValue PtrOff = DAG.getIntPtrConstant(40); 4018 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 4019 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(), 4020 false, false, 0); 4021 // R12 must contain the address of an indirect callee. This does not 4022 // mean the MTCTR instruction must use R12; it's easier to model this 4023 // as an extra parameter, so do that. 4024 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee)); 4025 } 4026 4027 // Build a sequence of copy-to-reg nodes chained together with token chain 4028 // and flag operands which copy the outgoing args into the appropriate regs. 4029 SDValue InFlag; 4030 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 4031 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 4032 RegsToPass[i].second, InFlag); 4033 InFlag = Chain.getValue(1); 4034 } 4035 4036 if (isTailCall) 4037 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp, 4038 FPOp, true, TailCallArguments); 4039 4040 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 4041 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 4042 Ins, InVals); 4043} 4044 4045SDValue 4046PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, 4047 CallingConv::ID CallConv, bool isVarArg, 4048 bool isTailCall, 4049 const SmallVectorImpl<ISD::OutputArg> &Outs, 4050 const SmallVectorImpl<SDValue> &OutVals, 4051 const SmallVectorImpl<ISD::InputArg> &Ins, 4052 DebugLoc dl, SelectionDAG &DAG, 4053 SmallVectorImpl<SDValue> &InVals) const { 4054 4055 unsigned NumOps = Outs.size(); 4056 4057 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4058 bool isPPC64 = PtrVT == MVT::i64; 4059 unsigned PtrByteSize = isPPC64 ? 8 : 4; 4060 4061 MachineFunction &MF = DAG.getMachineFunction(); 4062 4063 // Mark this function as potentially containing a function that contains a 4064 // tail call. As a consequence the frame pointer will be used for dynamicalloc 4065 // and restoring the callers stack pointer in this functions epilog. This is 4066 // done because by tail calling the called function might overwrite the value 4067 // in this function's (MF) stack pointer stack slot 0(SP). 4068 if (getTargetMachine().Options.GuaranteedTailCallOpt && 4069 CallConv == CallingConv::Fast) 4070 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 4071 4072 unsigned nAltivecParamsAtEnd = 0; 4073 4074 // Count how many bytes are to be pushed on the stack, including the linkage 4075 // area, and parameter passing area. We start with 24/48 bytes, which is 4076 // prereserved space for [SP][CR][LR][3 x unused]. 4077 unsigned NumBytes = 4078 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv, 4079 Outs, OutVals, 4080 nAltivecParamsAtEnd); 4081 4082 // Calculate by how many bytes the stack has to be adjusted in case of tail 4083 // call optimization. 4084 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 4085 4086 // To protect arguments on the stack from being clobbered in a tail call, 4087 // force all the loads to happen before doing any other lowering. 4088 if (isTailCall) 4089 Chain = DAG.getStackArgumentTokenFactor(Chain); 4090 4091 // Adjust the stack pointer for the new arguments... 4092 // These operations are automatically eliminated by the prolog/epilog pass 4093 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 4094 SDValue CallSeqStart = Chain; 4095 4096 // Load the return address and frame pointer so it can be move somewhere else 4097 // later. 4098 SDValue LROp, FPOp; 4099 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 4100 dl); 4101 4102 // Set up a copy of the stack pointer for use loading and storing any 4103 // arguments that may not fit in the registers available for argument 4104 // passing. 4105 SDValue StackPtr; 4106 if (isPPC64) 4107 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 4108 else 4109 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 4110 4111 // Figure out which arguments are going to go in registers, and which in 4112 // memory. Also, if this is a vararg function, floating point operations 4113 // must be stored to our stack, and loaded into integer regs as well, if 4114 // any integer regs are available for argument passing. 4115 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); 4116 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 4117 4118 static const uint16_t GPR_32[] = { // 32-bit registers. 4119 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 4120 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 4121 }; 4122 static const uint16_t GPR_64[] = { // 64-bit registers. 4123 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 4124 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 4125 }; 4126 static const uint16_t *FPR = GetFPR(); 4127 4128 static const uint16_t VR[] = { 4129 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 4130 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 4131 }; 4132 const unsigned NumGPRs = array_lengthof(GPR_32); 4133 const unsigned NumFPRs = 13; 4134 const unsigned NumVRs = array_lengthof(VR); 4135 4136 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32; 4137 4138 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 4139 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 4140 4141 SmallVector<SDValue, 8> MemOpChains; 4142 for (unsigned i = 0; i != NumOps; ++i) { 4143 SDValue Arg = OutVals[i]; 4144 ISD::ArgFlagsTy Flags = Outs[i].Flags; 4145 4146 // PtrOff will be used to store the current argument to the stack if a 4147 // register cannot be found for it. 4148 SDValue PtrOff; 4149 4150 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 4151 4152 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 4153 4154 // On PPC64, promote integers to 64-bit values. 4155 if (isPPC64 && Arg.getValueType() == MVT::i32) { 4156 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 4157 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 4158 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 4159 } 4160 4161 // FIXME memcpy is used way more than necessary. Correctness first. 4162 // Note: "by value" is code for passing a structure by value, not 4163 // basic types. 4164 if (Flags.isByVal()) { 4165 unsigned Size = Flags.getByValSize(); 4166 // Very small objects are passed right-justified. Everything else is 4167 // passed left-justified. 4168 if (Size==1 || Size==2) { 4169 EVT VT = (Size==1) ? MVT::i8 : MVT::i16; 4170 if (GPR_idx != NumGPRs) { 4171 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, 4172 MachinePointerInfo(), VT, 4173 false, false, 0); 4174 MemOpChains.push_back(Load.getValue(1)); 4175 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4176 4177 ArgOffset += PtrByteSize; 4178 } else { 4179 SDValue Const = DAG.getConstant(PtrByteSize - Size, 4180 PtrOff.getValueType()); 4181 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 4182 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, 4183 CallSeqStart, 4184 Flags, DAG, dl); 4185 ArgOffset += PtrByteSize; 4186 } 4187 continue; 4188 } 4189 // Copy entire object into memory. There are cases where gcc-generated 4190 // code assumes it is there, even if it could be put entirely into 4191 // registers. (This is not what the doc says.) 4192 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff, 4193 CallSeqStart, 4194 Flags, DAG, dl); 4195 4196 // For small aggregates (Darwin only) and aggregates >= PtrByteSize, 4197 // copy the pieces of the object that fit into registers from the 4198 // parameter save area. 4199 for (unsigned j=0; j<Size; j+=PtrByteSize) { 4200 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 4201 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 4202 if (GPR_idx != NumGPRs) { 4203 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 4204 MachinePointerInfo(), 4205 false, false, false, 0); 4206 MemOpChains.push_back(Load.getValue(1)); 4207 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4208 ArgOffset += PtrByteSize; 4209 } else { 4210 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 4211 break; 4212 } 4213 } 4214 continue; 4215 } 4216 4217 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 4218 default: llvm_unreachable("Unexpected ValueType for argument!"); 4219 case MVT::i32: 4220 case MVT::i64: 4221 if (GPR_idx != NumGPRs) { 4222 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 4223 } else { 4224 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4225 isPPC64, isTailCall, false, MemOpChains, 4226 TailCallArguments, dl); 4227 } 4228 ArgOffset += PtrByteSize; 4229 break; 4230 case MVT::f32: 4231 case MVT::f64: 4232 if (FPR_idx != NumFPRs) { 4233 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 4234 4235 if (isVarArg) { 4236 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 4237 MachinePointerInfo(), false, false, 0); 4238 MemOpChains.push_back(Store); 4239 4240 // Float varargs are always shadowed in available integer registers 4241 if (GPR_idx != NumGPRs) { 4242 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 4243 MachinePointerInfo(), false, false, 4244 false, 0); 4245 MemOpChains.push_back(Load.getValue(1)); 4246 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4247 } 4248 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 4249 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 4250 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 4251 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 4252 MachinePointerInfo(), 4253 false, false, false, 0); 4254 MemOpChains.push_back(Load.getValue(1)); 4255 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4256 } 4257 } else { 4258 // If we have any FPRs remaining, we may also have GPRs remaining. 4259 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 4260 // GPRs. 4261 if (GPR_idx != NumGPRs) 4262 ++GPR_idx; 4263 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 4264 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 4265 ++GPR_idx; 4266 } 4267 } else 4268 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4269 isPPC64, isTailCall, false, MemOpChains, 4270 TailCallArguments, dl); 4271 if (isPPC64) 4272 ArgOffset += 8; 4273 else 4274 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 4275 break; 4276 case MVT::v4f32: 4277 case MVT::v4i32: 4278 case MVT::v8i16: 4279 case MVT::v16i8: 4280 if (isVarArg) { 4281 // These go aligned on the stack, or in the corresponding R registers 4282 // when within range. The Darwin PPC ABI doc claims they also go in 4283 // V registers; in fact gcc does this only for arguments that are 4284 // prototyped, not for those that match the ... We do it for all 4285 // arguments, seems to work. 4286 while (ArgOffset % 16 !=0) { 4287 ArgOffset += PtrByteSize; 4288 if (GPR_idx != NumGPRs) 4289 GPR_idx++; 4290 } 4291 // We could elide this store in the case where the object fits 4292 // entirely in R registers. Maybe later. 4293 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 4294 DAG.getConstant(ArgOffset, PtrVT)); 4295 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 4296 MachinePointerInfo(), false, false, 0); 4297 MemOpChains.push_back(Store); 4298 if (VR_idx != NumVRs) { 4299 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, 4300 MachinePointerInfo(), 4301 false, false, false, 0); 4302 MemOpChains.push_back(Load.getValue(1)); 4303 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 4304 } 4305 ArgOffset += 16; 4306 for (unsigned i=0; i<16; i+=PtrByteSize) { 4307 if (GPR_idx == NumGPRs) 4308 break; 4309 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 4310 DAG.getConstant(i, PtrVT)); 4311 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(), 4312 false, false, false, 0); 4313 MemOpChains.push_back(Load.getValue(1)); 4314 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4315 } 4316 break; 4317 } 4318 4319 // Non-varargs Altivec params generally go in registers, but have 4320 // stack space allocated at the end. 4321 if (VR_idx != NumVRs) { 4322 // Doesn't have GPR space allocated. 4323 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 4324 } else if (nAltivecParamsAtEnd==0) { 4325 // We are emitting Altivec params in order. 4326 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4327 isPPC64, isTailCall, true, MemOpChains, 4328 TailCallArguments, dl); 4329 ArgOffset += 16; 4330 } 4331 break; 4332 } 4333 } 4334 // If all Altivec parameters fit in registers, as they usually do, 4335 // they get stack space following the non-Altivec parameters. We 4336 // don't track this here because nobody below needs it. 4337 // If there are more Altivec parameters than fit in registers emit 4338 // the stores here. 4339 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) { 4340 unsigned j = 0; 4341 // Offset is aligned; skip 1st 12 params which go in V registers. 4342 ArgOffset = ((ArgOffset+15)/16)*16; 4343 ArgOffset += 12*16; 4344 for (unsigned i = 0; i != NumOps; ++i) { 4345 SDValue Arg = OutVals[i]; 4346 EVT ArgType = Outs[i].VT; 4347 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || 4348 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { 4349 if (++j > NumVRs) { 4350 SDValue PtrOff; 4351 // We are emitting Altivec params in order. 4352 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4353 isPPC64, isTailCall, true, MemOpChains, 4354 TailCallArguments, dl); 4355 ArgOffset += 16; 4356 } 4357 } 4358 } 4359 } 4360 4361 if (!MemOpChains.empty()) 4362 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 4363 &MemOpChains[0], MemOpChains.size()); 4364 4365 // On Darwin, R12 must contain the address of an indirect callee. This does 4366 // not mean the MTCTR instruction must use R12; it's easier to model this as 4367 // an extra parameter, so do that. 4368 if (!isTailCall && 4369 !dyn_cast<GlobalAddressSDNode>(Callee) && 4370 !dyn_cast<ExternalSymbolSDNode>(Callee) && 4371 !isBLACompatibleAddress(Callee, DAG)) 4372 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 : 4373 PPC::R12), Callee)); 4374 4375 // Build a sequence of copy-to-reg nodes chained together with token chain 4376 // and flag operands which copy the outgoing args into the appropriate regs. 4377 SDValue InFlag; 4378 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 4379 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 4380 RegsToPass[i].second, InFlag); 4381 InFlag = Chain.getValue(1); 4382 } 4383 4384 if (isTailCall) 4385 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp, 4386 FPOp, true, TailCallArguments); 4387 4388 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 4389 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 4390 Ins, InVals); 4391} 4392 4393bool 4394PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 4395 MachineFunction &MF, bool isVarArg, 4396 const SmallVectorImpl<ISD::OutputArg> &Outs, 4397 LLVMContext &Context) const { 4398 SmallVector<CCValAssign, 16> RVLocs; 4399 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 4400 RVLocs, Context); 4401 return CCInfo.CheckReturn(Outs, RetCC_PPC); 4402} 4403 4404SDValue 4405PPCTargetLowering::LowerReturn(SDValue Chain, 4406 CallingConv::ID CallConv, bool isVarArg, 4407 const SmallVectorImpl<ISD::OutputArg> &Outs, 4408 const SmallVectorImpl<SDValue> &OutVals, 4409 DebugLoc dl, SelectionDAG &DAG) const { 4410 4411 SmallVector<CCValAssign, 16> RVLocs; 4412 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 4413 getTargetMachine(), RVLocs, *DAG.getContext()); 4414 CCInfo.AnalyzeReturn(Outs, RetCC_PPC); 4415 4416 SDValue Flag; 4417 SmallVector<SDValue, 4> RetOps(1, Chain); 4418 4419 // Copy the result values into the output registers. 4420 for (unsigned i = 0; i != RVLocs.size(); ++i) { 4421 CCValAssign &VA = RVLocs[i]; 4422 assert(VA.isRegLoc() && "Can only return in registers!"); 4423 4424 SDValue Arg = OutVals[i]; 4425 4426 switch (VA.getLocInfo()) { 4427 default: llvm_unreachable("Unknown loc info!"); 4428 case CCValAssign::Full: break; 4429 case CCValAssign::AExt: 4430 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 4431 break; 4432 case CCValAssign::ZExt: 4433 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 4434 break; 4435 case CCValAssign::SExt: 4436 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 4437 break; 4438 } 4439 4440 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 4441 Flag = Chain.getValue(1); 4442 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 4443 } 4444 4445 RetOps[0] = Chain; // Update chain. 4446 4447 // Add the flag if we have it. 4448 if (Flag.getNode()) 4449 RetOps.push_back(Flag); 4450 4451 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, 4452 &RetOps[0], RetOps.size()); 4453} 4454 4455SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 4456 const PPCSubtarget &Subtarget) const { 4457 // When we pop the dynamic allocation we need to restore the SP link. 4458 DebugLoc dl = Op.getDebugLoc(); 4459 4460 // Get the corect type for pointers. 4461 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4462 4463 // Construct the stack pointer operand. 4464 bool isPPC64 = Subtarget.isPPC64(); 4465 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; 4466 SDValue StackPtr = DAG.getRegister(SP, PtrVT); 4467 4468 // Get the operands for the STACKRESTORE. 4469 SDValue Chain = Op.getOperand(0); 4470 SDValue SaveSP = Op.getOperand(1); 4471 4472 // Load the old link SP. 4473 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, 4474 MachinePointerInfo(), 4475 false, false, false, 0); 4476 4477 // Restore the stack pointer. 4478 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); 4479 4480 // Store the old link SP. 4481 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(), 4482 false, false, 0); 4483} 4484 4485 4486 4487SDValue 4488PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { 4489 MachineFunction &MF = DAG.getMachineFunction(); 4490 bool isPPC64 = PPCSubTarget.isPPC64(); 4491 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 4492 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4493 4494 // Get current frame pointer save index. The users of this index will be 4495 // primarily DYNALLOC instructions. 4496 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 4497 int RASI = FI->getReturnAddrSaveIndex(); 4498 4499 // If the frame pointer save index hasn't been defined yet. 4500 if (!RASI) { 4501 // Find out what the fix offset of the frame pointer save area. 4502 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 4503 // Allocate the frame index for frame pointer save area. 4504 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true); 4505 // Save the result. 4506 FI->setReturnAddrSaveIndex(RASI); 4507 } 4508 return DAG.getFrameIndex(RASI, PtrVT); 4509} 4510 4511SDValue 4512PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { 4513 MachineFunction &MF = DAG.getMachineFunction(); 4514 bool isPPC64 = PPCSubTarget.isPPC64(); 4515 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 4516 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4517 4518 // Get current frame pointer save index. The users of this index will be 4519 // primarily DYNALLOC instructions. 4520 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 4521 int FPSI = FI->getFramePointerSaveIndex(); 4522 4523 // If the frame pointer save index hasn't been defined yet. 4524 if (!FPSI) { 4525 // Find out what the fix offset of the frame pointer save area. 4526 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, 4527 isDarwinABI); 4528 4529 // Allocate the frame index for frame pointer save area. 4530 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 4531 // Save the result. 4532 FI->setFramePointerSaveIndex(FPSI); 4533 } 4534 return DAG.getFrameIndex(FPSI, PtrVT); 4535} 4536 4537SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 4538 SelectionDAG &DAG, 4539 const PPCSubtarget &Subtarget) const { 4540 // Get the inputs. 4541 SDValue Chain = Op.getOperand(0); 4542 SDValue Size = Op.getOperand(1); 4543 DebugLoc dl = Op.getDebugLoc(); 4544 4545 // Get the corect type for pointers. 4546 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4547 // Negate the size. 4548 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, 4549 DAG.getConstant(0, PtrVT), Size); 4550 // Construct a node for the frame pointer save index. 4551 SDValue FPSIdx = getFramePointerFrameIndex(DAG); 4552 // Build a DYNALLOC node. 4553 SDValue Ops[3] = { Chain, NegSize, FPSIdx }; 4554 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 4555 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3); 4556} 4557 4558/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 4559/// possible. 4560SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 4561 // Not FP? Not a fsel. 4562 if (!Op.getOperand(0).getValueType().isFloatingPoint() || 4563 !Op.getOperand(2).getValueType().isFloatingPoint()) 4564 return Op; 4565 4566 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 4567 4568 // Cannot handle SETEQ/SETNE. 4569 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op; 4570 4571 EVT ResVT = Op.getValueType(); 4572 EVT CmpVT = Op.getOperand(0).getValueType(); 4573 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4574 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); 4575 DebugLoc dl = Op.getDebugLoc(); 4576 4577 // If the RHS of the comparison is a 0.0, we don't need to do the 4578 // subtraction at all. 4579 if (isFloatingPointZero(RHS)) 4580 switch (CC) { 4581 default: break; // SETUO etc aren't handled by fsel. 4582 case ISD::SETULT: 4583 case ISD::SETLT: 4584 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 4585 case ISD::SETOGE: 4586 case ISD::SETGE: 4587 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 4588 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 4589 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); 4590 case ISD::SETUGT: 4591 case ISD::SETGT: 4592 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 4593 case ISD::SETOLE: 4594 case ISD::SETLE: 4595 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 4596 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 4597 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 4598 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); 4599 } 4600 4601 SDValue Cmp; 4602 switch (CC) { 4603 default: break; // SETUO etc aren't handled by fsel. 4604 case ISD::SETULT: 4605 case ISD::SETLT: 4606 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 4607 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4608 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4609 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 4610 case ISD::SETOGE: 4611 case ISD::SETGE: 4612 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 4613 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4614 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4615 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 4616 case ISD::SETUGT: 4617 case ISD::SETGT: 4618 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 4619 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4620 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4621 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 4622 case ISD::SETOLE: 4623 case ISD::SETLE: 4624 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 4625 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4626 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4627 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 4628 } 4629 return Op; 4630} 4631 4632// FIXME: Split this code up when LegalizeDAGTypes lands. 4633SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 4634 DebugLoc dl) const { 4635 assert(Op.getOperand(0).getValueType().isFloatingPoint()); 4636 SDValue Src = Op.getOperand(0); 4637 if (Src.getValueType() == MVT::f32) 4638 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); 4639 4640 SDValue Tmp; 4641 switch (Op.getValueType().getSimpleVT().SimpleTy) { 4642 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); 4643 case MVT::i32: 4644 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : 4645 PPCISD::FCTIDZ, 4646 dl, MVT::f64, Src); 4647 break; 4648 case MVT::i64: 4649 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src); 4650 break; 4651 } 4652 4653 // Convert the FP value to an int value through memory. 4654 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); 4655 4656 // Emit a store to the stack slot. 4657 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, 4658 MachinePointerInfo(), false, false, 0); 4659 4660 // Result is a load from the stack slot. If loading 4 bytes, make sure to 4661 // add in a bias. 4662 if (Op.getValueType() == MVT::i32) 4663 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, 4664 DAG.getConstant(4, FIPtr.getValueType())); 4665 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(), 4666 false, false, false, 0); 4667} 4668 4669SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, 4670 SelectionDAG &DAG) const { 4671 DebugLoc dl = Op.getDebugLoc(); 4672 // Don't handle ppc_fp128 here; let it be lowered to a libcall. 4673 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) 4674 return SDValue(); 4675 4676 if (Op.getOperand(0).getValueType() == MVT::i64) { 4677 SDValue SINT = Op.getOperand(0); 4678 // When converting to single-precision, we actually need to convert 4679 // to double-precision first and then round to single-precision. 4680 // To avoid double-rounding effects during that operation, we have 4681 // to prepare the input operand. Bits that might be truncated when 4682 // converting to double-precision are replaced by a bit that won't 4683 // be lost at this stage, but is below the single-precision rounding 4684 // position. 4685 // 4686 // However, if -enable-unsafe-fp-math is in effect, accept double 4687 // rounding to avoid the extra overhead. 4688 if (Op.getValueType() == MVT::f32 && 4689 !DAG.getTarget().Options.UnsafeFPMath) { 4690 4691 // Twiddle input to make sure the low 11 bits are zero. (If this 4692 // is the case, we are guaranteed the value will fit into the 53 bit 4693 // mantissa of an IEEE double-precision value without rounding.) 4694 // If any of those low 11 bits were not zero originally, make sure 4695 // bit 12 (value 2048) is set instead, so that the final rounding 4696 // to single-precision gets the correct result. 4697 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64, 4698 SINT, DAG.getConstant(2047, MVT::i64)); 4699 Round = DAG.getNode(ISD::ADD, dl, MVT::i64, 4700 Round, DAG.getConstant(2047, MVT::i64)); 4701 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT); 4702 Round = DAG.getNode(ISD::AND, dl, MVT::i64, 4703 Round, DAG.getConstant(-2048, MVT::i64)); 4704 4705 // However, we cannot use that value unconditionally: if the magnitude 4706 // of the input value is small, the bit-twiddling we did above might 4707 // end up visibly changing the output. Fortunately, in that case, we 4708 // don't need to twiddle bits since the original input will convert 4709 // exactly to double-precision floating-point already. Therefore, 4710 // construct a conditional to use the original value if the top 11 4711 // bits are all sign-bit copies, and use the rounded value computed 4712 // above otherwise. 4713 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64, 4714 SINT, DAG.getConstant(53, MVT::i32)); 4715 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64, 4716 Cond, DAG.getConstant(1, MVT::i64)); 4717 Cond = DAG.getSetCC(dl, MVT::i32, 4718 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT); 4719 4720 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT); 4721 } 4722 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT); 4723 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); 4724 if (Op.getValueType() == MVT::f32) 4725 FP = DAG.getNode(ISD::FP_ROUND, dl, 4726 MVT::f32, FP, DAG.getIntPtrConstant(0)); 4727 return FP; 4728 } 4729 4730 assert(Op.getOperand(0).getValueType() == MVT::i32 && 4731 "Unhandled SINT_TO_FP type in custom expander!"); 4732 // Since we only generate this in 64-bit mode, we can take advantage of 4733 // 64-bit registers. In particular, sign extend the input value into the 4734 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 4735 // then lfd it and fcfid it. 4736 MachineFunction &MF = DAG.getMachineFunction(); 4737 MachineFrameInfo *FrameInfo = MF.getFrameInfo(); 4738 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false); 4739 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4740 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 4741 4742 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32, 4743 Op.getOperand(0)); 4744 4745 // STD the extended value into the stack slot. 4746 MachineMemOperand *MMO = 4747 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 4748 MachineMemOperand::MOStore, 8, 8); 4749 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx }; 4750 SDValue Store = 4751 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other), 4752 Ops, 4, MVT::i64, MMO); 4753 // Load the value as a double. 4754 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(), 4755 false, false, false, 0); 4756 4757 // FCFID it and return it. 4758 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); 4759 if (Op.getValueType() == MVT::f32) 4760 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); 4761 return FP; 4762} 4763 4764SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 4765 SelectionDAG &DAG) const { 4766 DebugLoc dl = Op.getDebugLoc(); 4767 /* 4768 The rounding mode is in bits 30:31 of FPSR, and has the following 4769 settings: 4770 00 Round to nearest 4771 01 Round to 0 4772 10 Round to +inf 4773 11 Round to -inf 4774 4775 FLT_ROUNDS, on the other hand, expects the following: 4776 -1 Undefined 4777 0 Round to 0 4778 1 Round to nearest 4779 2 Round to +inf 4780 3 Round to -inf 4781 4782 To perform the conversion, we do: 4783 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 4784 */ 4785 4786 MachineFunction &MF = DAG.getMachineFunction(); 4787 EVT VT = Op.getValueType(); 4788 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4789 std::vector<EVT> NodeTys; 4790 SDValue MFFSreg, InFlag; 4791 4792 // Save FP Control Word to register 4793 NodeTys.push_back(MVT::f64); // return register 4794 NodeTys.push_back(MVT::Glue); // unused in this context 4795 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 4796 4797 // Save FP register to stack slot 4798 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 4799 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 4800 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, 4801 StackSlot, MachinePointerInfo(), false, false,0); 4802 4803 // Load FP Control Word from low 32 bits of stack slot. 4804 SDValue Four = DAG.getConstant(4, PtrVT); 4805 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); 4806 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(), 4807 false, false, false, 0); 4808 4809 // Transform as necessary 4810 SDValue CWD1 = 4811 DAG.getNode(ISD::AND, dl, MVT::i32, 4812 CWD, DAG.getConstant(3, MVT::i32)); 4813 SDValue CWD2 = 4814 DAG.getNode(ISD::SRL, dl, MVT::i32, 4815 DAG.getNode(ISD::AND, dl, MVT::i32, 4816 DAG.getNode(ISD::XOR, dl, MVT::i32, 4817 CWD, DAG.getConstant(3, MVT::i32)), 4818 DAG.getConstant(3, MVT::i32)), 4819 DAG.getConstant(1, MVT::i32)); 4820 4821 SDValue RetVal = 4822 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); 4823 4824 return DAG.getNode((VT.getSizeInBits() < 16 ? 4825 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 4826} 4827 4828SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const { 4829 EVT VT = Op.getValueType(); 4830 unsigned BitWidth = VT.getSizeInBits(); 4831 DebugLoc dl = Op.getDebugLoc(); 4832 assert(Op.getNumOperands() == 3 && 4833 VT == Op.getOperand(1).getValueType() && 4834 "Unexpected SHL!"); 4835 4836 // Expand into a bunch of logical ops. Note that these ops 4837 // depend on the PPC behavior for oversized shift amounts. 4838 SDValue Lo = Op.getOperand(0); 4839 SDValue Hi = Op.getOperand(1); 4840 SDValue Amt = Op.getOperand(2); 4841 EVT AmtVT = Amt.getValueType(); 4842 4843 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 4844 DAG.getConstant(BitWidth, AmtVT), Amt); 4845 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); 4846 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); 4847 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); 4848 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 4849 DAG.getConstant(-BitWidth, AmtVT)); 4850 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); 4851 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 4852 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); 4853 SDValue OutOps[] = { OutLo, OutHi }; 4854 return DAG.getMergeValues(OutOps, 2, dl); 4855} 4856 4857SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const { 4858 EVT VT = Op.getValueType(); 4859 DebugLoc dl = Op.getDebugLoc(); 4860 unsigned BitWidth = VT.getSizeInBits(); 4861 assert(Op.getNumOperands() == 3 && 4862 VT == Op.getOperand(1).getValueType() && 4863 "Unexpected SRL!"); 4864 4865 // Expand into a bunch of logical ops. Note that these ops 4866 // depend on the PPC behavior for oversized shift amounts. 4867 SDValue Lo = Op.getOperand(0); 4868 SDValue Hi = Op.getOperand(1); 4869 SDValue Amt = Op.getOperand(2); 4870 EVT AmtVT = Amt.getValueType(); 4871 4872 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 4873 DAG.getConstant(BitWidth, AmtVT), Amt); 4874 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 4875 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 4876 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 4877 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 4878 DAG.getConstant(-BitWidth, AmtVT)); 4879 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); 4880 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 4881 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); 4882 SDValue OutOps[] = { OutLo, OutHi }; 4883 return DAG.getMergeValues(OutOps, 2, dl); 4884} 4885 4886SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const { 4887 DebugLoc dl = Op.getDebugLoc(); 4888 EVT VT = Op.getValueType(); 4889 unsigned BitWidth = VT.getSizeInBits(); 4890 assert(Op.getNumOperands() == 3 && 4891 VT == Op.getOperand(1).getValueType() && 4892 "Unexpected SRA!"); 4893 4894 // Expand into a bunch of logical ops, followed by a select_cc. 4895 SDValue Lo = Op.getOperand(0); 4896 SDValue Hi = Op.getOperand(1); 4897 SDValue Amt = Op.getOperand(2); 4898 EVT AmtVT = Amt.getValueType(); 4899 4900 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 4901 DAG.getConstant(BitWidth, AmtVT), Amt); 4902 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 4903 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 4904 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 4905 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 4906 DAG.getConstant(-BitWidth, AmtVT)); 4907 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); 4908 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); 4909 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), 4910 Tmp4, Tmp6, ISD::SETLE); 4911 SDValue OutOps[] = { OutLo, OutHi }; 4912 return DAG.getMergeValues(OutOps, 2, dl); 4913} 4914 4915//===----------------------------------------------------------------------===// 4916// Vector related lowering. 4917// 4918 4919/// BuildSplatI - Build a canonical splati of Val with an element size of 4920/// SplatSize. Cast the result to VT. 4921static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT, 4922 SelectionDAG &DAG, DebugLoc dl) { 4923 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 4924 4925 static const EVT VTys[] = { // canonical VT to use for each size. 4926 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 4927 }; 4928 4929 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 4930 4931 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 4932 if (Val == -1) 4933 SplatSize = 1; 4934 4935 EVT CanonicalVT = VTys[SplatSize-1]; 4936 4937 // Build a canonical splat for this value. 4938 SDValue Elt = DAG.getConstant(Val, MVT::i32); 4939 SmallVector<SDValue, 8> Ops; 4940 Ops.assign(CanonicalVT.getVectorNumElements(), Elt); 4941 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, 4942 &Ops[0], Ops.size()); 4943 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res); 4944} 4945 4946/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 4947/// specified intrinsic ID. 4948static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, 4949 SelectionDAG &DAG, DebugLoc dl, 4950 EVT DestVT = MVT::Other) { 4951 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 4952 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4953 DAG.getConstant(IID, MVT::i32), LHS, RHS); 4954} 4955 4956/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 4957/// specified intrinsic ID. 4958static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, 4959 SDValue Op2, SelectionDAG &DAG, 4960 DebugLoc dl, EVT DestVT = MVT::Other) { 4961 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 4962 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4963 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 4964} 4965 4966 4967/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 4968/// amount. The result has the specified value type. 4969static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, 4970 EVT VT, SelectionDAG &DAG, DebugLoc dl) { 4971 // Force LHS/RHS to be the right type. 4972 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS); 4973 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS); 4974 4975 int Ops[16]; 4976 for (unsigned i = 0; i != 16; ++i) 4977 Ops[i] = i + Amt; 4978 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); 4979 return DAG.getNode(ISD::BITCAST, dl, VT, T); 4980} 4981 4982// If this is a case we can't handle, return null and let the default 4983// expansion code take care of it. If we CAN select this case, and if it 4984// selects to a single instruction, return Op. Otherwise, if we can codegen 4985// this case more efficiently than a constant pool load, lower it to the 4986// sequence of ops that should be used. 4987SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, 4988 SelectionDAG &DAG) const { 4989 DebugLoc dl = Op.getDebugLoc(); 4990 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 4991 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR"); 4992 4993 // Check if this is a splat of a constant value. 4994 APInt APSplatBits, APSplatUndef; 4995 unsigned SplatBitSize; 4996 bool HasAnyUndefs; 4997 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize, 4998 HasAnyUndefs, 0, true) || SplatBitSize > 32) 4999 return SDValue(); 5000 5001 unsigned SplatBits = APSplatBits.getZExtValue(); 5002 unsigned SplatUndef = APSplatUndef.getZExtValue(); 5003 unsigned SplatSize = SplatBitSize / 8; 5004 5005 // First, handle single instruction cases. 5006 5007 // All zeros? 5008 if (SplatBits == 0) { 5009 // Canonicalize all zero vectors to be v4i32. 5010 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 5011 SDValue Z = DAG.getConstant(0, MVT::i32); 5012 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); 5013 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z); 5014 } 5015 return Op; 5016 } 5017 5018 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 5019 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >> 5020 (32-SplatBitSize)); 5021 if (SextVal >= -16 && SextVal <= 15) 5022 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl); 5023 5024 5025 // Two instruction sequences. 5026 5027 // If this value is in the range [-32,30] and is even, use: 5028 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2) 5029 // If this value is in the range [17,31] and is odd, use: 5030 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16) 5031 // If this value is in the range [-31,-17] and is odd, use: 5032 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16) 5033 // Note the last two are three-instruction sequences. 5034 if (SextVal >= -32 && SextVal <= 31) { 5035 // To avoid having these optimizations undone by constant folding, 5036 // we convert to a pseudo that will be expanded later into one of 5037 // the above forms. 5038 SDValue Elt = DAG.getConstant(SextVal, MVT::i32); 5039 EVT VT = Op.getValueType(); 5040 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4); 5041 SDValue EltSize = DAG.getConstant(Size, MVT::i32); 5042 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize); 5043 } 5044 5045 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 5046 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 5047 // for fneg/fabs. 5048 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 5049 // Make -1 and vspltisw -1: 5050 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); 5051 5052 // Make the VSLW intrinsic, computing 0x8000_0000. 5053 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 5054 OnesV, DAG, dl); 5055 5056 // xor by OnesV to invert it. 5057 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); 5058 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5059 } 5060 5061 // Check to see if this is a wide variety of vsplti*, binop self cases. 5062 static const signed char SplatCsts[] = { 5063 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 5064 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 5065 }; 5066 5067 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 5068 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 5069 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 5070 int i = SplatCsts[idx]; 5071 5072 // Figure out what shift amount will be used by altivec if shifted by i in 5073 // this splat size. 5074 unsigned TypeShiftAmt = i & (SplatBitSize-1); 5075 5076 // vsplti + shl self. 5077 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) { 5078 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5079 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5080 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 5081 Intrinsic::ppc_altivec_vslw 5082 }; 5083 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5084 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5085 } 5086 5087 // vsplti + srl self. 5088 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 5089 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5090 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5091 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 5092 Intrinsic::ppc_altivec_vsrw 5093 }; 5094 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5095 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5096 } 5097 5098 // vsplti + sra self. 5099 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 5100 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5101 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5102 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 5103 Intrinsic::ppc_altivec_vsraw 5104 }; 5105 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5106 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5107 } 5108 5109 // vsplti + rol self. 5110 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 5111 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 5112 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5113 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5114 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 5115 Intrinsic::ppc_altivec_vrlw 5116 }; 5117 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5118 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5119 } 5120 5121 // t = vsplti c, result = vsldoi t, t, 1 5122 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) { 5123 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 5124 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); 5125 } 5126 // t = vsplti c, result = vsldoi t, t, 2 5127 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) { 5128 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 5129 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); 5130 } 5131 // t = vsplti c, result = vsldoi t, t, 3 5132 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) { 5133 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 5134 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); 5135 } 5136 } 5137 5138 return SDValue(); 5139} 5140 5141/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 5142/// the specified operations to build the shuffle. 5143static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 5144 SDValue RHS, SelectionDAG &DAG, 5145 DebugLoc dl) { 5146 unsigned OpNum = (PFEntry >> 26) & 0x0F; 5147 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 5148 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 5149 5150 enum { 5151 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 5152 OP_VMRGHW, 5153 OP_VMRGLW, 5154 OP_VSPLTISW0, 5155 OP_VSPLTISW1, 5156 OP_VSPLTISW2, 5157 OP_VSPLTISW3, 5158 OP_VSLDOI4, 5159 OP_VSLDOI8, 5160 OP_VSLDOI12 5161 }; 5162 5163 if (OpNum == OP_COPY) { 5164 if (LHSID == (1*9+2)*9+3) return LHS; 5165 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 5166 return RHS; 5167 } 5168 5169 SDValue OpLHS, OpRHS; 5170 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 5171 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 5172 5173 int ShufIdxs[16]; 5174 switch (OpNum) { 5175 default: llvm_unreachable("Unknown i32 permute!"); 5176 case OP_VMRGHW: 5177 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 5178 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 5179 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 5180 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 5181 break; 5182 case OP_VMRGLW: 5183 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 5184 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 5185 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 5186 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 5187 break; 5188 case OP_VSPLTISW0: 5189 for (unsigned i = 0; i != 16; ++i) 5190 ShufIdxs[i] = (i&3)+0; 5191 break; 5192 case OP_VSPLTISW1: 5193 for (unsigned i = 0; i != 16; ++i) 5194 ShufIdxs[i] = (i&3)+4; 5195 break; 5196 case OP_VSPLTISW2: 5197 for (unsigned i = 0; i != 16; ++i) 5198 ShufIdxs[i] = (i&3)+8; 5199 break; 5200 case OP_VSPLTISW3: 5201 for (unsigned i = 0; i != 16; ++i) 5202 ShufIdxs[i] = (i&3)+12; 5203 break; 5204 case OP_VSLDOI4: 5205 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl); 5206 case OP_VSLDOI8: 5207 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl); 5208 case OP_VSLDOI12: 5209 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl); 5210 } 5211 EVT VT = OpLHS.getValueType(); 5212 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS); 5213 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS); 5214 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); 5215 return DAG.getNode(ISD::BITCAST, dl, VT, T); 5216} 5217 5218/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 5219/// is a shuffle we can handle in a single instruction, return it. Otherwise, 5220/// return the code it can be lowered into. Worst case, it can always be 5221/// lowered into a vperm. 5222SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 5223 SelectionDAG &DAG) const { 5224 DebugLoc dl = Op.getDebugLoc(); 5225 SDValue V1 = Op.getOperand(0); 5226 SDValue V2 = Op.getOperand(1); 5227 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5228 EVT VT = Op.getValueType(); 5229 5230 // Cases that are handled by instructions that take permute immediates 5231 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 5232 // selected by the instruction selector. 5233 if (V2.getOpcode() == ISD::UNDEF) { 5234 if (PPC::isSplatShuffleMask(SVOp, 1) || 5235 PPC::isSplatShuffleMask(SVOp, 2) || 5236 PPC::isSplatShuffleMask(SVOp, 4) || 5237 PPC::isVPKUWUMShuffleMask(SVOp, true) || 5238 PPC::isVPKUHUMShuffleMask(SVOp, true) || 5239 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 || 5240 PPC::isVMRGLShuffleMask(SVOp, 1, true) || 5241 PPC::isVMRGLShuffleMask(SVOp, 2, true) || 5242 PPC::isVMRGLShuffleMask(SVOp, 4, true) || 5243 PPC::isVMRGHShuffleMask(SVOp, 1, true) || 5244 PPC::isVMRGHShuffleMask(SVOp, 2, true) || 5245 PPC::isVMRGHShuffleMask(SVOp, 4, true)) { 5246 return Op; 5247 } 5248 } 5249 5250 // Altivec has a variety of "shuffle immediates" that take two vector inputs 5251 // and produce a fixed permutation. If any of these match, do not lower to 5252 // VPERM. 5253 if (PPC::isVPKUWUMShuffleMask(SVOp, false) || 5254 PPC::isVPKUHUMShuffleMask(SVOp, false) || 5255 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 || 5256 PPC::isVMRGLShuffleMask(SVOp, 1, false) || 5257 PPC::isVMRGLShuffleMask(SVOp, 2, false) || 5258 PPC::isVMRGLShuffleMask(SVOp, 4, false) || 5259 PPC::isVMRGHShuffleMask(SVOp, 1, false) || 5260 PPC::isVMRGHShuffleMask(SVOp, 2, false) || 5261 PPC::isVMRGHShuffleMask(SVOp, 4, false)) 5262 return Op; 5263 5264 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 5265 // perfect shuffle table to emit an optimal matching sequence. 5266 ArrayRef<int> PermMask = SVOp->getMask(); 5267 5268 unsigned PFIndexes[4]; 5269 bool isFourElementShuffle = true; 5270 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 5271 unsigned EltNo = 8; // Start out undef. 5272 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 5273 if (PermMask[i*4+j] < 0) 5274 continue; // Undef, ignore it. 5275 5276 unsigned ByteSource = PermMask[i*4+j]; 5277 if ((ByteSource & 3) != j) { 5278 isFourElementShuffle = false; 5279 break; 5280 } 5281 5282 if (EltNo == 8) { 5283 EltNo = ByteSource/4; 5284 } else if (EltNo != ByteSource/4) { 5285 isFourElementShuffle = false; 5286 break; 5287 } 5288 } 5289 PFIndexes[i] = EltNo; 5290 } 5291 5292 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 5293 // perfect shuffle vector to determine if it is cost effective to do this as 5294 // discrete instructions, or whether we should use a vperm. 5295 if (isFourElementShuffle) { 5296 // Compute the index in the perfect shuffle table. 5297 unsigned PFTableIndex = 5298 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 5299 5300 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 5301 unsigned Cost = (PFEntry >> 30); 5302 5303 // Determining when to avoid vperm is tricky. Many things affect the cost 5304 // of vperm, particularly how many times the perm mask needs to be computed. 5305 // For example, if the perm mask can be hoisted out of a loop or is already 5306 // used (perhaps because there are multiple permutes with the same shuffle 5307 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 5308 // the loop requires an extra register. 5309 // 5310 // As a compromise, we only emit discrete instructions if the shuffle can be 5311 // generated in 3 or fewer operations. When we have loop information 5312 // available, if this block is within a loop, we should avoid using vperm 5313 // for 3-operation perms and use a constant pool load instead. 5314 if (Cost < 3) 5315 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 5316 } 5317 5318 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 5319 // vector that will get spilled to the constant pool. 5320 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 5321 5322 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 5323 // that it is in input element units, not in bytes. Convert now. 5324 EVT EltVT = V1.getValueType().getVectorElementType(); 5325 unsigned BytesPerElement = EltVT.getSizeInBits()/8; 5326 5327 SmallVector<SDValue, 16> ResultMask; 5328 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { 5329 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i]; 5330 5331 for (unsigned j = 0; j != BytesPerElement; ++j) 5332 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 5333 MVT::i32)); 5334 } 5335 5336 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, 5337 &ResultMask[0], ResultMask.size()); 5338 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); 5339} 5340 5341/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 5342/// altivec comparison. If it is, return true and fill in Opc/isDot with 5343/// information about the intrinsic. 5344static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, 5345 bool &isDot) { 5346 unsigned IntrinsicID = 5347 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue(); 5348 CompareOpc = -1; 5349 isDot = false; 5350 switch (IntrinsicID) { 5351 default: return false; 5352 // Comparison predicates. 5353 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 5354 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 5355 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 5356 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 5357 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 5358 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 5359 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 5360 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 5361 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 5362 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 5363 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 5364 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 5365 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 5366 5367 // Normal Comparisons. 5368 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 5369 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 5370 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 5371 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 5372 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 5373 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 5374 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 5375 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 5376 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 5377 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 5378 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 5379 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 5380 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 5381 } 5382 return true; 5383} 5384 5385/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 5386/// lower, do it, otherwise return null. 5387SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 5388 SelectionDAG &DAG) const { 5389 // If this is a lowered altivec predicate compare, CompareOpc is set to the 5390 // opcode number of the comparison. 5391 DebugLoc dl = Op.getDebugLoc(); 5392 int CompareOpc; 5393 bool isDot; 5394 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 5395 return SDValue(); // Don't custom lower most intrinsics. 5396 5397 // If this is a non-dot comparison, make the VCMP node and we are done. 5398 if (!isDot) { 5399 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), 5400 Op.getOperand(1), Op.getOperand(2), 5401 DAG.getConstant(CompareOpc, MVT::i32)); 5402 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp); 5403 } 5404 5405 // Create the PPCISD altivec 'dot' comparison node. 5406 SDValue Ops[] = { 5407 Op.getOperand(2), // LHS 5408 Op.getOperand(3), // RHS 5409 DAG.getConstant(CompareOpc, MVT::i32) 5410 }; 5411 std::vector<EVT> VTs; 5412 VTs.push_back(Op.getOperand(2).getValueType()); 5413 VTs.push_back(MVT::Glue); 5414 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 5415 5416 // Now that we have the comparison, emit a copy from the CR to a GPR. 5417 // This is flagged to the above dot comparison. 5418 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32, 5419 DAG.getRegister(PPC::CR6, MVT::i32), 5420 CompNode.getValue(1)); 5421 5422 // Unpack the result based on how the target uses it. 5423 unsigned BitNo; // Bit # of CR6. 5424 bool InvertBit; // Invert result? 5425 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) { 5426 default: // Can't happen, don't crash on invalid number though. 5427 case 0: // Return the value of the EQ bit of CR6. 5428 BitNo = 0; InvertBit = false; 5429 break; 5430 case 1: // Return the inverted value of the EQ bit of CR6. 5431 BitNo = 0; InvertBit = true; 5432 break; 5433 case 2: // Return the value of the LT bit of CR6. 5434 BitNo = 2; InvertBit = false; 5435 break; 5436 case 3: // Return the inverted value of the LT bit of CR6. 5437 BitNo = 2; InvertBit = true; 5438 break; 5439 } 5440 5441 // Shift the bit into the low position. 5442 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, 5443 DAG.getConstant(8-(3-BitNo), MVT::i32)); 5444 // Isolate the bit. 5445 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, 5446 DAG.getConstant(1, MVT::i32)); 5447 5448 // If we are supposed to, toggle the bit. 5449 if (InvertBit) 5450 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, 5451 DAG.getConstant(1, MVT::i32)); 5452 return Flags; 5453} 5454 5455SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, 5456 SelectionDAG &DAG) const { 5457 DebugLoc dl = Op.getDebugLoc(); 5458 // Create a stack slot that is 16-byte aligned. 5459 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 5460 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false); 5461 EVT PtrVT = getPointerTy(); 5462 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 5463 5464 // Store the input value into Value#0 of the stack slot. 5465 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 5466 Op.getOperand(0), FIdx, MachinePointerInfo(), 5467 false, false, 0); 5468 // Load it out. 5469 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(), 5470 false, false, false, 0); 5471} 5472 5473SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 5474 DebugLoc dl = Op.getDebugLoc(); 5475 if (Op.getValueType() == MVT::v4i32) { 5476 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 5477 5478 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); 5479 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. 5480 5481 SDValue RHSSwap = // = vrlw RHS, 16 5482 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); 5483 5484 // Shrinkify inputs to v8i16. 5485 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS); 5486 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS); 5487 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap); 5488 5489 // Low parts multiplied together, generating 32-bit results (we ignore the 5490 // top parts). 5491 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 5492 LHS, RHS, DAG, dl, MVT::v4i32); 5493 5494 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 5495 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); 5496 // Shift the high parts up 16 bits. 5497 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, 5498 Neg16, DAG, dl); 5499 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); 5500 } else if (Op.getValueType() == MVT::v8i16) { 5501 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 5502 5503 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); 5504 5505 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 5506 LHS, RHS, Zero, DAG, dl); 5507 } else if (Op.getValueType() == MVT::v16i8) { 5508 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 5509 5510 // Multiply the even 8-bit parts, producing 16-bit sums. 5511 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 5512 LHS, RHS, DAG, dl, MVT::v8i16); 5513 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts); 5514 5515 // Multiply the odd 8-bit parts, producing 16-bit sums. 5516 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 5517 LHS, RHS, DAG, dl, MVT::v8i16); 5518 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts); 5519 5520 // Merge the results together. 5521 int Ops[16]; 5522 for (unsigned i = 0; i != 8; ++i) { 5523 Ops[i*2 ] = 2*i+1; 5524 Ops[i*2+1] = 2*i+1+16; 5525 } 5526 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); 5527 } else { 5528 llvm_unreachable("Unknown mul to lower!"); 5529 } 5530} 5531 5532/// LowerOperation - Provide custom lowering hooks for some operations. 5533/// 5534SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 5535 switch (Op.getOpcode()) { 5536 default: llvm_unreachable("Wasn't expecting to be able to lower this!"); 5537 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 5538 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 5539 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 5540 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 5541 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 5542 case ISD::SETCC: return LowerSETCC(Op, DAG); 5543 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 5544 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 5545 case ISD::VASTART: 5546 return LowerVASTART(Op, DAG, PPCSubTarget); 5547 5548 case ISD::VAARG: 5549 return LowerVAARG(Op, DAG, PPCSubTarget); 5550 5551 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 5552 case ISD::DYNAMIC_STACKALLOC: 5553 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 5554 5555 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 5556 case ISD::FP_TO_UINT: 5557 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, 5558 Op.getDebugLoc()); 5559 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 5560 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 5561 5562 // Lower 64-bit shifts. 5563 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 5564 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 5565 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 5566 5567 // Vector-related lowering. 5568 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 5569 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 5570 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 5571 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 5572 case ISD::MUL: return LowerMUL(Op, DAG); 5573 5574 // Frame & Return address. 5575 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 5576 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 5577 } 5578} 5579 5580void PPCTargetLowering::ReplaceNodeResults(SDNode *N, 5581 SmallVectorImpl<SDValue>&Results, 5582 SelectionDAG &DAG) const { 5583 const TargetMachine &TM = getTargetMachine(); 5584 DebugLoc dl = N->getDebugLoc(); 5585 switch (N->getOpcode()) { 5586 default: 5587 llvm_unreachable("Do not know how to custom type legalize this operation!"); 5588 case ISD::VAARG: { 5589 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI() 5590 || TM.getSubtarget<PPCSubtarget>().isPPC64()) 5591 return; 5592 5593 EVT VT = N->getValueType(0); 5594 5595 if (VT == MVT::i64) { 5596 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget); 5597 5598 Results.push_back(NewNode); 5599 Results.push_back(NewNode.getValue(1)); 5600 } 5601 return; 5602 } 5603 case ISD::FP_ROUND_INREG: { 5604 assert(N->getValueType(0) == MVT::ppcf128); 5605 assert(N->getOperand(0).getValueType() == MVT::ppcf128); 5606 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 5607 MVT::f64, N->getOperand(0), 5608 DAG.getIntPtrConstant(0)); 5609 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 5610 MVT::f64, N->getOperand(0), 5611 DAG.getIntPtrConstant(1)); 5612 5613 // This sequence changes FPSCR to do round-to-zero, adds the two halves 5614 // of the long double, and puts FPSCR back the way it was. We do not 5615 // actually model FPSCR. 5616 std::vector<EVT> NodeTys; 5617 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg; 5618 5619 NodeTys.push_back(MVT::f64); // Return register 5620 NodeTys.push_back(MVT::Glue); // Returns a flag for later insns 5621 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 5622 MFFSreg = Result.getValue(0); 5623 InFlag = Result.getValue(1); 5624 5625 NodeTys.clear(); 5626 NodeTys.push_back(MVT::Glue); // Returns a flag 5627 Ops[0] = DAG.getConstant(31, MVT::i32); 5628 Ops[1] = InFlag; 5629 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2); 5630 InFlag = Result.getValue(0); 5631 5632 NodeTys.clear(); 5633 NodeTys.push_back(MVT::Glue); // Returns a flag 5634 Ops[0] = DAG.getConstant(30, MVT::i32); 5635 Ops[1] = InFlag; 5636 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2); 5637 InFlag = Result.getValue(0); 5638 5639 NodeTys.clear(); 5640 NodeTys.push_back(MVT::f64); // result of add 5641 NodeTys.push_back(MVT::Glue); // Returns a flag 5642 Ops[0] = Lo; 5643 Ops[1] = Hi; 5644 Ops[2] = InFlag; 5645 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3); 5646 FPreg = Result.getValue(0); 5647 InFlag = Result.getValue(1); 5648 5649 NodeTys.clear(); 5650 NodeTys.push_back(MVT::f64); 5651 Ops[0] = DAG.getConstant(1, MVT::i32); 5652 Ops[1] = MFFSreg; 5653 Ops[2] = FPreg; 5654 Ops[3] = InFlag; 5655 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4); 5656 FPreg = Result.getValue(0); 5657 5658 // We know the low half is about to be thrown away, so just use something 5659 // convenient. 5660 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, 5661 FPreg, FPreg)); 5662 return; 5663 } 5664 case ISD::FP_TO_SINT: 5665 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl)); 5666 return; 5667 } 5668} 5669 5670 5671//===----------------------------------------------------------------------===// 5672// Other Lowering Code 5673//===----------------------------------------------------------------------===// 5674 5675MachineBasicBlock * 5676PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 5677 bool is64bit, unsigned BinOpcode) const { 5678 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 5679 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5680 5681 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5682 MachineFunction *F = BB->getParent(); 5683 MachineFunction::iterator It = BB; 5684 ++It; 5685 5686 unsigned dest = MI->getOperand(0).getReg(); 5687 unsigned ptrA = MI->getOperand(1).getReg(); 5688 unsigned ptrB = MI->getOperand(2).getReg(); 5689 unsigned incr = MI->getOperand(3).getReg(); 5690 DebugLoc dl = MI->getDebugLoc(); 5691 5692 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 5693 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 5694 F->insert(It, loopMBB); 5695 F->insert(It, exitMBB); 5696 exitMBB->splice(exitMBB->begin(), BB, 5697 llvm::next(MachineBasicBlock::iterator(MI)), 5698 BB->end()); 5699 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5700 5701 MachineRegisterInfo &RegInfo = F->getRegInfo(); 5702 unsigned TmpReg = (!BinOpcode) ? incr : 5703 RegInfo.createVirtualRegister( 5704 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 5705 (const TargetRegisterClass *) &PPC::GPRCRegClass); 5706 5707 // thisMBB: 5708 // ... 5709 // fallthrough --> loopMBB 5710 BB->addSuccessor(loopMBB); 5711 5712 // loopMBB: 5713 // l[wd]arx dest, ptr 5714 // add r0, dest, incr 5715 // st[wd]cx. r0, ptr 5716 // bne- loopMBB 5717 // fallthrough --> exitMBB 5718 BB = loopMBB; 5719 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 5720 .addReg(ptrA).addReg(ptrB); 5721 if (BinOpcode) 5722 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); 5723 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 5724 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); 5725 BuildMI(BB, dl, TII->get(PPC::BCC)) 5726 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 5727 BB->addSuccessor(loopMBB); 5728 BB->addSuccessor(exitMBB); 5729 5730 // exitMBB: 5731 // ... 5732 BB = exitMBB; 5733 return BB; 5734} 5735 5736MachineBasicBlock * 5737PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, 5738 MachineBasicBlock *BB, 5739 bool is8bit, // operation 5740 unsigned BinOpcode) const { 5741 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 5742 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5743 // In 64 bit mode we have to use 64 bits for addresses, even though the 5744 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address 5745 // registers without caring whether they're 32 or 64, but here we're 5746 // doing actual arithmetic on the addresses. 5747 bool is64bit = PPCSubTarget.isPPC64(); 5748 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; 5749 5750 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5751 MachineFunction *F = BB->getParent(); 5752 MachineFunction::iterator It = BB; 5753 ++It; 5754 5755 unsigned dest = MI->getOperand(0).getReg(); 5756 unsigned ptrA = MI->getOperand(1).getReg(); 5757 unsigned ptrB = MI->getOperand(2).getReg(); 5758 unsigned incr = MI->getOperand(3).getReg(); 5759 DebugLoc dl = MI->getDebugLoc(); 5760 5761 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 5762 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 5763 F->insert(It, loopMBB); 5764 F->insert(It, exitMBB); 5765 exitMBB->splice(exitMBB->begin(), BB, 5766 llvm::next(MachineBasicBlock::iterator(MI)), 5767 BB->end()); 5768 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5769 5770 MachineRegisterInfo &RegInfo = F->getRegInfo(); 5771 const TargetRegisterClass *RC = 5772 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 5773 (const TargetRegisterClass *) &PPC::GPRCRegClass; 5774 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 5775 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 5776 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 5777 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC); 5778 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 5779 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 5780 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 5781 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 5782 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC); 5783 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 5784 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 5785 unsigned Ptr1Reg; 5786 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); 5787 5788 // thisMBB: 5789 // ... 5790 // fallthrough --> loopMBB 5791 BB->addSuccessor(loopMBB); 5792 5793 // The 4-byte load must be aligned, while a char or short may be 5794 // anywhere in the word. Hence all this nasty bookkeeping code. 5795 // add ptr1, ptrA, ptrB [copy if ptrA==0] 5796 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 5797 // xori shift, shift1, 24 [16] 5798 // rlwinm ptr, ptr1, 0, 0, 29 5799 // slw incr2, incr, shift 5800 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 5801 // slw mask, mask2, shift 5802 // loopMBB: 5803 // lwarx tmpDest, ptr 5804 // add tmp, tmpDest, incr2 5805 // andc tmp2, tmpDest, mask 5806 // and tmp3, tmp, mask 5807 // or tmp4, tmp3, tmp2 5808 // stwcx. tmp4, ptr 5809 // bne- loopMBB 5810 // fallthrough --> exitMBB 5811 // srw dest, tmpDest, shift 5812 if (ptrA != ZeroReg) { 5813 Ptr1Reg = RegInfo.createVirtualRegister(RC); 5814 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 5815 .addReg(ptrA).addReg(ptrB); 5816 } else { 5817 Ptr1Reg = ptrB; 5818 } 5819 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 5820 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 5821 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 5822 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 5823 if (is64bit) 5824 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 5825 .addReg(Ptr1Reg).addImm(0).addImm(61); 5826 else 5827 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 5828 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 5829 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg) 5830 .addReg(incr).addReg(ShiftReg); 5831 if (is8bit) 5832 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 5833 else { 5834 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 5835 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535); 5836 } 5837 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 5838 .addReg(Mask2Reg).addReg(ShiftReg); 5839 5840 BB = loopMBB; 5841 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 5842 .addReg(ZeroReg).addReg(PtrReg); 5843 if (BinOpcode) 5844 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) 5845 .addReg(Incr2Reg).addReg(TmpDestReg); 5846 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) 5847 .addReg(TmpDestReg).addReg(MaskReg); 5848 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) 5849 .addReg(TmpReg).addReg(MaskReg); 5850 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) 5851 .addReg(Tmp3Reg).addReg(Tmp2Reg); 5852 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 5853 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg); 5854 BuildMI(BB, dl, TII->get(PPC::BCC)) 5855 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 5856 BB->addSuccessor(loopMBB); 5857 BB->addSuccessor(exitMBB); 5858 5859 // exitMBB: 5860 // ... 5861 BB = exitMBB; 5862 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg) 5863 .addReg(ShiftReg); 5864 return BB; 5865} 5866 5867MachineBasicBlock * 5868PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 5869 MachineBasicBlock *BB) const { 5870 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5871 5872 // To "insert" these instructions we actually have to insert their 5873 // control-flow patterns. 5874 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5875 MachineFunction::iterator It = BB; 5876 ++It; 5877 5878 MachineFunction *F = BB->getParent(); 5879 5880 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 || 5881 MI->getOpcode() == PPC::SELECT_CC_I8)) { 5882 unsigned OpCode = MI->getOpcode() == PPC::SELECT_CC_I8 ? 5883 PPC::ISEL8 : PPC::ISEL; 5884 unsigned SelectPred = MI->getOperand(4).getImm(); 5885 DebugLoc dl = MI->getDebugLoc(); 5886 5887 // The SelectPred is ((BI << 5) | BO) for a BCC 5888 unsigned BO = SelectPred & 0xF; 5889 assert((BO == 12 || BO == 4) && "invalid predicate BO field for isel"); 5890 5891 unsigned TrueOpNo, FalseOpNo; 5892 if (BO == 12) { 5893 TrueOpNo = 2; 5894 FalseOpNo = 3; 5895 } else { 5896 TrueOpNo = 3; 5897 FalseOpNo = 2; 5898 SelectPred = PPC::InvertPredicate((PPC::Predicate)SelectPred); 5899 } 5900 5901 BuildMI(*BB, MI, dl, TII->get(OpCode), MI->getOperand(0).getReg()) 5902 .addReg(MI->getOperand(TrueOpNo).getReg()) 5903 .addReg(MI->getOperand(FalseOpNo).getReg()) 5904 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()); 5905 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 || 5906 MI->getOpcode() == PPC::SELECT_CC_I8 || 5907 MI->getOpcode() == PPC::SELECT_CC_F4 || 5908 MI->getOpcode() == PPC::SELECT_CC_F8 || 5909 MI->getOpcode() == PPC::SELECT_CC_VRRC) { 5910 5911 5912 // The incoming instruction knows the destination vreg to set, the 5913 // condition code register to branch on, the true/false values to 5914 // select between, and a branch opcode to use. 5915 5916 // thisMBB: 5917 // ... 5918 // TrueVal = ... 5919 // cmpTY ccX, r1, r2 5920 // bCC copy1MBB 5921 // fallthrough --> copy0MBB 5922 MachineBasicBlock *thisMBB = BB; 5923 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 5924 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 5925 unsigned SelectPred = MI->getOperand(4).getImm(); 5926 DebugLoc dl = MI->getDebugLoc(); 5927 F->insert(It, copy0MBB); 5928 F->insert(It, sinkMBB); 5929 5930 // Transfer the remainder of BB and its successor edges to sinkMBB. 5931 sinkMBB->splice(sinkMBB->begin(), BB, 5932 llvm::next(MachineBasicBlock::iterator(MI)), 5933 BB->end()); 5934 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 5935 5936 // Next, add the true and fallthrough blocks as its successors. 5937 BB->addSuccessor(copy0MBB); 5938 BB->addSuccessor(sinkMBB); 5939 5940 BuildMI(BB, dl, TII->get(PPC::BCC)) 5941 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 5942 5943 // copy0MBB: 5944 // %FalseValue = ... 5945 // # fallthrough to sinkMBB 5946 BB = copy0MBB; 5947 5948 // Update machine-CFG edges 5949 BB->addSuccessor(sinkMBB); 5950 5951 // sinkMBB: 5952 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 5953 // ... 5954 BB = sinkMBB; 5955 BuildMI(*BB, BB->begin(), dl, 5956 TII->get(PPC::PHI), MI->getOperand(0).getReg()) 5957 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 5958 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 5959 } 5960 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) 5961 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); 5962 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) 5963 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); 5964 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) 5965 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4); 5966 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) 5967 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8); 5968 5969 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8) 5970 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); 5971 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16) 5972 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); 5973 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32) 5974 BB = EmitAtomicBinary(MI, BB, false, PPC::AND); 5975 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64) 5976 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8); 5977 5978 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8) 5979 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); 5980 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16) 5981 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); 5982 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32) 5983 BB = EmitAtomicBinary(MI, BB, false, PPC::OR); 5984 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64) 5985 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8); 5986 5987 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) 5988 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); 5989 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) 5990 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); 5991 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) 5992 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR); 5993 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) 5994 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8); 5995 5996 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) 5997 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC); 5998 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) 5999 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC); 6000 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) 6001 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC); 6002 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) 6003 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8); 6004 6005 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) 6006 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); 6007 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) 6008 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); 6009 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) 6010 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF); 6011 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) 6012 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8); 6013 6014 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8) 6015 BB = EmitPartwordAtomicBinary(MI, BB, true, 0); 6016 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16) 6017 BB = EmitPartwordAtomicBinary(MI, BB, false, 0); 6018 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32) 6019 BB = EmitAtomicBinary(MI, BB, false, 0); 6020 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64) 6021 BB = EmitAtomicBinary(MI, BB, true, 0); 6022 6023 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || 6024 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) { 6025 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; 6026 6027 unsigned dest = MI->getOperand(0).getReg(); 6028 unsigned ptrA = MI->getOperand(1).getReg(); 6029 unsigned ptrB = MI->getOperand(2).getReg(); 6030 unsigned oldval = MI->getOperand(3).getReg(); 6031 unsigned newval = MI->getOperand(4).getReg(); 6032 DebugLoc dl = MI->getDebugLoc(); 6033 6034 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 6035 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 6036 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 6037 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 6038 F->insert(It, loop1MBB); 6039 F->insert(It, loop2MBB); 6040 F->insert(It, midMBB); 6041 F->insert(It, exitMBB); 6042 exitMBB->splice(exitMBB->begin(), BB, 6043 llvm::next(MachineBasicBlock::iterator(MI)), 6044 BB->end()); 6045 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 6046 6047 // thisMBB: 6048 // ... 6049 // fallthrough --> loopMBB 6050 BB->addSuccessor(loop1MBB); 6051 6052 // loop1MBB: 6053 // l[wd]arx dest, ptr 6054 // cmp[wd] dest, oldval 6055 // bne- midMBB 6056 // loop2MBB: 6057 // st[wd]cx. newval, ptr 6058 // bne- loopMBB 6059 // b exitBB 6060 // midMBB: 6061 // st[wd]cx. dest, ptr 6062 // exitBB: 6063 BB = loop1MBB; 6064 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 6065 .addReg(ptrA).addReg(ptrB); 6066 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) 6067 .addReg(oldval).addReg(dest); 6068 BuildMI(BB, dl, TII->get(PPC::BCC)) 6069 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 6070 BB->addSuccessor(loop2MBB); 6071 BB->addSuccessor(midMBB); 6072 6073 BB = loop2MBB; 6074 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 6075 .addReg(newval).addReg(ptrA).addReg(ptrB); 6076 BuildMI(BB, dl, TII->get(PPC::BCC)) 6077 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 6078 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 6079 BB->addSuccessor(loop1MBB); 6080 BB->addSuccessor(exitMBB); 6081 6082 BB = midMBB; 6083 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 6084 .addReg(dest).addReg(ptrA).addReg(ptrB); 6085 BB->addSuccessor(exitMBB); 6086 6087 // exitMBB: 6088 // ... 6089 BB = exitMBB; 6090 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || 6091 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { 6092 // We must use 64-bit registers for addresses when targeting 64-bit, 6093 // since we're actually doing arithmetic on them. Other registers 6094 // can be 32-bit. 6095 bool is64bit = PPCSubTarget.isPPC64(); 6096 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; 6097 6098 unsigned dest = MI->getOperand(0).getReg(); 6099 unsigned ptrA = MI->getOperand(1).getReg(); 6100 unsigned ptrB = MI->getOperand(2).getReg(); 6101 unsigned oldval = MI->getOperand(3).getReg(); 6102 unsigned newval = MI->getOperand(4).getReg(); 6103 DebugLoc dl = MI->getDebugLoc(); 6104 6105 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 6106 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 6107 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 6108 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 6109 F->insert(It, loop1MBB); 6110 F->insert(It, loop2MBB); 6111 F->insert(It, midMBB); 6112 F->insert(It, exitMBB); 6113 exitMBB->splice(exitMBB->begin(), BB, 6114 llvm::next(MachineBasicBlock::iterator(MI)), 6115 BB->end()); 6116 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 6117 6118 MachineRegisterInfo &RegInfo = F->getRegInfo(); 6119 const TargetRegisterClass *RC = 6120 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 6121 (const TargetRegisterClass *) &PPC::GPRCRegClass; 6122 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 6123 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 6124 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 6125 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC); 6126 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC); 6127 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC); 6128 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC); 6129 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 6130 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 6131 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 6132 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 6133 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 6134 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 6135 unsigned Ptr1Reg; 6136 unsigned TmpReg = RegInfo.createVirtualRegister(RC); 6137 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; 6138 // thisMBB: 6139 // ... 6140 // fallthrough --> loopMBB 6141 BB->addSuccessor(loop1MBB); 6142 6143 // The 4-byte load must be aligned, while a char or short may be 6144 // anywhere in the word. Hence all this nasty bookkeeping code. 6145 // add ptr1, ptrA, ptrB [copy if ptrA==0] 6146 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 6147 // xori shift, shift1, 24 [16] 6148 // rlwinm ptr, ptr1, 0, 0, 29 6149 // slw newval2, newval, shift 6150 // slw oldval2, oldval,shift 6151 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 6152 // slw mask, mask2, shift 6153 // and newval3, newval2, mask 6154 // and oldval3, oldval2, mask 6155 // loop1MBB: 6156 // lwarx tmpDest, ptr 6157 // and tmp, tmpDest, mask 6158 // cmpw tmp, oldval3 6159 // bne- midMBB 6160 // loop2MBB: 6161 // andc tmp2, tmpDest, mask 6162 // or tmp4, tmp2, newval3 6163 // stwcx. tmp4, ptr 6164 // bne- loop1MBB 6165 // b exitBB 6166 // midMBB: 6167 // stwcx. tmpDest, ptr 6168 // exitBB: 6169 // srw dest, tmpDest, shift 6170 if (ptrA != ZeroReg) { 6171 Ptr1Reg = RegInfo.createVirtualRegister(RC); 6172 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 6173 .addReg(ptrA).addReg(ptrB); 6174 } else { 6175 Ptr1Reg = ptrB; 6176 } 6177 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 6178 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 6179 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 6180 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 6181 if (is64bit) 6182 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 6183 .addReg(Ptr1Reg).addImm(0).addImm(61); 6184 else 6185 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 6186 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 6187 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) 6188 .addReg(newval).addReg(ShiftReg); 6189 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) 6190 .addReg(oldval).addReg(ShiftReg); 6191 if (is8bit) 6192 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 6193 else { 6194 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 6195 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) 6196 .addReg(Mask3Reg).addImm(65535); 6197 } 6198 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 6199 .addReg(Mask2Reg).addReg(ShiftReg); 6200 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg) 6201 .addReg(NewVal2Reg).addReg(MaskReg); 6202 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg) 6203 .addReg(OldVal2Reg).addReg(MaskReg); 6204 6205 BB = loop1MBB; 6206 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 6207 .addReg(ZeroReg).addReg(PtrReg); 6208 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) 6209 .addReg(TmpDestReg).addReg(MaskReg); 6210 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0) 6211 .addReg(TmpReg).addReg(OldVal3Reg); 6212 BuildMI(BB, dl, TII->get(PPC::BCC)) 6213 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 6214 BB->addSuccessor(loop2MBB); 6215 BB->addSuccessor(midMBB); 6216 6217 BB = loop2MBB; 6218 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg) 6219 .addReg(TmpDestReg).addReg(MaskReg); 6220 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg) 6221 .addReg(Tmp2Reg).addReg(NewVal3Reg); 6222 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg) 6223 .addReg(ZeroReg).addReg(PtrReg); 6224 BuildMI(BB, dl, TII->get(PPC::BCC)) 6225 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 6226 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 6227 BB->addSuccessor(loop1MBB); 6228 BB->addSuccessor(exitMBB); 6229 6230 BB = midMBB; 6231 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg) 6232 .addReg(ZeroReg).addReg(PtrReg); 6233 BB->addSuccessor(exitMBB); 6234 6235 // exitMBB: 6236 // ... 6237 BB = exitMBB; 6238 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg) 6239 .addReg(ShiftReg); 6240 } else { 6241 llvm_unreachable("Unexpected instr type to insert"); 6242 } 6243 6244 MI->eraseFromParent(); // The pseudo instruction is gone now. 6245 return BB; 6246} 6247 6248//===----------------------------------------------------------------------===// 6249// Target Optimization Hooks 6250//===----------------------------------------------------------------------===// 6251 6252SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, 6253 DAGCombinerInfo &DCI) const { 6254 const TargetMachine &TM = getTargetMachine(); 6255 SelectionDAG &DAG = DCI.DAG; 6256 DebugLoc dl = N->getDebugLoc(); 6257 switch (N->getOpcode()) { 6258 default: break; 6259 case PPCISD::SHL: 6260 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 6261 if (C->isNullValue()) // 0 << V -> 0. 6262 return N->getOperand(0); 6263 } 6264 break; 6265 case PPCISD::SRL: 6266 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 6267 if (C->isNullValue()) // 0 >>u V -> 0. 6268 return N->getOperand(0); 6269 } 6270 break; 6271 case PPCISD::SRA: 6272 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 6273 if (C->isNullValue() || // 0 >>s V -> 0. 6274 C->isAllOnesValue()) // -1 >>s V -> -1. 6275 return N->getOperand(0); 6276 } 6277 break; 6278 6279 case ISD::SINT_TO_FP: 6280 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 6281 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 6282 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 6283 // We allow the src/dst to be either f32/f64, but the intermediate 6284 // type must be i64. 6285 if (N->getOperand(0).getValueType() == MVT::i64 && 6286 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 6287 SDValue Val = N->getOperand(0).getOperand(0); 6288 if (Val.getValueType() == MVT::f32) { 6289 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 6290 DCI.AddToWorklist(Val.getNode()); 6291 } 6292 6293 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val); 6294 DCI.AddToWorklist(Val.getNode()); 6295 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val); 6296 DCI.AddToWorklist(Val.getNode()); 6297 if (N->getValueType(0) == MVT::f32) { 6298 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val, 6299 DAG.getIntPtrConstant(0)); 6300 DCI.AddToWorklist(Val.getNode()); 6301 } 6302 return Val; 6303 } else if (N->getOperand(0).getValueType() == MVT::i32) { 6304 // If the intermediate type is i32, we can avoid the load/store here 6305 // too. 6306 } 6307 } 6308 } 6309 break; 6310 case ISD::STORE: 6311 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 6312 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 6313 !cast<StoreSDNode>(N)->isTruncatingStore() && 6314 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 6315 N->getOperand(1).getValueType() == MVT::i32 && 6316 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 6317 SDValue Val = N->getOperand(1).getOperand(0); 6318 if (Val.getValueType() == MVT::f32) { 6319 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 6320 DCI.AddToWorklist(Val.getNode()); 6321 } 6322 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); 6323 DCI.AddToWorklist(Val.getNode()); 6324 6325 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val, 6326 N->getOperand(2), N->getOperand(3)); 6327 DCI.AddToWorklist(Val.getNode()); 6328 return Val; 6329 } 6330 6331 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 6332 if (cast<StoreSDNode>(N)->isUnindexed() && 6333 N->getOperand(1).getOpcode() == ISD::BSWAP && 6334 N->getOperand(1).getNode()->hasOneUse() && 6335 (N->getOperand(1).getValueType() == MVT::i32 || 6336 N->getOperand(1).getValueType() == MVT::i16)) { 6337 SDValue BSwapOp = N->getOperand(1).getOperand(0); 6338 // Do an any-extend to 32-bits if this is a half-word input. 6339 if (BSwapOp.getValueType() == MVT::i16) 6340 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); 6341 6342 SDValue Ops[] = { 6343 N->getOperand(0), BSwapOp, N->getOperand(2), 6344 DAG.getValueType(N->getOperand(1).getValueType()) 6345 }; 6346 return 6347 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), 6348 Ops, array_lengthof(Ops), 6349 cast<StoreSDNode>(N)->getMemoryVT(), 6350 cast<StoreSDNode>(N)->getMemOperand()); 6351 } 6352 break; 6353 case ISD::BSWAP: 6354 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 6355 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) && 6356 N->getOperand(0).hasOneUse() && 6357 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 6358 SDValue Load = N->getOperand(0); 6359 LoadSDNode *LD = cast<LoadSDNode>(Load); 6360 // Create the byte-swapping load. 6361 SDValue Ops[] = { 6362 LD->getChain(), // Chain 6363 LD->getBasePtr(), // Ptr 6364 DAG.getValueType(N->getValueType(0)) // VT 6365 }; 6366 SDValue BSLoad = 6367 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl, 6368 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3, 6369 LD->getMemoryVT(), LD->getMemOperand()); 6370 6371 // If this is an i16 load, insert the truncate. 6372 SDValue ResVal = BSLoad; 6373 if (N->getValueType(0) == MVT::i16) 6374 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); 6375 6376 // First, combine the bswap away. This makes the value produced by the 6377 // load dead. 6378 DCI.CombineTo(N, ResVal); 6379 6380 // Next, combine the load away, we give it a bogus result value but a real 6381 // chain result. The result value is dead because the bswap is dead. 6382 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1)); 6383 6384 // Return N so it doesn't get rechecked! 6385 return SDValue(N, 0); 6386 } 6387 6388 break; 6389 case PPCISD::VCMP: { 6390 // If a VCMPo node already exists with exactly the same operands as this 6391 // node, use its result instead of this node (VCMPo computes both a CR6 and 6392 // a normal output). 6393 // 6394 if (!N->getOperand(0).hasOneUse() && 6395 !N->getOperand(1).hasOneUse() && 6396 !N->getOperand(2).hasOneUse()) { 6397 6398 // Scan all of the users of the LHS, looking for VCMPo's that match. 6399 SDNode *VCMPoNode = 0; 6400 6401 SDNode *LHSN = N->getOperand(0).getNode(); 6402 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 6403 UI != E; ++UI) 6404 if (UI->getOpcode() == PPCISD::VCMPo && 6405 UI->getOperand(1) == N->getOperand(1) && 6406 UI->getOperand(2) == N->getOperand(2) && 6407 UI->getOperand(0) == N->getOperand(0)) { 6408 VCMPoNode = *UI; 6409 break; 6410 } 6411 6412 // If there is no VCMPo node, or if the flag value has a single use, don't 6413 // transform this. 6414 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 6415 break; 6416 6417 // Look at the (necessarily single) use of the flag value. If it has a 6418 // chain, this transformation is more complex. Note that multiple things 6419 // could use the value result, which we should ignore. 6420 SDNode *FlagUser = 0; 6421 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 6422 FlagUser == 0; ++UI) { 6423 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 6424 SDNode *User = *UI; 6425 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 6426 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) { 6427 FlagUser = User; 6428 break; 6429 } 6430 } 6431 } 6432 6433 // If the user is a MFCR instruction, we know this is safe. Otherwise we 6434 // give up for right now. 6435 if (FlagUser->getOpcode() == PPCISD::MFCR) 6436 return SDValue(VCMPoNode, 0); 6437 } 6438 break; 6439 } 6440 case ISD::BR_CC: { 6441 // If this is a branch on an altivec predicate comparison, lower this so 6442 // that we don't have to do a MFCR: instead, branch directly on CR6. This 6443 // lowering is done pre-legalize, because the legalizer lowers the predicate 6444 // compare down to code that is difficult to reassemble. 6445 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 6446 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 6447 int CompareOpc; 6448 bool isDot; 6449 6450 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 6451 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 6452 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 6453 assert(isDot && "Can't compare against a vector result!"); 6454 6455 // If this is a comparison against something other than 0/1, then we know 6456 // that the condition is never/always true. 6457 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue(); 6458 if (Val != 0 && Val != 1) { 6459 if (CC == ISD::SETEQ) // Cond never true, remove branch. 6460 return N->getOperand(0); 6461 // Always !=, turn it into an unconditional branch. 6462 return DAG.getNode(ISD::BR, dl, MVT::Other, 6463 N->getOperand(0), N->getOperand(4)); 6464 } 6465 6466 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 6467 6468 // Create the PPCISD altivec 'dot' comparison node. 6469 std::vector<EVT> VTs; 6470 SDValue Ops[] = { 6471 LHS.getOperand(2), // LHS of compare 6472 LHS.getOperand(3), // RHS of compare 6473 DAG.getConstant(CompareOpc, MVT::i32) 6474 }; 6475 VTs.push_back(LHS.getOperand(2).getValueType()); 6476 VTs.push_back(MVT::Glue); 6477 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 6478 6479 // Unpack the result based on how the target uses it. 6480 PPC::Predicate CompOpc; 6481 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) { 6482 default: // Can't happen, don't crash on invalid number though. 6483 case 0: // Branch on the value of the EQ bit of CR6. 6484 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 6485 break; 6486 case 1: // Branch on the inverted value of the EQ bit of CR6. 6487 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 6488 break; 6489 case 2: // Branch on the value of the LT bit of CR6. 6490 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 6491 break; 6492 case 3: // Branch on the inverted value of the LT bit of CR6. 6493 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 6494 break; 6495 } 6496 6497 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), 6498 DAG.getConstant(CompOpc, MVT::i32), 6499 DAG.getRegister(PPC::CR6, MVT::i32), 6500 N->getOperand(4), CompNode.getValue(1)); 6501 } 6502 break; 6503 } 6504 } 6505 6506 return SDValue(); 6507} 6508 6509//===----------------------------------------------------------------------===// 6510// Inline Assembly Support 6511//===----------------------------------------------------------------------===// 6512 6513void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 6514 APInt &KnownZero, 6515 APInt &KnownOne, 6516 const SelectionDAG &DAG, 6517 unsigned Depth) const { 6518 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); 6519 switch (Op.getOpcode()) { 6520 default: break; 6521 case PPCISD::LBRX: { 6522 // lhbrx is known to have the top bits cleared out. 6523 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) 6524 KnownZero = 0xFFFF0000; 6525 break; 6526 } 6527 case ISD::INTRINSIC_WO_CHAIN: { 6528 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) { 6529 default: break; 6530 case Intrinsic::ppc_altivec_vcmpbfp_p: 6531 case Intrinsic::ppc_altivec_vcmpeqfp_p: 6532 case Intrinsic::ppc_altivec_vcmpequb_p: 6533 case Intrinsic::ppc_altivec_vcmpequh_p: 6534 case Intrinsic::ppc_altivec_vcmpequw_p: 6535 case Intrinsic::ppc_altivec_vcmpgefp_p: 6536 case Intrinsic::ppc_altivec_vcmpgtfp_p: 6537 case Intrinsic::ppc_altivec_vcmpgtsb_p: 6538 case Intrinsic::ppc_altivec_vcmpgtsh_p: 6539 case Intrinsic::ppc_altivec_vcmpgtsw_p: 6540 case Intrinsic::ppc_altivec_vcmpgtub_p: 6541 case Intrinsic::ppc_altivec_vcmpgtuh_p: 6542 case Intrinsic::ppc_altivec_vcmpgtuw_p: 6543 KnownZero = ~1U; // All bits but the low one are known to be zero. 6544 break; 6545 } 6546 } 6547 } 6548} 6549 6550 6551/// getConstraintType - Given a constraint, return the type of 6552/// constraint it is for this target. 6553PPCTargetLowering::ConstraintType 6554PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 6555 if (Constraint.size() == 1) { 6556 switch (Constraint[0]) { 6557 default: break; 6558 case 'b': 6559 case 'r': 6560 case 'f': 6561 case 'v': 6562 case 'y': 6563 return C_RegisterClass; 6564 case 'Z': 6565 // FIXME: While Z does indicate a memory constraint, it specifically 6566 // indicates an r+r address (used in conjunction with the 'y' modifier 6567 // in the replacement string). Currently, we're forcing the base 6568 // register to be r0 in the asm printer (which is interpreted as zero) 6569 // and forming the complete address in the second register. This is 6570 // suboptimal. 6571 return C_Memory; 6572 } 6573 } 6574 return TargetLowering::getConstraintType(Constraint); 6575} 6576 6577/// Examine constraint type and operand type and determine a weight value. 6578/// This object must already have been set up with the operand type 6579/// and the current alternative constraint selected. 6580TargetLowering::ConstraintWeight 6581PPCTargetLowering::getSingleConstraintMatchWeight( 6582 AsmOperandInfo &info, const char *constraint) const { 6583 ConstraintWeight weight = CW_Invalid; 6584 Value *CallOperandVal = info.CallOperandVal; 6585 // If we don't have a value, we can't do a match, 6586 // but allow it at the lowest weight. 6587 if (CallOperandVal == NULL) 6588 return CW_Default; 6589 Type *type = CallOperandVal->getType(); 6590 // Look at the constraint type. 6591 switch (*constraint) { 6592 default: 6593 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 6594 break; 6595 case 'b': 6596 if (type->isIntegerTy()) 6597 weight = CW_Register; 6598 break; 6599 case 'f': 6600 if (type->isFloatTy()) 6601 weight = CW_Register; 6602 break; 6603 case 'd': 6604 if (type->isDoubleTy()) 6605 weight = CW_Register; 6606 break; 6607 case 'v': 6608 if (type->isVectorTy()) 6609 weight = CW_Register; 6610 break; 6611 case 'y': 6612 weight = CW_Register; 6613 break; 6614 case 'Z': 6615 weight = CW_Memory; 6616 break; 6617 } 6618 return weight; 6619} 6620 6621std::pair<unsigned, const TargetRegisterClass*> 6622PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 6623 EVT VT) const { 6624 if (Constraint.size() == 1) { 6625 // GCC RS6000 Constraint Letters 6626 switch (Constraint[0]) { 6627 case 'b': // R1-R31 6628 case 'r': // R0-R31 6629 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 6630 return std::make_pair(0U, &PPC::G8RCRegClass); 6631 return std::make_pair(0U, &PPC::GPRCRegClass); 6632 case 'f': 6633 if (VT == MVT::f32 || VT == MVT::i32) 6634 return std::make_pair(0U, &PPC::F4RCRegClass); 6635 if (VT == MVT::f64 || VT == MVT::i64) 6636 return std::make_pair(0U, &PPC::F8RCRegClass); 6637 break; 6638 case 'v': 6639 return std::make_pair(0U, &PPC::VRRCRegClass); 6640 case 'y': // crrc 6641 return std::make_pair(0U, &PPC::CRRCRegClass); 6642 } 6643 } 6644 6645 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 6646} 6647 6648 6649/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 6650/// vector. If it is invalid, don't add anything to Ops. 6651void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 6652 std::string &Constraint, 6653 std::vector<SDValue>&Ops, 6654 SelectionDAG &DAG) const { 6655 SDValue Result(0,0); 6656 6657 // Only support length 1 constraints. 6658 if (Constraint.length() > 1) return; 6659 6660 char Letter = Constraint[0]; 6661 switch (Letter) { 6662 default: break; 6663 case 'I': 6664 case 'J': 6665 case 'K': 6666 case 'L': 6667 case 'M': 6668 case 'N': 6669 case 'O': 6670 case 'P': { 6671 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 6672 if (!CST) return; // Must be an immediate to match. 6673 unsigned Value = CST->getZExtValue(); 6674 switch (Letter) { 6675 default: llvm_unreachable("Unknown constraint letter!"); 6676 case 'I': // "I" is a signed 16-bit constant. 6677 if ((short)Value == (int)Value) 6678 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6679 break; 6680 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 6681 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 6682 if ((short)Value == 0) 6683 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6684 break; 6685 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 6686 if ((Value >> 16) == 0) 6687 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6688 break; 6689 case 'M': // "M" is a constant that is greater than 31. 6690 if (Value > 31) 6691 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6692 break; 6693 case 'N': // "N" is a positive constant that is an exact power of two. 6694 if ((int)Value > 0 && isPowerOf2_32(Value)) 6695 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6696 break; 6697 case 'O': // "O" is the constant zero. 6698 if (Value == 0) 6699 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6700 break; 6701 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 6702 if ((short)-Value == (int)-Value) 6703 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6704 break; 6705 } 6706 break; 6707 } 6708 } 6709 6710 if (Result.getNode()) { 6711 Ops.push_back(Result); 6712 return; 6713 } 6714 6715 // Handle standard constraint letters. 6716 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 6717} 6718 6719// isLegalAddressingMode - Return true if the addressing mode represented 6720// by AM is legal for this target, for a load/store of the specified type. 6721bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 6722 Type *Ty) const { 6723 // FIXME: PPC does not allow r+i addressing modes for vectors! 6724 6725 // PPC allows a sign-extended 16-bit immediate field. 6726 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 6727 return false; 6728 6729 // No global is ever allowed as a base. 6730 if (AM.BaseGV) 6731 return false; 6732 6733 // PPC only support r+r, 6734 switch (AM.Scale) { 6735 case 0: // "r+i" or just "i", depending on HasBaseReg. 6736 break; 6737 case 1: 6738 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 6739 return false; 6740 // Otherwise we have r+r or r+i. 6741 break; 6742 case 2: 6743 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 6744 return false; 6745 // Allow 2*r as r+r. 6746 break; 6747 default: 6748 // No other scales are supported. 6749 return false; 6750 } 6751 6752 return true; 6753} 6754 6755/// isLegalAddressImmediate - Return true if the integer value can be used 6756/// as the offset of the target addressing mode for load / store of the 6757/// given type. 6758bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{ 6759 // PPC allows a sign-extended 16-bit immediate field. 6760 return (V > -(1 << 16) && V < (1 << 16)-1); 6761} 6762 6763bool PPCTargetLowering::isLegalAddressImmediate(GlobalValue* GV) const { 6764 return false; 6765} 6766 6767SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, 6768 SelectionDAG &DAG) const { 6769 MachineFunction &MF = DAG.getMachineFunction(); 6770 MachineFrameInfo *MFI = MF.getFrameInfo(); 6771 MFI->setReturnAddressIsTaken(true); 6772 6773 DebugLoc dl = Op.getDebugLoc(); 6774 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6775 6776 // Make sure the function does not optimize away the store of the RA to 6777 // the stack. 6778 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 6779 FuncInfo->setLRStoreRequired(); 6780 bool isPPC64 = PPCSubTarget.isPPC64(); 6781 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 6782 6783 if (Depth > 0) { 6784 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 6785 SDValue Offset = 6786 6787 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI), 6788 isPPC64? MVT::i64 : MVT::i32); 6789 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 6790 DAG.getNode(ISD::ADD, dl, getPointerTy(), 6791 FrameAddr, Offset), 6792 MachinePointerInfo(), false, false, false, 0); 6793 } 6794 6795 // Just load the return address off the stack. 6796 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); 6797 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 6798 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 6799} 6800 6801SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, 6802 SelectionDAG &DAG) const { 6803 DebugLoc dl = Op.getDebugLoc(); 6804 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6805 6806 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 6807 bool isPPC64 = PtrVT == MVT::i64; 6808 6809 MachineFunction &MF = DAG.getMachineFunction(); 6810 MachineFrameInfo *MFI = MF.getFrameInfo(); 6811 MFI->setFrameAddressIsTaken(true); 6812 bool is31 = (getTargetMachine().Options.DisableFramePointerElim(MF) || 6813 MFI->hasVarSizedObjects()) && 6814 MFI->getStackSize() && 6815 !MF.getFunction()->getAttributes(). 6816 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked); 6817 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) : 6818 (is31 ? PPC::R31 : PPC::R1); 6819 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, 6820 PtrVT); 6821 while (Depth--) 6822 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(), 6823 FrameAddr, MachinePointerInfo(), false, false, 6824 false, 0); 6825 return FrameAddr; 6826} 6827 6828bool 6829PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 6830 // The PowerPC target isn't yet aware of offsets. 6831 return false; 6832} 6833 6834/// getOptimalMemOpType - Returns the target specific optimal type for load 6835/// and store operations as a result of memset, memcpy, and memmove 6836/// lowering. If DstAlign is zero that means it's safe to destination 6837/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 6838/// means there isn't a need to check it against alignment requirement, 6839/// probably because the source does not need to be loaded. If 'IsMemset' is 6840/// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 6841/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 6842/// source is constant so it does not need to be loaded. 6843/// It returns EVT::Other if the type should be determined using generic 6844/// target-independent logic. 6845EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, 6846 unsigned DstAlign, unsigned SrcAlign, 6847 bool IsMemset, bool ZeroMemset, 6848 bool MemcpyStrSrc, 6849 MachineFunction &MF) const { 6850 if (this->PPCSubTarget.isPPC64()) { 6851 return MVT::i64; 6852 } else { 6853 return MVT::i32; 6854 } 6855} 6856 6857/// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than 6858/// a pair of mul and add instructions. fmuladd intrinsics will be expanded to 6859/// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd 6860/// is expanded to mul + add. 6861bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const { 6862 if (!VT.isSimple()) 6863 return false; 6864 6865 switch (VT.getSimpleVT().SimpleTy) { 6866 case MVT::f32: 6867 case MVT::f64: 6868 case MVT::v4f32: 6869 return true; 6870 default: 6871 break; 6872 } 6873 6874 return false; 6875} 6876 6877Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const { 6878 if (DisableILPPref) 6879 return TargetLowering::getSchedulingPreference(N); 6880 6881 return Sched::ILP; 6882} 6883 6884