PPCISelLowering.cpp revision 750ac1bdfa6f09bddfd9efce1d6360dde8fa74c0
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCTargetMachine.h" 16#include "llvm/ADT/VectorExtras.h" 17#include "llvm/CodeGen/MachineFrameInfo.h" 18#include "llvm/CodeGen/MachineFunction.h" 19#include "llvm/CodeGen/MachineInstrBuilder.h" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/CodeGen/SSARegMap.h" 22#include "llvm/Constants.h" 23#include "llvm/Function.h" 24#include "llvm/Support/MathExtras.h" 25using namespace llvm; 26 27PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) 28 : TargetLowering(TM) { 29 30 // Fold away setcc operations if possible. 31 setSetCCIsExpensive(); 32 setPow2DivIsCheap(); 33 34 // Use _setjmp/_longjmp instead of setjmp/longjmp. 35 setUseUnderscoreSetJmpLongJmp(true); 36 37 // Set up the register classes. 38 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 39 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 40 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 41 42 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 43 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 44 45 // PowerPC has no intrinsics for these particular operations 46 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 47 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 48 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 49 50 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 51 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand); 52 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand); 53 54 // PowerPC has no SREM/UREM instructions 55 setOperationAction(ISD::SREM, MVT::i32, Expand); 56 setOperationAction(ISD::UREM, MVT::i32, Expand); 57 58 // We don't support sin/cos/sqrt/fmod 59 setOperationAction(ISD::FSIN , MVT::f64, Expand); 60 setOperationAction(ISD::FCOS , MVT::f64, Expand); 61 setOperationAction(ISD::FREM , MVT::f64, Expand); 62 setOperationAction(ISD::FSIN , MVT::f32, Expand); 63 setOperationAction(ISD::FCOS , MVT::f32, Expand); 64 setOperationAction(ISD::FREM , MVT::f32, Expand); 65 66 // If we're enabling GP optimizations, use hardware square root 67 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 68 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 69 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 70 } 71 72 // PowerPC does not have BSWAP, CTPOP or CTTZ 73 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 74 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 75 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 76 77 // PowerPC does not have ROTR 78 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 79 80 // PowerPC does not have Select 81 setOperationAction(ISD::SELECT, MVT::i32, Expand); 82 setOperationAction(ISD::SELECT, MVT::f32, Expand); 83 setOperationAction(ISD::SELECT, MVT::f64, Expand); 84 85 // PowerPC wants to turn select_cc of FP into fsel when possible. 86 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 87 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 88 89 // PowerPC wants to optimize integer setcc a bit 90 setOperationAction(ISD::SETCC, MVT::i32, Custom); 91 92 // PowerPC does not have BRCOND* which requires SetCC 93 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 94 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 95 96 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 97 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 98 99 // PowerPC does not have [U|S]INT_TO_FP 100 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 101 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 102 103 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 104 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 105 106 // PowerPC does not have truncstore for i1. 107 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote); 108 109 // Support label based line numbers. 110 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 111 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 112 // FIXME - use subtarget debug flags 113 if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) 114 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 115 116 // We want to legalize GlobalAddress and ConstantPool nodes into the 117 // appropriate instructions to materialize the address. 118 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 119 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 120 121 // RET must be custom lowered, to meet ABI requirements 122 setOperationAction(ISD::RET , MVT::Other, Custom); 123 124 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 125 setOperationAction(ISD::VASTART , MVT::Other, Custom); 126 127 // Use the default implementation. 128 setOperationAction(ISD::VAARG , MVT::Other, Expand); 129 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 130 setOperationAction(ISD::VAEND , MVT::Other, Expand); 131 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 132 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 133 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 134 135 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) { 136 // They also have instructions for converting between i64 and fp. 137 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 138 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 139 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 140 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 141 } else { 142 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 143 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 144 } 145 146 if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) { 147 // 64 bit PowerPC implementations can support i64 types directly 148 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 149 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 150 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 151 } else { 152 // 32 bit PowerPC wants to expand i64 shifts itself. 153 setOperationAction(ISD::SHL, MVT::i64, Custom); 154 setOperationAction(ISD::SRL, MVT::i64, Custom); 155 setOperationAction(ISD::SRA, MVT::i64, Custom); 156 } 157 158 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 159 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 160 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 161 162 // FIXME: We don't support any ConstantVec's yet. We should custom expand 163 // the ones we do! 164 setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand); 165 setOperationAction(ISD::ConstantVec, MVT::v4i32, Expand); 166 } 167 168 setSetCCResultContents(ZeroOrOneSetCCResult); 169 setStackPointerRegisterToSaveRestore(PPC::R1); 170 171 computeRegisterProperties(); 172} 173 174const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 175 switch (Opcode) { 176 default: return 0; 177 case PPCISD::FSEL: return "PPCISD::FSEL"; 178 case PPCISD::FCFID: return "PPCISD::FCFID"; 179 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 180 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 181 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 182 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 183 case PPCISD::Hi: return "PPCISD::Hi"; 184 case PPCISD::Lo: return "PPCISD::Lo"; 185 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 186 case PPCISD::SRL: return "PPCISD::SRL"; 187 case PPCISD::SRA: return "PPCISD::SRA"; 188 case PPCISD::SHL: return "PPCISD::SHL"; 189 case PPCISD::CALL: return "PPCISD::CALL"; 190 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 191 } 192} 193 194/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 195static bool isFloatingPointZero(SDOperand Op) { 196 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 197 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 198 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) { 199 // Maybe this has already been legalized into the constant pool? 200 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 201 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get())) 202 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 203 } 204 return false; 205} 206 207/// LowerOperation - Provide custom lowering hooks for some operations. 208/// 209SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 210 switch (Op.getOpcode()) { 211 default: assert(0 && "Wasn't expecting to be able to lower this!"); 212 case ISD::FP_TO_SINT: { 213 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 214 SDOperand Src = Op.getOperand(0); 215 if (Src.getValueType() == MVT::f32) 216 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 217 218 SDOperand Tmp; 219 switch (Op.getValueType()) { 220 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 221 case MVT::i32: 222 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 223 break; 224 case MVT::i64: 225 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 226 break; 227 } 228 229 // Convert the FP value to an int value through memory. 230 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp); 231 if (Op.getValueType() == MVT::i32) 232 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits); 233 return Bits; 234 } 235 case ISD::SINT_TO_FP: { 236 assert(MVT::i64 == Op.getOperand(0).getValueType() && 237 "Unhandled SINT_TO_FP type in custom expander!"); 238 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 239 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 240 if (MVT::f32 == Op.getValueType()) 241 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 242 return FP; 243 } 244 case ISD::SELECT_CC: { 245 // Turn FP only select_cc's into fsel instructions. 246 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 247 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 248 break; 249 250 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 251 252 // Cannot handle SETEQ/SETNE. 253 if (CC == ISD::SETEQ || CC == ISD::SETNE) break; 254 255 MVT::ValueType ResVT = Op.getValueType(); 256 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 257 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 258 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 259 260 // If the RHS of the comparison is a 0.0, we don't need to do the 261 // subtraction at all. 262 if (isFloatingPointZero(RHS)) 263 switch (CC) { 264 default: break; // SETUO etc aren't handled by fsel. 265 case ISD::SETULT: 266 case ISD::SETLT: 267 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 268 case ISD::SETUGE: 269 case ISD::SETGE: 270 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 271 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 272 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 273 case ISD::SETUGT: 274 case ISD::SETGT: 275 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 276 case ISD::SETULE: 277 case ISD::SETLE: 278 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 279 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 280 return DAG.getNode(PPCISD::FSEL, ResVT, 281 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 282 } 283 284 SDOperand Cmp; 285 switch (CC) { 286 default: break; // SETUO etc aren't handled by fsel. 287 case ISD::SETULT: 288 case ISD::SETLT: 289 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 290 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 291 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 292 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 293 case ISD::SETUGE: 294 case ISD::SETGE: 295 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 296 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 297 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 298 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 299 case ISD::SETUGT: 300 case ISD::SETGT: 301 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 302 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 303 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 304 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 305 case ISD::SETULE: 306 case ISD::SETLE: 307 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 308 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 309 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 310 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 311 } 312 break; 313 } 314 case ISD::SHL: { 315 assert(Op.getValueType() == MVT::i64 && 316 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 317 // The generic code does a fine job expanding shift by a constant. 318 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 319 320 // Otherwise, expand into a bunch of logical ops. Note that these ops 321 // depend on the PPC behavior for oversized shift amounts. 322 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 323 DAG.getConstant(0, MVT::i32)); 324 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 325 DAG.getConstant(1, MVT::i32)); 326 SDOperand Amt = Op.getOperand(1); 327 328 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 329 DAG.getConstant(32, MVT::i32), Amt); 330 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); 331 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); 332 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 333 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 334 DAG.getConstant(-32U, MVT::i32)); 335 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); 336 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 337 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); 338 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 339 } 340 case ISD::SRL: { 341 assert(Op.getValueType() == MVT::i64 && 342 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 343 // The generic code does a fine job expanding shift by a constant. 344 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 345 346 // Otherwise, expand into a bunch of logical ops. Note that these ops 347 // depend on the PPC behavior for oversized shift amounts. 348 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 349 DAG.getConstant(0, MVT::i32)); 350 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 351 DAG.getConstant(1, MVT::i32)); 352 SDOperand Amt = Op.getOperand(1); 353 354 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 355 DAG.getConstant(32, MVT::i32), Amt); 356 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 357 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 358 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 359 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 360 DAG.getConstant(-32U, MVT::i32)); 361 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); 362 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 363 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); 364 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 365 } 366 case ISD::SRA: { 367 assert(Op.getValueType() == MVT::i64 && 368 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 369 // The generic code does a fine job expanding shift by a constant. 370 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 371 372 // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 373 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 374 DAG.getConstant(0, MVT::i32)); 375 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 376 DAG.getConstant(1, MVT::i32)); 377 SDOperand Amt = Op.getOperand(1); 378 379 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 380 DAG.getConstant(32, MVT::i32), Amt); 381 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 382 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 383 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 384 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 385 DAG.getConstant(-32U, MVT::i32)); 386 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); 387 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); 388 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 389 Tmp4, Tmp6, ISD::SETLE); 390 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 391 } 392 case ISD::ConstantPool: { 393 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 394 Constant *C = CP->get(); 395 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32, CP->getAlignment()); 396 SDOperand Zero = DAG.getConstant(0, MVT::i32); 397 398 if (PPCGenerateStaticCode) { 399 // Generate non-pic code that has direct accesses to the constant pool. 400 // The address of the global is just (hi(&g)+lo(&g)). 401 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); 402 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); 403 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 404 } 405 406 // Only lower ConstantPool on Darwin. 407 if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break; 408 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); 409 if (PICEnabled) { 410 // With PIC, the first instruction is actually "GR+hi(&G)". 411 Hi = DAG.getNode(ISD::ADD, MVT::i32, 412 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); 413 } 414 415 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); 416 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 417 return Lo; 418 } 419 case ISD::GlobalAddress: { 420 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 421 GlobalValue *GV = GSDN->getGlobal(); 422 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset()); 423 SDOperand Zero = DAG.getConstant(0, MVT::i32); 424 425 if (PPCGenerateStaticCode) { 426 // Generate non-pic code that has direct accesses to globals. 427 // The address of the global is just (hi(&g)+lo(&g)). 428 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); 429 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); 430 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 431 } 432 433 // Only lower GlobalAddress on Darwin. 434 if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break; 435 436 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); 437 if (PICEnabled) { 438 // With PIC, the first instruction is actually "GR+hi(&G)". 439 Hi = DAG.getNode(ISD::ADD, MVT::i32, 440 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); 441 } 442 443 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); 444 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 445 446 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() && 447 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode())) 448 return Lo; 449 450 // If the global is weak or external, we have to go through the lazy 451 // resolution stub. 452 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0)); 453 } 454 case ISD::SETCC: { 455 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 456 457 // If we're comparing for equality to zero, expose the fact that this is 458 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 459 // fold the new nodes. 460 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 461 if (C->isNullValue() && CC == ISD::SETEQ) { 462 MVT::ValueType VT = Op.getOperand(0).getValueType(); 463 SDOperand Zext = Op.getOperand(0); 464 if (VT < MVT::i32) { 465 VT = MVT::i32; 466 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); 467 } 468 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); 469 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); 470 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, 471 DAG.getConstant(Log2b, getShiftAmountTy())); 472 return DAG.getNode(ISD::TRUNCATE, getSetCCResultTy(), Scc); 473 } 474 // Leave comparisons against 0 and -1 alone for now, since they're usually 475 // optimized. FIXME: revisit this when we can custom lower all setcc 476 // optimizations. 477 if (C->isAllOnesValue() || C->isNullValue()) 478 break; 479 } 480 481 // If we have an integer seteq/setne, turn it into a compare against zero 482 // by subtracting the rhs from the lhs, which is faster than setting a 483 // condition register, reading it back out, and masking the correct bit. 484 MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); 485 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 486 MVT::ValueType VT = Op.getValueType(); 487 SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0), 488 Op.getOperand(1)); 489 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); 490 } 491 break; 492 } 493 case ISD::VASTART: { 494 // vastart just stores the address of the VarArgsFrameIndex slot into the 495 // memory location argument. 496 // FIXME: Replace MVT::i32 with PointerTy 497 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 498 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR, 499 Op.getOperand(1), Op.getOperand(2)); 500 } 501 case ISD::RET: { 502 SDOperand Copy; 503 504 switch(Op.getNumOperands()) { 505 default: 506 assert(0 && "Do not know how to return this many arguments!"); 507 abort(); 508 case 1: 509 return SDOperand(); // ret void is legal 510 case 2: { 511 MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); 512 unsigned ArgReg = MVT::isInteger(ArgVT) ? PPC::R3 : PPC::F1; 513 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 514 SDOperand()); 515 break; 516 } 517 case 3: 518 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2), 519 SDOperand()); 520 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1)); 521 break; 522 } 523 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 524 } 525 } 526 return SDOperand(); 527} 528 529std::vector<SDOperand> 530PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 531 // 532 // add beautiful description of PPC stack frame format, or at least some docs 533 // 534 MachineFunction &MF = DAG.getMachineFunction(); 535 MachineFrameInfo *MFI = MF.getFrameInfo(); 536 MachineBasicBlock& BB = MF.front(); 537 SSARegMap *RegMap = MF.getSSARegMap(); 538 std::vector<SDOperand> ArgValues; 539 540 unsigned ArgOffset = 24; 541 unsigned GPR_remaining = 8; 542 unsigned FPR_remaining = 13; 543 unsigned GPR_idx = 0, FPR_idx = 0; 544 static const unsigned GPR[] = { 545 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 546 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 547 }; 548 static const unsigned FPR[] = { 549 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 550 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 551 }; 552 553 // Add DAG nodes to load the arguments... On entry to a function on PPC, 554 // the arguments start at offset 24, although they are likely to be passed 555 // in registers. 556 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 557 SDOperand newroot, argt; 558 unsigned ObjSize; 559 bool needsLoad = false; 560 bool ArgLive = !I->use_empty(); 561 MVT::ValueType ObjectVT = getValueType(I->getType()); 562 563 switch (ObjectVT) { 564 default: assert(0 && "Unhandled argument type!"); 565 case MVT::i1: 566 case MVT::i8: 567 case MVT::i16: 568 case MVT::i32: 569 ObjSize = 4; 570 if (!ArgLive) break; 571 if (GPR_remaining > 0) { 572 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 573 MF.addLiveIn(GPR[GPR_idx], VReg); 574 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 575 if (ObjectVT != MVT::i32) { 576 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 577 : ISD::AssertZext; 578 argt = DAG.getNode(AssertOp, MVT::i32, argt, 579 DAG.getValueType(ObjectVT)); 580 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt); 581 } 582 } else { 583 needsLoad = true; 584 } 585 break; 586 case MVT::i64: 587 ObjSize = 8; 588 if (!ArgLive) break; 589 if (GPR_remaining > 0) { 590 SDOperand argHi, argLo; 591 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 592 MF.addLiveIn(GPR[GPR_idx], VReg); 593 argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 594 // If we have two or more remaining argument registers, then both halves 595 // of the i64 can be sourced from there. Otherwise, the lower half will 596 // have to come off the stack. This can happen when an i64 is preceded 597 // by 28 bytes of arguments. 598 if (GPR_remaining > 1) { 599 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 600 MF.addLiveIn(GPR[GPR_idx+1], VReg); 601 argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32); 602 } else { 603 int FI = MFI->CreateFixedObject(4, ArgOffset+4); 604 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 605 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, 606 DAG.getSrcValue(NULL)); 607 } 608 // Build the outgoing arg thingy 609 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi); 610 newroot = argLo; 611 } else { 612 needsLoad = true; 613 } 614 break; 615 case MVT::f32: 616 case MVT::f64: 617 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4; 618 if (!ArgLive) { 619 if (FPR_remaining > 0) { 620 --FPR_remaining; 621 ++FPR_idx; 622 } 623 break; 624 } 625 if (FPR_remaining > 0) { 626 unsigned VReg; 627 if (ObjectVT == MVT::f32) 628 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); 629 else 630 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 631 MF.addLiveIn(FPR[FPR_idx], VReg); 632 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT); 633 --FPR_remaining; 634 ++FPR_idx; 635 } else { 636 needsLoad = true; 637 } 638 break; 639 } 640 641 // We need to load the argument to a virtual register if we determined above 642 // that we ran out of physical registers of the appropriate type 643 if (needsLoad) { 644 unsigned SubregOffset = 0; 645 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3; 646 if (ObjectVT == MVT::i16) SubregOffset = 2; 647 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 648 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 649 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, 650 DAG.getConstant(SubregOffset, MVT::i32)); 651 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, 652 DAG.getSrcValue(NULL)); 653 } 654 655 // Every 4 bytes of argument space consumes one of the GPRs available for 656 // argument passing. 657 if (GPR_remaining > 0) { 658 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1; 659 GPR_remaining -= delta; 660 GPR_idx += delta; 661 } 662 ArgOffset += ObjSize; 663 if (newroot.Val) 664 DAG.setRoot(newroot.getValue(1)); 665 666 ArgValues.push_back(argt); 667 } 668 669 // If the function takes variable number of arguments, make a frame index for 670 // the start of the first vararg value... for expansion of llvm.va_start. 671 if (F.isVarArg()) { 672 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 673 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 674 // If this function is vararg, store any remaining integer argument regs 675 // to their spots on the stack so that they may be loaded by deferencing the 676 // result of va_next. 677 std::vector<SDOperand> MemOps; 678 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) { 679 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 680 MF.addLiveIn(GPR[GPR_idx], VReg); 681 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 682 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), 683 Val, FIN, DAG.getSrcValue(NULL)); 684 MemOps.push_back(Store); 685 // Increment the address by four for the next argument to store 686 SDOperand PtrOff = DAG.getConstant(4, getPointerTy()); 687 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff); 688 } 689 if (!MemOps.empty()) { 690 MemOps.push_back(DAG.getRoot()); 691 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps)); 692 } 693 } 694 695 // Finally, inform the code generator which regs we return values in. 696 switch (getValueType(F.getReturnType())) { 697 default: assert(0 && "Unknown type!"); 698 case MVT::isVoid: break; 699 case MVT::i1: 700 case MVT::i8: 701 case MVT::i16: 702 case MVT::i32: 703 MF.addLiveOut(PPC::R3); 704 break; 705 case MVT::i64: 706 MF.addLiveOut(PPC::R3); 707 MF.addLiveOut(PPC::R4); 708 break; 709 case MVT::f32: 710 case MVT::f64: 711 MF.addLiveOut(PPC::F1); 712 break; 713 } 714 715 return ArgValues; 716} 717 718std::pair<SDOperand, SDOperand> 719PPCTargetLowering::LowerCallTo(SDOperand Chain, 720 const Type *RetTy, bool isVarArg, 721 unsigned CallingConv, bool isTailCall, 722 SDOperand Callee, ArgListTy &Args, 723 SelectionDAG &DAG) { 724 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in 725 // SelectExpr to use to put the arguments in the appropriate registers. 726 std::vector<SDOperand> args_to_use; 727 728 // Count how many bytes are to be pushed on the stack, including the linkage 729 // area, and parameter passing area. 730 unsigned NumBytes = 24; 731 732 if (Args.empty()) { 733 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 734 DAG.getConstant(NumBytes, getPointerTy())); 735 } else { 736 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 737 switch (getValueType(Args[i].second)) { 738 default: assert(0 && "Unknown value type!"); 739 case MVT::i1: 740 case MVT::i8: 741 case MVT::i16: 742 case MVT::i32: 743 case MVT::f32: 744 NumBytes += 4; 745 break; 746 case MVT::i64: 747 case MVT::f64: 748 NumBytes += 8; 749 break; 750 } 751 } 752 753 // Just to be safe, we'll always reserve the full 24 bytes of linkage area 754 // plus 32 bytes of argument space in case any called code gets funky on us. 755 // (Required by ABI to support var arg) 756 if (NumBytes < 56) NumBytes = 56; 757 758 // Adjust the stack pointer for the new arguments... 759 // These operations are automatically eliminated by the prolog/epilog pass 760 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 761 DAG.getConstant(NumBytes, getPointerTy())); 762 763 // Set up a copy of the stack pointer for use loading and storing any 764 // arguments that may not fit in the registers available for argument 765 // passing. 766 SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 767 768 // Figure out which arguments are going to go in registers, and which in 769 // memory. Also, if this is a vararg function, floating point operations 770 // must be stored to our stack, and loaded into integer regs as well, if 771 // any integer regs are available for argument passing. 772 unsigned ArgOffset = 24; 773 unsigned GPR_remaining = 8; 774 unsigned FPR_remaining = 13; 775 776 std::vector<SDOperand> MemOps; 777 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 778 // PtrOff will be used to store the current argument to the stack if a 779 // register cannot be found for it. 780 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 781 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 782 MVT::ValueType ArgVT = getValueType(Args[i].second); 783 784 switch (ArgVT) { 785 default: assert(0 && "Unexpected ValueType for argument!"); 786 case MVT::i1: 787 case MVT::i8: 788 case MVT::i16: 789 // Promote the integer to 32 bits. If the input type is signed use a 790 // sign extend, otherwise use a zero extend. 791 if (Args[i].second->isSigned()) 792 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first); 793 else 794 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first); 795 // FALL THROUGH 796 case MVT::i32: 797 if (GPR_remaining > 0) { 798 args_to_use.push_back(Args[i].first); 799 --GPR_remaining; 800 } else { 801 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 802 Args[i].first, PtrOff, 803 DAG.getSrcValue(NULL))); 804 } 805 ArgOffset += 4; 806 break; 807 case MVT::i64: 808 // If we have one free GPR left, we can place the upper half of the i64 809 // in it, and store the other half to the stack. If we have two or more 810 // free GPRs, then we can pass both halves of the i64 in registers. 811 if (GPR_remaining > 0) { 812 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 813 Args[i].first, DAG.getConstant(1, MVT::i32)); 814 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 815 Args[i].first, DAG.getConstant(0, MVT::i32)); 816 args_to_use.push_back(Hi); 817 --GPR_remaining; 818 if (GPR_remaining > 0) { 819 args_to_use.push_back(Lo); 820 --GPR_remaining; 821 } else { 822 SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); 823 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); 824 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 825 Lo, PtrOff, DAG.getSrcValue(NULL))); 826 } 827 } else { 828 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 829 Args[i].first, PtrOff, 830 DAG.getSrcValue(NULL))); 831 } 832 ArgOffset += 8; 833 break; 834 case MVT::f32: 835 case MVT::f64: 836 if (FPR_remaining > 0) { 837 args_to_use.push_back(Args[i].first); 838 --FPR_remaining; 839 if (isVarArg) { 840 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 841 Args[i].first, PtrOff, 842 DAG.getSrcValue(NULL)); 843 MemOps.push_back(Store); 844 // Float varargs are always shadowed in available integer registers 845 if (GPR_remaining > 0) { 846 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, 847 DAG.getSrcValue(NULL)); 848 MemOps.push_back(Load.getValue(1)); 849 args_to_use.push_back(Load); 850 --GPR_remaining; 851 } 852 if (GPR_remaining > 0 && MVT::f64 == ArgVT) { 853 SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); 854 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); 855 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, 856 DAG.getSrcValue(NULL)); 857 MemOps.push_back(Load.getValue(1)); 858 args_to_use.push_back(Load); 859 --GPR_remaining; 860 } 861 } else { 862 // If we have any FPRs remaining, we may also have GPRs remaining. 863 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 864 // GPRs. 865 if (GPR_remaining > 0) { 866 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 867 --GPR_remaining; 868 } 869 if (GPR_remaining > 0 && MVT::f64 == ArgVT) { 870 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 871 --GPR_remaining; 872 } 873 } 874 } else { 875 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 876 Args[i].first, PtrOff, 877 DAG.getSrcValue(NULL))); 878 } 879 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8; 880 break; 881 } 882 } 883 if (!MemOps.empty()) 884 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps); 885 } 886 887 std::vector<MVT::ValueType> RetVals; 888 MVT::ValueType RetTyVT = getValueType(RetTy); 889 MVT::ValueType ActualRetTyVT = RetTyVT; 890 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16) 891 ActualRetTyVT = MVT::i32; // Promote result to i32. 892 893 if (RetTyVT == MVT::i64) { 894 RetVals.push_back(MVT::i32); 895 RetVals.push_back(MVT::i32); 896 } else if (RetTyVT != MVT::isVoid) { 897 RetVals.push_back(ActualRetTyVT); 898 } 899 RetVals.push_back(MVT::Other); 900 901 // If the callee is a GlobalAddress node (quite common, every direct call is) 902 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 903 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 904 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 905 906 std::vector<SDOperand> Ops; 907 Ops.push_back(Chain); 908 Ops.push_back(Callee); 909 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end()); 910 SDOperand TheCall = DAG.getNode(PPCISD::CALL, RetVals, Ops); 911 Chain = TheCall.getValue(TheCall.Val->getNumValues()-1); 912 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 913 DAG.getConstant(NumBytes, getPointerTy())); 914 SDOperand RetVal = TheCall; 915 916 // If the result is a small value, add a note so that we keep track of the 917 // information about whether it is sign or zero extended. 918 if (RetTyVT != ActualRetTyVT) { 919 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext, 920 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 921 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 922 } else if (RetTyVT == MVT::i64) { 923 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, RetVal, RetVal.getValue(1)); 924 } 925 926 return std::make_pair(RetVal, Chain); 927} 928 929MachineBasicBlock * 930PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 931 MachineBasicBlock *BB) { 932 assert((MI->getOpcode() == PPC::SELECT_CC_Int || 933 MI->getOpcode() == PPC::SELECT_CC_F4 || 934 MI->getOpcode() == PPC::SELECT_CC_F8) && 935 "Unexpected instr type to insert"); 936 937 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 938 // control-flow pattern. The incoming instruction knows the destination vreg 939 // to set, the condition code register to branch on, the true/false values to 940 // select between, and a branch opcode to use. 941 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 942 ilist<MachineBasicBlock>::iterator It = BB; 943 ++It; 944 945 // thisMBB: 946 // ... 947 // TrueVal = ... 948 // cmpTY ccX, r1, r2 949 // bCC copy1MBB 950 // fallthrough --> copy0MBB 951 MachineBasicBlock *thisMBB = BB; 952 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 953 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 954 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2) 955 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 956 MachineFunction *F = BB->getParent(); 957 F->getBasicBlockList().insert(It, copy0MBB); 958 F->getBasicBlockList().insert(It, sinkMBB); 959 // Update machine-CFG edges 960 BB->addSuccessor(copy0MBB); 961 BB->addSuccessor(sinkMBB); 962 963 // copy0MBB: 964 // %FalseValue = ... 965 // # fallthrough to sinkMBB 966 BB = copy0MBB; 967 968 // Update machine-CFG edges 969 BB->addSuccessor(sinkMBB); 970 971 // sinkMBB: 972 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 973 // ... 974 BB = sinkMBB; 975 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg()) 976 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 977 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 978 979 delete MI; // The pseudo instruction is gone now. 980 return BB; 981} 982 983std::vector<unsigned> PPCTargetLowering:: 984getRegForInlineAsmConstraint(const std::string &Constraint) const { 985 if (Constraint.size() == 1) { 986 switch (Constraint[0]) { // GCC RS6000 Constraint Letters 987 default: break; // Unknown constriant letter 988 case 'b': 989 return make_vector<unsigned>(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 , 990 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 , 991 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11, 992 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 993 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 994 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 995 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 996 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 997 0); 998 case 'r': 999 return make_vector<unsigned>(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 , 1000 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 , 1001 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11, 1002 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 1003 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 1004 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 1005 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 1006 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 1007 0); 1008 case 'f': 1009 return make_vector<unsigned>(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 , 1010 PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 , 1011 PPC::F8 , PPC::F9 , PPC::F10, PPC::F11, 1012 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 1013 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 1014 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 1015 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 1016 PPC::F28, PPC::F29, PPC::F30, PPC::F31, 1017 0); 1018 case 'v': 1019 return make_vector<unsigned>(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , 1020 PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 1021 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, 1022 PPC::V12, PPC::V13, PPC::V14, PPC::V15, 1023 PPC::V16, PPC::V17, PPC::V18, PPC::V19, 1024 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 1025 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 1026 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 1027 0); 1028 case 'y': 1029 return make_vector<unsigned>(PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, 1030 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 1031 0); 1032 } 1033 } 1034 1035 // Handle explicit register names. 1036 return TargetLowering::getRegForInlineAsmConstraint(Constraint); 1037} 1038