PPCISelLowering.cpp revision 86098bd6a63d2cdf0c9be9ef3151bd2728281fd7
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPredicates.h" 17#include "PPCTargetMachine.h" 18#include "PPCPerfectShuffle.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/ADT/VectorExtras.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/CallingConv.h" 29#include "llvm/Constants.h" 30#include "llvm/Function.h" 31#include "llvm/Intrinsics.h" 32#include "llvm/Support/MathExtras.h" 33#include "llvm/Target/TargetOptions.h" 34#include "llvm/Support/CommandLine.h" 35using namespace llvm; 36 37static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", 38cl::desc("enable preincrement load/store generation on PPC (experimental)"), 39 cl::Hidden); 40 41PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 42 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { 43 44 setPow2DivIsCheap(); 45 46 // Use _setjmp/_longjmp instead of setjmp/longjmp. 47 setUseUnderscoreSetJmp(true); 48 setUseUnderscoreLongJmp(true); 49 50 // Set up the register classes. 51 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 52 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 53 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 54 55 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 56 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 57 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); 58 59 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 60 61 // PowerPC has pre-inc load and store's. 62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 65 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 67 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 70 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 72 73 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg) 74 setConvertAction(MVT::ppcf128, MVT::f64, Expand); 75 setConvertAction(MVT::ppcf128, MVT::f32, Expand); 76 // This is used in the ppcf128->int sequence. Note it has different semantics 77 // from FP_ROUND: that rounds to nearest, this rounds to zero. 78 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 79 80 // PowerPC has no SREM/UREM instructions 81 setOperationAction(ISD::SREM, MVT::i32, Expand); 82 setOperationAction(ISD::UREM, MVT::i32, Expand); 83 setOperationAction(ISD::SREM, MVT::i64, Expand); 84 setOperationAction(ISD::UREM, MVT::i64, Expand); 85 86 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 87 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 88 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 89 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 90 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 91 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 92 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 93 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 94 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 95 96 // We don't support sin/cos/sqrt/fmod/pow 97 setOperationAction(ISD::FSIN , MVT::f64, Expand); 98 setOperationAction(ISD::FCOS , MVT::f64, Expand); 99 setOperationAction(ISD::FREM , MVT::f64, Expand); 100 setOperationAction(ISD::FPOW , MVT::f64, Expand); 101 setOperationAction(ISD::FSIN , MVT::f32, Expand); 102 setOperationAction(ISD::FCOS , MVT::f32, Expand); 103 setOperationAction(ISD::FREM , MVT::f32, Expand); 104 setOperationAction(ISD::FPOW , MVT::f32, Expand); 105 106 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 107 108 // If we're enabling GP optimizations, use hardware square root 109 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 110 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 111 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 112 } 113 114 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 115 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 116 117 // PowerPC does not have BSWAP, CTPOP or CTTZ 118 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 119 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 120 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 121 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 122 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 123 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 124 125 // PowerPC does not have ROTR 126 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 127 setOperationAction(ISD::ROTR, MVT::i64 , Expand); 128 129 // PowerPC does not have Select 130 setOperationAction(ISD::SELECT, MVT::i32, Expand); 131 setOperationAction(ISD::SELECT, MVT::i64, Expand); 132 setOperationAction(ISD::SELECT, MVT::f32, Expand); 133 setOperationAction(ISD::SELECT, MVT::f64, Expand); 134 135 // PowerPC wants to turn select_cc of FP into fsel when possible. 136 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 137 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 138 139 // PowerPC wants to optimize integer setcc a bit 140 setOperationAction(ISD::SETCC, MVT::i32, Custom); 141 142 // PowerPC does not have BRCOND which requires SetCC 143 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 144 145 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 146 147 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 148 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 149 150 // PowerPC does not have [U|S]INT_TO_FP 151 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 152 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 153 154 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 155 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 156 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 157 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 158 159 // We cannot sextinreg(i1). Expand to shifts. 160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 161 162 // Support label based line numbers. 163 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 164 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 165 166 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 167 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 168 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 169 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 170 171 172 // We want to legalize GlobalAddress and ConstantPool nodes into the 173 // appropriate instructions to materialize the address. 174 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 175 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 176 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 177 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 178 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 179 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 180 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 181 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 182 183 // RET must be custom lowered, to meet ABI requirements. 184 setOperationAction(ISD::RET , MVT::Other, Custom); 185 186 // TRAP is legal. 187 setOperationAction(ISD::TRAP, MVT::Other, Legal); 188 189 // TRAMPOLINE is custom lowered. 190 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 191 192 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 193 setOperationAction(ISD::VASTART , MVT::Other, Custom); 194 195 // VAARG is custom lowered with ELF 32 ABI 196 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI()) 197 setOperationAction(ISD::VAARG, MVT::Other, Custom); 198 else 199 setOperationAction(ISD::VAARG, MVT::Other, Expand); 200 201 // Use the default implementation. 202 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 203 setOperationAction(ISD::VAEND , MVT::Other, Expand); 204 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 205 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 208 209 // We want to custom lower some of our intrinsics. 210 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 211 212 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 213 // They also have instructions for converting between i64 and fp. 214 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 215 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 216 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 217 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 218 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 219 220 // FIXME: disable this lowered code. This generates 64-bit register values, 221 // and we don't model the fact that the top part is clobbered by calls. We 222 // need to flag these together so that the value isn't live across a call. 223 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 224 225 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 226 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 227 } else { 228 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 229 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 230 } 231 232 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 233 // 64-bit PowerPC implementations can support i64 types directly 234 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 235 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 236 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 237 // 64-bit PowerPC wants to expand i128 shifts itself. 238 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 239 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 240 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 241 } else { 242 // 32-bit PowerPC wants to expand i64 shifts itself. 243 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 244 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 245 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 246 } 247 248 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 249 // First set operation action for all vector types to expand. Then we 250 // will selectively turn on ones that can be effectively codegen'd. 251 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 252 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 253 MVT VT = (MVT::SimpleValueType)i; 254 255 // add/sub are legal for all supported vector VT's. 256 setOperationAction(ISD::ADD , VT, Legal); 257 setOperationAction(ISD::SUB , VT, Legal); 258 259 // We promote all shuffles to v16i8. 260 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 261 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 262 263 // We promote all non-typed operations to v4i32. 264 setOperationAction(ISD::AND , VT, Promote); 265 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 266 setOperationAction(ISD::OR , VT, Promote); 267 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 268 setOperationAction(ISD::XOR , VT, Promote); 269 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 270 setOperationAction(ISD::LOAD , VT, Promote); 271 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 272 setOperationAction(ISD::SELECT, VT, Promote); 273 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 274 setOperationAction(ISD::STORE, VT, Promote); 275 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 276 277 // No other operations are legal. 278 setOperationAction(ISD::MUL , VT, Expand); 279 setOperationAction(ISD::SDIV, VT, Expand); 280 setOperationAction(ISD::SREM, VT, Expand); 281 setOperationAction(ISD::UDIV, VT, Expand); 282 setOperationAction(ISD::UREM, VT, Expand); 283 setOperationAction(ISD::FDIV, VT, Expand); 284 setOperationAction(ISD::FNEG, VT, Expand); 285 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); 286 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 287 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); 288 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 289 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 290 setOperationAction(ISD::UDIVREM, VT, Expand); 291 setOperationAction(ISD::SDIVREM, VT, Expand); 292 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); 293 setOperationAction(ISD::FPOW, VT, Expand); 294 setOperationAction(ISD::CTPOP, VT, Expand); 295 setOperationAction(ISD::CTLZ, VT, Expand); 296 setOperationAction(ISD::CTTZ, VT, Expand); 297 } 298 299 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 300 // with merges, splats, etc. 301 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 302 303 setOperationAction(ISD::AND , MVT::v4i32, Legal); 304 setOperationAction(ISD::OR , MVT::v4i32, Legal); 305 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 306 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 307 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 308 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 309 310 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 311 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 312 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 313 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 314 315 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 316 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 317 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 318 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 319 320 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 321 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 322 323 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 324 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 325 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 326 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 327 } 328 329 setShiftAmountType(MVT::i32); 330 setSetCCResultContents(ZeroOrOneSetCCResult); 331 332 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 333 setStackPointerRegisterToSaveRestore(PPC::X1); 334 setExceptionPointerRegister(PPC::X3); 335 setExceptionSelectorRegister(PPC::X4); 336 } else { 337 setStackPointerRegisterToSaveRestore(PPC::R1); 338 setExceptionPointerRegister(PPC::R3); 339 setExceptionSelectorRegister(PPC::R4); 340 } 341 342 // We have target-specific dag combine patterns for the following nodes: 343 setTargetDAGCombine(ISD::SINT_TO_FP); 344 setTargetDAGCombine(ISD::STORE); 345 setTargetDAGCombine(ISD::BR_CC); 346 setTargetDAGCombine(ISD::BSWAP); 347 348 // Darwin long double math library functions have $LDBL128 appended. 349 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) { 350 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 351 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 352 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 353 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 354 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 355 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128"); 356 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128"); 357 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128"); 358 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128"); 359 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128"); 360 } 361 362 computeRegisterProperties(); 363} 364 365/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 366/// function arguments in the caller parameter area. 367unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const { 368 TargetMachine &TM = getTargetMachine(); 369 // Darwin passes everything on 4 byte boundary. 370 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) 371 return 4; 372 // FIXME Elf TBD 373 return 4; 374} 375 376const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 377 switch (Opcode) { 378 default: return 0; 379 case PPCISD::FSEL: return "PPCISD::FSEL"; 380 case PPCISD::FCFID: return "PPCISD::FCFID"; 381 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 382 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 383 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 384 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 385 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 386 case PPCISD::VPERM: return "PPCISD::VPERM"; 387 case PPCISD::Hi: return "PPCISD::Hi"; 388 case PPCISD::Lo: return "PPCISD::Lo"; 389 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 390 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 391 case PPCISD::SRL: return "PPCISD::SRL"; 392 case PPCISD::SRA: return "PPCISD::SRA"; 393 case PPCISD::SHL: return "PPCISD::SHL"; 394 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 395 case PPCISD::STD_32: return "PPCISD::STD_32"; 396 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF"; 397 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho"; 398 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 399 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho"; 400 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF"; 401 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 402 case PPCISD::MFCR: return "PPCISD::MFCR"; 403 case PPCISD::VCMP: return "PPCISD::VCMP"; 404 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 405 case PPCISD::LBRX: return "PPCISD::LBRX"; 406 case PPCISD::STBRX: return "PPCISD::STBRX"; 407 case PPCISD::LARX: return "PPCISD::LARX"; 408 case PPCISD::STCX: return "PPCISD::STCX"; 409 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 410 case PPCISD::MFFS: return "PPCISD::MFFS"; 411 case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; 412 case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; 413 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 414 case PPCISD::MTFSF: return "PPCISD::MTFSF"; 415 case PPCISD::TAILCALL: return "PPCISD::TAILCALL"; 416 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; 417 } 418} 419 420 421MVT PPCTargetLowering::getSetCCResultType(const SDValue &) const { 422 return MVT::i32; 423} 424 425 426//===----------------------------------------------------------------------===// 427// Node matching predicates, for use by the tblgen matching code. 428//===----------------------------------------------------------------------===// 429 430/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 431static bool isFloatingPointZero(SDValue Op) { 432 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 433 return CFP->getValueAPF().isZero(); 434 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 435 // Maybe this has already been legalized into the constant pool? 436 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 437 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 438 return CFP->getValueAPF().isZero(); 439 } 440 return false; 441} 442 443/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 444/// true if Op is undef or if it matches the specified value. 445static bool isConstantOrUndef(SDValue Op, unsigned Val) { 446 return Op.getOpcode() == ISD::UNDEF || 447 cast<ConstantSDNode>(Op)->getZExtValue() == Val; 448} 449 450/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 451/// VPKUHUM instruction. 452bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { 453 if (!isUnary) { 454 for (unsigned i = 0; i != 16; ++i) 455 if (!isConstantOrUndef(N->getOperand(i), i*2+1)) 456 return false; 457 } else { 458 for (unsigned i = 0; i != 8; ++i) 459 if (!isConstantOrUndef(N->getOperand(i), i*2+1) || 460 !isConstantOrUndef(N->getOperand(i+8), i*2+1)) 461 return false; 462 } 463 return true; 464} 465 466/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 467/// VPKUWUM instruction. 468bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { 469 if (!isUnary) { 470 for (unsigned i = 0; i != 16; i += 2) 471 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 472 !isConstantOrUndef(N->getOperand(i+1), i*2+3)) 473 return false; 474 } else { 475 for (unsigned i = 0; i != 8; i += 2) 476 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 477 !isConstantOrUndef(N->getOperand(i+1), i*2+3) || 478 !isConstantOrUndef(N->getOperand(i+8), i*2+2) || 479 !isConstantOrUndef(N->getOperand(i+9), i*2+3)) 480 return false; 481 } 482 return true; 483} 484 485/// isVMerge - Common function, used to match vmrg* shuffles. 486/// 487static bool isVMerge(SDNode *N, unsigned UnitSize, 488 unsigned LHSStart, unsigned RHSStart) { 489 assert(N->getOpcode() == ISD::BUILD_VECTOR && 490 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 491 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 492 "Unsupported merge size!"); 493 494 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 495 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 496 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), 497 LHSStart+j+i*UnitSize) || 498 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), 499 RHSStart+j+i*UnitSize)) 500 return false; 501 } 502 return true; 503} 504 505/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 506/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 507bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 508 if (!isUnary) 509 return isVMerge(N, UnitSize, 8, 24); 510 return isVMerge(N, UnitSize, 8, 8); 511} 512 513/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 514/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 515bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 516 if (!isUnary) 517 return isVMerge(N, UnitSize, 0, 16); 518 return isVMerge(N, UnitSize, 0, 0); 519} 520 521 522/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 523/// amount, otherwise return -1. 524int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 525 assert(N->getOpcode() == ISD::BUILD_VECTOR && 526 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 527 // Find the first non-undef value in the shuffle mask. 528 unsigned i; 529 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) 530 /*search*/; 531 532 if (i == 16) return -1; // all undef. 533 534 // Otherwise, check to see if the rest of the elements are consequtively 535 // numbered from this value. 536 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getZExtValue(); 537 if (ShiftAmt < i) return -1; 538 ShiftAmt -= i; 539 540 if (!isUnary) { 541 // Check the rest of the elements to see if they are consequtive. 542 for (++i; i != 16; ++i) 543 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) 544 return -1; 545 } else { 546 // Check the rest of the elements to see if they are consequtive. 547 for (++i; i != 16; ++i) 548 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) 549 return -1; 550 } 551 552 return ShiftAmt; 553} 554 555/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 556/// specifies a splat of a single element that is suitable for input to 557/// VSPLTB/VSPLTH/VSPLTW. 558bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { 559 assert(N->getOpcode() == ISD::BUILD_VECTOR && 560 N->getNumOperands() == 16 && 561 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 562 563 // This is a splat operation if each element of the permute is the same, and 564 // if the value doesn't reference the second vector. 565 unsigned ElementBase = 0; 566 SDValue Elt = N->getOperand(0); 567 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) 568 ElementBase = EltV->getZExtValue(); 569 else 570 return false; // FIXME: Handle UNDEF elements too! 571 572 if (cast<ConstantSDNode>(Elt)->getZExtValue() >= 16) 573 return false; 574 575 // Check that they are consequtive. 576 for (unsigned i = 1; i != EltSize; ++i) { 577 if (!isa<ConstantSDNode>(N->getOperand(i)) || 578 cast<ConstantSDNode>(N->getOperand(i))->getZExtValue() != i+ElementBase) 579 return false; 580 } 581 582 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); 583 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 584 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 585 assert(isa<ConstantSDNode>(N->getOperand(i)) && 586 "Invalid VECTOR_SHUFFLE mask!"); 587 for (unsigned j = 0; j != EltSize; ++j) 588 if (N->getOperand(i+j) != N->getOperand(j)) 589 return false; 590 } 591 592 return true; 593} 594 595/// isAllNegativeZeroVector - Returns true if all elements of build_vector 596/// are -0.0. 597bool PPC::isAllNegativeZeroVector(SDNode *N) { 598 assert(N->getOpcode() == ISD::BUILD_VECTOR); 599 if (PPC::isSplatShuffleMask(N, N->getNumOperands())) 600 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N)) 601 return CFP->getValueAPF().isNegZero(); 602 return false; 603} 604 605/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 606/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 607unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 608 assert(isSplatShuffleMask(N, EltSize)); 609 return cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() / EltSize; 610} 611 612/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 613/// by using a vspltis[bhw] instruction of the specified element size, return 614/// the constant being splatted. The ByteSize field indicates the number of 615/// bytes of each element [124] -> [bhw]. 616SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 617 SDValue OpVal(0, 0); 618 619 // If ByteSize of the splat is bigger than the element size of the 620 // build_vector, then we have a case where we are checking for a splat where 621 // multiple elements of the buildvector are folded together into a single 622 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 623 unsigned EltSize = 16/N->getNumOperands(); 624 if (EltSize < ByteSize) { 625 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 626 SDValue UniquedVals[4]; 627 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 628 629 // See if all of the elements in the buildvector agree across. 630 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 631 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 632 // If the element isn't a constant, bail fully out. 633 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue(); 634 635 636 if (UniquedVals[i&(Multiple-1)].getNode() == 0) 637 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 638 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 639 return SDValue(); // no match. 640 } 641 642 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 643 // either constant or undef values that are identical for each chunk. See 644 // if these chunks can form into a larger vspltis*. 645 646 // Check to see if all of the leading entries are either 0 or -1. If 647 // neither, then this won't fit into the immediate field. 648 bool LeadingZero = true; 649 bool LeadingOnes = true; 650 for (unsigned i = 0; i != Multiple-1; ++i) { 651 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs. 652 653 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 654 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 655 } 656 // Finally, check the least significant entry. 657 if (LeadingZero) { 658 if (UniquedVals[Multiple-1].getNode() == 0) 659 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 660 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue(); 661 if (Val < 16) 662 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 663 } 664 if (LeadingOnes) { 665 if (UniquedVals[Multiple-1].getNode() == 0) 666 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 667 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended(); 668 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 669 return DAG.getTargetConstant(Val, MVT::i32); 670 } 671 672 return SDValue(); 673 } 674 675 // Check to see if this buildvec has a single non-undef value in its elements. 676 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 677 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 678 if (OpVal.getNode() == 0) 679 OpVal = N->getOperand(i); 680 else if (OpVal != N->getOperand(i)) 681 return SDValue(); 682 } 683 684 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def. 685 686 unsigned ValSizeInBytes = 0; 687 uint64_t Value = 0; 688 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 689 Value = CN->getZExtValue(); 690 ValSizeInBytes = CN->getValueType(0).getSizeInBits()/8; 691 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 692 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 693 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 694 ValSizeInBytes = 4; 695 } 696 697 // If the splat value is larger than the element value, then we can never do 698 // this splat. The only case that we could fit the replicated bits into our 699 // immediate field for would be zero, and we prefer to use vxor for it. 700 if (ValSizeInBytes < ByteSize) return SDValue(); 701 702 // If the element value is larger than the splat value, cut it in half and 703 // check to see if the two halves are equal. Continue doing this until we 704 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 705 while (ValSizeInBytes > ByteSize) { 706 ValSizeInBytes >>= 1; 707 708 // If the top half equals the bottom half, we're still ok. 709 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 710 (Value & ((1 << (8*ValSizeInBytes))-1))) 711 return SDValue(); 712 } 713 714 // Properly sign extend the value. 715 int ShAmt = (4-ByteSize)*8; 716 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 717 718 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 719 if (MaskVal == 0) return SDValue(); 720 721 // Finally, if this value fits in a 5 bit sext field, return it 722 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 723 return DAG.getTargetConstant(MaskVal, MVT::i32); 724 return SDValue(); 725} 726 727//===----------------------------------------------------------------------===// 728// Addressing Mode Selection 729//===----------------------------------------------------------------------===// 730 731/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 732/// or 64-bit immediate, and if the value can be accurately represented as a 733/// sign extension from a 16-bit value. If so, this returns true and the 734/// immediate. 735static bool isIntS16Immediate(SDNode *N, short &Imm) { 736 if (N->getOpcode() != ISD::Constant) 737 return false; 738 739 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 740 if (N->getValueType(0) == MVT::i32) 741 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 742 else 743 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 744} 745static bool isIntS16Immediate(SDValue Op, short &Imm) { 746 return isIntS16Immediate(Op.getNode(), Imm); 747} 748 749 750/// SelectAddressRegReg - Given the specified addressed, check to see if it 751/// can be represented as an indexed [r+r] operation. Returns false if it 752/// can be more efficiently represented with [r+imm]. 753bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, 754 SDValue &Index, 755 SelectionDAG &DAG) { 756 short imm = 0; 757 if (N.getOpcode() == ISD::ADD) { 758 if (isIntS16Immediate(N.getOperand(1), imm)) 759 return false; // r+i 760 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 761 return false; // r+i 762 763 Base = N.getOperand(0); 764 Index = N.getOperand(1); 765 return true; 766 } else if (N.getOpcode() == ISD::OR) { 767 if (isIntS16Immediate(N.getOperand(1), imm)) 768 return false; // r+i can fold it if we can. 769 770 // If this is an or of disjoint bitfields, we can codegen this as an add 771 // (for better address arithmetic) if the LHS and RHS of the OR are provably 772 // disjoint. 773 APInt LHSKnownZero, LHSKnownOne; 774 APInt RHSKnownZero, RHSKnownOne; 775 DAG.ComputeMaskedBits(N.getOperand(0), 776 APInt::getAllOnesValue(N.getOperand(0) 777 .getValueSizeInBits()), 778 LHSKnownZero, LHSKnownOne); 779 780 if (LHSKnownZero.getBoolValue()) { 781 DAG.ComputeMaskedBits(N.getOperand(1), 782 APInt::getAllOnesValue(N.getOperand(1) 783 .getValueSizeInBits()), 784 RHSKnownZero, RHSKnownOne); 785 // If all of the bits are known zero on the LHS or RHS, the add won't 786 // carry. 787 if (~(LHSKnownZero | RHSKnownZero) == 0) { 788 Base = N.getOperand(0); 789 Index = N.getOperand(1); 790 return true; 791 } 792 } 793 } 794 795 return false; 796} 797 798/// Returns true if the address N can be represented by a base register plus 799/// a signed 16-bit displacement [r+imm], and if it is not better 800/// represented as reg+reg. 801bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, 802 SDValue &Base, SelectionDAG &DAG){ 803 // If this can be more profitably realized as r+r, fail. 804 if (SelectAddressRegReg(N, Disp, Base, DAG)) 805 return false; 806 807 if (N.getOpcode() == ISD::ADD) { 808 short imm = 0; 809 if (isIntS16Immediate(N.getOperand(1), imm)) { 810 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 811 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 812 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 813 } else { 814 Base = N.getOperand(0); 815 } 816 return true; // [r+i] 817 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 818 // Match LOAD (ADD (X, Lo(G))). 819 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 820 && "Cannot handle constant offsets yet!"); 821 Disp = N.getOperand(1).getOperand(0); // The global address. 822 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 823 Disp.getOpcode() == ISD::TargetConstantPool || 824 Disp.getOpcode() == ISD::TargetJumpTable); 825 Base = N.getOperand(0); 826 return true; // [&g+r] 827 } 828 } else if (N.getOpcode() == ISD::OR) { 829 short imm = 0; 830 if (isIntS16Immediate(N.getOperand(1), imm)) { 831 // If this is an or of disjoint bitfields, we can codegen this as an add 832 // (for better address arithmetic) if the LHS and RHS of the OR are 833 // provably disjoint. 834 APInt LHSKnownZero, LHSKnownOne; 835 DAG.ComputeMaskedBits(N.getOperand(0), 836 APInt::getAllOnesValue(N.getOperand(0) 837 .getValueSizeInBits()), 838 LHSKnownZero, LHSKnownOne); 839 840 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 841 // If all of the bits are known zero on the LHS or RHS, the add won't 842 // carry. 843 Base = N.getOperand(0); 844 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 845 return true; 846 } 847 } 848 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 849 // Loading from a constant address. 850 851 // If this address fits entirely in a 16-bit sext immediate field, codegen 852 // this as "d, 0" 853 short Imm; 854 if (isIntS16Immediate(CN, Imm)) { 855 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 856 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 857 return true; 858 } 859 860 // Handle 32-bit sext immediates with LIS + addr mode. 861 if (CN->getValueType(0) == MVT::i32 || 862 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 863 int Addr = (int)CN->getZExtValue(); 864 865 // Otherwise, break this down into an LIS + disp. 866 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 867 868 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 869 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 870 Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 871 return true; 872 } 873 } 874 875 Disp = DAG.getTargetConstant(0, getPointerTy()); 876 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 877 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 878 else 879 Base = N; 880 return true; // [r+0] 881} 882 883/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 884/// represented as an indexed [r+r] operation. 885bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, 886 SDValue &Index, 887 SelectionDAG &DAG) { 888 // Check to see if we can easily represent this as an [r+r] address. This 889 // will fail if it thinks that the address is more profitably represented as 890 // reg+imm, e.g. where imm = 0. 891 if (SelectAddressRegReg(N, Base, Index, DAG)) 892 return true; 893 894 // If the operand is an addition, always emit this as [r+r], since this is 895 // better (for code size, and execution, as the memop does the add for free) 896 // than emitting an explicit add. 897 if (N.getOpcode() == ISD::ADD) { 898 Base = N.getOperand(0); 899 Index = N.getOperand(1); 900 return true; 901 } 902 903 // Otherwise, do it the hard way, using R0 as the base register. 904 Base = DAG.getRegister(PPC::R0, N.getValueType()); 905 Index = N; 906 return true; 907} 908 909/// SelectAddressRegImmShift - Returns true if the address N can be 910/// represented by a base register plus a signed 14-bit displacement 911/// [r+imm*4]. Suitable for use by STD and friends. 912bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, 913 SDValue &Base, 914 SelectionDAG &DAG) { 915 // If this can be more profitably realized as r+r, fail. 916 if (SelectAddressRegReg(N, Disp, Base, DAG)) 917 return false; 918 919 if (N.getOpcode() == ISD::ADD) { 920 short imm = 0; 921 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 922 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 923 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 924 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 925 } else { 926 Base = N.getOperand(0); 927 } 928 return true; // [r+i] 929 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 930 // Match LOAD (ADD (X, Lo(G))). 931 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 932 && "Cannot handle constant offsets yet!"); 933 Disp = N.getOperand(1).getOperand(0); // The global address. 934 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 935 Disp.getOpcode() == ISD::TargetConstantPool || 936 Disp.getOpcode() == ISD::TargetJumpTable); 937 Base = N.getOperand(0); 938 return true; // [&g+r] 939 } 940 } else if (N.getOpcode() == ISD::OR) { 941 short imm = 0; 942 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 943 // If this is an or of disjoint bitfields, we can codegen this as an add 944 // (for better address arithmetic) if the LHS and RHS of the OR are 945 // provably disjoint. 946 APInt LHSKnownZero, LHSKnownOne; 947 DAG.ComputeMaskedBits(N.getOperand(0), 948 APInt::getAllOnesValue(N.getOperand(0) 949 .getValueSizeInBits()), 950 LHSKnownZero, LHSKnownOne); 951 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 952 // If all of the bits are known zero on the LHS or RHS, the add won't 953 // carry. 954 Base = N.getOperand(0); 955 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 956 return true; 957 } 958 } 959 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 960 // Loading from a constant address. Verify low two bits are clear. 961 if ((CN->getZExtValue() & 3) == 0) { 962 // If this address fits entirely in a 14-bit sext immediate field, codegen 963 // this as "d, 0" 964 short Imm; 965 if (isIntS16Immediate(CN, Imm)) { 966 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 967 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 968 return true; 969 } 970 971 // Fold the low-part of 32-bit absolute addresses into addr mode. 972 if (CN->getValueType(0) == MVT::i32 || 973 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 974 int Addr = (int)CN->getZExtValue(); 975 976 // Otherwise, break this down into an LIS + disp. 977 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 978 979 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 980 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 981 Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 982 return true; 983 } 984 } 985 } 986 987 Disp = DAG.getTargetConstant(0, getPointerTy()); 988 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 989 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 990 else 991 Base = N; 992 return true; // [r+0] 993} 994 995 996/// getPreIndexedAddressParts - returns true by value, base pointer and 997/// offset pointer and addressing mode by reference if the node's address 998/// can be legally represented as pre-indexed load / store address. 999bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1000 SDValue &Offset, 1001 ISD::MemIndexedMode &AM, 1002 SelectionDAG &DAG) { 1003 // Disabled by default for now. 1004 if (!EnablePPCPreinc) return false; 1005 1006 SDValue Ptr; 1007 MVT VT; 1008 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1009 Ptr = LD->getBasePtr(); 1010 VT = LD->getMemoryVT(); 1011 1012 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1013 ST = ST; 1014 Ptr = ST->getBasePtr(); 1015 VT = ST->getMemoryVT(); 1016 } else 1017 return false; 1018 1019 // PowerPC doesn't have preinc load/store instructions for vectors. 1020 if (VT.isVector()) 1021 return false; 1022 1023 // TODO: Check reg+reg first. 1024 1025 // LDU/STU use reg+imm*4, others use reg+imm. 1026 if (VT != MVT::i64) { 1027 // reg + imm 1028 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 1029 return false; 1030 } else { 1031 // reg + imm * 4. 1032 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 1033 return false; 1034 } 1035 1036 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1037 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 1038 // sext i32 to i64 when addr mode is r+i. 1039 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 1040 LD->getExtensionType() == ISD::SEXTLOAD && 1041 isa<ConstantSDNode>(Offset)) 1042 return false; 1043 } 1044 1045 AM = ISD::PRE_INC; 1046 return true; 1047} 1048 1049//===----------------------------------------------------------------------===// 1050// LowerOperation implementation 1051//===----------------------------------------------------------------------===// 1052 1053SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, 1054 SelectionDAG &DAG) { 1055 MVT PtrVT = Op.getValueType(); 1056 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1057 Constant *C = CP->getConstVal(); 1058 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 1059 SDValue Zero = DAG.getConstant(0, PtrVT); 1060 1061 const TargetMachine &TM = DAG.getTarget(); 1062 1063 SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); 1064 SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); 1065 1066 // If this is a non-darwin platform, we don't support non-static relo models 1067 // yet. 1068 if (TM.getRelocationModel() == Reloc::Static || 1069 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1070 // Generate non-pic code that has direct accesses to the constant pool. 1071 // The address of the global is just (hi(&g)+lo(&g)). 1072 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1073 } 1074 1075 if (TM.getRelocationModel() == Reloc::PIC_) { 1076 // With PIC, the first instruction is actually "GR+hi(&G)". 1077 Hi = DAG.getNode(ISD::ADD, PtrVT, 1078 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1079 } 1080 1081 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1082 return Lo; 1083} 1084 1085SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { 1086 MVT PtrVT = Op.getValueType(); 1087 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1088 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1089 SDValue Zero = DAG.getConstant(0, PtrVT); 1090 1091 const TargetMachine &TM = DAG.getTarget(); 1092 1093 SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); 1094 SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); 1095 1096 // If this is a non-darwin platform, we don't support non-static relo models 1097 // yet. 1098 if (TM.getRelocationModel() == Reloc::Static || 1099 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1100 // Generate non-pic code that has direct accesses to the constant pool. 1101 // The address of the global is just (hi(&g)+lo(&g)). 1102 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1103 } 1104 1105 if (TM.getRelocationModel() == Reloc::PIC_) { 1106 // With PIC, the first instruction is actually "GR+hi(&G)". 1107 Hi = DAG.getNode(ISD::ADD, PtrVT, 1108 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1109 } 1110 1111 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1112 return Lo; 1113} 1114 1115SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, 1116 SelectionDAG &DAG) { 1117 assert(0 && "TLS not implemented for PPC."); 1118 return SDValue(); // Not reached 1119} 1120 1121SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, 1122 SelectionDAG &DAG) { 1123 MVT PtrVT = Op.getValueType(); 1124 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1125 GlobalValue *GV = GSDN->getGlobal(); 1126 SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); 1127 // If it's a debug information descriptor, don't mess with it. 1128 if (DAG.isVerifiedDebugInfoDesc(Op)) 1129 return GA; 1130 SDValue Zero = DAG.getConstant(0, PtrVT); 1131 1132 const TargetMachine &TM = DAG.getTarget(); 1133 1134 SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); 1135 SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); 1136 1137 // If this is a non-darwin platform, we don't support non-static relo models 1138 // yet. 1139 if (TM.getRelocationModel() == Reloc::Static || 1140 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1141 // Generate non-pic code that has direct accesses to globals. 1142 // The address of the global is just (hi(&g)+lo(&g)). 1143 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1144 } 1145 1146 if (TM.getRelocationModel() == Reloc::PIC_) { 1147 // With PIC, the first instruction is actually "GR+hi(&G)". 1148 Hi = DAG.getNode(ISD::ADD, PtrVT, 1149 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1150 } 1151 1152 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1153 1154 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV)) 1155 return Lo; 1156 1157 // If the global is weak or external, we have to go through the lazy 1158 // resolution stub. 1159 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); 1160} 1161 1162SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { 1163 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1164 1165 // If we're comparing for equality to zero, expose the fact that this is 1166 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1167 // fold the new nodes. 1168 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1169 if (C->isNullValue() && CC == ISD::SETEQ) { 1170 MVT VT = Op.getOperand(0).getValueType(); 1171 SDValue Zext = Op.getOperand(0); 1172 if (VT.bitsLT(MVT::i32)) { 1173 VT = MVT::i32; 1174 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); 1175 } 1176 unsigned Log2b = Log2_32(VT.getSizeInBits()); 1177 SDValue Clz = DAG.getNode(ISD::CTLZ, VT, Zext); 1178 SDValue Scc = DAG.getNode(ISD::SRL, VT, Clz, 1179 DAG.getConstant(Log2b, MVT::i32)); 1180 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); 1181 } 1182 // Leave comparisons against 0 and -1 alone for now, since they're usually 1183 // optimized. FIXME: revisit this when we can custom lower all setcc 1184 // optimizations. 1185 if (C->isAllOnesValue() || C->isNullValue()) 1186 return SDValue(); 1187 } 1188 1189 // If we have an integer seteq/setne, turn it into a compare against zero 1190 // by xor'ing the rhs with the lhs, which is faster than setting a 1191 // condition register, reading it back out, and masking the correct bit. The 1192 // normal approach here uses sub to do this instead of xor. Using xor exposes 1193 // the result to other bit-twiddling opportunities. 1194 MVT LHSVT = Op.getOperand(0).getValueType(); 1195 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1196 MVT VT = Op.getValueType(); 1197 SDValue Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), 1198 Op.getOperand(1)); 1199 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); 1200 } 1201 return SDValue(); 1202} 1203 1204SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, 1205 int VarArgsFrameIndex, 1206 int VarArgsStackOffset, 1207 unsigned VarArgsNumGPR, 1208 unsigned VarArgsNumFPR, 1209 const PPCSubtarget &Subtarget) { 1210 1211 assert(0 && "VAARG in ELF32 ABI not implemented yet!"); 1212 return SDValue(); // Not reached 1213} 1214 1215SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) { 1216 SDValue Chain = Op.getOperand(0); 1217 SDValue Trmp = Op.getOperand(1); // trampoline 1218 SDValue FPtr = Op.getOperand(2); // nested function 1219 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 1220 1221 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1222 bool isPPC64 = (PtrVT == MVT::i64); 1223 const Type *IntPtrTy = 1224 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType(); 1225 1226 TargetLowering::ArgListTy Args; 1227 TargetLowering::ArgListEntry Entry; 1228 1229 Entry.Ty = IntPtrTy; 1230 Entry.Node = Trmp; Args.push_back(Entry); 1231 1232 // TrampSize == (isPPC64 ? 48 : 40); 1233 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, 1234 isPPC64 ? MVT::i64 : MVT::i32); 1235 Args.push_back(Entry); 1236 1237 Entry.Node = FPtr; Args.push_back(Entry); 1238 Entry.Node = Nest; Args.push_back(Entry); 1239 1240 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) 1241 std::pair<SDValue, SDValue> CallResult = 1242 LowerCallTo(Chain, Op.getValueType().getTypeForMVT(), false, false, 1243 false, false, CallingConv::C, false, 1244 DAG.getExternalSymbol("__trampoline_setup", PtrVT), 1245 Args, DAG); 1246 1247 SDValue Ops[] = 1248 { CallResult.first, CallResult.second }; 1249 1250 return DAG.getMergeValues(Ops, 2, false); 1251} 1252 1253SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, 1254 int VarArgsFrameIndex, 1255 int VarArgsStackOffset, 1256 unsigned VarArgsNumGPR, 1257 unsigned VarArgsNumFPR, 1258 const PPCSubtarget &Subtarget) { 1259 1260 if (Subtarget.isMachoABI()) { 1261 // vastart just stores the address of the VarArgsFrameIndex slot into the 1262 // memory location argument. 1263 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1264 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1265 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1266 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); 1267 } 1268 1269 // For ELF 32 ABI we follow the layout of the va_list struct. 1270 // We suppose the given va_list is already allocated. 1271 // 1272 // typedef struct { 1273 // char gpr; /* index into the array of 8 GPRs 1274 // * stored in the register save area 1275 // * gpr=0 corresponds to r3, 1276 // * gpr=1 to r4, etc. 1277 // */ 1278 // char fpr; /* index into the array of 8 FPRs 1279 // * stored in the register save area 1280 // * fpr=0 corresponds to f1, 1281 // * fpr=1 to f2, etc. 1282 // */ 1283 // char *overflow_arg_area; 1284 // /* location on stack that holds 1285 // * the next overflow argument 1286 // */ 1287 // char *reg_save_area; 1288 // /* where r3:r10 and f1:f8 (if saved) 1289 // * are stored 1290 // */ 1291 // } va_list[1]; 1292 1293 1294 SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8); 1295 SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8); 1296 1297 1298 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1299 1300 SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); 1301 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1302 1303 uint64_t FrameOffset = PtrVT.getSizeInBits()/8; 1304 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1305 1306 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; 1307 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1308 1309 uint64_t FPROffset = 1; 1310 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1311 1312 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1313 1314 // Store first byte : number of int regs 1315 SDValue firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, 1316 Op.getOperand(1), SV, 0); 1317 uint64_t nextOffset = FPROffset; 1318 SDValue nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), 1319 ConstFPROffset); 1320 1321 // Store second byte : number of float regs 1322 SDValue secondStore = 1323 DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset); 1324 nextOffset += StackOffset; 1325 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset); 1326 1327 // Store second word : arguments given on stack 1328 SDValue thirdStore = 1329 DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset); 1330 nextOffset += FrameOffset; 1331 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset); 1332 1333 // Store third word : arguments given in registers 1334 return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset); 1335 1336} 1337 1338#include "PPCGenCallingConv.inc" 1339 1340/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1341/// depending on which subtarget is selected. 1342static const unsigned *GetFPR(const PPCSubtarget &Subtarget) { 1343 if (Subtarget.isMachoABI()) { 1344 static const unsigned FPR[] = { 1345 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1346 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1347 }; 1348 return FPR; 1349 } 1350 1351 1352 static const unsigned FPR[] = { 1353 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1354 PPC::F8 1355 }; 1356 return FPR; 1357} 1358 1359/// CalculateStackSlotSize - Calculates the size reserved for this argument on 1360/// the stack. 1361static unsigned CalculateStackSlotSize(SDValue Arg, ISD::ArgFlagsTy Flags, 1362 bool isVarArg, unsigned PtrByteSize) { 1363 MVT ArgVT = Arg.getValueType(); 1364 unsigned ArgSize =ArgVT.getSizeInBits()/8; 1365 if (Flags.isByVal()) 1366 ArgSize = Flags.getByValSize(); 1367 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1368 1369 return ArgSize; 1370} 1371 1372SDValue 1373PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, 1374 SelectionDAG &DAG, 1375 int &VarArgsFrameIndex, 1376 int &VarArgsStackOffset, 1377 unsigned &VarArgsNumGPR, 1378 unsigned &VarArgsNumFPR, 1379 const PPCSubtarget &Subtarget) { 1380 // TODO: add description of PPC stack frame format, or at least some docs. 1381 // 1382 MachineFunction &MF = DAG.getMachineFunction(); 1383 MachineFrameInfo *MFI = MF.getFrameInfo(); 1384 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 1385 SmallVector<SDValue, 8> ArgValues; 1386 SDValue Root = Op.getOperand(0); 1387 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0; 1388 1389 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1390 bool isPPC64 = PtrVT == MVT::i64; 1391 bool isMachoABI = Subtarget.isMachoABI(); 1392 bool isELF32_ABI = Subtarget.isELF32_ABI(); 1393 // Potential tail calls could cause overwriting of argument stack slots. 1394 unsigned CC = MF.getFunction()->getCallingConv(); 1395 bool isImmutable = !(PerformTailCallOpt && (CC==CallingConv::Fast)); 1396 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1397 1398 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1399 // Area that is at least reserved in caller of this function. 1400 unsigned MinReservedArea = ArgOffset; 1401 1402 static const unsigned GPR_32[] = { // 32-bit registers. 1403 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1404 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1405 }; 1406 static const unsigned GPR_64[] = { // 64-bit registers. 1407 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1408 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1409 }; 1410 1411 static const unsigned *FPR = GetFPR(Subtarget); 1412 1413 static const unsigned VR[] = { 1414 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1415 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1416 }; 1417 1418 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 1419 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8; 1420 const unsigned Num_VR_Regs = array_lengthof( VR); 1421 1422 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1423 1424 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1425 1426 // In 32-bit non-varargs functions, the stack space for vectors is after the 1427 // stack space for non-vectors. We do not use this space unless we have 1428 // too many vectors to fit in registers, something that only occurs in 1429 // constructed examples:), but we have to walk the arglist to figure 1430 // that out...for the pathological case, compute VecArgOffset as the 1431 // start of the vector parameter area. Computing VecArgOffset is the 1432 // entire point of the following loop. 1433 // Altivec is not mentioned in the ppc32 Elf Supplement, so I'm not trying 1434 // to handle Elf here. 1435 unsigned VecArgOffset = ArgOffset; 1436 if (!isVarArg && !isPPC64) { 1437 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e; 1438 ++ArgNo) { 1439 MVT ObjectVT = Op.getValue(ArgNo).getValueType(); 1440 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1441 ISD::ArgFlagsTy Flags = 1442 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags(); 1443 1444 if (Flags.isByVal()) { 1445 // ObjSize is the true size, ArgSize rounded up to multiple of regs. 1446 ObjSize = Flags.getByValSize(); 1447 unsigned ArgSize = 1448 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1449 VecArgOffset += ArgSize; 1450 continue; 1451 } 1452 1453 switch(ObjectVT.getSimpleVT()) { 1454 default: assert(0 && "Unhandled argument type!"); 1455 case MVT::i32: 1456 case MVT::f32: 1457 VecArgOffset += isPPC64 ? 8 : 4; 1458 break; 1459 case MVT::i64: // PPC64 1460 case MVT::f64: 1461 VecArgOffset += 8; 1462 break; 1463 case MVT::v4f32: 1464 case MVT::v4i32: 1465 case MVT::v8i16: 1466 case MVT::v16i8: 1467 // Nothing to do, we're only looking at Nonvector args here. 1468 break; 1469 } 1470 } 1471 } 1472 // We've found where the vector parameter area in memory is. Skip the 1473 // first 12 parameters; these don't use that memory. 1474 VecArgOffset = ((VecArgOffset+15)/16)*16; 1475 VecArgOffset += 12*16; 1476 1477 // Add DAG nodes to load the arguments or copy them out of registers. On 1478 // entry to a function on PPC, the arguments start after the linkage area, 1479 // although the first ones are often in registers. 1480 // 1481 // In the ELF 32 ABI, GPRs and stack are double word align: an argument 1482 // represented with two words (long long or double) must be copied to an 1483 // even GPR_idx value or to an even ArgOffset value. 1484 1485 SmallVector<SDValue, 8> MemOps; 1486 unsigned nAltivecParamsAtEnd = 0; 1487 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues() - 1; 1488 ArgNo != e; ++ArgNo) { 1489 SDValue ArgVal; 1490 bool needsLoad = false; 1491 MVT ObjectVT = Op.getValue(ArgNo).getValueType(); 1492 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1493 unsigned ArgSize = ObjSize; 1494 ISD::ArgFlagsTy Flags = 1495 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags(); 1496 // See if next argument requires stack alignment in ELF 1497 bool Align = Flags.isSplit(); 1498 1499 unsigned CurArgOffset = ArgOffset; 1500 1501 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 1502 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 1503 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 1504 if (isVarArg || isPPC64) { 1505 MinReservedArea = ((MinReservedArea+15)/16)*16; 1506 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo), 1507 Flags, 1508 isVarArg, 1509 PtrByteSize); 1510 } else nAltivecParamsAtEnd++; 1511 } else 1512 // Calculate min reserved area. 1513 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo), 1514 Flags, 1515 isVarArg, 1516 PtrByteSize); 1517 1518 // FIXME alignment for ELF may not be right 1519 // FIXME the codegen can be much improved in some cases. 1520 // We do not have to keep everything in memory. 1521 if (Flags.isByVal()) { 1522 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 1523 ObjSize = Flags.getByValSize(); 1524 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1525 // Double word align in ELF 1526 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2); 1527 // Objects of size 1 and 2 are right justified, everything else is 1528 // left justified. This means the memory address is adjusted forwards. 1529 if (ObjSize==1 || ObjSize==2) { 1530 CurArgOffset = CurArgOffset + (4 - ObjSize); 1531 } 1532 // The value of the object is its address. 1533 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset); 1534 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1535 ArgValues.push_back(FIN); 1536 if (ObjSize==1 || ObjSize==2) { 1537 if (GPR_idx != Num_GPR_Regs) { 1538 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1539 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1540 SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 1541 SDValue Store = DAG.getTruncStore(Val.getValue(1), Val, FIN, 1542 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 ); 1543 MemOps.push_back(Store); 1544 ++GPR_idx; 1545 if (isMachoABI) ArgOffset += PtrByteSize; 1546 } else { 1547 ArgOffset += PtrByteSize; 1548 } 1549 continue; 1550 } 1551 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 1552 // Store whatever pieces of the object are in registers 1553 // to memory. ArgVal will be address of the beginning of 1554 // the object. 1555 if (GPR_idx != Num_GPR_Regs) { 1556 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1557 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1558 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset); 1559 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1560 SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 1561 SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1562 MemOps.push_back(Store); 1563 ++GPR_idx; 1564 if (isMachoABI) ArgOffset += PtrByteSize; 1565 } else { 1566 ArgOffset += ArgSize - (ArgOffset-CurArgOffset); 1567 break; 1568 } 1569 } 1570 continue; 1571 } 1572 1573 switch (ObjectVT.getSimpleVT()) { 1574 default: assert(0 && "Unhandled argument type!"); 1575 case MVT::i32: 1576 if (!isPPC64) { 1577 // Double word align in ELF 1578 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2); 1579 1580 if (GPR_idx != Num_GPR_Regs) { 1581 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1582 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1583 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1584 ++GPR_idx; 1585 } else { 1586 needsLoad = true; 1587 ArgSize = PtrByteSize; 1588 } 1589 // Stack align in ELF 1590 if (needsLoad && Align && isELF32_ABI) 1591 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1592 // All int arguments reserve stack space in Macho ABI. 1593 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize; 1594 break; 1595 } 1596 // FALLTHROUGH 1597 case MVT::i64: // PPC64 1598 if (GPR_idx != Num_GPR_Regs) { 1599 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); 1600 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1601 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); 1602 1603 if (ObjectVT == MVT::i32) { 1604 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 1605 // value to MVT::i64 and then truncate to the correct register size. 1606 if (Flags.isSExt()) 1607 ArgVal = DAG.getNode(ISD::AssertSext, MVT::i64, ArgVal, 1608 DAG.getValueType(ObjectVT)); 1609 else if (Flags.isZExt()) 1610 ArgVal = DAG.getNode(ISD::AssertZext, MVT::i64, ArgVal, 1611 DAG.getValueType(ObjectVT)); 1612 1613 ArgVal = DAG.getNode(ISD::TRUNCATE, MVT::i32, ArgVal); 1614 } 1615 1616 ++GPR_idx; 1617 } else { 1618 needsLoad = true; 1619 ArgSize = PtrByteSize; 1620 } 1621 // All int arguments reserve stack space in Macho ABI. 1622 if (isMachoABI || needsLoad) ArgOffset += 8; 1623 break; 1624 1625 case MVT::f32: 1626 case MVT::f64: 1627 // Every 4 bytes of argument space consumes one of the GPRs available for 1628 // argument passing. 1629 if (GPR_idx != Num_GPR_Regs && isMachoABI) { 1630 ++GPR_idx; 1631 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 1632 ++GPR_idx; 1633 } 1634 if (FPR_idx != Num_FPR_Regs) { 1635 unsigned VReg; 1636 if (ObjectVT == MVT::f32) 1637 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass); 1638 else 1639 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); 1640 RegInfo.addLiveIn(FPR[FPR_idx], VReg); 1641 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1642 ++FPR_idx; 1643 } else { 1644 needsLoad = true; 1645 } 1646 1647 // Stack align in ELF 1648 if (needsLoad && Align && isELF32_ABI) 1649 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1650 // All FP arguments reserve stack space in Macho ABI. 1651 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize; 1652 break; 1653 case MVT::v4f32: 1654 case MVT::v4i32: 1655 case MVT::v8i16: 1656 case MVT::v16i8: 1657 // Note that vector arguments in registers don't reserve stack space, 1658 // except in varargs functions. 1659 if (VR_idx != Num_VR_Regs) { 1660 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass); 1661 RegInfo.addLiveIn(VR[VR_idx], VReg); 1662 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1663 if (isVarArg) { 1664 while ((ArgOffset % 16) != 0) { 1665 ArgOffset += PtrByteSize; 1666 if (GPR_idx != Num_GPR_Regs) 1667 GPR_idx++; 1668 } 1669 ArgOffset += 16; 1670 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); 1671 } 1672 ++VR_idx; 1673 } else { 1674 if (!isVarArg && !isPPC64) { 1675 // Vectors go after all the nonvectors. 1676 CurArgOffset = VecArgOffset; 1677 VecArgOffset += 16; 1678 } else { 1679 // Vectors are aligned. 1680 ArgOffset = ((ArgOffset+15)/16)*16; 1681 CurArgOffset = ArgOffset; 1682 ArgOffset += 16; 1683 } 1684 needsLoad = true; 1685 } 1686 break; 1687 } 1688 1689 // We need to load the argument to a virtual register if we determined above 1690 // that we ran out of physical registers of the appropriate type. 1691 if (needsLoad) { 1692 int FI = MFI->CreateFixedObject(ObjSize, 1693 CurArgOffset + (ArgSize - ObjSize), 1694 isImmutable); 1695 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1696 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 1697 } 1698 1699 ArgValues.push_back(ArgVal); 1700 } 1701 1702 // Set the size that is at least reserved in caller of this function. Tail 1703 // call optimized function's reserved stack space needs to be aligned so that 1704 // taking the difference between two stack areas will result in an aligned 1705 // stack. 1706 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1707 // Add the Altivec parameters at the end, if needed. 1708 if (nAltivecParamsAtEnd) { 1709 MinReservedArea = ((MinReservedArea+15)/16)*16; 1710 MinReservedArea += 16*nAltivecParamsAtEnd; 1711 } 1712 MinReservedArea = 1713 std::max(MinReservedArea, 1714 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI)); 1715 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 1716 getStackAlignment(); 1717 unsigned AlignMask = TargetAlign-1; 1718 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 1719 FI->setMinReservedArea(MinReservedArea); 1720 1721 // If the function takes variable number of arguments, make a frame index for 1722 // the start of the first vararg value... for expansion of llvm.va_start. 1723 if (isVarArg) { 1724 1725 int depth; 1726 if (isELF32_ABI) { 1727 VarArgsNumGPR = GPR_idx; 1728 VarArgsNumFPR = FPR_idx; 1729 1730 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame 1731 // pointer. 1732 depth = -(Num_GPR_Regs * PtrVT.getSizeInBits()/8 + 1733 Num_FPR_Regs * MVT(MVT::f64).getSizeInBits()/8 + 1734 PtrVT.getSizeInBits()/8); 1735 1736 VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 1737 ArgOffset); 1738 1739 } 1740 else 1741 depth = ArgOffset; 1742 1743 VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 1744 depth); 1745 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1746 1747 // In ELF 32 ABI, the fixed integer arguments of a variadic function are 1748 // stored to the VarArgsFrameIndex on the stack. 1749 if (isELF32_ABI) { 1750 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) { 1751 SDValue Val = DAG.getRegister(GPR[GPR_idx], PtrVT); 1752 SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0); 1753 MemOps.push_back(Store); 1754 // Increment the address by four for the next argument to store 1755 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 1756 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1757 } 1758 } 1759 1760 // If this function is vararg, store any remaining integer argument regs 1761 // to their spots on the stack so that they may be loaded by deferencing the 1762 // result of va_next. 1763 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 1764 unsigned VReg; 1765 if (isPPC64) 1766 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); 1767 else 1768 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1769 1770 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1771 SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 1772 SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1773 MemOps.push_back(Store); 1774 // Increment the address by four for the next argument to store 1775 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 1776 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1777 } 1778 1779 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex 1780 // on the stack. 1781 if (isELF32_ABI) { 1782 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) { 1783 SDValue Val = DAG.getRegister(FPR[FPR_idx], MVT::f64); 1784 SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0); 1785 MemOps.push_back(Store); 1786 // Increment the address by eight for the next argument to store 1787 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, 1788 PtrVT); 1789 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1790 } 1791 1792 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) { 1793 unsigned VReg; 1794 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); 1795 1796 RegInfo.addLiveIn(FPR[FPR_idx], VReg); 1797 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::f64); 1798 SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1799 MemOps.push_back(Store); 1800 // Increment the address by eight for the next argument to store 1801 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, 1802 PtrVT); 1803 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1804 } 1805 } 1806 } 1807 1808 if (!MemOps.empty()) 1809 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); 1810 1811 ArgValues.push_back(Root); 1812 1813 // Return the new list of results. 1814 return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0], 1815 ArgValues.size()); 1816} 1817 1818/// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus 1819/// linkage area. 1820static unsigned 1821CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, 1822 bool isPPC64, 1823 bool isMachoABI, 1824 bool isVarArg, 1825 unsigned CC, 1826 CallSDNode *TheCall, 1827 unsigned &nAltivecParamsAtEnd) { 1828 // Count how many bytes are to be pushed on the stack, including the linkage 1829 // area, and parameter passing area. We start with 24/48 bytes, which is 1830 // prereserved space for [SP][CR][LR][3 x unused]. 1831 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1832 unsigned NumOps = TheCall->getNumArgs(); 1833 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1834 1835 // Add up all the space actually used. 1836 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually 1837 // they all go in registers, but we must reserve stack space for them for 1838 // possible use by the caller. In varargs or 64-bit calls, parameters are 1839 // assigned stack space in order, with padding so Altivec parameters are 1840 // 16-byte aligned. 1841 nAltivecParamsAtEnd = 0; 1842 for (unsigned i = 0; i != NumOps; ++i) { 1843 SDValue Arg = TheCall->getArg(i); 1844 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i); 1845 MVT ArgVT = Arg.getValueType(); 1846 // Varargs Altivec parameters are padded to a 16 byte boundary. 1847 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 1848 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { 1849 if (!isVarArg && !isPPC64) { 1850 // Non-varargs Altivec parameters go after all the non-Altivec 1851 // parameters; handle those later so we know how much padding we need. 1852 nAltivecParamsAtEnd++; 1853 continue; 1854 } 1855 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. 1856 NumBytes = ((NumBytes+15)/16)*16; 1857 } 1858 NumBytes += CalculateStackSlotSize(Arg, Flags, isVarArg, PtrByteSize); 1859 } 1860 1861 // Allow for Altivec parameters at the end, if needed. 1862 if (nAltivecParamsAtEnd) { 1863 NumBytes = ((NumBytes+15)/16)*16; 1864 NumBytes += 16*nAltivecParamsAtEnd; 1865 } 1866 1867 // The prolog code of the callee may store up to 8 GPR argument registers to 1868 // the stack, allowing va_start to index over them in memory if its varargs. 1869 // Because we cannot tell if this is needed on the caller side, we have to 1870 // conservatively assume that it is needed. As such, make sure we have at 1871 // least enough stack space for the caller to store the 8 GPRs. 1872 NumBytes = std::max(NumBytes, 1873 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI)); 1874 1875 // Tail call needs the stack to be aligned. 1876 if (CC==CallingConv::Fast && PerformTailCallOpt) { 1877 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 1878 getStackAlignment(); 1879 unsigned AlignMask = TargetAlign-1; 1880 NumBytes = (NumBytes + AlignMask) & ~AlignMask; 1881 } 1882 1883 return NumBytes; 1884} 1885 1886/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be 1887/// adjusted to accomodate the arguments for the tailcall. 1888static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall, 1889 unsigned ParamSize) { 1890 1891 if (!IsTailCall) return 0; 1892 1893 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>(); 1894 unsigned CallerMinReservedArea = FI->getMinReservedArea(); 1895 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize; 1896 // Remember only if the new adjustement is bigger. 1897 if (SPDiff < FI->getTailCallSPDelta()) 1898 FI->setTailCallSPDelta(SPDiff); 1899 1900 return SPDiff; 1901} 1902 1903/// IsEligibleForTailCallElimination - Check to see whether the next instruction 1904/// following the call is a return. A function is eligible if caller/callee 1905/// calling conventions match, currently only fastcc supports tail calls, and 1906/// the function CALL is immediatly followed by a RET. 1907bool 1908PPCTargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall, 1909 SDValue Ret, 1910 SelectionDAG& DAG) const { 1911 // Variable argument functions are not supported. 1912 if (!PerformTailCallOpt || TheCall->isVarArg()) 1913 return false; 1914 1915 if (CheckTailCallReturnConstraints(TheCall, Ret)) { 1916 MachineFunction &MF = DAG.getMachineFunction(); 1917 unsigned CallerCC = MF.getFunction()->getCallingConv(); 1918 unsigned CalleeCC = TheCall->getCallingConv(); 1919 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 1920 // Functions containing by val parameters are not supported. 1921 for (unsigned i = 0; i != TheCall->getNumArgs(); i++) { 1922 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i); 1923 if (Flags.isByVal()) return false; 1924 } 1925 1926 SDValue Callee = TheCall->getCallee(); 1927 // Non PIC/GOT tail calls are supported. 1928 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 1929 return true; 1930 1931 // At the moment we can only do local tail calls (in same module, hidden 1932 // or protected) if we are generating PIC. 1933 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1934 return G->getGlobal()->hasHiddenVisibility() 1935 || G->getGlobal()->hasProtectedVisibility(); 1936 } 1937 } 1938 1939 return false; 1940} 1941 1942/// isCallCompatibleAddress - Return the immediate to use if the specified 1943/// 32-bit value is representable in the immediate field of a BxA instruction. 1944static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { 1945 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1946 if (!C) return 0; 1947 1948 int Addr = C->getZExtValue(); 1949 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 1950 (Addr << 6 >> 6) != Addr) 1951 return 0; // Top 6 bits have to be sext of immediate. 1952 1953 return DAG.getConstant((int)C->getZExtValue() >> 2, 1954 DAG.getTargetLoweringInfo().getPointerTy()).getNode(); 1955} 1956 1957namespace { 1958 1959struct TailCallArgumentInfo { 1960 SDValue Arg; 1961 SDValue FrameIdxOp; 1962 int FrameIdx; 1963 1964 TailCallArgumentInfo() : FrameIdx(0) {} 1965}; 1966 1967} 1968 1969/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. 1970static void 1971StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, 1972 SDValue Chain, 1973 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, 1974 SmallVector<SDValue, 8> &MemOpChains) { 1975 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { 1976 SDValue Arg = TailCallArgs[i].Arg; 1977 SDValue FIN = TailCallArgs[i].FrameIdxOp; 1978 int FI = TailCallArgs[i].FrameIdx; 1979 // Store relative to framepointer. 1980 MemOpChains.push_back(DAG.getStore(Chain, Arg, FIN, 1981 PseudoSourceValue::getFixedStack(FI), 1982 0)); 1983 } 1984} 1985 1986/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to 1987/// the appropriate stack slot for the tail call optimized function call. 1988static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, 1989 MachineFunction &MF, 1990 SDValue Chain, 1991 SDValue OldRetAddr, 1992 SDValue OldFP, 1993 int SPDiff, 1994 bool isPPC64, 1995 bool isMachoABI) { 1996 if (SPDiff) { 1997 // Calculate the new stack slot for the return address. 1998 int SlotSize = isPPC64 ? 8 : 4; 1999 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64, 2000 isMachoABI); 2001 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, 2002 NewRetAddrLoc); 2003 int NewFPLoc = SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, 2004 isMachoABI); 2005 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc); 2006 2007 MVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2008 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); 2009 Chain = DAG.getStore(Chain, OldRetAddr, NewRetAddrFrIdx, 2010 PseudoSourceValue::getFixedStack(NewRetAddr), 0); 2011 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); 2012 Chain = DAG.getStore(Chain, OldFP, NewFramePtrIdx, 2013 PseudoSourceValue::getFixedStack(NewFPIdx), 0); 2014 } 2015 return Chain; 2016} 2017 2018/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate 2019/// the position of the argument. 2020static void 2021CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, 2022 SDValue Arg, int SPDiff, unsigned ArgOffset, 2023 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 2024 int Offset = ArgOffset + SPDiff; 2025 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; 2026 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset); 2027 MVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2028 SDValue FIN = DAG.getFrameIndex(FI, VT); 2029 TailCallArgumentInfo Info; 2030 Info.Arg = Arg; 2031 Info.FrameIdxOp = FIN; 2032 Info.FrameIdx = FI; 2033 TailCallArguments.push_back(Info); 2034} 2035 2036/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address 2037/// stack slot. Returns the chain as result and the loaded frame pointers in 2038/// LROpOut/FPOpout. Used when tail calling. 2039SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 2040 int SPDiff, 2041 SDValue Chain, 2042 SDValue &LROpOut, 2043 SDValue &FPOpOut) { 2044 if (SPDiff) { 2045 // Load the LR and FP stack slot for later adjusting. 2046 MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; 2047 LROpOut = getReturnAddrFrameIndex(DAG); 2048 LROpOut = DAG.getLoad(VT, Chain, LROpOut, NULL, 0); 2049 Chain = SDValue(LROpOut.getNode(), 1); 2050 FPOpOut = getFramePointerFrameIndex(DAG); 2051 FPOpOut = DAG.getLoad(VT, Chain, FPOpOut, NULL, 0); 2052 Chain = SDValue(FPOpOut.getNode(), 1); 2053 } 2054 return Chain; 2055} 2056 2057/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 2058/// by "Src" to address "Dst" of size "Size". Alignment information is 2059/// specified by the specific parameter attribute. The copy will be passed as 2060/// a byval function parameter. 2061/// Sometimes what we are copying is the end of a larger object, the part that 2062/// does not fit in registers. 2063static SDValue 2064CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 2065 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 2066 unsigned Size) { 2067 SDValue SizeNode = DAG.getConstant(Size, MVT::i32); 2068 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), false, 2069 NULL, 0, NULL, 0); 2070} 2071 2072/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of 2073/// tail calls. 2074static void 2075LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, 2076 SDValue Arg, SDValue PtrOff, int SPDiff, 2077 unsigned ArgOffset, bool isPPC64, bool isTailCall, 2078 bool isVector, SmallVector<SDValue, 8> &MemOpChains, 2079 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 2080 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2081 if (!isTailCall) { 2082 if (isVector) { 2083 SDValue StackPtr; 2084 if (isPPC64) 2085 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2086 else 2087 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2088 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, 2089 DAG.getConstant(ArgOffset, PtrVT)); 2090 } 2091 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 2092 // Calculate and remember argument location. 2093 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, 2094 TailCallArguments); 2095} 2096 2097SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG, 2098 const PPCSubtarget &Subtarget, 2099 TargetMachine &TM) { 2100 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode()); 2101 SDValue Chain = TheCall->getChain(); 2102 bool isVarArg = TheCall->isVarArg(); 2103 unsigned CC = TheCall->getCallingConv(); 2104 bool isTailCall = TheCall->isTailCall() 2105 && CC == CallingConv::Fast && PerformTailCallOpt; 2106 SDValue Callee = TheCall->getCallee(); 2107 unsigned NumOps = TheCall->getNumArgs(); 2108 2109 bool isMachoABI = Subtarget.isMachoABI(); 2110 bool isELF32_ABI = Subtarget.isELF32_ABI(); 2111 2112 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2113 bool isPPC64 = PtrVT == MVT::i64; 2114 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2115 2116 MachineFunction &MF = DAG.getMachineFunction(); 2117 2118 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in 2119 // SelectExpr to use to put the arguments in the appropriate registers. 2120 std::vector<SDValue> args_to_use; 2121 2122 // Mark this function as potentially containing a function that contains a 2123 // tail call. As a consequence the frame pointer will be used for dynamicalloc 2124 // and restoring the callers stack pointer in this functions epilog. This is 2125 // done because by tail calling the called function might overwrite the value 2126 // in this function's (MF) stack pointer stack slot 0(SP). 2127 if (PerformTailCallOpt && CC==CallingConv::Fast) 2128 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 2129 2130 unsigned nAltivecParamsAtEnd = 0; 2131 2132 // Count how many bytes are to be pushed on the stack, including the linkage 2133 // area, and parameter passing area. We start with 24/48 bytes, which is 2134 // prereserved space for [SP][CR][LR][3 x unused]. 2135 unsigned NumBytes = 2136 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isMachoABI, isVarArg, CC, 2137 TheCall, nAltivecParamsAtEnd); 2138 2139 // Calculate by how many bytes the stack has to be adjusted in case of tail 2140 // call optimization. 2141 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 2142 2143 // Adjust the stack pointer for the new arguments... 2144 // These operations are automatically eliminated by the prolog/epilog pass 2145 Chain = DAG.getCALLSEQ_START(Chain, 2146 DAG.getConstant(NumBytes, PtrVT)); 2147 SDValue CallSeqStart = Chain; 2148 2149 // Load the return address and frame pointer so it can be move somewhere else 2150 // later. 2151 SDValue LROp, FPOp; 2152 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp); 2153 2154 // Set up a copy of the stack pointer for use loading and storing any 2155 // arguments that may not fit in the registers available for argument 2156 // passing. 2157 SDValue StackPtr; 2158 if (isPPC64) 2159 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2160 else 2161 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2162 2163 // Figure out which arguments are going to go in registers, and which in 2164 // memory. Also, if this is a vararg function, floating point operations 2165 // must be stored to our stack, and loaded into integer regs as well, if 2166 // any integer regs are available for argument passing. 2167 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 2168 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 2169 2170 static const unsigned GPR_32[] = { // 32-bit registers. 2171 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 2172 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 2173 }; 2174 static const unsigned GPR_64[] = { // 64-bit registers. 2175 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 2176 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 2177 }; 2178 static const unsigned *FPR = GetFPR(Subtarget); 2179 2180 static const unsigned VR[] = { 2181 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 2182 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 2183 }; 2184 const unsigned NumGPRs = array_lengthof(GPR_32); 2185 const unsigned NumFPRs = isMachoABI ? 13 : 8; 2186 const unsigned NumVRs = array_lengthof( VR); 2187 2188 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 2189 2190 std::vector<std::pair<unsigned, SDValue> > RegsToPass; 2191 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 2192 2193 SmallVector<SDValue, 8> MemOpChains; 2194 for (unsigned i = 0; i != NumOps; ++i) { 2195 bool inMem = false; 2196 SDValue Arg = TheCall->getArg(i); 2197 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i); 2198 // See if next argument requires stack alignment in ELF 2199 bool Align = Flags.isSplit(); 2200 2201 // PtrOff will be used to store the current argument to the stack if a 2202 // register cannot be found for it. 2203 SDValue PtrOff; 2204 2205 // Stack align in ELF 32 2206 if (isELF32_ABI && Align) 2207 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize, 2208 StackPtr.getValueType()); 2209 else 2210 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 2211 2212 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); 2213 2214 // On PPC64, promote integers to 64-bit values. 2215 if (isPPC64 && Arg.getValueType() == MVT::i32) { 2216 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 2217 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 2218 Arg = DAG.getNode(ExtOp, MVT::i64, Arg); 2219 } 2220 2221 // FIXME Elf untested, what are alignment rules? 2222 // FIXME memcpy is used way more than necessary. Correctness first. 2223 if (Flags.isByVal()) { 2224 unsigned Size = Flags.getByValSize(); 2225 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2); 2226 if (Size==1 || Size==2) { 2227 // Very small objects are passed right-justified. 2228 // Everything else is passed left-justified. 2229 MVT VT = (Size==1) ? MVT::i8 : MVT::i16; 2230 if (GPR_idx != NumGPRs) { 2231 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg, 2232 NULL, 0, VT); 2233 MemOpChains.push_back(Load.getValue(1)); 2234 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 2235 if (isMachoABI) 2236 ArgOffset += PtrByteSize; 2237 } else { 2238 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType()); 2239 SDValue AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const); 2240 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, 2241 CallSeqStart.getNode()->getOperand(0), 2242 Flags, DAG, Size); 2243 // This must go outside the CALLSEQ_START..END. 2244 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 2245 CallSeqStart.getNode()->getOperand(1)); 2246 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 2247 NewCallSeqStart.getNode()); 2248 Chain = CallSeqStart = NewCallSeqStart; 2249 ArgOffset += PtrByteSize; 2250 } 2251 continue; 2252 } 2253 // Copy entire object into memory. There are cases where gcc-generated 2254 // code assumes it is there, even if it could be put entirely into 2255 // registers. (This is not what the doc says.) 2256 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, 2257 CallSeqStart.getNode()->getOperand(0), 2258 Flags, DAG, Size); 2259 // This must go outside the CALLSEQ_START..END. 2260 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 2261 CallSeqStart.getNode()->getOperand(1)); 2262 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode()); 2263 Chain = CallSeqStart = NewCallSeqStart; 2264 // And copy the pieces of it that fit into registers. 2265 for (unsigned j=0; j<Size; j+=PtrByteSize) { 2266 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 2267 SDValue AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const); 2268 if (GPR_idx != NumGPRs) { 2269 SDValue Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0); 2270 MemOpChains.push_back(Load.getValue(1)); 2271 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 2272 if (isMachoABI) 2273 ArgOffset += PtrByteSize; 2274 } else { 2275 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 2276 break; 2277 } 2278 } 2279 continue; 2280 } 2281 2282 switch (Arg.getValueType().getSimpleVT()) { 2283 default: assert(0 && "Unexpected ValueType for argument!"); 2284 case MVT::i32: 2285 case MVT::i64: 2286 // Double word align in ELF 2287 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2); 2288 if (GPR_idx != NumGPRs) { 2289 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 2290 } else { 2291 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 2292 isPPC64, isTailCall, false, MemOpChains, 2293 TailCallArguments); 2294 inMem = true; 2295 } 2296 if (inMem || isMachoABI) { 2297 // Stack align in ELF 2298 if (isELF32_ABI && Align) 2299 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 2300 2301 ArgOffset += PtrByteSize; 2302 } 2303 break; 2304 case MVT::f32: 2305 case MVT::f64: 2306 if (FPR_idx != NumFPRs) { 2307 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 2308 2309 if (isVarArg) { 2310 SDValue Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); 2311 MemOpChains.push_back(Store); 2312 2313 // Float varargs are always shadowed in available integer registers 2314 if (GPR_idx != NumGPRs) { 2315 SDValue Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 2316 MemOpChains.push_back(Load.getValue(1)); 2317 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 2318 Load)); 2319 } 2320 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 2321 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 2322 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); 2323 SDValue Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 2324 MemOpChains.push_back(Load.getValue(1)); 2325 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 2326 Load)); 2327 } 2328 } else { 2329 // If we have any FPRs remaining, we may also have GPRs remaining. 2330 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 2331 // GPRs. 2332 if (isMachoABI) { 2333 if (GPR_idx != NumGPRs) 2334 ++GPR_idx; 2335 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 2336 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 2337 ++GPR_idx; 2338 } 2339 } 2340 } else { 2341 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 2342 isPPC64, isTailCall, false, MemOpChains, 2343 TailCallArguments); 2344 inMem = true; 2345 } 2346 if (inMem || isMachoABI) { 2347 // Stack align in ELF 2348 if (isELF32_ABI && Align) 2349 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 2350 if (isPPC64) 2351 ArgOffset += 8; 2352 else 2353 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 2354 } 2355 break; 2356 case MVT::v4f32: 2357 case MVT::v4i32: 2358 case MVT::v8i16: 2359 case MVT::v16i8: 2360 if (isVarArg) { 2361 // These go aligned on the stack, or in the corresponding R registers 2362 // when within range. The Darwin PPC ABI doc claims they also go in 2363 // V registers; in fact gcc does this only for arguments that are 2364 // prototyped, not for those that match the ... We do it for all 2365 // arguments, seems to work. 2366 while (ArgOffset % 16 !=0) { 2367 ArgOffset += PtrByteSize; 2368 if (GPR_idx != NumGPRs) 2369 GPR_idx++; 2370 } 2371 // We could elide this store in the case where the object fits 2372 // entirely in R registers. Maybe later. 2373 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, 2374 DAG.getConstant(ArgOffset, PtrVT)); 2375 SDValue Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); 2376 MemOpChains.push_back(Store); 2377 if (VR_idx != NumVRs) { 2378 SDValue Load = DAG.getLoad(MVT::v4f32, Store, PtrOff, NULL, 0); 2379 MemOpChains.push_back(Load.getValue(1)); 2380 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 2381 } 2382 ArgOffset += 16; 2383 for (unsigned i=0; i<16; i+=PtrByteSize) { 2384 if (GPR_idx == NumGPRs) 2385 break; 2386 SDValue Ix = DAG.getNode(ISD::ADD, PtrVT, PtrOff, 2387 DAG.getConstant(i, PtrVT)); 2388 SDValue Load = DAG.getLoad(PtrVT, Store, Ix, NULL, 0); 2389 MemOpChains.push_back(Load.getValue(1)); 2390 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 2391 } 2392 break; 2393 } 2394 2395 // Non-varargs Altivec params generally go in registers, but have 2396 // stack space allocated at the end. 2397 if (VR_idx != NumVRs) { 2398 // Doesn't have GPR space allocated. 2399 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 2400 } else if (nAltivecParamsAtEnd==0) { 2401 // We are emitting Altivec params in order. 2402 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 2403 isPPC64, isTailCall, true, MemOpChains, 2404 TailCallArguments); 2405 ArgOffset += 16; 2406 } 2407 break; 2408 } 2409 } 2410 // If all Altivec parameters fit in registers, as they usually do, 2411 // they get stack space following the non-Altivec parameters. We 2412 // don't track this here because nobody below needs it. 2413 // If there are more Altivec parameters than fit in registers emit 2414 // the stores here. 2415 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) { 2416 unsigned j = 0; 2417 // Offset is aligned; skip 1st 12 params which go in V registers. 2418 ArgOffset = ((ArgOffset+15)/16)*16; 2419 ArgOffset += 12*16; 2420 for (unsigned i = 0; i != NumOps; ++i) { 2421 SDValue Arg = TheCall->getArg(i); 2422 MVT ArgType = Arg.getValueType(); 2423 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || 2424 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { 2425 if (++j > NumVRs) { 2426 SDValue PtrOff; 2427 // We are emitting Altivec params in order. 2428 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 2429 isPPC64, isTailCall, true, MemOpChains, 2430 TailCallArguments); 2431 ArgOffset += 16; 2432 } 2433 } 2434 } 2435 } 2436 2437 if (!MemOpChains.empty()) 2438 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 2439 &MemOpChains[0], MemOpChains.size()); 2440 2441 // Build a sequence of copy-to-reg nodes chained together with token chain 2442 // and flag operands which copy the outgoing args into the appropriate regs. 2443 SDValue InFlag; 2444 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2445 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 2446 InFlag); 2447 InFlag = Chain.getValue(1); 2448 } 2449 2450 // With the ELF 32 ABI, set CR6 to true if this is a vararg call. 2451 if (isVarArg && isELF32_ABI) { 2452 SDValue SetCR(DAG.getTargetNode(PPC::CRSET, MVT::i32), 0); 2453 Chain = DAG.getCopyToReg(Chain, PPC::CR1EQ, SetCR, InFlag); 2454 InFlag = Chain.getValue(1); 2455 } 2456 2457 // Emit a sequence of copyto/copyfrom virtual registers for arguments that 2458 // might overwrite each other in case of tail call optimization. 2459 if (isTailCall) { 2460 SmallVector<SDValue, 8> MemOpChains2; 2461 // Do not flag preceeding copytoreg stuff together with the following stuff. 2462 InFlag = SDValue(); 2463 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, 2464 MemOpChains2); 2465 if (!MemOpChains2.empty()) 2466 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 2467 &MemOpChains2[0], MemOpChains2.size()); 2468 2469 // Store the return address to the appropriate stack slot. 2470 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, 2471 isPPC64, isMachoABI); 2472 } 2473 2474 // Emit callseq_end just before tailcall node. 2475 if (isTailCall) { 2476 SmallVector<SDValue, 8> CallSeqOps; 2477 SDVTList CallSeqNodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 2478 CallSeqOps.push_back(Chain); 2479 CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes)); 2480 CallSeqOps.push_back(DAG.getIntPtrConstant(0)); 2481 if (InFlag.getNode()) 2482 CallSeqOps.push_back(InFlag); 2483 Chain = DAG.getNode(ISD::CALLSEQ_END, CallSeqNodeTys, &CallSeqOps[0], 2484 CallSeqOps.size()); 2485 InFlag = Chain.getValue(1); 2486 } 2487 2488 std::vector<MVT> NodeTys; 2489 NodeTys.push_back(MVT::Other); // Returns a chain 2490 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 2491 2492 SmallVector<SDValue, 8> Ops; 2493 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF; 2494 2495 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2496 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2497 // node so that legalize doesn't hack it. 2498 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2499 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); 2500 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 2501 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); 2502 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) 2503 // If this is an absolute destination address, use the munged value. 2504 Callee = SDValue(Dest, 0); 2505 else { 2506 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 2507 // to do the call, we can't use PPCISD::CALL. 2508 SDValue MTCTROps[] = {Chain, Callee, InFlag}; 2509 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2510 2 + (InFlag.getNode() != 0)); 2511 InFlag = Chain.getValue(1); 2512 2513 // Copy the callee address into R12/X12 on darwin. 2514 if (isMachoABI) { 2515 unsigned Reg = Callee.getValueType() == MVT::i32 ? PPC::R12 : PPC::X12; 2516 Chain = DAG.getCopyToReg(Chain, Reg, Callee, InFlag); 2517 InFlag = Chain.getValue(1); 2518 } 2519 2520 NodeTys.clear(); 2521 NodeTys.push_back(MVT::Other); 2522 NodeTys.push_back(MVT::Flag); 2523 Ops.push_back(Chain); 2524 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF; 2525 Callee.setNode(0); 2526 // Add CTR register as callee so a bctr can be emitted later. 2527 if (isTailCall) 2528 Ops.push_back(DAG.getRegister(PPC::CTR, getPointerTy())); 2529 } 2530 2531 // If this is a direct call, pass the chain and the callee. 2532 if (Callee.getNode()) { 2533 Ops.push_back(Chain); 2534 Ops.push_back(Callee); 2535 } 2536 // If this is a tail call add stack pointer delta. 2537 if (isTailCall) 2538 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); 2539 2540 // Add argument registers to the end of the list so that they are known live 2541 // into the call. 2542 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2543 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2544 RegsToPass[i].second.getValueType())); 2545 2546 // When performing tail call optimization the callee pops its arguments off 2547 // the stack. Account for this here so these bytes can be pushed back on in 2548 // PPCRegisterInfo::eliminateCallFramePseudoInstr. 2549 int BytesCalleePops = 2550 (CC==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0; 2551 2552 if (InFlag.getNode()) 2553 Ops.push_back(InFlag); 2554 2555 // Emit tail call. 2556 if (isTailCall) { 2557 assert(InFlag.getNode() && 2558 "Flag must be set. Depend on flag being set in LowerRET"); 2559 Chain = DAG.getNode(PPCISD::TAILCALL, 2560 TheCall->getVTList(), &Ops[0], Ops.size()); 2561 return SDValue(Chain.getNode(), Op.getResNo()); 2562 } 2563 2564 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 2565 InFlag = Chain.getValue(1); 2566 2567 Chain = DAG.getCALLSEQ_END(Chain, 2568 DAG.getConstant(NumBytes, PtrVT), 2569 DAG.getConstant(BytesCalleePops, PtrVT), 2570 InFlag); 2571 if (TheCall->getValueType(0) != MVT::Other) 2572 InFlag = Chain.getValue(1); 2573 2574 SmallVector<SDValue, 16> ResultVals; 2575 SmallVector<CCValAssign, 16> RVLocs; 2576 unsigned CallerCC = DAG.getMachineFunction().getFunction()->getCallingConv(); 2577 CCState CCInfo(CallerCC, isVarArg, TM, RVLocs); 2578 CCInfo.AnalyzeCallResult(TheCall, RetCC_PPC); 2579 2580 // Copy all of the result registers out of their specified physreg. 2581 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2582 CCValAssign &VA = RVLocs[i]; 2583 MVT VT = VA.getValVT(); 2584 assert(VA.isRegLoc() && "Can only return in registers!"); 2585 Chain = DAG.getCopyFromReg(Chain, VA.getLocReg(), VT, InFlag).getValue(1); 2586 ResultVals.push_back(Chain.getValue(0)); 2587 InFlag = Chain.getValue(2); 2588 } 2589 2590 // If the function returns void, just return the chain. 2591 if (RVLocs.empty()) 2592 return Chain; 2593 2594 // Otherwise, merge everything together with a MERGE_VALUES node. 2595 ResultVals.push_back(Chain); 2596 SDValue Res = DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0], 2597 ResultVals.size()); 2598 return Res.getValue(Op.getResNo()); 2599} 2600 2601SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG, 2602 TargetMachine &TM) { 2603 SmallVector<CCValAssign, 16> RVLocs; 2604 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 2605 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 2606 CCState CCInfo(CC, isVarArg, TM, RVLocs); 2607 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_PPC); 2608 2609 // If this is the first return lowered for this function, add the regs to the 2610 // liveout set for the function. 2611 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2612 for (unsigned i = 0; i != RVLocs.size(); ++i) 2613 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2614 } 2615 2616 SDValue Chain = Op.getOperand(0); 2617 2618 Chain = GetPossiblePreceedingTailCall(Chain, PPCISD::TAILCALL); 2619 if (Chain.getOpcode() == PPCISD::TAILCALL) { 2620 SDValue TailCall = Chain; 2621 SDValue TargetAddress = TailCall.getOperand(1); 2622 SDValue StackAdjustment = TailCall.getOperand(2); 2623 2624 assert(((TargetAddress.getOpcode() == ISD::Register && 2625 cast<RegisterSDNode>(TargetAddress)->getReg() == PPC::CTR) || 2626 TargetAddress.getOpcode() == ISD::TargetExternalSymbol || 2627 TargetAddress.getOpcode() == ISD::TargetGlobalAddress || 2628 isa<ConstantSDNode>(TargetAddress)) && 2629 "Expecting an global address, external symbol, absolute value or register"); 2630 2631 assert(StackAdjustment.getOpcode() == ISD::Constant && 2632 "Expecting a const value"); 2633 2634 SmallVector<SDValue,8> Operands; 2635 Operands.push_back(Chain.getOperand(0)); 2636 Operands.push_back(TargetAddress); 2637 Operands.push_back(StackAdjustment); 2638 // Copy registers used by the call. Last operand is a flag so it is not 2639 // copied. 2640 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) { 2641 Operands.push_back(Chain.getOperand(i)); 2642 } 2643 return DAG.getNode(PPCISD::TC_RETURN, MVT::Other, &Operands[0], 2644 Operands.size()); 2645 } 2646 2647 SDValue Flag; 2648 2649 // Copy the result values into the output registers. 2650 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2651 CCValAssign &VA = RVLocs[i]; 2652 assert(VA.isRegLoc() && "Can only return in registers!"); 2653 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); 2654 Flag = Chain.getValue(1); 2655 } 2656 2657 if (Flag.getNode()) 2658 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag); 2659 else 2660 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain); 2661} 2662 2663SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 2664 const PPCSubtarget &Subtarget) { 2665 // When we pop the dynamic allocation we need to restore the SP link. 2666 2667 // Get the corect type for pointers. 2668 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2669 2670 // Construct the stack pointer operand. 2671 bool IsPPC64 = Subtarget.isPPC64(); 2672 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1; 2673 SDValue StackPtr = DAG.getRegister(SP, PtrVT); 2674 2675 // Get the operands for the STACKRESTORE. 2676 SDValue Chain = Op.getOperand(0); 2677 SDValue SaveSP = Op.getOperand(1); 2678 2679 // Load the old link SP. 2680 SDValue LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0); 2681 2682 // Restore the stack pointer. 2683 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP); 2684 2685 // Store the old link SP. 2686 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0); 2687} 2688 2689 2690 2691SDValue 2692PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { 2693 MachineFunction &MF = DAG.getMachineFunction(); 2694 bool IsPPC64 = PPCSubTarget.isPPC64(); 2695 bool isMachoABI = PPCSubTarget.isMachoABI(); 2696 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2697 2698 // Get current frame pointer save index. The users of this index will be 2699 // primarily DYNALLOC instructions. 2700 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2701 int RASI = FI->getReturnAddrSaveIndex(); 2702 2703 // If the frame pointer save index hasn't been defined yet. 2704 if (!RASI) { 2705 // Find out what the fix offset of the frame pointer save area. 2706 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isMachoABI); 2707 // Allocate the frame index for frame pointer save area. 2708 RASI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, LROffset); 2709 // Save the result. 2710 FI->setReturnAddrSaveIndex(RASI); 2711 } 2712 return DAG.getFrameIndex(RASI, PtrVT); 2713} 2714 2715SDValue 2716PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { 2717 MachineFunction &MF = DAG.getMachineFunction(); 2718 bool IsPPC64 = PPCSubTarget.isPPC64(); 2719 bool isMachoABI = PPCSubTarget.isMachoABI(); 2720 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2721 2722 // Get current frame pointer save index. The users of this index will be 2723 // primarily DYNALLOC instructions. 2724 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2725 int FPSI = FI->getFramePointerSaveIndex(); 2726 2727 // If the frame pointer save index hasn't been defined yet. 2728 if (!FPSI) { 2729 // Find out what the fix offset of the frame pointer save area. 2730 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI); 2731 2732 // Allocate the frame index for frame pointer save area. 2733 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 2734 // Save the result. 2735 FI->setFramePointerSaveIndex(FPSI); 2736 } 2737 return DAG.getFrameIndex(FPSI, PtrVT); 2738} 2739 2740SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 2741 SelectionDAG &DAG, 2742 const PPCSubtarget &Subtarget) { 2743 // Get the inputs. 2744 SDValue Chain = Op.getOperand(0); 2745 SDValue Size = Op.getOperand(1); 2746 2747 // Get the corect type for pointers. 2748 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2749 // Negate the size. 2750 SDValue NegSize = DAG.getNode(ISD::SUB, PtrVT, 2751 DAG.getConstant(0, PtrVT), Size); 2752 // Construct a node for the frame pointer save index. 2753 SDValue FPSIdx = getFramePointerFrameIndex(DAG); 2754 // Build a DYNALLOC node. 2755 SDValue Ops[3] = { Chain, NegSize, FPSIdx }; 2756 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 2757 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3); 2758} 2759 2760/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 2761/// possible. 2762SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 2763 // Not FP? Not a fsel. 2764 if (!Op.getOperand(0).getValueType().isFloatingPoint() || 2765 !Op.getOperand(2).getValueType().isFloatingPoint()) 2766 return SDValue(); 2767 2768 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2769 2770 // Cannot handle SETEQ/SETNE. 2771 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDValue(); 2772 2773 MVT ResVT = Op.getValueType(); 2774 MVT CmpVT = Op.getOperand(0).getValueType(); 2775 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2776 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); 2777 2778 // If the RHS of the comparison is a 0.0, we don't need to do the 2779 // subtraction at all. 2780 if (isFloatingPointZero(RHS)) 2781 switch (CC) { 2782 default: break; // SETUO etc aren't handled by fsel. 2783 case ISD::SETULT: 2784 case ISD::SETLT: 2785 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 2786 case ISD::SETOGE: 2787 case ISD::SETGE: 2788 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 2789 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 2790 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 2791 case ISD::SETUGT: 2792 case ISD::SETGT: 2793 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 2794 case ISD::SETOLE: 2795 case ISD::SETLE: 2796 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 2797 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 2798 return DAG.getNode(PPCISD::FSEL, ResVT, 2799 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 2800 } 2801 2802 SDValue Cmp; 2803 switch (CC) { 2804 default: break; // SETUO etc aren't handled by fsel. 2805 case ISD::SETULT: 2806 case ISD::SETLT: 2807 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2808 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2809 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2810 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2811 case ISD::SETOGE: 2812 case ISD::SETGE: 2813 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2814 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2815 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2816 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2817 case ISD::SETUGT: 2818 case ISD::SETGT: 2819 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2820 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2821 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2822 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2823 case ISD::SETOLE: 2824 case ISD::SETLE: 2825 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2826 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2827 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2828 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2829 } 2830 return SDValue(); 2831} 2832 2833// FIXME: Split this code up when LegalizeDAGTypes lands. 2834SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 2835 assert(Op.getOperand(0).getValueType().isFloatingPoint()); 2836 SDValue Src = Op.getOperand(0); 2837 if (Src.getValueType() == MVT::f32) 2838 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 2839 2840 SDValue Tmp; 2841 switch (Op.getValueType().getSimpleVT()) { 2842 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 2843 case MVT::i32: 2844 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 2845 break; 2846 case MVT::i64: 2847 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 2848 break; 2849 } 2850 2851 // Convert the FP value to an int value through memory. 2852 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); 2853 2854 // Emit a store to the stack slot. 2855 SDValue Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0); 2856 2857 // Result is a load from the stack slot. If loading 4 bytes, make sure to 2858 // add in a bias. 2859 if (Op.getValueType() == MVT::i32) 2860 FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, 2861 DAG.getConstant(4, FIPtr.getValueType())); 2862 return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0); 2863} 2864 2865SDValue PPCTargetLowering::LowerFP_ROUND_INREG(SDValue Op, 2866 SelectionDAG &DAG) { 2867 assert(Op.getValueType() == MVT::ppcf128); 2868 SDNode *Node = Op.getNode(); 2869 assert(Node->getOperand(0).getValueType() == MVT::ppcf128); 2870 assert(Node->getOperand(0).getNode()->getOpcode() == ISD::BUILD_PAIR); 2871 SDValue Lo = Node->getOperand(0).getNode()->getOperand(0); 2872 SDValue Hi = Node->getOperand(0).getNode()->getOperand(1); 2873 2874 // This sequence changes FPSCR to do round-to-zero, adds the two halves 2875 // of the long double, and puts FPSCR back the way it was. We do not 2876 // actually model FPSCR. 2877 std::vector<MVT> NodeTys; 2878 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg; 2879 2880 NodeTys.push_back(MVT::f64); // Return register 2881 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns 2882 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); 2883 MFFSreg = Result.getValue(0); 2884 InFlag = Result.getValue(1); 2885 2886 NodeTys.clear(); 2887 NodeTys.push_back(MVT::Flag); // Returns a flag 2888 Ops[0] = DAG.getConstant(31, MVT::i32); 2889 Ops[1] = InFlag; 2890 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2); 2891 InFlag = Result.getValue(0); 2892 2893 NodeTys.clear(); 2894 NodeTys.push_back(MVT::Flag); // Returns a flag 2895 Ops[0] = DAG.getConstant(30, MVT::i32); 2896 Ops[1] = InFlag; 2897 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2); 2898 InFlag = Result.getValue(0); 2899 2900 NodeTys.clear(); 2901 NodeTys.push_back(MVT::f64); // result of add 2902 NodeTys.push_back(MVT::Flag); // Returns a flag 2903 Ops[0] = Lo; 2904 Ops[1] = Hi; 2905 Ops[2] = InFlag; 2906 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3); 2907 FPreg = Result.getValue(0); 2908 InFlag = Result.getValue(1); 2909 2910 NodeTys.clear(); 2911 NodeTys.push_back(MVT::f64); 2912 Ops[0] = DAG.getConstant(1, MVT::i32); 2913 Ops[1] = MFFSreg; 2914 Ops[2] = FPreg; 2915 Ops[3] = InFlag; 2916 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4); 2917 FPreg = Result.getValue(0); 2918 2919 // We know the low half is about to be thrown away, so just use something 2920 // convenient. 2921 return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg); 2922} 2923 2924SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 2925 // Don't handle ppc_fp128 here; let it be lowered to a libcall. 2926 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) 2927 return SDValue(); 2928 2929 if (Op.getOperand(0).getValueType() == MVT::i64) { 2930 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 2931 SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 2932 if (Op.getValueType() == MVT::f32) 2933 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); 2934 return FP; 2935 } 2936 2937 assert(Op.getOperand(0).getValueType() == MVT::i32 && 2938 "Unhandled SINT_TO_FP type in custom expander!"); 2939 // Since we only generate this in 64-bit mode, we can take advantage of 2940 // 64-bit registers. In particular, sign extend the input value into the 2941 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 2942 // then lfd it and fcfid it. 2943 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2944 int FrameIdx = FrameInfo->CreateStackObject(8, 8); 2945 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2946 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2947 2948 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, 2949 Op.getOperand(0)); 2950 2951 // STD the extended value into the stack slot. 2952 MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx), 2953 MachineMemOperand::MOStore, 0, 8, 8); 2954 SDValue Store = DAG.getNode(PPCISD::STD_32, MVT::Other, 2955 DAG.getEntryNode(), Ext64, FIdx, 2956 DAG.getMemOperand(MO)); 2957 // Load the value as a double. 2958 SDValue Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); 2959 2960 // FCFID it and return it. 2961 SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); 2962 if (Op.getValueType() == MVT::f32) 2963 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); 2964 return FP; 2965} 2966 2967SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { 2968 /* 2969 The rounding mode is in bits 30:31 of FPSR, and has the following 2970 settings: 2971 00 Round to nearest 2972 01 Round to 0 2973 10 Round to +inf 2974 11 Round to -inf 2975 2976 FLT_ROUNDS, on the other hand, expects the following: 2977 -1 Undefined 2978 0 Round to 0 2979 1 Round to nearest 2980 2 Round to +inf 2981 3 Round to -inf 2982 2983 To perform the conversion, we do: 2984 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 2985 */ 2986 2987 MachineFunction &MF = DAG.getMachineFunction(); 2988 MVT VT = Op.getValueType(); 2989 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2990 std::vector<MVT> NodeTys; 2991 SDValue MFFSreg, InFlag; 2992 2993 // Save FP Control Word to register 2994 NodeTys.push_back(MVT::f64); // return register 2995 NodeTys.push_back(MVT::Flag); // unused in this context 2996 SDValue Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); 2997 2998 // Save FP register to stack slot 2999 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 3000 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 3001 SDValue Store = DAG.getStore(DAG.getEntryNode(), Chain, 3002 StackSlot, NULL, 0); 3003 3004 // Load FP Control Word from low 32 bits of stack slot. 3005 SDValue Four = DAG.getConstant(4, PtrVT); 3006 SDValue Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four); 3007 SDValue CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0); 3008 3009 // Transform as necessary 3010 SDValue CWD1 = 3011 DAG.getNode(ISD::AND, MVT::i32, 3012 CWD, DAG.getConstant(3, MVT::i32)); 3013 SDValue CWD2 = 3014 DAG.getNode(ISD::SRL, MVT::i32, 3015 DAG.getNode(ISD::AND, MVT::i32, 3016 DAG.getNode(ISD::XOR, MVT::i32, 3017 CWD, DAG.getConstant(3, MVT::i32)), 3018 DAG.getConstant(3, MVT::i32)), 3019 DAG.getConstant(1, MVT::i8)); 3020 3021 SDValue RetVal = 3022 DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2); 3023 3024 return DAG.getNode((VT.getSizeInBits() < 16 ? 3025 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); 3026} 3027 3028SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) { 3029 MVT VT = Op.getValueType(); 3030 unsigned BitWidth = VT.getSizeInBits(); 3031 assert(Op.getNumOperands() == 3 && 3032 VT == Op.getOperand(1).getValueType() && 3033 "Unexpected SHL!"); 3034 3035 // Expand into a bunch of logical ops. Note that these ops 3036 // depend on the PPC behavior for oversized shift amounts. 3037 SDValue Lo = Op.getOperand(0); 3038 SDValue Hi = Op.getOperand(1); 3039 SDValue Amt = Op.getOperand(2); 3040 MVT AmtVT = Amt.getValueType(); 3041 3042 SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT, 3043 DAG.getConstant(BitWidth, AmtVT), Amt); 3044 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt); 3045 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1); 3046 SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); 3047 SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, 3048 DAG.getConstant(-BitWidth, AmtVT)); 3049 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5); 3050 SDValue OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); 3051 SDValue OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt); 3052 SDValue OutOps[] = { OutLo, OutHi }; 3053 return DAG.getMergeValues(OutOps, 2); 3054} 3055 3056SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) { 3057 MVT VT = Op.getValueType(); 3058 unsigned BitWidth = VT.getSizeInBits(); 3059 assert(Op.getNumOperands() == 3 && 3060 VT == Op.getOperand(1).getValueType() && 3061 "Unexpected SRL!"); 3062 3063 // Expand into a bunch of logical ops. Note that these ops 3064 // depend on the PPC behavior for oversized shift amounts. 3065 SDValue Lo = Op.getOperand(0); 3066 SDValue Hi = Op.getOperand(1); 3067 SDValue Amt = Op.getOperand(2); 3068 MVT AmtVT = Amt.getValueType(); 3069 3070 SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT, 3071 DAG.getConstant(BitWidth, AmtVT), Amt); 3072 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt); 3073 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1); 3074 SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); 3075 SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, 3076 DAG.getConstant(-BitWidth, AmtVT)); 3077 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5); 3078 SDValue OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); 3079 SDValue OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt); 3080 SDValue OutOps[] = { OutLo, OutHi }; 3081 return DAG.getMergeValues(OutOps, 2); 3082} 3083 3084SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) { 3085 MVT VT = Op.getValueType(); 3086 unsigned BitWidth = VT.getSizeInBits(); 3087 assert(Op.getNumOperands() == 3 && 3088 VT == Op.getOperand(1).getValueType() && 3089 "Unexpected SRA!"); 3090 3091 // Expand into a bunch of logical ops, followed by a select_cc. 3092 SDValue Lo = Op.getOperand(0); 3093 SDValue Hi = Op.getOperand(1); 3094 SDValue Amt = Op.getOperand(2); 3095 MVT AmtVT = Amt.getValueType(); 3096 3097 SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT, 3098 DAG.getConstant(BitWidth, AmtVT), Amt); 3099 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt); 3100 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1); 3101 SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); 3102 SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, 3103 DAG.getConstant(-BitWidth, AmtVT)); 3104 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5); 3105 SDValue OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt); 3106 SDValue OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT), 3107 Tmp4, Tmp6, ISD::SETLE); 3108 SDValue OutOps[] = { OutLo, OutHi }; 3109 return DAG.getMergeValues(OutOps, 2); 3110} 3111 3112//===----------------------------------------------------------------------===// 3113// Vector related lowering. 3114// 3115 3116// If this is a vector of constants or undefs, get the bits. A bit in 3117// UndefBits is set if the corresponding element of the vector is an 3118// ISD::UNDEF value. For undefs, the corresponding VectorBits values are 3119// zero. Return true if this is not an array of constants, false if it is. 3120// 3121static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], 3122 uint64_t UndefBits[2]) { 3123 // Start with zero'd results. 3124 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; 3125 3126 unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits(); 3127 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3128 SDValue OpVal = BV->getOperand(i); 3129 3130 unsigned PartNo = i >= e/2; // In the upper 128 bits? 3131 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. 3132 3133 uint64_t EltBits = 0; 3134 if (OpVal.getOpcode() == ISD::UNDEF) { 3135 uint64_t EltUndefBits = ~0U >> (32-EltBitSize); 3136 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); 3137 continue; 3138 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 3139 EltBits = CN->getZExtValue() & (~0U >> (32-EltBitSize)); 3140 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 3141 assert(CN->getValueType(0) == MVT::f32 && 3142 "Only one legal FP vector type!"); 3143 EltBits = FloatToBits(CN->getValueAPF().convertToFloat()); 3144 } else { 3145 // Nonconstant element. 3146 return true; 3147 } 3148 3149 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); 3150 } 3151 3152 //printf("%llx %llx %llx %llx\n", 3153 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); 3154 return false; 3155} 3156 3157// If this is a splat (repetition) of a value across the whole vector, return 3158// the smallest size that splats it. For example, "0x01010101010101..." is a 3159// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 3160// SplatSize = 1 byte. 3161static bool isConstantSplat(const uint64_t Bits128[2], 3162 const uint64_t Undef128[2], 3163 unsigned &SplatBits, unsigned &SplatUndef, 3164 unsigned &SplatSize) { 3165 3166 // Don't let undefs prevent splats from matching. See if the top 64-bits are 3167 // the same as the lower 64-bits, ignoring undefs. 3168 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0])) 3169 return false; // Can't be a splat if two pieces don't match. 3170 3171 uint64_t Bits64 = Bits128[0] | Bits128[1]; 3172 uint64_t Undef64 = Undef128[0] & Undef128[1]; 3173 3174 // Check that the top 32-bits are the same as the lower 32-bits, ignoring 3175 // undefs. 3176 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64)) 3177 return false; // Can't be a splat if two pieces don't match. 3178 3179 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32); 3180 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32); 3181 3182 // If the top 16-bits are different than the lower 16-bits, ignoring 3183 // undefs, we have an i32 splat. 3184 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) { 3185 SplatBits = Bits32; 3186 SplatUndef = Undef32; 3187 SplatSize = 4; 3188 return true; 3189 } 3190 3191 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16); 3192 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16); 3193 3194 // If the top 8-bits are different than the lower 8-bits, ignoring 3195 // undefs, we have an i16 splat. 3196 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) { 3197 SplatBits = Bits16; 3198 SplatUndef = Undef16; 3199 SplatSize = 2; 3200 return true; 3201 } 3202 3203 // Otherwise, we have an 8-bit splat. 3204 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); 3205 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); 3206 SplatSize = 1; 3207 return true; 3208} 3209 3210/// BuildSplatI - Build a canonical splati of Val with an element size of 3211/// SplatSize. Cast the result to VT. 3212static SDValue BuildSplatI(int Val, unsigned SplatSize, MVT VT, 3213 SelectionDAG &DAG) { 3214 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 3215 3216 static const MVT VTys[] = { // canonical VT to use for each size. 3217 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 3218 }; 3219 3220 MVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 3221 3222 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 3223 if (Val == -1) 3224 SplatSize = 1; 3225 3226 MVT CanonicalVT = VTys[SplatSize-1]; 3227 3228 // Build a canonical splat for this value. 3229 SDValue Elt = DAG.getConstant(Val, CanonicalVT.getVectorElementType()); 3230 SmallVector<SDValue, 8> Ops; 3231 Ops.assign(CanonicalVT.getVectorNumElements(), Elt); 3232 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, 3233 &Ops[0], Ops.size()); 3234 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res); 3235} 3236 3237/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 3238/// specified intrinsic ID. 3239static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, 3240 SelectionDAG &DAG, 3241 MVT DestVT = MVT::Other) { 3242 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 3243 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 3244 DAG.getConstant(IID, MVT::i32), LHS, RHS); 3245} 3246 3247/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 3248/// specified intrinsic ID. 3249static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, 3250 SDValue Op2, SelectionDAG &DAG, 3251 MVT DestVT = MVT::Other) { 3252 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 3253 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 3254 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 3255} 3256 3257 3258/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 3259/// amount. The result has the specified value type. 3260static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, 3261 MVT VT, SelectionDAG &DAG) { 3262 // Force LHS/RHS to be the right type. 3263 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); 3264 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); 3265 3266 SDValue Ops[16]; 3267 for (unsigned i = 0; i != 16; ++i) 3268 Ops[i] = DAG.getConstant(i+Amt, MVT::i8); 3269 SDValue T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, 3270 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16)); 3271 return DAG.getNode(ISD::BIT_CONVERT, VT, T); 3272} 3273 3274// If this is a case we can't handle, return null and let the default 3275// expansion code take care of it. If we CAN select this case, and if it 3276// selects to a single instruction, return Op. Otherwise, if we can codegen 3277// this case more efficiently than a constant pool load, lower it to the 3278// sequence of ops that should be used. 3279SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, 3280 SelectionDAG &DAG) { 3281 // If this is a vector of constants or undefs, get the bits. A bit in 3282 // UndefBits is set if the corresponding element of the vector is an 3283 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are 3284 // zero. 3285 uint64_t VectorBits[2]; 3286 uint64_t UndefBits[2]; 3287 if (GetConstantBuildVectorBits(Op.getNode(), VectorBits, UndefBits)) 3288 return SDValue(); // Not a constant vector. 3289 3290 // If this is a splat (repetition) of a value across the whole vector, return 3291 // the smallest size that splats it. For example, "0x01010101010101..." is a 3292 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 3293 // SplatSize = 1 byte. 3294 unsigned SplatBits, SplatUndef, SplatSize; 3295 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){ 3296 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0; 3297 3298 // First, handle single instruction cases. 3299 3300 // All zeros? 3301 if (SplatBits == 0) { 3302 // Canonicalize all zero vectors to be v4i32. 3303 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 3304 SDValue Z = DAG.getConstant(0, MVT::i32); 3305 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); 3306 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); 3307 } 3308 return Op; 3309 } 3310 3311 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 3312 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); 3313 if (SextVal >= -16 && SextVal <= 15) 3314 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG); 3315 3316 3317 // Two instruction sequences. 3318 3319 // If this value is in the range [-32,30] and is even, use: 3320 // tmp = VSPLTI[bhw], result = add tmp, tmp 3321 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 3322 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG); 3323 Res = DAG.getNode(ISD::ADD, Res.getValueType(), Res, Res); 3324 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 3325 } 3326 3327 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 3328 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 3329 // for fneg/fabs. 3330 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 3331 // Make -1 and vspltisw -1: 3332 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); 3333 3334 // Make the VSLW intrinsic, computing 0x8000_0000. 3335 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 3336 OnesV, DAG); 3337 3338 // xor by OnesV to invert it. 3339 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); 3340 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 3341 } 3342 3343 // Check to see if this is a wide variety of vsplti*, binop self cases. 3344 unsigned SplatBitSize = SplatSize*8; 3345 static const signed char SplatCsts[] = { 3346 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 3347 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 3348 }; 3349 3350 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 3351 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 3352 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 3353 int i = SplatCsts[idx]; 3354 3355 // Figure out what shift amount will be used by altivec if shifted by i in 3356 // this splat size. 3357 unsigned TypeShiftAmt = i & (SplatBitSize-1); 3358 3359 // vsplti + shl self. 3360 if (SextVal == (i << (int)TypeShiftAmt)) { 3361 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 3362 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3363 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 3364 Intrinsic::ppc_altivec_vslw 3365 }; 3366 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 3367 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 3368 } 3369 3370 // vsplti + srl self. 3371 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 3372 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 3373 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3374 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 3375 Intrinsic::ppc_altivec_vsrw 3376 }; 3377 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 3378 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 3379 } 3380 3381 // vsplti + sra self. 3382 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 3383 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 3384 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3385 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 3386 Intrinsic::ppc_altivec_vsraw 3387 }; 3388 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 3389 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 3390 } 3391 3392 // vsplti + rol self. 3393 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 3394 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 3395 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 3396 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3397 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 3398 Intrinsic::ppc_altivec_vrlw 3399 }; 3400 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 3401 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 3402 } 3403 3404 // t = vsplti c, result = vsldoi t, t, 1 3405 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { 3406 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 3407 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG); 3408 } 3409 // t = vsplti c, result = vsldoi t, t, 2 3410 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { 3411 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 3412 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG); 3413 } 3414 // t = vsplti c, result = vsldoi t, t, 3 3415 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { 3416 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 3417 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG); 3418 } 3419 } 3420 3421 // Three instruction sequences. 3422 3423 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 3424 if (SextVal >= 0 && SextVal <= 31) { 3425 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG); 3426 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 3427 LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS); 3428 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 3429 } 3430 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 3431 if (SextVal >= -31 && SextVal <= 0) { 3432 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG); 3433 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 3434 LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS); 3435 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 3436 } 3437 } 3438 3439 return SDValue(); 3440} 3441 3442/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 3443/// the specified operations to build the shuffle. 3444static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 3445 SDValue RHS, SelectionDAG &DAG) { 3446 unsigned OpNum = (PFEntry >> 26) & 0x0F; 3447 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 3448 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 3449 3450 enum { 3451 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 3452 OP_VMRGHW, 3453 OP_VMRGLW, 3454 OP_VSPLTISW0, 3455 OP_VSPLTISW1, 3456 OP_VSPLTISW2, 3457 OP_VSPLTISW3, 3458 OP_VSLDOI4, 3459 OP_VSLDOI8, 3460 OP_VSLDOI12 3461 }; 3462 3463 if (OpNum == OP_COPY) { 3464 if (LHSID == (1*9+2)*9+3) return LHS; 3465 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 3466 return RHS; 3467 } 3468 3469 SDValue OpLHS, OpRHS; 3470 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG); 3471 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG); 3472 3473 unsigned ShufIdxs[16]; 3474 switch (OpNum) { 3475 default: assert(0 && "Unknown i32 permute!"); 3476 case OP_VMRGHW: 3477 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 3478 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 3479 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 3480 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 3481 break; 3482 case OP_VMRGLW: 3483 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 3484 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 3485 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 3486 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 3487 break; 3488 case OP_VSPLTISW0: 3489 for (unsigned i = 0; i != 16; ++i) 3490 ShufIdxs[i] = (i&3)+0; 3491 break; 3492 case OP_VSPLTISW1: 3493 for (unsigned i = 0; i != 16; ++i) 3494 ShufIdxs[i] = (i&3)+4; 3495 break; 3496 case OP_VSPLTISW2: 3497 for (unsigned i = 0; i != 16; ++i) 3498 ShufIdxs[i] = (i&3)+8; 3499 break; 3500 case OP_VSPLTISW3: 3501 for (unsigned i = 0; i != 16; ++i) 3502 ShufIdxs[i] = (i&3)+12; 3503 break; 3504 case OP_VSLDOI4: 3505 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG); 3506 case OP_VSLDOI8: 3507 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG); 3508 case OP_VSLDOI12: 3509 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); 3510 } 3511 SDValue Ops[16]; 3512 for (unsigned i = 0; i != 16; ++i) 3513 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i8); 3514 3515 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS, 3516 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 3517} 3518 3519/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 3520/// is a shuffle we can handle in a single instruction, return it. Otherwise, 3521/// return the code it can be lowered into. Worst case, it can always be 3522/// lowered into a vperm. 3523SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 3524 SelectionDAG &DAG) { 3525 SDValue V1 = Op.getOperand(0); 3526 SDValue V2 = Op.getOperand(1); 3527 SDValue PermMask = Op.getOperand(2); 3528 3529 // Cases that are handled by instructions that take permute immediates 3530 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 3531 // selected by the instruction selector. 3532 if (V2.getOpcode() == ISD::UNDEF) { 3533 if (PPC::isSplatShuffleMask(PermMask.getNode(), 1) || 3534 PPC::isSplatShuffleMask(PermMask.getNode(), 2) || 3535 PPC::isSplatShuffleMask(PermMask.getNode(), 4) || 3536 PPC::isVPKUWUMShuffleMask(PermMask.getNode(), true) || 3537 PPC::isVPKUHUMShuffleMask(PermMask.getNode(), true) || 3538 PPC::isVSLDOIShuffleMask(PermMask.getNode(), true) != -1 || 3539 PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, true) || 3540 PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, true) || 3541 PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, true) || 3542 PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, true) || 3543 PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, true) || 3544 PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, true)) { 3545 return Op; 3546 } 3547 } 3548 3549 // Altivec has a variety of "shuffle immediates" that take two vector inputs 3550 // and produce a fixed permutation. If any of these match, do not lower to 3551 // VPERM. 3552 if (PPC::isVPKUWUMShuffleMask(PermMask.getNode(), false) || 3553 PPC::isVPKUHUMShuffleMask(PermMask.getNode(), false) || 3554 PPC::isVSLDOIShuffleMask(PermMask.getNode(), false) != -1 || 3555 PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, false) || 3556 PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, false) || 3557 PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, false) || 3558 PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, false) || 3559 PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, false) || 3560 PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, false)) 3561 return Op; 3562 3563 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 3564 // perfect shuffle table to emit an optimal matching sequence. 3565 unsigned PFIndexes[4]; 3566 bool isFourElementShuffle = true; 3567 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 3568 unsigned EltNo = 8; // Start out undef. 3569 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 3570 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF) 3571 continue; // Undef, ignore it. 3572 3573 unsigned ByteSource = 3574 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getZExtValue(); 3575 if ((ByteSource & 3) != j) { 3576 isFourElementShuffle = false; 3577 break; 3578 } 3579 3580 if (EltNo == 8) { 3581 EltNo = ByteSource/4; 3582 } else if (EltNo != ByteSource/4) { 3583 isFourElementShuffle = false; 3584 break; 3585 } 3586 } 3587 PFIndexes[i] = EltNo; 3588 } 3589 3590 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 3591 // perfect shuffle vector to determine if it is cost effective to do this as 3592 // discrete instructions, or whether we should use a vperm. 3593 if (isFourElementShuffle) { 3594 // Compute the index in the perfect shuffle table. 3595 unsigned PFTableIndex = 3596 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 3597 3598 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 3599 unsigned Cost = (PFEntry >> 30); 3600 3601 // Determining when to avoid vperm is tricky. Many things affect the cost 3602 // of vperm, particularly how many times the perm mask needs to be computed. 3603 // For example, if the perm mask can be hoisted out of a loop or is already 3604 // used (perhaps because there are multiple permutes with the same shuffle 3605 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 3606 // the loop requires an extra register. 3607 // 3608 // As a compromise, we only emit discrete instructions if the shuffle can be 3609 // generated in 3 or fewer operations. When we have loop information 3610 // available, if this block is within a loop, we should avoid using vperm 3611 // for 3-operation perms and use a constant pool load instead. 3612 if (Cost < 3) 3613 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG); 3614 } 3615 3616 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 3617 // vector that will get spilled to the constant pool. 3618 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 3619 3620 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 3621 // that it is in input element units, not in bytes. Convert now. 3622 MVT EltVT = V1.getValueType().getVectorElementType(); 3623 unsigned BytesPerElement = EltVT.getSizeInBits()/8; 3624 3625 SmallVector<SDValue, 16> ResultMask; 3626 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { 3627 unsigned SrcElt; 3628 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) 3629 SrcElt = 0; 3630 else 3631 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getZExtValue(); 3632 3633 for (unsigned j = 0; j != BytesPerElement; ++j) 3634 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 3635 MVT::i8)); 3636 } 3637 3638 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, 3639 &ResultMask[0], ResultMask.size()); 3640 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); 3641} 3642 3643/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 3644/// altivec comparison. If it is, return true and fill in Opc/isDot with 3645/// information about the intrinsic. 3646static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, 3647 bool &isDot) { 3648 unsigned IntrinsicID = 3649 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue(); 3650 CompareOpc = -1; 3651 isDot = false; 3652 switch (IntrinsicID) { 3653 default: return false; 3654 // Comparison predicates. 3655 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 3656 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 3657 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 3658 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 3659 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 3660 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 3661 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 3662 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 3663 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 3664 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 3665 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 3666 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 3667 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 3668 3669 // Normal Comparisons. 3670 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 3671 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 3672 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 3673 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 3674 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 3675 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 3676 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 3677 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 3678 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 3679 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 3680 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 3681 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 3682 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 3683 } 3684 return true; 3685} 3686 3687/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 3688/// lower, do it, otherwise return null. 3689SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 3690 SelectionDAG &DAG) { 3691 // If this is a lowered altivec predicate compare, CompareOpc is set to the 3692 // opcode number of the comparison. 3693 int CompareOpc; 3694 bool isDot; 3695 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 3696 return SDValue(); // Don't custom lower most intrinsics. 3697 3698 // If this is a non-dot comparison, make the VCMP node and we are done. 3699 if (!isDot) { 3700 SDValue Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), 3701 Op.getOperand(1), Op.getOperand(2), 3702 DAG.getConstant(CompareOpc, MVT::i32)); 3703 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); 3704 } 3705 3706 // Create the PPCISD altivec 'dot' comparison node. 3707 SDValue Ops[] = { 3708 Op.getOperand(2), // LHS 3709 Op.getOperand(3), // RHS 3710 DAG.getConstant(CompareOpc, MVT::i32) 3711 }; 3712 std::vector<MVT> VTs; 3713 VTs.push_back(Op.getOperand(2).getValueType()); 3714 VTs.push_back(MVT::Flag); 3715 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 3716 3717 // Now that we have the comparison, emit a copy from the CR to a GPR. 3718 // This is flagged to the above dot comparison. 3719 SDValue Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, 3720 DAG.getRegister(PPC::CR6, MVT::i32), 3721 CompNode.getValue(1)); 3722 3723 // Unpack the result based on how the target uses it. 3724 unsigned BitNo; // Bit # of CR6. 3725 bool InvertBit; // Invert result? 3726 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) { 3727 default: // Can't happen, don't crash on invalid number though. 3728 case 0: // Return the value of the EQ bit of CR6. 3729 BitNo = 0; InvertBit = false; 3730 break; 3731 case 1: // Return the inverted value of the EQ bit of CR6. 3732 BitNo = 0; InvertBit = true; 3733 break; 3734 case 2: // Return the value of the LT bit of CR6. 3735 BitNo = 2; InvertBit = false; 3736 break; 3737 case 3: // Return the inverted value of the LT bit of CR6. 3738 BitNo = 2; InvertBit = true; 3739 break; 3740 } 3741 3742 // Shift the bit into the low position. 3743 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, 3744 DAG.getConstant(8-(3-BitNo), MVT::i32)); 3745 // Isolate the bit. 3746 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, 3747 DAG.getConstant(1, MVT::i32)); 3748 3749 // If we are supposed to, toggle the bit. 3750 if (InvertBit) 3751 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, 3752 DAG.getConstant(1, MVT::i32)); 3753 return Flags; 3754} 3755 3756SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, 3757 SelectionDAG &DAG) { 3758 // Create a stack slot that is 16-byte aligned. 3759 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 3760 int FrameIdx = FrameInfo->CreateStackObject(16, 16); 3761 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3762 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 3763 3764 // Store the input value into Value#0 of the stack slot. 3765 SDValue Store = DAG.getStore(DAG.getEntryNode(), 3766 Op.getOperand(0), FIdx, NULL, 0); 3767 // Load it out. 3768 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); 3769} 3770 3771SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { 3772 if (Op.getValueType() == MVT::v4i32) { 3773 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3774 3775 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); 3776 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. 3777 3778 SDValue RHSSwap = // = vrlw RHS, 16 3779 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG); 3780 3781 // Shrinkify inputs to v8i16. 3782 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS); 3783 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS); 3784 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap); 3785 3786 // Low parts multiplied together, generating 32-bit results (we ignore the 3787 // top parts). 3788 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 3789 LHS, RHS, DAG, MVT::v4i32); 3790 3791 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 3792 LHS, RHSSwap, Zero, DAG, MVT::v4i32); 3793 // Shift the high parts up 16 bits. 3794 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG); 3795 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd); 3796 } else if (Op.getValueType() == MVT::v8i16) { 3797 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3798 3799 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); 3800 3801 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 3802 LHS, RHS, Zero, DAG); 3803 } else if (Op.getValueType() == MVT::v16i8) { 3804 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3805 3806 // Multiply the even 8-bit parts, producing 16-bit sums. 3807 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 3808 LHS, RHS, DAG, MVT::v8i16); 3809 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts); 3810 3811 // Multiply the odd 8-bit parts, producing 16-bit sums. 3812 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 3813 LHS, RHS, DAG, MVT::v8i16); 3814 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); 3815 3816 // Merge the results together. 3817 SDValue Ops[16]; 3818 for (unsigned i = 0; i != 8; ++i) { 3819 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); 3820 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); 3821 } 3822 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts, 3823 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 3824 } else { 3825 assert(0 && "Unknown mul to lower!"); 3826 abort(); 3827 } 3828} 3829 3830/// LowerOperation - Provide custom lowering hooks for some operations. 3831/// 3832SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 3833 switch (Op.getOpcode()) { 3834 default: assert(0 && "Wasn't expecting to be able to lower this!"); 3835 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 3836 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 3837 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 3838 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 3839 case ISD::SETCC: return LowerSETCC(Op, DAG); 3840 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 3841 case ISD::VASTART: 3842 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 3843 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 3844 3845 case ISD::VAARG: 3846 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 3847 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 3848 3849 case ISD::FORMAL_ARGUMENTS: 3850 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex, 3851 VarArgsStackOffset, VarArgsNumGPR, 3852 VarArgsNumFPR, PPCSubTarget); 3853 3854 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget, 3855 getTargetMachine()); 3856 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine()); 3857 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 3858 case ISD::DYNAMIC_STACKALLOC: 3859 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 3860 3861 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 3862 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 3863 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 3864 case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG); 3865 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 3866 3867 // Lower 64-bit shifts. 3868 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 3869 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 3870 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 3871 3872 // Vector-related lowering. 3873 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 3874 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 3875 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 3876 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 3877 case ISD::MUL: return LowerMUL(Op, DAG); 3878 3879 // Frame & Return address. 3880 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 3881 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 3882 } 3883 return SDValue(); 3884} 3885 3886SDNode *PPCTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) { 3887 switch (N->getOpcode()) { 3888 default: assert(0 && "Wasn't expecting to be able to lower this!"); 3889 case ISD::FP_TO_SINT: { 3890 SDValue Res = LowerFP_TO_SINT(SDValue(N, 0), DAG); 3891 // Use MERGE_VALUES to drop the chain result value and get a node with one 3892 // result. This requires turning off getMergeValues simplification, since 3893 // otherwise it will give us Res back. 3894 return DAG.getMergeValues(&Res, 1, false).getNode(); 3895 } 3896 } 3897} 3898 3899 3900//===----------------------------------------------------------------------===// 3901// Other Lowering Code 3902//===----------------------------------------------------------------------===// 3903 3904MachineBasicBlock * 3905PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 3906 bool is64bit, unsigned BinOpcode) { 3907 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 3908 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 3909 3910 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3911 MachineFunction *F = BB->getParent(); 3912 MachineFunction::iterator It = BB; 3913 ++It; 3914 3915 unsigned dest = MI->getOperand(0).getReg(); 3916 unsigned ptrA = MI->getOperand(1).getReg(); 3917 unsigned ptrB = MI->getOperand(2).getReg(); 3918 unsigned incr = MI->getOperand(3).getReg(); 3919 3920 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 3921 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 3922 F->insert(It, loopMBB); 3923 F->insert(It, exitMBB); 3924 exitMBB->transferSuccessors(BB); 3925 3926 MachineRegisterInfo &RegInfo = F->getRegInfo(); 3927 unsigned TmpReg = (!BinOpcode) ? incr : 3928 RegInfo.createVirtualRegister( 3929 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 3930 (const TargetRegisterClass *) &PPC::GPRCRegClass); 3931 3932 // thisMBB: 3933 // ... 3934 // fallthrough --> loopMBB 3935 BB->addSuccessor(loopMBB); 3936 3937 // loopMBB: 3938 // l[wd]arx dest, ptr 3939 // add r0, dest, incr 3940 // st[wd]cx. r0, ptr 3941 // bne- loopMBB 3942 // fallthrough --> exitMBB 3943 BB = loopMBB; 3944 BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 3945 .addReg(ptrA).addReg(ptrB); 3946 if (BinOpcode) 3947 BuildMI(BB, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); 3948 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 3949 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); 3950 BuildMI(BB, TII->get(PPC::BCC)) 3951 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 3952 BB->addSuccessor(loopMBB); 3953 BB->addSuccessor(exitMBB); 3954 3955 // exitMBB: 3956 // ... 3957 BB = exitMBB; 3958 return BB; 3959} 3960 3961MachineBasicBlock * 3962PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, 3963 MachineBasicBlock *BB, 3964 bool is8bit, // operation 3965 unsigned BinOpcode) { 3966 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 3967 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 3968 // In 64 bit mode we have to use 64 bits for addresses, even though the 3969 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address 3970 // registers without caring whether they're 32 or 64, but here we're 3971 // doing actual arithmetic on the addresses. 3972 bool is64bit = PPCSubTarget.isPPC64(); 3973 3974 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3975 MachineFunction *F = BB->getParent(); 3976 MachineFunction::iterator It = BB; 3977 ++It; 3978 3979 unsigned dest = MI->getOperand(0).getReg(); 3980 unsigned ptrA = MI->getOperand(1).getReg(); 3981 unsigned ptrB = MI->getOperand(2).getReg(); 3982 unsigned incr = MI->getOperand(3).getReg(); 3983 3984 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 3985 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 3986 F->insert(It, loopMBB); 3987 F->insert(It, exitMBB); 3988 exitMBB->transferSuccessors(BB); 3989 3990 MachineRegisterInfo &RegInfo = F->getRegInfo(); 3991 const TargetRegisterClass *RC = 3992 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 3993 (const TargetRegisterClass *) &PPC::GPRCRegClass; 3994 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 3995 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 3996 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 3997 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC); 3998 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 3999 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4000 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4001 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4002 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC); 4003 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4004 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4005 unsigned Ptr1Reg; 4006 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); 4007 4008 // thisMBB: 4009 // ... 4010 // fallthrough --> loopMBB 4011 BB->addSuccessor(loopMBB); 4012 4013 // The 4-byte load must be aligned, while a char or short may be 4014 // anywhere in the word. Hence all this nasty bookkeeping code. 4015 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4016 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4017 // xori shift, shift1, 24 [16] 4018 // rlwinm ptr, ptr1, 0, 0, 29 4019 // slw incr2, incr, shift 4020 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 4021 // slw mask, mask2, shift 4022 // loopMBB: 4023 // lwarx tmpDest, ptr 4024 // add tmp, tmpDest, incr2 4025 // andc tmp2, tmpDest, mask 4026 // and tmp3, tmp, mask 4027 // or tmp4, tmp3, tmp2 4028 // stwcx. tmp4, ptr 4029 // bne- loopMBB 4030 // fallthrough --> exitMBB 4031 // srw dest, tmpDest, shift 4032 4033 if (ptrA!=PPC::R0) { 4034 Ptr1Reg = RegInfo.createVirtualRegister(RC); 4035 BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 4036 .addReg(ptrA).addReg(ptrB); 4037 } else { 4038 Ptr1Reg = ptrB; 4039 } 4040 BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 4041 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 4042 BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 4043 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 4044 if (is64bit) 4045 BuildMI(BB, TII->get(PPC::RLDICR), PtrReg) 4046 .addReg(Ptr1Reg).addImm(0).addImm(61); 4047 else 4048 BuildMI(BB, TII->get(PPC::RLWINM), PtrReg) 4049 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 4050 BuildMI(BB, TII->get(PPC::SLW), Incr2Reg) 4051 .addReg(incr).addReg(ShiftReg); 4052 if (is8bit) 4053 BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255); 4054 else { 4055 BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0); 4056 BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535); 4057 } 4058 BuildMI(BB, TII->get(PPC::SLW), MaskReg) 4059 .addReg(Mask2Reg).addReg(ShiftReg); 4060 4061 BB = loopMBB; 4062 BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg) 4063 .addReg(PPC::R0).addReg(PtrReg); 4064 if (BinOpcode) 4065 BuildMI(BB, TII->get(BinOpcode), TmpReg) 4066 .addReg(Incr2Reg).addReg(TmpDestReg); 4067 BuildMI(BB, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) 4068 .addReg(TmpDestReg).addReg(MaskReg); 4069 BuildMI(BB, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) 4070 .addReg(TmpReg).addReg(MaskReg); 4071 BuildMI(BB, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) 4072 .addReg(Tmp3Reg).addReg(Tmp2Reg); 4073 BuildMI(BB, TII->get(PPC::STWCX)) 4074 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg); 4075 BuildMI(BB, TII->get(PPC::BCC)) 4076 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4077 BB->addSuccessor(loopMBB); 4078 BB->addSuccessor(exitMBB); 4079 4080 // exitMBB: 4081 // ... 4082 BB = exitMBB; 4083 BuildMI(BB, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg); 4084 return BB; 4085} 4086 4087MachineBasicBlock * 4088PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 4089 MachineBasicBlock *BB) { 4090 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4091 4092 // To "insert" these instructions we actually have to insert their 4093 // control-flow patterns. 4094 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4095 MachineFunction::iterator It = BB; 4096 ++It; 4097 4098 MachineFunction *F = BB->getParent(); 4099 4100 if (MI->getOpcode() == PPC::SELECT_CC_I4 || 4101 MI->getOpcode() == PPC::SELECT_CC_I8 || 4102 MI->getOpcode() == PPC::SELECT_CC_F4 || 4103 MI->getOpcode() == PPC::SELECT_CC_F8 || 4104 MI->getOpcode() == PPC::SELECT_CC_VRRC) { 4105 4106 // The incoming instruction knows the destination vreg to set, the 4107 // condition code register to branch on, the true/false values to 4108 // select between, and a branch opcode to use. 4109 4110 // thisMBB: 4111 // ... 4112 // TrueVal = ... 4113 // cmpTY ccX, r1, r2 4114 // bCC copy1MBB 4115 // fallthrough --> copy0MBB 4116 MachineBasicBlock *thisMBB = BB; 4117 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4118 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4119 unsigned SelectPred = MI->getOperand(4).getImm(); 4120 BuildMI(BB, TII->get(PPC::BCC)) 4121 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 4122 F->insert(It, copy0MBB); 4123 F->insert(It, sinkMBB); 4124 // Update machine-CFG edges by transferring all successors of the current 4125 // block to the new block which will contain the Phi node for the select. 4126 sinkMBB->transferSuccessors(BB); 4127 // Next, add the true and fallthrough blocks as its successors. 4128 BB->addSuccessor(copy0MBB); 4129 BB->addSuccessor(sinkMBB); 4130 4131 // copy0MBB: 4132 // %FalseValue = ... 4133 // # fallthrough to sinkMBB 4134 BB = copy0MBB; 4135 4136 // Update machine-CFG edges 4137 BB->addSuccessor(sinkMBB); 4138 4139 // sinkMBB: 4140 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 4141 // ... 4142 BB = sinkMBB; 4143 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg()) 4144 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 4145 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 4146 } 4147 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) 4148 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); 4149 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) 4150 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); 4151 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) 4152 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4); 4153 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) 4154 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8); 4155 4156 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8) 4157 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); 4158 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16) 4159 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); 4160 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32) 4161 BB = EmitAtomicBinary(MI, BB, false, PPC::AND); 4162 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64) 4163 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8); 4164 4165 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8) 4166 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); 4167 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16) 4168 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); 4169 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32) 4170 BB = EmitAtomicBinary(MI, BB, false, PPC::OR); 4171 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64) 4172 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8); 4173 4174 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) 4175 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); 4176 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) 4177 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); 4178 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) 4179 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR); 4180 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) 4181 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8); 4182 4183 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) 4184 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC); 4185 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) 4186 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC); 4187 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) 4188 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC); 4189 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) 4190 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8); 4191 4192 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) 4193 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); 4194 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) 4195 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); 4196 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) 4197 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF); 4198 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) 4199 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8); 4200 4201 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8) 4202 BB = EmitPartwordAtomicBinary(MI, BB, true, 0); 4203 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16) 4204 BB = EmitPartwordAtomicBinary(MI, BB, false, 0); 4205 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32) 4206 BB = EmitAtomicBinary(MI, BB, false, 0); 4207 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64) 4208 BB = EmitAtomicBinary(MI, BB, true, 0); 4209 4210 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || 4211 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) { 4212 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; 4213 4214 unsigned dest = MI->getOperand(0).getReg(); 4215 unsigned ptrA = MI->getOperand(1).getReg(); 4216 unsigned ptrB = MI->getOperand(2).getReg(); 4217 unsigned oldval = MI->getOperand(3).getReg(); 4218 unsigned newval = MI->getOperand(4).getReg(); 4219 4220 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 4221 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 4222 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 4223 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4224 F->insert(It, loop1MBB); 4225 F->insert(It, loop2MBB); 4226 F->insert(It, midMBB); 4227 F->insert(It, exitMBB); 4228 exitMBB->transferSuccessors(BB); 4229 4230 // thisMBB: 4231 // ... 4232 // fallthrough --> loopMBB 4233 BB->addSuccessor(loop1MBB); 4234 4235 // loop1MBB: 4236 // l[wd]arx dest, ptr 4237 // cmp[wd] dest, oldval 4238 // bne- midMBB 4239 // loop2MBB: 4240 // st[wd]cx. newval, ptr 4241 // bne- loopMBB 4242 // b exitBB 4243 // midMBB: 4244 // st[wd]cx. dest, ptr 4245 // exitBB: 4246 BB = loop1MBB; 4247 BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4248 .addReg(ptrA).addReg(ptrB); 4249 BuildMI(BB, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) 4250 .addReg(oldval).addReg(dest); 4251 BuildMI(BB, TII->get(PPC::BCC)) 4252 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 4253 BB->addSuccessor(loop2MBB); 4254 BB->addSuccessor(midMBB); 4255 4256 BB = loop2MBB; 4257 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4258 .addReg(newval).addReg(ptrA).addReg(ptrB); 4259 BuildMI(BB, TII->get(PPC::BCC)) 4260 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 4261 BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB); 4262 BB->addSuccessor(loop1MBB); 4263 BB->addSuccessor(exitMBB); 4264 4265 BB = midMBB; 4266 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4267 .addReg(dest).addReg(ptrA).addReg(ptrB); 4268 BB->addSuccessor(exitMBB); 4269 4270 // exitMBB: 4271 // ... 4272 BB = exitMBB; 4273 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || 4274 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { 4275 // We must use 64-bit registers for addresses when targeting 64-bit, 4276 // since we're actually doing arithmetic on them. Other registers 4277 // can be 32-bit. 4278 bool is64bit = PPCSubTarget.isPPC64(); 4279 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; 4280 4281 unsigned dest = MI->getOperand(0).getReg(); 4282 unsigned ptrA = MI->getOperand(1).getReg(); 4283 unsigned ptrB = MI->getOperand(2).getReg(); 4284 unsigned oldval = MI->getOperand(3).getReg(); 4285 unsigned newval = MI->getOperand(4).getReg(); 4286 4287 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 4288 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 4289 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 4290 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4291 F->insert(It, loop1MBB); 4292 F->insert(It, loop2MBB); 4293 F->insert(It, midMBB); 4294 F->insert(It, exitMBB); 4295 exitMBB->transferSuccessors(BB); 4296 4297 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4298 const TargetRegisterClass *RC = 4299 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4300 (const TargetRegisterClass *) &PPC::GPRCRegClass; 4301 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 4302 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 4303 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 4304 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC); 4305 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC); 4306 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC); 4307 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC); 4308 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 4309 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4310 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4311 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4312 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4313 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4314 unsigned Ptr1Reg; 4315 unsigned TmpReg = RegInfo.createVirtualRegister(RC); 4316 // thisMBB: 4317 // ... 4318 // fallthrough --> loopMBB 4319 BB->addSuccessor(loop1MBB); 4320 4321 // The 4-byte load must be aligned, while a char or short may be 4322 // anywhere in the word. Hence all this nasty bookkeeping code. 4323 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4324 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4325 // xori shift, shift1, 24 [16] 4326 // rlwinm ptr, ptr1, 0, 0, 29 4327 // slw newval2, newval, shift 4328 // slw oldval2, oldval,shift 4329 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 4330 // slw mask, mask2, shift 4331 // and newval3, newval2, mask 4332 // and oldval3, oldval2, mask 4333 // loop1MBB: 4334 // lwarx tmpDest, ptr 4335 // and tmp, tmpDest, mask 4336 // cmpw tmp, oldval3 4337 // bne- midMBB 4338 // loop2MBB: 4339 // andc tmp2, tmpDest, mask 4340 // or tmp4, tmp2, newval3 4341 // stwcx. tmp4, ptr 4342 // bne- loop1MBB 4343 // b exitBB 4344 // midMBB: 4345 // stwcx. tmpDest, ptr 4346 // exitBB: 4347 // srw dest, tmpDest, shift 4348 if (ptrA!=PPC::R0) { 4349 Ptr1Reg = RegInfo.createVirtualRegister(RC); 4350 BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 4351 .addReg(ptrA).addReg(ptrB); 4352 } else { 4353 Ptr1Reg = ptrB; 4354 } 4355 BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 4356 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 4357 BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 4358 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 4359 if (is64bit) 4360 BuildMI(BB, TII->get(PPC::RLDICR), PtrReg) 4361 .addReg(Ptr1Reg).addImm(0).addImm(61); 4362 else 4363 BuildMI(BB, TII->get(PPC::RLWINM), PtrReg) 4364 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 4365 BuildMI(BB, TII->get(PPC::SLW), NewVal2Reg) 4366 .addReg(newval).addReg(ShiftReg); 4367 BuildMI(BB, TII->get(PPC::SLW), OldVal2Reg) 4368 .addReg(oldval).addReg(ShiftReg); 4369 if (is8bit) 4370 BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255); 4371 else { 4372 BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0); 4373 BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535); 4374 } 4375 BuildMI(BB, TII->get(PPC::SLW), MaskReg) 4376 .addReg(Mask2Reg).addReg(ShiftReg); 4377 BuildMI(BB, TII->get(PPC::AND), NewVal3Reg) 4378 .addReg(NewVal2Reg).addReg(MaskReg); 4379 BuildMI(BB, TII->get(PPC::AND), OldVal3Reg) 4380 .addReg(OldVal2Reg).addReg(MaskReg); 4381 4382 BB = loop1MBB; 4383 BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg) 4384 .addReg(PPC::R0).addReg(PtrReg); 4385 BuildMI(BB, TII->get(PPC::AND),TmpReg).addReg(TmpDestReg).addReg(MaskReg); 4386 BuildMI(BB, TII->get(PPC::CMPW), PPC::CR0) 4387 .addReg(TmpReg).addReg(OldVal3Reg); 4388 BuildMI(BB, TII->get(PPC::BCC)) 4389 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 4390 BB->addSuccessor(loop2MBB); 4391 BB->addSuccessor(midMBB); 4392 4393 BB = loop2MBB; 4394 BuildMI(BB, TII->get(PPC::ANDC),Tmp2Reg).addReg(TmpDestReg).addReg(MaskReg); 4395 BuildMI(BB, TII->get(PPC::OR),Tmp4Reg).addReg(Tmp2Reg).addReg(NewVal3Reg); 4396 BuildMI(BB, TII->get(PPC::STWCX)).addReg(Tmp4Reg) 4397 .addReg(PPC::R0).addReg(PtrReg); 4398 BuildMI(BB, TII->get(PPC::BCC)) 4399 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 4400 BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB); 4401 BB->addSuccessor(loop1MBB); 4402 BB->addSuccessor(exitMBB); 4403 4404 BB = midMBB; 4405 BuildMI(BB, TII->get(PPC::STWCX)).addReg(TmpDestReg) 4406 .addReg(PPC::R0).addReg(PtrReg); 4407 BB->addSuccessor(exitMBB); 4408 4409 // exitMBB: 4410 // ... 4411 BB = exitMBB; 4412 BuildMI(BB, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg); 4413 } else { 4414 assert(0 && "Unexpected instr type to insert"); 4415 } 4416 4417 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 4418 return BB; 4419} 4420 4421//===----------------------------------------------------------------------===// 4422// Target Optimization Hooks 4423//===----------------------------------------------------------------------===// 4424 4425SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, 4426 DAGCombinerInfo &DCI) const { 4427 TargetMachine &TM = getTargetMachine(); 4428 SelectionDAG &DAG = DCI.DAG; 4429 switch (N->getOpcode()) { 4430 default: break; 4431 case PPCISD::SHL: 4432 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 4433 if (C->getZExtValue() == 0) // 0 << V -> 0. 4434 return N->getOperand(0); 4435 } 4436 break; 4437 case PPCISD::SRL: 4438 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 4439 if (C->getZExtValue() == 0) // 0 >>u V -> 0. 4440 return N->getOperand(0); 4441 } 4442 break; 4443 case PPCISD::SRA: 4444 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 4445 if (C->getZExtValue() == 0 || // 0 >>s V -> 0. 4446 C->isAllOnesValue()) // -1 >>s V -> -1. 4447 return N->getOperand(0); 4448 } 4449 break; 4450 4451 case ISD::SINT_TO_FP: 4452 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 4453 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 4454 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 4455 // We allow the src/dst to be either f32/f64, but the intermediate 4456 // type must be i64. 4457 if (N->getOperand(0).getValueType() == MVT::i64 && 4458 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 4459 SDValue Val = N->getOperand(0).getOperand(0); 4460 if (Val.getValueType() == MVT::f32) { 4461 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 4462 DCI.AddToWorklist(Val.getNode()); 4463 } 4464 4465 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); 4466 DCI.AddToWorklist(Val.getNode()); 4467 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); 4468 DCI.AddToWorklist(Val.getNode()); 4469 if (N->getValueType(0) == MVT::f32) { 4470 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val, 4471 DAG.getIntPtrConstant(0)); 4472 DCI.AddToWorklist(Val.getNode()); 4473 } 4474 return Val; 4475 } else if (N->getOperand(0).getValueType() == MVT::i32) { 4476 // If the intermediate type is i32, we can avoid the load/store here 4477 // too. 4478 } 4479 } 4480 } 4481 break; 4482 case ISD::STORE: 4483 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 4484 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 4485 !cast<StoreSDNode>(N)->isTruncatingStore() && 4486 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 4487 N->getOperand(1).getValueType() == MVT::i32 && 4488 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 4489 SDValue Val = N->getOperand(1).getOperand(0); 4490 if (Val.getValueType() == MVT::f32) { 4491 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 4492 DCI.AddToWorklist(Val.getNode()); 4493 } 4494 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); 4495 DCI.AddToWorklist(Val.getNode()); 4496 4497 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, 4498 N->getOperand(2), N->getOperand(3)); 4499 DCI.AddToWorklist(Val.getNode()); 4500 return Val; 4501 } 4502 4503 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 4504 if (N->getOperand(1).getOpcode() == ISD::BSWAP && 4505 N->getOperand(1).getNode()->hasOneUse() && 4506 (N->getOperand(1).getValueType() == MVT::i32 || 4507 N->getOperand(1).getValueType() == MVT::i16)) { 4508 SDValue BSwapOp = N->getOperand(1).getOperand(0); 4509 // Do an any-extend to 32-bits if this is a half-word input. 4510 if (BSwapOp.getValueType() == MVT::i16) 4511 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp); 4512 4513 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp, 4514 N->getOperand(2), N->getOperand(3), 4515 DAG.getValueType(N->getOperand(1).getValueType())); 4516 } 4517 break; 4518 case ISD::BSWAP: 4519 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 4520 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) && 4521 N->getOperand(0).hasOneUse() && 4522 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 4523 SDValue Load = N->getOperand(0); 4524 LoadSDNode *LD = cast<LoadSDNode>(Load); 4525 // Create the byte-swapping load. 4526 std::vector<MVT> VTs; 4527 VTs.push_back(MVT::i32); 4528 VTs.push_back(MVT::Other); 4529 SDValue MO = DAG.getMemOperand(LD->getMemOperand()); 4530 SDValue Ops[] = { 4531 LD->getChain(), // Chain 4532 LD->getBasePtr(), // Ptr 4533 MO, // MemOperand 4534 DAG.getValueType(N->getValueType(0)) // VT 4535 }; 4536 SDValue BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); 4537 4538 // If this is an i16 load, insert the truncate. 4539 SDValue ResVal = BSLoad; 4540 if (N->getValueType(0) == MVT::i16) 4541 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad); 4542 4543 // First, combine the bswap away. This makes the value produced by the 4544 // load dead. 4545 DCI.CombineTo(N, ResVal); 4546 4547 // Next, combine the load away, we give it a bogus result value but a real 4548 // chain result. The result value is dead because the bswap is dead. 4549 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1)); 4550 4551 // Return N so it doesn't get rechecked! 4552 return SDValue(N, 0); 4553 } 4554 4555 break; 4556 case PPCISD::VCMP: { 4557 // If a VCMPo node already exists with exactly the same operands as this 4558 // node, use its result instead of this node (VCMPo computes both a CR6 and 4559 // a normal output). 4560 // 4561 if (!N->getOperand(0).hasOneUse() && 4562 !N->getOperand(1).hasOneUse() && 4563 !N->getOperand(2).hasOneUse()) { 4564 4565 // Scan all of the users of the LHS, looking for VCMPo's that match. 4566 SDNode *VCMPoNode = 0; 4567 4568 SDNode *LHSN = N->getOperand(0).getNode(); 4569 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 4570 UI != E; ++UI) 4571 if (UI->getOpcode() == PPCISD::VCMPo && 4572 UI->getOperand(1) == N->getOperand(1) && 4573 UI->getOperand(2) == N->getOperand(2) && 4574 UI->getOperand(0) == N->getOperand(0)) { 4575 VCMPoNode = *UI; 4576 break; 4577 } 4578 4579 // If there is no VCMPo node, or if the flag value has a single use, don't 4580 // transform this. 4581 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 4582 break; 4583 4584 // Look at the (necessarily single) use of the flag value. If it has a 4585 // chain, this transformation is more complex. Note that multiple things 4586 // could use the value result, which we should ignore. 4587 SDNode *FlagUser = 0; 4588 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 4589 FlagUser == 0; ++UI) { 4590 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 4591 SDNode *User = *UI; 4592 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 4593 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) { 4594 FlagUser = User; 4595 break; 4596 } 4597 } 4598 } 4599 4600 // If the user is a MFCR instruction, we know this is safe. Otherwise we 4601 // give up for right now. 4602 if (FlagUser->getOpcode() == PPCISD::MFCR) 4603 return SDValue(VCMPoNode, 0); 4604 } 4605 break; 4606 } 4607 case ISD::BR_CC: { 4608 // If this is a branch on an altivec predicate comparison, lower this so 4609 // that we don't have to do a MFCR: instead, branch directly on CR6. This 4610 // lowering is done pre-legalize, because the legalizer lowers the predicate 4611 // compare down to code that is difficult to reassemble. 4612 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 4613 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 4614 int CompareOpc; 4615 bool isDot; 4616 4617 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 4618 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 4619 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 4620 assert(isDot && "Can't compare against a vector result!"); 4621 4622 // If this is a comparison against something other than 0/1, then we know 4623 // that the condition is never/always true. 4624 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue(); 4625 if (Val != 0 && Val != 1) { 4626 if (CC == ISD::SETEQ) // Cond never true, remove branch. 4627 return N->getOperand(0); 4628 // Always !=, turn it into an unconditional branch. 4629 return DAG.getNode(ISD::BR, MVT::Other, 4630 N->getOperand(0), N->getOperand(4)); 4631 } 4632 4633 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 4634 4635 // Create the PPCISD altivec 'dot' comparison node. 4636 std::vector<MVT> VTs; 4637 SDValue Ops[] = { 4638 LHS.getOperand(2), // LHS of compare 4639 LHS.getOperand(3), // RHS of compare 4640 DAG.getConstant(CompareOpc, MVT::i32) 4641 }; 4642 VTs.push_back(LHS.getOperand(2).getValueType()); 4643 VTs.push_back(MVT::Flag); 4644 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 4645 4646 // Unpack the result based on how the target uses it. 4647 PPC::Predicate CompOpc; 4648 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) { 4649 default: // Can't happen, don't crash on invalid number though. 4650 case 0: // Branch on the value of the EQ bit of CR6. 4651 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 4652 break; 4653 case 1: // Branch on the inverted value of the EQ bit of CR6. 4654 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 4655 break; 4656 case 2: // Branch on the value of the LT bit of CR6. 4657 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 4658 break; 4659 case 3: // Branch on the inverted value of the LT bit of CR6. 4660 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 4661 break; 4662 } 4663 4664 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), 4665 DAG.getConstant(CompOpc, MVT::i32), 4666 DAG.getRegister(PPC::CR6, MVT::i32), 4667 N->getOperand(4), CompNode.getValue(1)); 4668 } 4669 break; 4670 } 4671 } 4672 4673 return SDValue(); 4674} 4675 4676//===----------------------------------------------------------------------===// 4677// Inline Assembly Support 4678//===----------------------------------------------------------------------===// 4679 4680void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 4681 const APInt &Mask, 4682 APInt &KnownZero, 4683 APInt &KnownOne, 4684 const SelectionDAG &DAG, 4685 unsigned Depth) const { 4686 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 4687 switch (Op.getOpcode()) { 4688 default: break; 4689 case PPCISD::LBRX: { 4690 // lhbrx is known to have the top bits cleared out. 4691 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16) 4692 KnownZero = 0xFFFF0000; 4693 break; 4694 } 4695 case ISD::INTRINSIC_WO_CHAIN: { 4696 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) { 4697 default: break; 4698 case Intrinsic::ppc_altivec_vcmpbfp_p: 4699 case Intrinsic::ppc_altivec_vcmpeqfp_p: 4700 case Intrinsic::ppc_altivec_vcmpequb_p: 4701 case Intrinsic::ppc_altivec_vcmpequh_p: 4702 case Intrinsic::ppc_altivec_vcmpequw_p: 4703 case Intrinsic::ppc_altivec_vcmpgefp_p: 4704 case Intrinsic::ppc_altivec_vcmpgtfp_p: 4705 case Intrinsic::ppc_altivec_vcmpgtsb_p: 4706 case Intrinsic::ppc_altivec_vcmpgtsh_p: 4707 case Intrinsic::ppc_altivec_vcmpgtsw_p: 4708 case Intrinsic::ppc_altivec_vcmpgtub_p: 4709 case Intrinsic::ppc_altivec_vcmpgtuh_p: 4710 case Intrinsic::ppc_altivec_vcmpgtuw_p: 4711 KnownZero = ~1U; // All bits but the low one are known to be zero. 4712 break; 4713 } 4714 } 4715 } 4716} 4717 4718 4719/// getConstraintType - Given a constraint, return the type of 4720/// constraint it is for this target. 4721PPCTargetLowering::ConstraintType 4722PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 4723 if (Constraint.size() == 1) { 4724 switch (Constraint[0]) { 4725 default: break; 4726 case 'b': 4727 case 'r': 4728 case 'f': 4729 case 'v': 4730 case 'y': 4731 return C_RegisterClass; 4732 } 4733 } 4734 return TargetLowering::getConstraintType(Constraint); 4735} 4736 4737std::pair<unsigned, const TargetRegisterClass*> 4738PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 4739 MVT VT) const { 4740 if (Constraint.size() == 1) { 4741 // GCC RS6000 Constraint Letters 4742 switch (Constraint[0]) { 4743 case 'b': // R1-R31 4744 case 'r': // R0-R31 4745 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 4746 return std::make_pair(0U, PPC::G8RCRegisterClass); 4747 return std::make_pair(0U, PPC::GPRCRegisterClass); 4748 case 'f': 4749 if (VT == MVT::f32) 4750 return std::make_pair(0U, PPC::F4RCRegisterClass); 4751 else if (VT == MVT::f64) 4752 return std::make_pair(0U, PPC::F8RCRegisterClass); 4753 break; 4754 case 'v': 4755 return std::make_pair(0U, PPC::VRRCRegisterClass); 4756 case 'y': // crrc 4757 return std::make_pair(0U, PPC::CRRCRegisterClass); 4758 } 4759 } 4760 4761 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 4762} 4763 4764 4765/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 4766/// vector. If it is invalid, don't add anything to Ops. If hasMemory is true 4767/// it means one of the asm constraint of the inline asm instruction being 4768/// processed is 'm'. 4769void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter, 4770 bool hasMemory, 4771 std::vector<SDValue>&Ops, 4772 SelectionDAG &DAG) const { 4773 SDValue Result(0,0); 4774 switch (Letter) { 4775 default: break; 4776 case 'I': 4777 case 'J': 4778 case 'K': 4779 case 'L': 4780 case 'M': 4781 case 'N': 4782 case 'O': 4783 case 'P': { 4784 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 4785 if (!CST) return; // Must be an immediate to match. 4786 unsigned Value = CST->getZExtValue(); 4787 switch (Letter) { 4788 default: assert(0 && "Unknown constraint letter!"); 4789 case 'I': // "I" is a signed 16-bit constant. 4790 if ((short)Value == (int)Value) 4791 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4792 break; 4793 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 4794 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 4795 if ((short)Value == 0) 4796 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4797 break; 4798 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 4799 if ((Value >> 16) == 0) 4800 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4801 break; 4802 case 'M': // "M" is a constant that is greater than 31. 4803 if (Value > 31) 4804 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4805 break; 4806 case 'N': // "N" is a positive constant that is an exact power of two. 4807 if ((int)Value > 0 && isPowerOf2_32(Value)) 4808 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4809 break; 4810 case 'O': // "O" is the constant zero. 4811 if (Value == 0) 4812 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4813 break; 4814 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 4815 if ((short)-Value == (int)-Value) 4816 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4817 break; 4818 } 4819 break; 4820 } 4821 } 4822 4823 if (Result.getNode()) { 4824 Ops.push_back(Result); 4825 return; 4826 } 4827 4828 // Handle standard constraint letters. 4829 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, hasMemory, Ops, DAG); 4830} 4831 4832// isLegalAddressingMode - Return true if the addressing mode represented 4833// by AM is legal for this target, for a load/store of the specified type. 4834bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 4835 const Type *Ty) const { 4836 // FIXME: PPC does not allow r+i addressing modes for vectors! 4837 4838 // PPC allows a sign-extended 16-bit immediate field. 4839 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 4840 return false; 4841 4842 // No global is ever allowed as a base. 4843 if (AM.BaseGV) 4844 return false; 4845 4846 // PPC only support r+r, 4847 switch (AM.Scale) { 4848 case 0: // "r+i" or just "i", depending on HasBaseReg. 4849 break; 4850 case 1: 4851 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 4852 return false; 4853 // Otherwise we have r+r or r+i. 4854 break; 4855 case 2: 4856 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 4857 return false; 4858 // Allow 2*r as r+r. 4859 break; 4860 default: 4861 // No other scales are supported. 4862 return false; 4863 } 4864 4865 return true; 4866} 4867 4868/// isLegalAddressImmediate - Return true if the integer value can be used 4869/// as the offset of the target addressing mode for load / store of the 4870/// given type. 4871bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{ 4872 // PPC allows a sign-extended 16-bit immediate field. 4873 return (V > -(1 << 16) && V < (1 << 16)-1); 4874} 4875 4876bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 4877 return false; 4878} 4879 4880SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 4881 // Depths > 0 not supported yet! 4882 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) 4883 return SDValue(); 4884 4885 MachineFunction &MF = DAG.getMachineFunction(); 4886 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 4887 4888 // Just load the return address off the stack. 4889 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); 4890 4891 // Make sure the function really does not optimize away the store of the RA 4892 // to the stack. 4893 FuncInfo->setLRStoreRequired(); 4894 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); 4895} 4896 4897SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 4898 // Depths > 0 not supported yet! 4899 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) 4900 return SDValue(); 4901 4902 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4903 bool isPPC64 = PtrVT == MVT::i64; 4904 4905 MachineFunction &MF = DAG.getMachineFunction(); 4906 MachineFrameInfo *MFI = MF.getFrameInfo(); 4907 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects()) 4908 && MFI->getStackSize(); 4909 4910 if (isPPC64) 4911 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1, 4912 MVT::i64); 4913 else 4914 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1, 4915 MVT::i32); 4916} 4917