PPCISelLowering.cpp revision 942619695f4bd77934c09a1cae0fb39ae59edac3
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPredicates.h" 17#include "PPCTargetMachine.h" 18#include "PPCPerfectShuffle.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/ADT/VectorExtras.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/CallingConv.h" 29#include "llvm/Constants.h" 30#include "llvm/Function.h" 31#include "llvm/Intrinsics.h" 32#include "llvm/Support/MathExtras.h" 33#include "llvm/Target/TargetOptions.h" 34#include "llvm/Target/TargetLoweringObjectFile.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38#include "llvm/DerivedTypes.h" 39using namespace llvm; 40 41static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 42 CCValAssign::LocInfo &LocInfo, 43 ISD::ArgFlagsTy &ArgFlags, 44 CCState &State); 45static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT, 46 EVT &LocVT, 47 CCValAssign::LocInfo &LocInfo, 48 ISD::ArgFlagsTy &ArgFlags, 49 CCState &State); 50static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT, 51 EVT &LocVT, 52 CCValAssign::LocInfo &LocInfo, 53 ISD::ArgFlagsTy &ArgFlags, 54 CCState &State); 55 56static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", 57cl::desc("enable preincrement load/store generation on PPC (experimental)"), 58 cl::Hidden); 59 60static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) { 61 if (TM.getSubtargetImpl()->isDarwin()) 62 return new TargetLoweringObjectFileMachO(); 63 return new TargetLoweringObjectFileELF(); 64} 65 66 67PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) { 69 70 setPow2DivIsCheap(); 71 72 // Use _setjmp/_longjmp instead of setjmp/longjmp. 73 setUseUnderscoreSetJmp(true); 74 setUseUnderscoreLongJmp(true); 75 76 // Set up the register classes. 77 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 78 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 79 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 80 81 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 82 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 83 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 84 85 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 86 87 // PowerPC has pre-inc load and store's. 88 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 89 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 90 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 91 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 92 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 93 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 94 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 95 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 96 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 97 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 98 99 // This is used in the ppcf128->int sequence. Note it has different semantics 100 // from FP_ROUND: that rounds to nearest, this rounds to zero. 101 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 102 103 // PowerPC has no SREM/UREM instructions 104 setOperationAction(ISD::SREM, MVT::i32, Expand); 105 setOperationAction(ISD::UREM, MVT::i32, Expand); 106 setOperationAction(ISD::SREM, MVT::i64, Expand); 107 setOperationAction(ISD::UREM, MVT::i64, Expand); 108 109 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 110 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 111 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 112 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 113 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 114 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 115 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 116 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 117 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 118 119 // We don't support sin/cos/sqrt/fmod/pow 120 setOperationAction(ISD::FSIN , MVT::f64, Expand); 121 setOperationAction(ISD::FCOS , MVT::f64, Expand); 122 setOperationAction(ISD::FREM , MVT::f64, Expand); 123 setOperationAction(ISD::FPOW , MVT::f64, Expand); 124 setOperationAction(ISD::FSIN , MVT::f32, Expand); 125 setOperationAction(ISD::FCOS , MVT::f32, Expand); 126 setOperationAction(ISD::FREM , MVT::f32, Expand); 127 setOperationAction(ISD::FPOW , MVT::f32, Expand); 128 129 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 130 131 // If we're enabling GP optimizations, use hardware square root 132 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 133 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 134 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 135 } 136 137 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 138 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 139 140 // PowerPC does not have BSWAP, CTPOP or CTTZ 141 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 142 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 143 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 144 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 145 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 146 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 147 148 // PowerPC does not have ROTR 149 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 150 setOperationAction(ISD::ROTR, MVT::i64 , Expand); 151 152 // PowerPC does not have Select 153 setOperationAction(ISD::SELECT, MVT::i32, Expand); 154 setOperationAction(ISD::SELECT, MVT::i64, Expand); 155 setOperationAction(ISD::SELECT, MVT::f32, Expand); 156 setOperationAction(ISD::SELECT, MVT::f64, Expand); 157 158 // PowerPC wants to turn select_cc of FP into fsel when possible. 159 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 160 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 161 162 // PowerPC wants to optimize integer setcc a bit 163 setOperationAction(ISD::SETCC, MVT::i32, Custom); 164 165 // PowerPC does not have BRCOND which requires SetCC 166 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 167 168 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 169 170 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 171 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 172 173 // PowerPC does not have [U|S]INT_TO_FP 174 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 175 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 176 177 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 178 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 179 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 180 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 181 182 // We cannot sextinreg(i1). Expand to shifts. 183 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 184 185 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 186 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 187 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 188 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 189 190 191 // We want to legalize GlobalAddress and ConstantPool nodes into the 192 // appropriate instructions to materialize the address. 193 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 194 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 195 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 196 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 197 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 198 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 199 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 200 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 201 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 202 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 203 204 // TRAP is legal. 205 setOperationAction(ISD::TRAP, MVT::Other, Legal); 206 207 // TRAMPOLINE is custom lowered. 208 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 209 210 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 211 setOperationAction(ISD::VASTART , MVT::Other, Custom); 212 213 // VAARG is custom lowered with the 32-bit SVR4 ABI. 214 if ( TM.getSubtarget<PPCSubtarget>().isSVR4ABI() 215 && !TM.getSubtarget<PPCSubtarget>().isPPC64()) 216 setOperationAction(ISD::VAARG, MVT::Other, Custom); 217 else 218 setOperationAction(ISD::VAARG, MVT::Other, Expand); 219 220 // Use the default implementation. 221 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 222 setOperationAction(ISD::VAEND , MVT::Other, Expand); 223 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 224 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 225 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 226 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 227 228 // We want to custom lower some of our intrinsics. 229 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 230 231 // Comparisons that require checking two conditions. 232 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 233 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); 234 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); 235 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); 236 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); 237 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); 238 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 239 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 240 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 241 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 242 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); 243 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); 244 245 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 246 // They also have instructions for converting between i64 and fp. 247 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 248 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 249 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 250 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 251 // This is just the low 32 bits of a (signed) fp->i64 conversion. 252 // We cannot do this with Promote because i64 is not a legal type. 253 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 254 255 // FIXME: disable this lowered code. This generates 64-bit register values, 256 // and we don't model the fact that the top part is clobbered by calls. We 257 // need to flag these together so that the value isn't live across a call. 258 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 259 } else { 260 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 261 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 262 } 263 264 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 265 // 64-bit PowerPC implementations can support i64 types directly 266 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 267 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 268 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 269 // 64-bit PowerPC wants to expand i128 shifts itself. 270 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 271 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 272 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 273 } else { 274 // 32-bit PowerPC wants to expand i64 shifts itself. 275 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 276 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 277 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 278 } 279 280 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 281 // First set operation action for all vector types to expand. Then we 282 // will selectively turn on ones that can be effectively codegen'd. 283 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 284 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 285 MVT::SimpleValueType VT = (MVT::SimpleValueType)i; 286 287 // add/sub are legal for all supported vector VT's. 288 setOperationAction(ISD::ADD , VT, Legal); 289 setOperationAction(ISD::SUB , VT, Legal); 290 291 // We promote all shuffles to v16i8. 292 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 293 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 294 295 // We promote all non-typed operations to v4i32. 296 setOperationAction(ISD::AND , VT, Promote); 297 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 298 setOperationAction(ISD::OR , VT, Promote); 299 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 300 setOperationAction(ISD::XOR , VT, Promote); 301 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 302 setOperationAction(ISD::LOAD , VT, Promote); 303 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 304 setOperationAction(ISD::SELECT, VT, Promote); 305 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 306 setOperationAction(ISD::STORE, VT, Promote); 307 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 308 309 // No other operations are legal. 310 setOperationAction(ISD::MUL , VT, Expand); 311 setOperationAction(ISD::SDIV, VT, Expand); 312 setOperationAction(ISD::SREM, VT, Expand); 313 setOperationAction(ISD::UDIV, VT, Expand); 314 setOperationAction(ISD::UREM, VT, Expand); 315 setOperationAction(ISD::FDIV, VT, Expand); 316 setOperationAction(ISD::FNEG, VT, Expand); 317 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); 318 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 319 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); 320 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 321 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 322 setOperationAction(ISD::UDIVREM, VT, Expand); 323 setOperationAction(ISD::SDIVREM, VT, Expand); 324 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); 325 setOperationAction(ISD::FPOW, VT, Expand); 326 setOperationAction(ISD::CTPOP, VT, Expand); 327 setOperationAction(ISD::CTLZ, VT, Expand); 328 setOperationAction(ISD::CTTZ, VT, Expand); 329 } 330 331 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 332 // with merges, splats, etc. 333 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 334 335 setOperationAction(ISD::AND , MVT::v4i32, Legal); 336 setOperationAction(ISD::OR , MVT::v4i32, Legal); 337 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 338 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 339 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 340 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 341 342 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 343 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 344 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 345 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 346 347 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 348 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 349 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 350 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 351 352 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 353 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 354 355 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 356 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 357 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 358 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 359 } 360 361 setShiftAmountType(MVT::i32); 362 setBooleanContents(ZeroOrOneBooleanContent); 363 364 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 365 setStackPointerRegisterToSaveRestore(PPC::X1); 366 setExceptionPointerRegister(PPC::X3); 367 setExceptionSelectorRegister(PPC::X4); 368 } else { 369 setStackPointerRegisterToSaveRestore(PPC::R1); 370 setExceptionPointerRegister(PPC::R3); 371 setExceptionSelectorRegister(PPC::R4); 372 } 373 374 // We have target-specific dag combine patterns for the following nodes: 375 setTargetDAGCombine(ISD::SINT_TO_FP); 376 setTargetDAGCombine(ISD::STORE); 377 setTargetDAGCombine(ISD::BR_CC); 378 setTargetDAGCombine(ISD::BSWAP); 379 380 // Darwin long double math library functions have $LDBL128 appended. 381 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) { 382 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 383 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 384 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 385 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 386 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 387 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128"); 388 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128"); 389 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128"); 390 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128"); 391 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128"); 392 } 393 394 computeRegisterProperties(); 395} 396 397/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 398/// function arguments in the caller parameter area. 399unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const { 400 TargetMachine &TM = getTargetMachine(); 401 // Darwin passes everything on 4 byte boundary. 402 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) 403 return 4; 404 // FIXME SVR4 TBD 405 return 4; 406} 407 408const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 409 switch (Opcode) { 410 default: return 0; 411 case PPCISD::FSEL: return "PPCISD::FSEL"; 412 case PPCISD::FCFID: return "PPCISD::FCFID"; 413 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 414 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 415 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 416 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 417 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 418 case PPCISD::VPERM: return "PPCISD::VPERM"; 419 case PPCISD::Hi: return "PPCISD::Hi"; 420 case PPCISD::Lo: return "PPCISD::Lo"; 421 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY"; 422 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE"; 423 case PPCISD::LOAD: return "PPCISD::LOAD"; 424 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC"; 425 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 426 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 427 case PPCISD::SRL: return "PPCISD::SRL"; 428 case PPCISD::SRA: return "PPCISD::SRA"; 429 case PPCISD::SHL: return "PPCISD::SHL"; 430 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 431 case PPCISD::STD_32: return "PPCISD::STD_32"; 432 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4"; 433 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin"; 434 case PPCISD::NOP: return "PPCISD::NOP"; 435 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 436 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin"; 437 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4"; 438 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 439 case PPCISD::MFCR: return "PPCISD::MFCR"; 440 case PPCISD::VCMP: return "PPCISD::VCMP"; 441 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 442 case PPCISD::LBRX: return "PPCISD::LBRX"; 443 case PPCISD::STBRX: return "PPCISD::STBRX"; 444 case PPCISD::LARX: return "PPCISD::LARX"; 445 case PPCISD::STCX: return "PPCISD::STCX"; 446 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 447 case PPCISD::MFFS: return "PPCISD::MFFS"; 448 case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; 449 case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; 450 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 451 case PPCISD::MTFSF: return "PPCISD::MTFSF"; 452 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; 453 } 454} 455 456MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const { 457 return MVT::i32; 458} 459 460/// getFunctionAlignment - Return the Log2 alignment of this function. 461unsigned PPCTargetLowering::getFunctionAlignment(const Function *F) const { 462 if (getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) 463 return F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4; 464 else 465 return 2; 466} 467 468//===----------------------------------------------------------------------===// 469// Node matching predicates, for use by the tblgen matching code. 470//===----------------------------------------------------------------------===// 471 472/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 473static bool isFloatingPointZero(SDValue Op) { 474 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 475 return CFP->getValueAPF().isZero(); 476 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 477 // Maybe this has already been legalized into the constant pool? 478 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 479 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 480 return CFP->getValueAPF().isZero(); 481 } 482 return false; 483} 484 485/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 486/// true if Op is undef or if it matches the specified value. 487static bool isConstantOrUndef(int Op, int Val) { 488 return Op < 0 || Op == Val; 489} 490 491/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 492/// VPKUHUM instruction. 493bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 494 if (!isUnary) { 495 for (unsigned i = 0; i != 16; ++i) 496 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1)) 497 return false; 498 } else { 499 for (unsigned i = 0; i != 8; ++i) 500 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) || 501 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1)) 502 return false; 503 } 504 return true; 505} 506 507/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 508/// VPKUWUM instruction. 509bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 510 if (!isUnary) { 511 for (unsigned i = 0; i != 16; i += 2) 512 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 513 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3)) 514 return false; 515 } else { 516 for (unsigned i = 0; i != 8; i += 2) 517 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 518 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) || 519 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) || 520 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3)) 521 return false; 522 } 523 return true; 524} 525 526/// isVMerge - Common function, used to match vmrg* shuffles. 527/// 528static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, 529 unsigned LHSStart, unsigned RHSStart) { 530 assert(N->getValueType(0) == MVT::v16i8 && 531 "PPC only supports shuffles by bytes!"); 532 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 533 "Unsupported merge size!"); 534 535 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 536 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 537 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j), 538 LHSStart+j+i*UnitSize) || 539 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j), 540 RHSStart+j+i*UnitSize)) 541 return false; 542 } 543 return true; 544} 545 546/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 547/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 548bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 549 bool isUnary) { 550 if (!isUnary) 551 return isVMerge(N, UnitSize, 8, 24); 552 return isVMerge(N, UnitSize, 8, 8); 553} 554 555/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 556/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 557bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 558 bool isUnary) { 559 if (!isUnary) 560 return isVMerge(N, UnitSize, 0, 16); 561 return isVMerge(N, UnitSize, 0, 0); 562} 563 564 565/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 566/// amount, otherwise return -1. 567int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 568 assert(N->getValueType(0) == MVT::v16i8 && 569 "PPC only supports shuffles by bytes!"); 570 571 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 572 573 // Find the first non-undef value in the shuffle mask. 574 unsigned i; 575 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i) 576 /*search*/; 577 578 if (i == 16) return -1; // all undef. 579 580 // Otherwise, check to see if the rest of the elements are consecutively 581 // numbered from this value. 582 unsigned ShiftAmt = SVOp->getMaskElt(i); 583 if (ShiftAmt < i) return -1; 584 ShiftAmt -= i; 585 586 if (!isUnary) { 587 // Check the rest of the elements to see if they are consecutive. 588 for (++i; i != 16; ++i) 589 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) 590 return -1; 591 } else { 592 // Check the rest of the elements to see if they are consecutive. 593 for (++i; i != 16; ++i) 594 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) 595 return -1; 596 } 597 return ShiftAmt; 598} 599 600/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 601/// specifies a splat of a single element that is suitable for input to 602/// VSPLTB/VSPLTH/VSPLTW. 603bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { 604 assert(N->getValueType(0) == MVT::v16i8 && 605 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 606 607 // This is a splat operation if each element of the permute is the same, and 608 // if the value doesn't reference the second vector. 609 unsigned ElementBase = N->getMaskElt(0); 610 611 // FIXME: Handle UNDEF elements too! 612 if (ElementBase >= 16) 613 return false; 614 615 // Check that the indices are consecutive, in the case of a multi-byte element 616 // splatted with a v16i8 mask. 617 for (unsigned i = 1; i != EltSize; ++i) 618 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase)) 619 return false; 620 621 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 622 if (N->getMaskElt(i) < 0) continue; 623 for (unsigned j = 0; j != EltSize; ++j) 624 if (N->getMaskElt(i+j) != N->getMaskElt(j)) 625 return false; 626 } 627 return true; 628} 629 630/// isAllNegativeZeroVector - Returns true if all elements of build_vector 631/// are -0.0. 632bool PPC::isAllNegativeZeroVector(SDNode *N) { 633 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N); 634 635 APInt APVal, APUndef; 636 unsigned BitSize; 637 bool HasAnyUndefs; 638 639 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true)) 640 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 641 return CFP->getValueAPF().isNegZero(); 642 643 return false; 644} 645 646/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 647/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 648unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 649 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 650 assert(isSplatShuffleMask(SVOp, EltSize)); 651 return SVOp->getMaskElt(0) / EltSize; 652} 653 654/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 655/// by using a vspltis[bhw] instruction of the specified element size, return 656/// the constant being splatted. The ByteSize field indicates the number of 657/// bytes of each element [124] -> [bhw]. 658SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 659 SDValue OpVal(0, 0); 660 661 // If ByteSize of the splat is bigger than the element size of the 662 // build_vector, then we have a case where we are checking for a splat where 663 // multiple elements of the buildvector are folded together into a single 664 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 665 unsigned EltSize = 16/N->getNumOperands(); 666 if (EltSize < ByteSize) { 667 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 668 SDValue UniquedVals[4]; 669 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 670 671 // See if all of the elements in the buildvector agree across. 672 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 673 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 674 // If the element isn't a constant, bail fully out. 675 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue(); 676 677 678 if (UniquedVals[i&(Multiple-1)].getNode() == 0) 679 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 680 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 681 return SDValue(); // no match. 682 } 683 684 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 685 // either constant or undef values that are identical for each chunk. See 686 // if these chunks can form into a larger vspltis*. 687 688 // Check to see if all of the leading entries are either 0 or -1. If 689 // neither, then this won't fit into the immediate field. 690 bool LeadingZero = true; 691 bool LeadingOnes = true; 692 for (unsigned i = 0; i != Multiple-1; ++i) { 693 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs. 694 695 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 696 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 697 } 698 // Finally, check the least significant entry. 699 if (LeadingZero) { 700 if (UniquedVals[Multiple-1].getNode() == 0) 701 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 702 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue(); 703 if (Val < 16) 704 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 705 } 706 if (LeadingOnes) { 707 if (UniquedVals[Multiple-1].getNode() == 0) 708 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 709 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue(); 710 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 711 return DAG.getTargetConstant(Val, MVT::i32); 712 } 713 714 return SDValue(); 715 } 716 717 // Check to see if this buildvec has a single non-undef value in its elements. 718 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 719 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 720 if (OpVal.getNode() == 0) 721 OpVal = N->getOperand(i); 722 else if (OpVal != N->getOperand(i)) 723 return SDValue(); 724 } 725 726 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def. 727 728 unsigned ValSizeInBytes = EltSize; 729 uint64_t Value = 0; 730 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 731 Value = CN->getZExtValue(); 732 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 733 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 734 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 735 } 736 737 // If the splat value is larger than the element value, then we can never do 738 // this splat. The only case that we could fit the replicated bits into our 739 // immediate field for would be zero, and we prefer to use vxor for it. 740 if (ValSizeInBytes < ByteSize) return SDValue(); 741 742 // If the element value is larger than the splat value, cut it in half and 743 // check to see if the two halves are equal. Continue doing this until we 744 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 745 while (ValSizeInBytes > ByteSize) { 746 ValSizeInBytes >>= 1; 747 748 // If the top half equals the bottom half, we're still ok. 749 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 750 (Value & ((1 << (8*ValSizeInBytes))-1))) 751 return SDValue(); 752 } 753 754 // Properly sign extend the value. 755 int ShAmt = (4-ByteSize)*8; 756 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 757 758 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 759 if (MaskVal == 0) return SDValue(); 760 761 // Finally, if this value fits in a 5 bit sext field, return it 762 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 763 return DAG.getTargetConstant(MaskVal, MVT::i32); 764 return SDValue(); 765} 766 767//===----------------------------------------------------------------------===// 768// Addressing Mode Selection 769//===----------------------------------------------------------------------===// 770 771/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 772/// or 64-bit immediate, and if the value can be accurately represented as a 773/// sign extension from a 16-bit value. If so, this returns true and the 774/// immediate. 775static bool isIntS16Immediate(SDNode *N, short &Imm) { 776 if (N->getOpcode() != ISD::Constant) 777 return false; 778 779 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 780 if (N->getValueType(0) == MVT::i32) 781 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 782 else 783 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 784} 785static bool isIntS16Immediate(SDValue Op, short &Imm) { 786 return isIntS16Immediate(Op.getNode(), Imm); 787} 788 789 790/// SelectAddressRegReg - Given the specified addressed, check to see if it 791/// can be represented as an indexed [r+r] operation. Returns false if it 792/// can be more efficiently represented with [r+imm]. 793bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, 794 SDValue &Index, 795 SelectionDAG &DAG) const { 796 short imm = 0; 797 if (N.getOpcode() == ISD::ADD) { 798 if (isIntS16Immediate(N.getOperand(1), imm)) 799 return false; // r+i 800 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 801 return false; // r+i 802 803 Base = N.getOperand(0); 804 Index = N.getOperand(1); 805 return true; 806 } else if (N.getOpcode() == ISD::OR) { 807 if (isIntS16Immediate(N.getOperand(1), imm)) 808 return false; // r+i can fold it if we can. 809 810 // If this is an or of disjoint bitfields, we can codegen this as an add 811 // (for better address arithmetic) if the LHS and RHS of the OR are provably 812 // disjoint. 813 APInt LHSKnownZero, LHSKnownOne; 814 APInt RHSKnownZero, RHSKnownOne; 815 DAG.ComputeMaskedBits(N.getOperand(0), 816 APInt::getAllOnesValue(N.getOperand(0) 817 .getValueSizeInBits()), 818 LHSKnownZero, LHSKnownOne); 819 820 if (LHSKnownZero.getBoolValue()) { 821 DAG.ComputeMaskedBits(N.getOperand(1), 822 APInt::getAllOnesValue(N.getOperand(1) 823 .getValueSizeInBits()), 824 RHSKnownZero, RHSKnownOne); 825 // If all of the bits are known zero on the LHS or RHS, the add won't 826 // carry. 827 if (~(LHSKnownZero | RHSKnownZero) == 0) { 828 Base = N.getOperand(0); 829 Index = N.getOperand(1); 830 return true; 831 } 832 } 833 } 834 835 return false; 836} 837 838/// Returns true if the address N can be represented by a base register plus 839/// a signed 16-bit displacement [r+imm], and if it is not better 840/// represented as reg+reg. 841bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, 842 SDValue &Base, 843 SelectionDAG &DAG) const { 844 // FIXME dl should come from parent load or store, not from address 845 DebugLoc dl = N.getDebugLoc(); 846 // If this can be more profitably realized as r+r, fail. 847 if (SelectAddressRegReg(N, Disp, Base, DAG)) 848 return false; 849 850 if (N.getOpcode() == ISD::ADD) { 851 short imm = 0; 852 if (isIntS16Immediate(N.getOperand(1), imm)) { 853 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 854 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 855 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 856 } else { 857 Base = N.getOperand(0); 858 } 859 return true; // [r+i] 860 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 861 // Match LOAD (ADD (X, Lo(G))). 862 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 863 && "Cannot handle constant offsets yet!"); 864 Disp = N.getOperand(1).getOperand(0); // The global address. 865 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 866 Disp.getOpcode() == ISD::TargetConstantPool || 867 Disp.getOpcode() == ISD::TargetJumpTable); 868 Base = N.getOperand(0); 869 return true; // [&g+r] 870 } 871 } else if (N.getOpcode() == ISD::OR) { 872 short imm = 0; 873 if (isIntS16Immediate(N.getOperand(1), imm)) { 874 // If this is an or of disjoint bitfields, we can codegen this as an add 875 // (for better address arithmetic) if the LHS and RHS of the OR are 876 // provably disjoint. 877 APInt LHSKnownZero, LHSKnownOne; 878 DAG.ComputeMaskedBits(N.getOperand(0), 879 APInt::getAllOnesValue(N.getOperand(0) 880 .getValueSizeInBits()), 881 LHSKnownZero, LHSKnownOne); 882 883 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 884 // If all of the bits are known zero on the LHS or RHS, the add won't 885 // carry. 886 Base = N.getOperand(0); 887 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 888 return true; 889 } 890 } 891 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 892 // Loading from a constant address. 893 894 // If this address fits entirely in a 16-bit sext immediate field, codegen 895 // this as "d, 0" 896 short Imm; 897 if (isIntS16Immediate(CN, Imm)) { 898 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 899 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 900 return true; 901 } 902 903 // Handle 32-bit sext immediates with LIS + addr mode. 904 if (CN->getValueType(0) == MVT::i32 || 905 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 906 int Addr = (int)CN->getZExtValue(); 907 908 // Otherwise, break this down into an LIS + disp. 909 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 910 911 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 912 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 913 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); 914 return true; 915 } 916 } 917 918 Disp = DAG.getTargetConstant(0, getPointerTy()); 919 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 920 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 921 else 922 Base = N; 923 return true; // [r+0] 924} 925 926/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 927/// represented as an indexed [r+r] operation. 928bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, 929 SDValue &Index, 930 SelectionDAG &DAG) const { 931 // Check to see if we can easily represent this as an [r+r] address. This 932 // will fail if it thinks that the address is more profitably represented as 933 // reg+imm, e.g. where imm = 0. 934 if (SelectAddressRegReg(N, Base, Index, DAG)) 935 return true; 936 937 // If the operand is an addition, always emit this as [r+r], since this is 938 // better (for code size, and execution, as the memop does the add for free) 939 // than emitting an explicit add. 940 if (N.getOpcode() == ISD::ADD) { 941 Base = N.getOperand(0); 942 Index = N.getOperand(1); 943 return true; 944 } 945 946 // Otherwise, do it the hard way, using R0 as the base register. 947 Base = DAG.getRegister(PPC::R0, N.getValueType()); 948 Index = N; 949 return true; 950} 951 952/// SelectAddressRegImmShift - Returns true if the address N can be 953/// represented by a base register plus a signed 14-bit displacement 954/// [r+imm*4]. Suitable for use by STD and friends. 955bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, 956 SDValue &Base, 957 SelectionDAG &DAG) const { 958 // FIXME dl should come from the parent load or store, not the address 959 DebugLoc dl = N.getDebugLoc(); 960 // If this can be more profitably realized as r+r, fail. 961 if (SelectAddressRegReg(N, Disp, Base, DAG)) 962 return false; 963 964 if (N.getOpcode() == ISD::ADD) { 965 short imm = 0; 966 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 967 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 968 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 969 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 970 } else { 971 Base = N.getOperand(0); 972 } 973 return true; // [r+i] 974 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 975 // Match LOAD (ADD (X, Lo(G))). 976 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 977 && "Cannot handle constant offsets yet!"); 978 Disp = N.getOperand(1).getOperand(0); // The global address. 979 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 980 Disp.getOpcode() == ISD::TargetConstantPool || 981 Disp.getOpcode() == ISD::TargetJumpTable); 982 Base = N.getOperand(0); 983 return true; // [&g+r] 984 } 985 } else if (N.getOpcode() == ISD::OR) { 986 short imm = 0; 987 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 988 // If this is an or of disjoint bitfields, we can codegen this as an add 989 // (for better address arithmetic) if the LHS and RHS of the OR are 990 // provably disjoint. 991 APInt LHSKnownZero, LHSKnownOne; 992 DAG.ComputeMaskedBits(N.getOperand(0), 993 APInt::getAllOnesValue(N.getOperand(0) 994 .getValueSizeInBits()), 995 LHSKnownZero, LHSKnownOne); 996 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 997 // If all of the bits are known zero on the LHS or RHS, the add won't 998 // carry. 999 Base = N.getOperand(0); 1000 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 1001 return true; 1002 } 1003 } 1004 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 1005 // Loading from a constant address. Verify low two bits are clear. 1006 if ((CN->getZExtValue() & 3) == 0) { 1007 // If this address fits entirely in a 14-bit sext immediate field, codegen 1008 // this as "d, 0" 1009 short Imm; 1010 if (isIntS16Immediate(CN, Imm)) { 1011 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 1012 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 1013 return true; 1014 } 1015 1016 // Fold the low-part of 32-bit absolute addresses into addr mode. 1017 if (CN->getValueType(0) == MVT::i32 || 1018 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 1019 int Addr = (int)CN->getZExtValue(); 1020 1021 // Otherwise, break this down into an LIS + disp. 1022 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 1023 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 1024 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1025 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0); 1026 return true; 1027 } 1028 } 1029 } 1030 1031 Disp = DAG.getTargetConstant(0, getPointerTy()); 1032 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1033 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1034 else 1035 Base = N; 1036 return true; // [r+0] 1037} 1038 1039 1040/// getPreIndexedAddressParts - returns true by value, base pointer and 1041/// offset pointer and addressing mode by reference if the node's address 1042/// can be legally represented as pre-indexed load / store address. 1043bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1044 SDValue &Offset, 1045 ISD::MemIndexedMode &AM, 1046 SelectionDAG &DAG) const { 1047 // Disabled by default for now. 1048 if (!EnablePPCPreinc) return false; 1049 1050 SDValue Ptr; 1051 EVT VT; 1052 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1053 Ptr = LD->getBasePtr(); 1054 VT = LD->getMemoryVT(); 1055 1056 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1057 ST = ST; 1058 Ptr = ST->getBasePtr(); 1059 VT = ST->getMemoryVT(); 1060 } else 1061 return false; 1062 1063 // PowerPC doesn't have preinc load/store instructions for vectors. 1064 if (VT.isVector()) 1065 return false; 1066 1067 // TODO: Check reg+reg first. 1068 1069 // LDU/STU use reg+imm*4, others use reg+imm. 1070 if (VT != MVT::i64) { 1071 // reg + imm 1072 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 1073 return false; 1074 } else { 1075 // reg + imm * 4. 1076 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 1077 return false; 1078 } 1079 1080 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1081 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 1082 // sext i32 to i64 when addr mode is r+i. 1083 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 1084 LD->getExtensionType() == ISD::SEXTLOAD && 1085 isa<ConstantSDNode>(Offset)) 1086 return false; 1087 } 1088 1089 AM = ISD::PRE_INC; 1090 return true; 1091} 1092 1093//===----------------------------------------------------------------------===// 1094// LowerOperation implementation 1095//===----------------------------------------------------------------------===// 1096 1097SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, 1098 SelectionDAG &DAG) { 1099 EVT PtrVT = Op.getValueType(); 1100 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1101 Constant *C = CP->getConstVal(); 1102 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 1103 SDValue Zero = DAG.getConstant(0, PtrVT); 1104 // FIXME there isn't really any debug info here 1105 DebugLoc dl = Op.getDebugLoc(); 1106 1107 const TargetMachine &TM = DAG.getTarget(); 1108 1109 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero); 1110 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero); 1111 1112 // If this is a non-darwin platform, we don't support non-static relo models 1113 // yet. 1114 if (TM.getRelocationModel() == Reloc::Static || 1115 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1116 // Generate non-pic code that has direct accesses to the constant pool. 1117 // The address of the global is just (hi(&g)+lo(&g)). 1118 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1119 } 1120 1121 if (TM.getRelocationModel() == Reloc::PIC_) { 1122 // With PIC, the first instruction is actually "GR+hi(&G)". 1123 Hi = DAG.getNode(ISD::ADD, dl, PtrVT, 1124 DAG.getNode(PPCISD::GlobalBaseReg, 1125 DebugLoc::getUnknownLoc(), PtrVT), Hi); 1126 } 1127 1128 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1129 return Lo; 1130} 1131 1132SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { 1133 EVT PtrVT = Op.getValueType(); 1134 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1135 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1136 SDValue Zero = DAG.getConstant(0, PtrVT); 1137 // FIXME there isn't really any debug loc here 1138 DebugLoc dl = Op.getDebugLoc(); 1139 1140 const TargetMachine &TM = DAG.getTarget(); 1141 1142 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero); 1143 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, JTI, Zero); 1144 1145 // If this is a non-darwin platform, we don't support non-static relo models 1146 // yet. 1147 if (TM.getRelocationModel() == Reloc::Static || 1148 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1149 // Generate non-pic code that has direct accesses to the constant pool. 1150 // The address of the global is just (hi(&g)+lo(&g)). 1151 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1152 } 1153 1154 if (TM.getRelocationModel() == Reloc::PIC_) { 1155 // With PIC, the first instruction is actually "GR+hi(&G)". 1156 Hi = DAG.getNode(ISD::ADD, dl, PtrVT, 1157 DAG.getNode(PPCISD::GlobalBaseReg, 1158 DebugLoc::getUnknownLoc(), PtrVT), Hi); 1159 } 1160 1161 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1162 return Lo; 1163} 1164 1165SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, 1166 SelectionDAG &DAG) { 1167 llvm_unreachable("TLS not implemented for PPC."); 1168 return SDValue(); // Not reached 1169} 1170 1171SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) { 1172 EVT PtrVT = Op.getValueType(); 1173 DebugLoc DL = Op.getDebugLoc(); 1174 1175 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1176 SDValue TgtBA = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true); 1177 SDValue Zero = DAG.getConstant(0, PtrVT); 1178 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, TgtBA, Zero); 1179 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, TgtBA, Zero); 1180 1181 // If this is a non-darwin platform, we don't support non-static relo models 1182 // yet. 1183 const TargetMachine &TM = DAG.getTarget(); 1184 if (TM.getRelocationModel() == Reloc::Static || 1185 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1186 // Generate non-pic code that has direct accesses to globals. 1187 // The address of the global is just (hi(&g)+lo(&g)). 1188 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1189 } 1190 1191 if (TM.getRelocationModel() == Reloc::PIC_) { 1192 // With PIC, the first instruction is actually "GR+hi(&G)". 1193 Hi = DAG.getNode(ISD::ADD, DL, PtrVT, 1194 DAG.getNode(PPCISD::GlobalBaseReg, 1195 DebugLoc::getUnknownLoc(), PtrVT), Hi); 1196 } 1197 1198 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1199} 1200 1201SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, 1202 SelectionDAG &DAG) { 1203 EVT PtrVT = Op.getValueType(); 1204 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1205 GlobalValue *GV = GSDN->getGlobal(); 1206 SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); 1207 SDValue Zero = DAG.getConstant(0, PtrVT); 1208 // FIXME there isn't really any debug info here 1209 DebugLoc dl = GSDN->getDebugLoc(); 1210 1211 const TargetMachine &TM = DAG.getTarget(); 1212 1213 // 64-bit SVR4 ABI code is always position-independent. 1214 // The actual address of the GlobalValue is stored in the TOC. 1215 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1216 return DAG.getNode(PPCISD::TOC_ENTRY, dl, MVT::i64, GA, 1217 DAG.getRegister(PPC::X2, MVT::i64)); 1218 } 1219 1220 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero); 1221 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero); 1222 1223 // If this is a non-darwin platform, we don't support non-static relo models 1224 // yet. 1225 if (TM.getRelocationModel() == Reloc::Static || 1226 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1227 // Generate non-pic code that has direct accesses to globals. 1228 // The address of the global is just (hi(&g)+lo(&g)). 1229 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1230 } 1231 1232 if (TM.getRelocationModel() == Reloc::PIC_) { 1233 // With PIC, the first instruction is actually "GR+hi(&G)". 1234 Hi = DAG.getNode(ISD::ADD, dl, PtrVT, 1235 DAG.getNode(PPCISD::GlobalBaseReg, 1236 DebugLoc::getUnknownLoc(), PtrVT), Hi); 1237 } 1238 1239 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1240 1241 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) 1242 return Lo; 1243 1244 // If the global is weak or external, we have to go through the lazy 1245 // resolution stub. 1246 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0); 1247} 1248 1249SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { 1250 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1251 DebugLoc dl = Op.getDebugLoc(); 1252 1253 // If we're comparing for equality to zero, expose the fact that this is 1254 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1255 // fold the new nodes. 1256 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1257 if (C->isNullValue() && CC == ISD::SETEQ) { 1258 EVT VT = Op.getOperand(0).getValueType(); 1259 SDValue Zext = Op.getOperand(0); 1260 if (VT.bitsLT(MVT::i32)) { 1261 VT = MVT::i32; 1262 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); 1263 } 1264 unsigned Log2b = Log2_32(VT.getSizeInBits()); 1265 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); 1266 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, 1267 DAG.getConstant(Log2b, MVT::i32)); 1268 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); 1269 } 1270 // Leave comparisons against 0 and -1 alone for now, since they're usually 1271 // optimized. FIXME: revisit this when we can custom lower all setcc 1272 // optimizations. 1273 if (C->isAllOnesValue() || C->isNullValue()) 1274 return SDValue(); 1275 } 1276 1277 // If we have an integer seteq/setne, turn it into a compare against zero 1278 // by xor'ing the rhs with the lhs, which is faster than setting a 1279 // condition register, reading it back out, and masking the correct bit. The 1280 // normal approach here uses sub to do this instead of xor. Using xor exposes 1281 // the result to other bit-twiddling opportunities. 1282 EVT LHSVT = Op.getOperand(0).getValueType(); 1283 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1284 EVT VT = Op.getValueType(); 1285 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), 1286 Op.getOperand(1)); 1287 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); 1288 } 1289 return SDValue(); 1290} 1291 1292SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, 1293 int VarArgsFrameIndex, 1294 int VarArgsStackOffset, 1295 unsigned VarArgsNumGPR, 1296 unsigned VarArgsNumFPR, 1297 const PPCSubtarget &Subtarget) { 1298 1299 llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!"); 1300 return SDValue(); // Not reached 1301} 1302 1303SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) { 1304 SDValue Chain = Op.getOperand(0); 1305 SDValue Trmp = Op.getOperand(1); // trampoline 1306 SDValue FPtr = Op.getOperand(2); // nested function 1307 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 1308 DebugLoc dl = Op.getDebugLoc(); 1309 1310 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1311 bool isPPC64 = (PtrVT == MVT::i64); 1312 const Type *IntPtrTy = 1313 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType( 1314 *DAG.getContext()); 1315 1316 TargetLowering::ArgListTy Args; 1317 TargetLowering::ArgListEntry Entry; 1318 1319 Entry.Ty = IntPtrTy; 1320 Entry.Node = Trmp; Args.push_back(Entry); 1321 1322 // TrampSize == (isPPC64 ? 48 : 40); 1323 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, 1324 isPPC64 ? MVT::i64 : MVT::i32); 1325 Args.push_back(Entry); 1326 1327 Entry.Node = FPtr; Args.push_back(Entry); 1328 Entry.Node = Nest; Args.push_back(Entry); 1329 1330 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) 1331 std::pair<SDValue, SDValue> CallResult = 1332 LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()), 1333 false, false, false, false, 0, CallingConv::C, false, 1334 /*isReturnValueUsed=*/true, 1335 DAG.getExternalSymbol("__trampoline_setup", PtrVT), 1336 Args, DAG, dl, DAG.GetOrdering(Chain.getNode())); 1337 1338 SDValue Ops[] = 1339 { CallResult.first, CallResult.second }; 1340 1341 return DAG.getMergeValues(Ops, 2, dl); 1342} 1343 1344SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, 1345 int VarArgsFrameIndex, 1346 int VarArgsStackOffset, 1347 unsigned VarArgsNumGPR, 1348 unsigned VarArgsNumFPR, 1349 const PPCSubtarget &Subtarget) { 1350 DebugLoc dl = Op.getDebugLoc(); 1351 1352 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) { 1353 // vastart just stores the address of the VarArgsFrameIndex slot into the 1354 // memory location argument. 1355 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1356 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1357 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1358 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); 1359 } 1360 1361 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct. 1362 // We suppose the given va_list is already allocated. 1363 // 1364 // typedef struct { 1365 // char gpr; /* index into the array of 8 GPRs 1366 // * stored in the register save area 1367 // * gpr=0 corresponds to r3, 1368 // * gpr=1 to r4, etc. 1369 // */ 1370 // char fpr; /* index into the array of 8 FPRs 1371 // * stored in the register save area 1372 // * fpr=0 corresponds to f1, 1373 // * fpr=1 to f2, etc. 1374 // */ 1375 // char *overflow_arg_area; 1376 // /* location on stack that holds 1377 // * the next overflow argument 1378 // */ 1379 // char *reg_save_area; 1380 // /* where r3:r10 and f1:f8 (if saved) 1381 // * are stored 1382 // */ 1383 // } va_list[1]; 1384 1385 1386 SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i32); 1387 SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i32); 1388 1389 1390 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1391 1392 SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); 1393 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1394 1395 uint64_t FrameOffset = PtrVT.getSizeInBits()/8; 1396 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1397 1398 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; 1399 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1400 1401 uint64_t FPROffset = 1; 1402 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1403 1404 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1405 1406 // Store first byte : number of int regs 1407 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, 1408 Op.getOperand(1), SV, 0, MVT::i8); 1409 uint64_t nextOffset = FPROffset; 1410 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), 1411 ConstFPROffset); 1412 1413 // Store second byte : number of float regs 1414 SDValue secondStore = 1415 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset, MVT::i8); 1416 nextOffset += StackOffset; 1417 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); 1418 1419 // Store second word : arguments given on stack 1420 SDValue thirdStore = 1421 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset); 1422 nextOffset += FrameOffset; 1423 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset); 1424 1425 // Store third word : arguments given in registers 1426 return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset); 1427 1428} 1429 1430#include "PPCGenCallingConv.inc" 1431 1432static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 1433 CCValAssign::LocInfo &LocInfo, 1434 ISD::ArgFlagsTy &ArgFlags, 1435 CCState &State) { 1436 return true; 1437} 1438 1439static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT, 1440 EVT &LocVT, 1441 CCValAssign::LocInfo &LocInfo, 1442 ISD::ArgFlagsTy &ArgFlags, 1443 CCState &State) { 1444 static const unsigned ArgRegs[] = { 1445 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1446 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1447 }; 1448 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1449 1450 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1451 1452 // Skip one register if the first unallocated register has an even register 1453 // number and there are still argument registers available which have not been 1454 // allocated yet. RegNum is actually an index into ArgRegs, which means we 1455 // need to skip a register if RegNum is odd. 1456 if (RegNum != NumArgRegs && RegNum % 2 == 1) { 1457 State.AllocateReg(ArgRegs[RegNum]); 1458 } 1459 1460 // Always return false here, as this function only makes sure that the first 1461 // unallocated register has an odd register number and does not actually 1462 // allocate a register for the current argument. 1463 return false; 1464} 1465 1466static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT, 1467 EVT &LocVT, 1468 CCValAssign::LocInfo &LocInfo, 1469 ISD::ArgFlagsTy &ArgFlags, 1470 CCState &State) { 1471 static const unsigned ArgRegs[] = { 1472 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1473 PPC::F8 1474 }; 1475 1476 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1477 1478 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1479 1480 // If there is only one Floating-point register left we need to put both f64 1481 // values of a split ppc_fp128 value on the stack. 1482 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { 1483 State.AllocateReg(ArgRegs[RegNum]); 1484 } 1485 1486 // Always return false here, as this function only makes sure that the two f64 1487 // values a ppc_fp128 value is split into are both passed in registers or both 1488 // passed on the stack and does not actually allocate a register for the 1489 // current argument. 1490 return false; 1491} 1492 1493/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1494/// on Darwin. 1495static const unsigned *GetFPR() { 1496 static const unsigned FPR[] = { 1497 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1498 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1499 }; 1500 1501 return FPR; 1502} 1503 1504/// CalculateStackSlotSize - Calculates the size reserved for this argument on 1505/// the stack. 1506static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, 1507 unsigned PtrByteSize) { 1508 unsigned ArgSize = ArgVT.getSizeInBits()/8; 1509 if (Flags.isByVal()) 1510 ArgSize = Flags.getByValSize(); 1511 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1512 1513 return ArgSize; 1514} 1515 1516SDValue 1517PPCTargetLowering::LowerFormalArguments(SDValue Chain, 1518 CallingConv::ID CallConv, bool isVarArg, 1519 const SmallVectorImpl<ISD::InputArg> 1520 &Ins, 1521 DebugLoc dl, SelectionDAG &DAG, 1522 SmallVectorImpl<SDValue> &InVals) { 1523 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) { 1524 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins, 1525 dl, DAG, InVals); 1526 } else { 1527 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, 1528 dl, DAG, InVals); 1529 } 1530} 1531 1532SDValue 1533PPCTargetLowering::LowerFormalArguments_SVR4( 1534 SDValue Chain, 1535 CallingConv::ID CallConv, bool isVarArg, 1536 const SmallVectorImpl<ISD::InputArg> 1537 &Ins, 1538 DebugLoc dl, SelectionDAG &DAG, 1539 SmallVectorImpl<SDValue> &InVals) { 1540 1541 // 32-bit SVR4 ABI Stack Frame Layout: 1542 // +-----------------------------------+ 1543 // +--> | Back chain | 1544 // | +-----------------------------------+ 1545 // | | Floating-point register save area | 1546 // | +-----------------------------------+ 1547 // | | General register save area | 1548 // | +-----------------------------------+ 1549 // | | CR save word | 1550 // | +-----------------------------------+ 1551 // | | VRSAVE save word | 1552 // | +-----------------------------------+ 1553 // | | Alignment padding | 1554 // | +-----------------------------------+ 1555 // | | Vector register save area | 1556 // | +-----------------------------------+ 1557 // | | Local variable space | 1558 // | +-----------------------------------+ 1559 // | | Parameter list area | 1560 // | +-----------------------------------+ 1561 // | | LR save word | 1562 // | +-----------------------------------+ 1563 // SP--> +--- | Back chain | 1564 // +-----------------------------------+ 1565 // 1566 // Specifications: 1567 // System V Application Binary Interface PowerPC Processor Supplement 1568 // AltiVec Technology Programming Interface Manual 1569 1570 MachineFunction &MF = DAG.getMachineFunction(); 1571 MachineFrameInfo *MFI = MF.getFrameInfo(); 1572 1573 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1574 // Potential tail calls could cause overwriting of argument stack slots. 1575 bool isImmutable = !(PerformTailCallOpt && (CallConv==CallingConv::Fast)); 1576 unsigned PtrByteSize = 4; 1577 1578 // Assign locations to all of the incoming arguments. 1579 SmallVector<CCValAssign, 16> ArgLocs; 1580 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, 1581 *DAG.getContext()); 1582 1583 // Reserve space for the linkage area on the stack. 1584 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize); 1585 1586 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4); 1587 1588 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1589 CCValAssign &VA = ArgLocs[i]; 1590 1591 // Arguments stored in registers. 1592 if (VA.isRegLoc()) { 1593 TargetRegisterClass *RC; 1594 EVT ValVT = VA.getValVT(); 1595 1596 switch (ValVT.getSimpleVT().SimpleTy) { 1597 default: 1598 llvm_unreachable("ValVT not supported by formal arguments Lowering"); 1599 case MVT::i32: 1600 RC = PPC::GPRCRegisterClass; 1601 break; 1602 case MVT::f32: 1603 RC = PPC::F4RCRegisterClass; 1604 break; 1605 case MVT::f64: 1606 RC = PPC::F8RCRegisterClass; 1607 break; 1608 case MVT::v16i8: 1609 case MVT::v8i16: 1610 case MVT::v4i32: 1611 case MVT::v4f32: 1612 RC = PPC::VRRCRegisterClass; 1613 break; 1614 } 1615 1616 // Transform the arguments stored in physical registers into virtual ones. 1617 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1618 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT); 1619 1620 InVals.push_back(ArgValue); 1621 } else { 1622 // Argument stored in memory. 1623 assert(VA.isMemLoc()); 1624 1625 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; 1626 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), 1627 isImmutable, false); 1628 1629 // Create load nodes to retrieve arguments from the stack. 1630 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1631 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0)); 1632 } 1633 } 1634 1635 // Assign locations to all of the incoming aggregate by value arguments. 1636 // Aggregates passed by value are stored in the local variable space of the 1637 // caller's stack frame, right above the parameter list area. 1638 SmallVector<CCValAssign, 16> ByValArgLocs; 1639 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), 1640 ByValArgLocs, *DAG.getContext()); 1641 1642 // Reserve stack space for the allocations in CCInfo. 1643 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 1644 1645 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal); 1646 1647 // Area that is at least reserved in the caller of this function. 1648 unsigned MinReservedArea = CCByValInfo.getNextStackOffset(); 1649 1650 // Set the size that is at least reserved in caller of this function. Tail 1651 // call optimized function's reserved stack space needs to be aligned so that 1652 // taking the difference between two stack areas will result in an aligned 1653 // stack. 1654 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1655 1656 MinReservedArea = 1657 std::max(MinReservedArea, 1658 PPCFrameInfo::getMinCallFrameSize(false, false)); 1659 1660 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 1661 getStackAlignment(); 1662 unsigned AlignMask = TargetAlign-1; 1663 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 1664 1665 FI->setMinReservedArea(MinReservedArea); 1666 1667 SmallVector<SDValue, 8> MemOps; 1668 1669 // If the function takes variable number of arguments, make a frame index for 1670 // the start of the first vararg value... for expansion of llvm.va_start. 1671 if (isVarArg) { 1672 static const unsigned GPArgRegs[] = { 1673 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1674 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1675 }; 1676 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs); 1677 1678 static const unsigned FPArgRegs[] = { 1679 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1680 PPC::F8 1681 }; 1682 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs); 1683 1684 VarArgsNumGPR = CCInfo.getFirstUnallocated(GPArgRegs, NumGPArgRegs); 1685 VarArgsNumFPR = CCInfo.getFirstUnallocated(FPArgRegs, NumFPArgRegs); 1686 1687 // Make room for NumGPArgRegs and NumFPArgRegs. 1688 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 + 1689 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8; 1690 1691 VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 1692 CCInfo.getNextStackOffset(), 1693 true, false); 1694 1695 VarArgsFrameIndex = MFI->CreateStackObject(Depth, 8, false); 1696 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1697 1698 // The fixed integer arguments of a variadic function are 1699 // stored to the VarArgsFrameIndex on the stack. 1700 unsigned GPRIndex = 0; 1701 for (; GPRIndex != VarArgsNumGPR; ++GPRIndex) { 1702 SDValue Val = DAG.getRegister(GPArgRegs[GPRIndex], PtrVT); 1703 SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0); 1704 MemOps.push_back(Store); 1705 // Increment the address by four for the next argument to store 1706 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 1707 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1708 } 1709 1710 // If this function is vararg, store any remaining integer argument regs 1711 // to their spots on the stack so that they may be loaded by deferencing the 1712 // result of va_next. 1713 for (; GPRIndex != NumGPArgRegs; ++GPRIndex) { 1714 unsigned VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); 1715 1716 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1717 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); 1718 MemOps.push_back(Store); 1719 // Increment the address by four for the next argument to store 1720 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 1721 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1722 } 1723 1724 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6 1725 // is set. 1726 1727 // The double arguments are stored to the VarArgsFrameIndex 1728 // on the stack. 1729 unsigned FPRIndex = 0; 1730 for (FPRIndex = 0; FPRIndex != VarArgsNumFPR; ++FPRIndex) { 1731 SDValue Val = DAG.getRegister(FPArgRegs[FPRIndex], MVT::f64); 1732 SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0); 1733 MemOps.push_back(Store); 1734 // Increment the address by eight for the next argument to store 1735 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8, 1736 PtrVT); 1737 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1738 } 1739 1740 for (; FPRIndex != NumFPArgRegs; ++FPRIndex) { 1741 unsigned VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); 1742 1743 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); 1744 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); 1745 MemOps.push_back(Store); 1746 // Increment the address by eight for the next argument to store 1747 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8, 1748 PtrVT); 1749 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1750 } 1751 } 1752 1753 if (!MemOps.empty()) 1754 Chain = DAG.getNode(ISD::TokenFactor, dl, 1755 MVT::Other, &MemOps[0], MemOps.size()); 1756 1757 return Chain; 1758} 1759 1760SDValue 1761PPCTargetLowering::LowerFormalArguments_Darwin( 1762 SDValue Chain, 1763 CallingConv::ID CallConv, bool isVarArg, 1764 const SmallVectorImpl<ISD::InputArg> 1765 &Ins, 1766 DebugLoc dl, SelectionDAG &DAG, 1767 SmallVectorImpl<SDValue> &InVals) { 1768 // TODO: add description of PPC stack frame format, or at least some docs. 1769 // 1770 MachineFunction &MF = DAG.getMachineFunction(); 1771 MachineFrameInfo *MFI = MF.getFrameInfo(); 1772 1773 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1774 bool isPPC64 = PtrVT == MVT::i64; 1775 // Potential tail calls could cause overwriting of argument stack slots. 1776 bool isImmutable = !(PerformTailCallOpt && (CallConv==CallingConv::Fast)); 1777 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1778 1779 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true); 1780 // Area that is at least reserved in caller of this function. 1781 unsigned MinReservedArea = ArgOffset; 1782 1783 static const unsigned GPR_32[] = { // 32-bit registers. 1784 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1785 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1786 }; 1787 static const unsigned GPR_64[] = { // 64-bit registers. 1788 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1789 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1790 }; 1791 1792 static const unsigned *FPR = GetFPR(); 1793 1794 static const unsigned VR[] = { 1795 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1796 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1797 }; 1798 1799 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 1800 const unsigned Num_FPR_Regs = 13; 1801 const unsigned Num_VR_Regs = array_lengthof( VR); 1802 1803 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1804 1805 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1806 1807 // In 32-bit non-varargs functions, the stack space for vectors is after the 1808 // stack space for non-vectors. We do not use this space unless we have 1809 // too many vectors to fit in registers, something that only occurs in 1810 // constructed examples:), but we have to walk the arglist to figure 1811 // that out...for the pathological case, compute VecArgOffset as the 1812 // start of the vector parameter area. Computing VecArgOffset is the 1813 // entire point of the following loop. 1814 unsigned VecArgOffset = ArgOffset; 1815 if (!isVarArg && !isPPC64) { 1816 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; 1817 ++ArgNo) { 1818 EVT ObjectVT = Ins[ArgNo].VT; 1819 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1820 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 1821 1822 if (Flags.isByVal()) { 1823 // ObjSize is the true size, ArgSize rounded up to multiple of regs. 1824 ObjSize = Flags.getByValSize(); 1825 unsigned ArgSize = 1826 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1827 VecArgOffset += ArgSize; 1828 continue; 1829 } 1830 1831 switch(ObjectVT.getSimpleVT().SimpleTy) { 1832 default: llvm_unreachable("Unhandled argument type!"); 1833 case MVT::i32: 1834 case MVT::f32: 1835 VecArgOffset += isPPC64 ? 8 : 4; 1836 break; 1837 case MVT::i64: // PPC64 1838 case MVT::f64: 1839 VecArgOffset += 8; 1840 break; 1841 case MVT::v4f32: 1842 case MVT::v4i32: 1843 case MVT::v8i16: 1844 case MVT::v16i8: 1845 // Nothing to do, we're only looking at Nonvector args here. 1846 break; 1847 } 1848 } 1849 } 1850 // We've found where the vector parameter area in memory is. Skip the 1851 // first 12 parameters; these don't use that memory. 1852 VecArgOffset = ((VecArgOffset+15)/16)*16; 1853 VecArgOffset += 12*16; 1854 1855 // Add DAG nodes to load the arguments or copy them out of registers. On 1856 // entry to a function on PPC, the arguments start after the linkage area, 1857 // although the first ones are often in registers. 1858 1859 SmallVector<SDValue, 8> MemOps; 1860 unsigned nAltivecParamsAtEnd = 0; 1861 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { 1862 SDValue ArgVal; 1863 bool needsLoad = false; 1864 EVT ObjectVT = Ins[ArgNo].VT; 1865 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1866 unsigned ArgSize = ObjSize; 1867 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 1868 1869 unsigned CurArgOffset = ArgOffset; 1870 1871 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 1872 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 1873 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 1874 if (isVarArg || isPPC64) { 1875 MinReservedArea = ((MinReservedArea+15)/16)*16; 1876 MinReservedArea += CalculateStackSlotSize(ObjectVT, 1877 Flags, 1878 PtrByteSize); 1879 } else nAltivecParamsAtEnd++; 1880 } else 1881 // Calculate min reserved area. 1882 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 1883 Flags, 1884 PtrByteSize); 1885 1886 // FIXME the codegen can be much improved in some cases. 1887 // We do not have to keep everything in memory. 1888 if (Flags.isByVal()) { 1889 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 1890 ObjSize = Flags.getByValSize(); 1891 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1892 // Objects of size 1 and 2 are right justified, everything else is 1893 // left justified. This means the memory address is adjusted forwards. 1894 if (ObjSize==1 || ObjSize==2) { 1895 CurArgOffset = CurArgOffset + (4 - ObjSize); 1896 } 1897 // The value of the object is its address. 1898 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true, false); 1899 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1900 InVals.push_back(FIN); 1901 if (ObjSize==1 || ObjSize==2) { 1902 if (GPR_idx != Num_GPR_Regs) { 1903 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1904 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1905 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 1906 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 ); 1907 MemOps.push_back(Store); 1908 ++GPR_idx; 1909 } 1910 1911 ArgOffset += PtrByteSize; 1912 1913 continue; 1914 } 1915 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 1916 // Store whatever pieces of the object are in registers 1917 // to memory. ArgVal will be address of the beginning of 1918 // the object. 1919 if (GPR_idx != Num_GPR_Regs) { 1920 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1921 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true, false); 1922 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1923 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1924 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); 1925 MemOps.push_back(Store); 1926 ++GPR_idx; 1927 ArgOffset += PtrByteSize; 1928 } else { 1929 ArgOffset += ArgSize - (ArgOffset-CurArgOffset); 1930 break; 1931 } 1932 } 1933 continue; 1934 } 1935 1936 switch (ObjectVT.getSimpleVT().SimpleTy) { 1937 default: llvm_unreachable("Unhandled argument type!"); 1938 case MVT::i32: 1939 if (!isPPC64) { 1940 if (GPR_idx != Num_GPR_Regs) { 1941 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1942 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 1943 ++GPR_idx; 1944 } else { 1945 needsLoad = true; 1946 ArgSize = PtrByteSize; 1947 } 1948 // All int arguments reserve stack space in the Darwin ABI. 1949 ArgOffset += PtrByteSize; 1950 break; 1951 } 1952 // FALLTHROUGH 1953 case MVT::i64: // PPC64 1954 if (GPR_idx != Num_GPR_Regs) { 1955 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 1956 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1957 1958 if (ObjectVT == MVT::i32) { 1959 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 1960 // value to MVT::i64 and then truncate to the correct register size. 1961 if (Flags.isSExt()) 1962 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, 1963 DAG.getValueType(ObjectVT)); 1964 else if (Flags.isZExt()) 1965 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, 1966 DAG.getValueType(ObjectVT)); 1967 1968 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); 1969 } 1970 1971 ++GPR_idx; 1972 } else { 1973 needsLoad = true; 1974 ArgSize = PtrByteSize; 1975 } 1976 // All int arguments reserve stack space in the Darwin ABI. 1977 ArgOffset += 8; 1978 break; 1979 1980 case MVT::f32: 1981 case MVT::f64: 1982 // Every 4 bytes of argument space consumes one of the GPRs available for 1983 // argument passing. 1984 if (GPR_idx != Num_GPR_Regs) { 1985 ++GPR_idx; 1986 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 1987 ++GPR_idx; 1988 } 1989 if (FPR_idx != Num_FPR_Regs) { 1990 unsigned VReg; 1991 1992 if (ObjectVT == MVT::f32) 1993 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 1994 else 1995 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 1996 1997 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 1998 ++FPR_idx; 1999 } else { 2000 needsLoad = true; 2001 } 2002 2003 // All FP arguments reserve stack space in the Darwin ABI. 2004 ArgOffset += isPPC64 ? 8 : ObjSize; 2005 break; 2006 case MVT::v4f32: 2007 case MVT::v4i32: 2008 case MVT::v8i16: 2009 case MVT::v16i8: 2010 // Note that vector arguments in registers don't reserve stack space, 2011 // except in varargs functions. 2012 if (VR_idx != Num_VR_Regs) { 2013 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 2014 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2015 if (isVarArg) { 2016 while ((ArgOffset % 16) != 0) { 2017 ArgOffset += PtrByteSize; 2018 if (GPR_idx != Num_GPR_Regs) 2019 GPR_idx++; 2020 } 2021 ArgOffset += 16; 2022 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 2023 } 2024 ++VR_idx; 2025 } else { 2026 if (!isVarArg && !isPPC64) { 2027 // Vectors go after all the nonvectors. 2028 CurArgOffset = VecArgOffset; 2029 VecArgOffset += 16; 2030 } else { 2031 // Vectors are aligned. 2032 ArgOffset = ((ArgOffset+15)/16)*16; 2033 CurArgOffset = ArgOffset; 2034 ArgOffset += 16; 2035 } 2036 needsLoad = true; 2037 } 2038 break; 2039 } 2040 2041 // We need to load the argument to a virtual register if we determined above 2042 // that we ran out of physical registers of the appropriate type. 2043 if (needsLoad) { 2044 int FI = MFI->CreateFixedObject(ObjSize, 2045 CurArgOffset + (ArgSize - ObjSize), 2046 isImmutable, false); 2047 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2048 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0); 2049 } 2050 2051 InVals.push_back(ArgVal); 2052 } 2053 2054 // Set the size that is at least reserved in caller of this function. Tail 2055 // call optimized function's reserved stack space needs to be aligned so that 2056 // taking the difference between two stack areas will result in an aligned 2057 // stack. 2058 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2059 // Add the Altivec parameters at the end, if needed. 2060 if (nAltivecParamsAtEnd) { 2061 MinReservedArea = ((MinReservedArea+15)/16)*16; 2062 MinReservedArea += 16*nAltivecParamsAtEnd; 2063 } 2064 MinReservedArea = 2065 std::max(MinReservedArea, 2066 PPCFrameInfo::getMinCallFrameSize(isPPC64, true)); 2067 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 2068 getStackAlignment(); 2069 unsigned AlignMask = TargetAlign-1; 2070 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 2071 FI->setMinReservedArea(MinReservedArea); 2072 2073 // If the function takes variable number of arguments, make a frame index for 2074 // the start of the first vararg value... for expansion of llvm.va_start. 2075 if (isVarArg) { 2076 int Depth = ArgOffset; 2077 2078 VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2079 Depth, true, false); 2080 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 2081 2082 // If this function is vararg, store any remaining integer argument regs 2083 // to their spots on the stack so that they may be loaded by deferencing the 2084 // result of va_next. 2085 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2086 unsigned VReg; 2087 2088 if (isPPC64) 2089 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2090 else 2091 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2092 2093 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2094 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); 2095 MemOps.push_back(Store); 2096 // Increment the address by four for the next argument to store 2097 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2098 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2099 } 2100 } 2101 2102 if (!MemOps.empty()) 2103 Chain = DAG.getNode(ISD::TokenFactor, dl, 2104 MVT::Other, &MemOps[0], MemOps.size()); 2105 2106 return Chain; 2107} 2108 2109/// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus 2110/// linkage area for the Darwin ABI. 2111static unsigned 2112CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, 2113 bool isPPC64, 2114 bool isVarArg, 2115 unsigned CC, 2116 const SmallVectorImpl<ISD::OutputArg> 2117 &Outs, 2118 unsigned &nAltivecParamsAtEnd) { 2119 // Count how many bytes are to be pushed on the stack, including the linkage 2120 // area, and parameter passing area. We start with 24/48 bytes, which is 2121 // prereserved space for [SP][CR][LR][3 x unused]. 2122 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, true); 2123 unsigned NumOps = Outs.size(); 2124 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2125 2126 // Add up all the space actually used. 2127 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually 2128 // they all go in registers, but we must reserve stack space for them for 2129 // possible use by the caller. In varargs or 64-bit calls, parameters are 2130 // assigned stack space in order, with padding so Altivec parameters are 2131 // 16-byte aligned. 2132 nAltivecParamsAtEnd = 0; 2133 for (unsigned i = 0; i != NumOps; ++i) { 2134 SDValue Arg = Outs[i].Val; 2135 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2136 EVT ArgVT = Arg.getValueType(); 2137 // Varargs Altivec parameters are padded to a 16 byte boundary. 2138 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 2139 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { 2140 if (!isVarArg && !isPPC64) { 2141 // Non-varargs Altivec parameters go after all the non-Altivec 2142 // parameters; handle those later so we know how much padding we need. 2143 nAltivecParamsAtEnd++; 2144 continue; 2145 } 2146 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. 2147 NumBytes = ((NumBytes+15)/16)*16; 2148 } 2149 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); 2150 } 2151 2152 // Allow for Altivec parameters at the end, if needed. 2153 if (nAltivecParamsAtEnd) { 2154 NumBytes = ((NumBytes+15)/16)*16; 2155 NumBytes += 16*nAltivecParamsAtEnd; 2156 } 2157 2158 // The prolog code of the callee may store up to 8 GPR argument registers to 2159 // the stack, allowing va_start to index over them in memory if its varargs. 2160 // Because we cannot tell if this is needed on the caller side, we have to 2161 // conservatively assume that it is needed. As such, make sure we have at 2162 // least enough stack space for the caller to store the 8 GPRs. 2163 NumBytes = std::max(NumBytes, 2164 PPCFrameInfo::getMinCallFrameSize(isPPC64, true)); 2165 2166 // Tail call needs the stack to be aligned. 2167 if (CC==CallingConv::Fast && PerformTailCallOpt) { 2168 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 2169 getStackAlignment(); 2170 unsigned AlignMask = TargetAlign-1; 2171 NumBytes = (NumBytes + AlignMask) & ~AlignMask; 2172 } 2173 2174 return NumBytes; 2175} 2176 2177/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be 2178/// adjusted to accomodate the arguments for the tailcall. 2179static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, 2180 unsigned ParamSize) { 2181 2182 if (!isTailCall) return 0; 2183 2184 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>(); 2185 unsigned CallerMinReservedArea = FI->getMinReservedArea(); 2186 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize; 2187 // Remember only if the new adjustement is bigger. 2188 if (SPDiff < FI->getTailCallSPDelta()) 2189 FI->setTailCallSPDelta(SPDiff); 2190 2191 return SPDiff; 2192} 2193 2194/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2195/// for tail call optimization. Targets which want to do tail call 2196/// optimization should implement this function. 2197bool 2198PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2199 CallingConv::ID CalleeCC, 2200 bool isVarArg, 2201 const SmallVectorImpl<ISD::InputArg> &Ins, 2202 SelectionDAG& DAG) const { 2203 if (!PerformTailCallOpt) 2204 return false; 2205 2206 // Variable argument functions are not supported. 2207 if (isVarArg) 2208 return false; 2209 2210 MachineFunction &MF = DAG.getMachineFunction(); 2211 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv(); 2212 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 2213 // Functions containing by val parameters are not supported. 2214 for (unsigned i = 0; i != Ins.size(); i++) { 2215 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2216 if (Flags.isByVal()) return false; 2217 } 2218 2219 // Non PIC/GOT tail calls are supported. 2220 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 2221 return true; 2222 2223 // At the moment we can only do local tail calls (in same module, hidden 2224 // or protected) if we are generating PIC. 2225 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2226 return G->getGlobal()->hasHiddenVisibility() 2227 || G->getGlobal()->hasProtectedVisibility(); 2228 } 2229 2230 return false; 2231} 2232 2233/// isCallCompatibleAddress - Return the immediate to use if the specified 2234/// 32-bit value is representable in the immediate field of a BxA instruction. 2235static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { 2236 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2237 if (!C) return 0; 2238 2239 int Addr = C->getZExtValue(); 2240 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 2241 (Addr << 6 >> 6) != Addr) 2242 return 0; // Top 6 bits have to be sext of immediate. 2243 2244 return DAG.getConstant((int)C->getZExtValue() >> 2, 2245 DAG.getTargetLoweringInfo().getPointerTy()).getNode(); 2246} 2247 2248namespace { 2249 2250struct TailCallArgumentInfo { 2251 SDValue Arg; 2252 SDValue FrameIdxOp; 2253 int FrameIdx; 2254 2255 TailCallArgumentInfo() : FrameIdx(0) {} 2256}; 2257 2258} 2259 2260/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. 2261static void 2262StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, 2263 SDValue Chain, 2264 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, 2265 SmallVector<SDValue, 8> &MemOpChains, 2266 DebugLoc dl) { 2267 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { 2268 SDValue Arg = TailCallArgs[i].Arg; 2269 SDValue FIN = TailCallArgs[i].FrameIdxOp; 2270 int FI = TailCallArgs[i].FrameIdx; 2271 // Store relative to framepointer. 2272 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN, 2273 PseudoSourceValue::getFixedStack(FI), 2274 0)); 2275 } 2276} 2277 2278/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to 2279/// the appropriate stack slot for the tail call optimized function call. 2280static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, 2281 MachineFunction &MF, 2282 SDValue Chain, 2283 SDValue OldRetAddr, 2284 SDValue OldFP, 2285 int SPDiff, 2286 bool isPPC64, 2287 bool isDarwinABI, 2288 DebugLoc dl) { 2289 if (SPDiff) { 2290 // Calculate the new stack slot for the return address. 2291 int SlotSize = isPPC64 ? 8 : 4; 2292 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64, 2293 isDarwinABI); 2294 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, 2295 NewRetAddrLoc, 2296 true, false); 2297 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2298 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); 2299 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, 2300 PseudoSourceValue::getFixedStack(NewRetAddr), 0); 2301 2302 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack 2303 // slot as the FP is never overwritten. 2304 if (isDarwinABI) { 2305 int NewFPLoc = 2306 SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); 2307 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc, 2308 true, false); 2309 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); 2310 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, 2311 PseudoSourceValue::getFixedStack(NewFPIdx), 0); 2312 } 2313 } 2314 return Chain; 2315} 2316 2317/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate 2318/// the position of the argument. 2319static void 2320CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, 2321 SDValue Arg, int SPDiff, unsigned ArgOffset, 2322 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 2323 int Offset = ArgOffset + SPDiff; 2324 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; 2325 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true,false); 2326 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2327 SDValue FIN = DAG.getFrameIndex(FI, VT); 2328 TailCallArgumentInfo Info; 2329 Info.Arg = Arg; 2330 Info.FrameIdxOp = FIN; 2331 Info.FrameIdx = FI; 2332 TailCallArguments.push_back(Info); 2333} 2334 2335/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address 2336/// stack slot. Returns the chain as result and the loaded frame pointers in 2337/// LROpOut/FPOpout. Used when tail calling. 2338SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 2339 int SPDiff, 2340 SDValue Chain, 2341 SDValue &LROpOut, 2342 SDValue &FPOpOut, 2343 bool isDarwinABI, 2344 DebugLoc dl) { 2345 if (SPDiff) { 2346 // Load the LR and FP stack slot for later adjusting. 2347 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; 2348 LROpOut = getReturnAddrFrameIndex(DAG); 2349 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0); 2350 Chain = SDValue(LROpOut.getNode(), 1); 2351 2352 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack 2353 // slot as the FP is never overwritten. 2354 if (isDarwinABI) { 2355 FPOpOut = getFramePointerFrameIndex(DAG); 2356 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0); 2357 Chain = SDValue(FPOpOut.getNode(), 1); 2358 } 2359 } 2360 return Chain; 2361} 2362 2363/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 2364/// by "Src" to address "Dst" of size "Size". Alignment information is 2365/// specified by the specific parameter attribute. The copy will be passed as 2366/// a byval function parameter. 2367/// Sometimes what we are copying is the end of a larger object, the part that 2368/// does not fit in registers. 2369static SDValue 2370CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 2371 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 2372 DebugLoc dl) { 2373 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 2374 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 2375 false, NULL, 0, NULL, 0); 2376} 2377 2378/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of 2379/// tail calls. 2380static void 2381LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, 2382 SDValue Arg, SDValue PtrOff, int SPDiff, 2383 unsigned ArgOffset, bool isPPC64, bool isTailCall, 2384 bool isVector, SmallVector<SDValue, 8> &MemOpChains, 2385 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments, 2386 DebugLoc dl) { 2387 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2388 if (!isTailCall) { 2389 if (isVector) { 2390 SDValue StackPtr; 2391 if (isPPC64) 2392 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2393 else 2394 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2395 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 2396 DAG.getConstant(ArgOffset, PtrVT)); 2397 } 2398 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); 2399 // Calculate and remember argument location. 2400 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, 2401 TailCallArguments); 2402} 2403 2404static 2405void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, 2406 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, 2407 SDValue LROp, SDValue FPOp, bool isDarwinABI, 2408 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) { 2409 MachineFunction &MF = DAG.getMachineFunction(); 2410 2411 // Emit a sequence of copyto/copyfrom virtual registers for arguments that 2412 // might overwrite each other in case of tail call optimization. 2413 SmallVector<SDValue, 8> MemOpChains2; 2414 // Do not flag preceeding copytoreg stuff together with the following stuff. 2415 InFlag = SDValue(); 2416 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, 2417 MemOpChains2, dl); 2418 if (!MemOpChains2.empty()) 2419 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2420 &MemOpChains2[0], MemOpChains2.size()); 2421 2422 // Store the return address to the appropriate stack slot. 2423 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, 2424 isPPC64, isDarwinABI, dl); 2425 2426 // Emit callseq_end just before tailcall node. 2427 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2428 DAG.getIntPtrConstant(0, true), InFlag); 2429 InFlag = Chain.getValue(1); 2430} 2431 2432static 2433unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, 2434 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall, 2435 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 2436 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys, 2437 bool isPPC64, bool isSVR4ABI) { 2438 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2439 NodeTys.push_back(MVT::Other); // Returns a chain 2440 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 2441 2442 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin; 2443 2444 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2445 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2446 // node so that legalize doesn't hack it. 2447 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2448 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); 2449 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 2450 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); 2451 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) 2452 // If this is an absolute destination address, use the munged value. 2453 Callee = SDValue(Dest, 0); 2454 else { 2455 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 2456 // to do the call, we can't use PPCISD::CALL. 2457 SDValue MTCTROps[] = {Chain, Callee, InFlag}; 2458 2459 if (isSVR4ABI && isPPC64) { 2460 // Function pointers in the 64-bit SVR4 ABI do not point to the function 2461 // entry point, but to the function descriptor (the function entry point 2462 // address is part of the function descriptor though). 2463 // The function descriptor is a three doubleword structure with the 2464 // following fields: function entry point, TOC base address and 2465 // environment pointer. 2466 // Thus for a call through a function pointer, the following actions need 2467 // to be performed: 2468 // 1. Save the TOC of the caller in the TOC save area of its stack 2469 // frame (this is done in LowerCall_Darwin()). 2470 // 2. Load the address of the function entry point from the function 2471 // descriptor. 2472 // 3. Load the TOC of the callee from the function descriptor into r2. 2473 // 4. Load the environment pointer from the function descriptor into 2474 // r11. 2475 // 5. Branch to the function entry point address. 2476 // 6. On return of the callee, the TOC of the caller needs to be 2477 // restored (this is done in FinishCall()). 2478 // 2479 // All those operations are flagged together to ensure that no other 2480 // operations can be scheduled in between. E.g. without flagging the 2481 // operations together, a TOC access in the caller could be scheduled 2482 // between the load of the callee TOC and the branch to the callee, which 2483 // results in the TOC access going through the TOC of the callee instead 2484 // of going through the TOC of the caller, which leads to incorrect code. 2485 2486 // Load the address of the function entry point from the function 2487 // descriptor. 2488 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Flag); 2489 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps, 2490 InFlag.getNode() ? 3 : 2); 2491 Chain = LoadFuncPtr.getValue(1); 2492 InFlag = LoadFuncPtr.getValue(2); 2493 2494 // Load environment pointer into r11. 2495 // Offset of the environment pointer within the function descriptor. 2496 SDValue PtrOff = DAG.getIntPtrConstant(16); 2497 2498 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff); 2499 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr, 2500 InFlag); 2501 Chain = LoadEnvPtr.getValue(1); 2502 InFlag = LoadEnvPtr.getValue(2); 2503 2504 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr, 2505 InFlag); 2506 Chain = EnvVal.getValue(0); 2507 InFlag = EnvVal.getValue(1); 2508 2509 // Load TOC of the callee into r2. We are using a target-specific load 2510 // with r2 hard coded, because the result of a target-independent load 2511 // would never go directly into r2, since r2 is a reserved register (which 2512 // prevents the register allocator from allocating it), resulting in an 2513 // additional register being allocated and an unnecessary move instruction 2514 // being generated. 2515 VTs = DAG.getVTList(MVT::Other, MVT::Flag); 2516 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, 2517 Callee, InFlag); 2518 Chain = LoadTOCPtr.getValue(0); 2519 InFlag = LoadTOCPtr.getValue(1); 2520 2521 MTCTROps[0] = Chain; 2522 MTCTROps[1] = LoadFuncPtr; 2523 MTCTROps[2] = InFlag; 2524 } 2525 2526 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps, 2527 2 + (InFlag.getNode() != 0)); 2528 InFlag = Chain.getValue(1); 2529 2530 NodeTys.clear(); 2531 NodeTys.push_back(MVT::Other); 2532 NodeTys.push_back(MVT::Flag); 2533 Ops.push_back(Chain); 2534 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin; 2535 Callee.setNode(0); 2536 // Add CTR register as callee so a bctr can be emitted later. 2537 if (isTailCall) 2538 Ops.push_back(DAG.getRegister(PPC::CTR, PtrVT)); 2539 } 2540 2541 // If this is a direct call, pass the chain and the callee. 2542 if (Callee.getNode()) { 2543 Ops.push_back(Chain); 2544 Ops.push_back(Callee); 2545 } 2546 // If this is a tail call add stack pointer delta. 2547 if (isTailCall) 2548 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); 2549 2550 // Add argument registers to the end of the list so that they are known live 2551 // into the call. 2552 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2553 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2554 RegsToPass[i].second.getValueType())); 2555 2556 return CallOpc; 2557} 2558 2559SDValue 2560PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2561 CallingConv::ID CallConv, bool isVarArg, 2562 const SmallVectorImpl<ISD::InputArg> &Ins, 2563 DebugLoc dl, SelectionDAG &DAG, 2564 SmallVectorImpl<SDValue> &InVals) { 2565 2566 SmallVector<CCValAssign, 16> RVLocs; 2567 CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(), 2568 RVLocs, *DAG.getContext()); 2569 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC); 2570 2571 // Copy all of the result registers out of their specified physreg. 2572 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2573 CCValAssign &VA = RVLocs[i]; 2574 EVT VT = VA.getValVT(); 2575 assert(VA.isRegLoc() && "Can only return in registers!"); 2576 Chain = DAG.getCopyFromReg(Chain, dl, 2577 VA.getLocReg(), VT, InFlag).getValue(1); 2578 InVals.push_back(Chain.getValue(0)); 2579 InFlag = Chain.getValue(2); 2580 } 2581 2582 return Chain; 2583} 2584 2585SDValue 2586PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl, 2587 bool isTailCall, bool isVarArg, 2588 SelectionDAG &DAG, 2589 SmallVector<std::pair<unsigned, SDValue>, 8> 2590 &RegsToPass, 2591 SDValue InFlag, SDValue Chain, 2592 SDValue &Callee, 2593 int SPDiff, unsigned NumBytes, 2594 const SmallVectorImpl<ISD::InputArg> &Ins, 2595 SmallVectorImpl<SDValue> &InVals) { 2596 std::vector<EVT> NodeTys; 2597 SmallVector<SDValue, 8> Ops; 2598 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff, 2599 isTailCall, RegsToPass, Ops, NodeTys, 2600 PPCSubTarget.isPPC64(), 2601 PPCSubTarget.isSVR4ABI()); 2602 2603 // When performing tail call optimization the callee pops its arguments off 2604 // the stack. Account for this here so these bytes can be pushed back on in 2605 // PPCRegisterInfo::eliminateCallFramePseudoInstr. 2606 int BytesCalleePops = 2607 (CallConv==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0; 2608 2609 if (InFlag.getNode()) 2610 Ops.push_back(InFlag); 2611 2612 // Emit tail call. 2613 if (isTailCall) { 2614 // If this is the first return lowered for this function, add the regs 2615 // to the liveout set for the function. 2616 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2617 SmallVector<CCValAssign, 16> RVLocs; 2618 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 2619 *DAG.getContext()); 2620 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC); 2621 for (unsigned i = 0; i != RVLocs.size(); ++i) 2622 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2623 } 2624 2625 assert(((Callee.getOpcode() == ISD::Register && 2626 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || 2627 Callee.getOpcode() == ISD::TargetExternalSymbol || 2628 Callee.getOpcode() == ISD::TargetGlobalAddress || 2629 isa<ConstantSDNode>(Callee)) && 2630 "Expecting an global address, external symbol, absolute value or register"); 2631 2632 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size()); 2633 } 2634 2635 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 2636 InFlag = Chain.getValue(1); 2637 2638 // Add a NOP immediately after the branch instruction when using the 64-bit 2639 // SVR4 ABI. At link time, if caller and callee are in a different module and 2640 // thus have a different TOC, the call will be replaced with a call to a stub 2641 // function which saves the current TOC, loads the TOC of the callee and 2642 // branches to the callee. The NOP will be replaced with a load instruction 2643 // which restores the TOC of the caller from the TOC save slot of the current 2644 // stack frame. If caller and callee belong to the same module (and have the 2645 // same TOC), the NOP will remain unchanged. 2646 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) { 2647 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag); 2648 if (CallOpc == PPCISD::BCTRL_SVR4) { 2649 // This is a call through a function pointer. 2650 // Restore the caller TOC from the save area into R2. 2651 // See PrepareCall() for more information about calls through function 2652 // pointers in the 64-bit SVR4 ABI. 2653 // We are using a target-specific load with r2 hard coded, because the 2654 // result of a target-independent load would never go directly into r2, 2655 // since r2 is a reserved register (which prevents the register allocator 2656 // from allocating it), resulting in an additional register being 2657 // allocated and an unnecessary move instruction being generated. 2658 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag); 2659 InFlag = Chain.getValue(1); 2660 } else { 2661 // Otherwise insert NOP. 2662 InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Flag, InFlag); 2663 } 2664 } 2665 2666 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2667 DAG.getIntPtrConstant(BytesCalleePops, true), 2668 InFlag); 2669 if (!Ins.empty()) 2670 InFlag = Chain.getValue(1); 2671 2672 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2673 Ins, dl, DAG, InVals); 2674} 2675 2676SDValue 2677PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, 2678 CallingConv::ID CallConv, bool isVarArg, 2679 bool &isTailCall, 2680 const SmallVectorImpl<ISD::OutputArg> &Outs, 2681 const SmallVectorImpl<ISD::InputArg> &Ins, 2682 DebugLoc dl, SelectionDAG &DAG, 2683 SmallVectorImpl<SDValue> &InVals) { 2684 if (isTailCall) 2685 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, 2686 Ins, DAG); 2687 2688 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) { 2689 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg, 2690 isTailCall, Outs, Ins, 2691 dl, DAG, InVals); 2692 } else { 2693 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg, 2694 isTailCall, Outs, Ins, 2695 dl, DAG, InVals); 2696 } 2697} 2698 2699SDValue 2700PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee, 2701 CallingConv::ID CallConv, bool isVarArg, 2702 bool isTailCall, 2703 const SmallVectorImpl<ISD::OutputArg> &Outs, 2704 const SmallVectorImpl<ISD::InputArg> &Ins, 2705 DebugLoc dl, SelectionDAG &DAG, 2706 SmallVectorImpl<SDValue> &InVals) { 2707 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description 2708 // of the 32-bit SVR4 ABI stack frame layout. 2709 2710 assert((CallConv == CallingConv::C || 2711 CallConv == CallingConv::Fast) && "Unknown calling convention!"); 2712 2713 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2714 unsigned PtrByteSize = 4; 2715 2716 MachineFunction &MF = DAG.getMachineFunction(); 2717 2718 // Mark this function as potentially containing a function that contains a 2719 // tail call. As a consequence the frame pointer will be used for dynamicalloc 2720 // and restoring the callers stack pointer in this functions epilog. This is 2721 // done because by tail calling the called function might overwrite the value 2722 // in this function's (MF) stack pointer stack slot 0(SP). 2723 if (PerformTailCallOpt && CallConv==CallingConv::Fast) 2724 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 2725 2726 // Count how many bytes are to be pushed on the stack, including the linkage 2727 // area, parameter list area and the part of the local variable space which 2728 // contains copies of aggregates which are passed by value. 2729 2730 // Assign locations to all of the outgoing arguments. 2731 SmallVector<CCValAssign, 16> ArgLocs; 2732 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 2733 ArgLocs, *DAG.getContext()); 2734 2735 // Reserve space for the linkage area on the stack. 2736 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize); 2737 2738 if (isVarArg) { 2739 // Handle fixed and variable vector arguments differently. 2740 // Fixed vector arguments go into registers as long as registers are 2741 // available. Variable vector arguments always go into memory. 2742 unsigned NumArgs = Outs.size(); 2743 2744 for (unsigned i = 0; i != NumArgs; ++i) { 2745 EVT ArgVT = Outs[i].Val.getValueType(); 2746 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 2747 bool Result; 2748 2749 if (Outs[i].IsFixed) { 2750 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, 2751 CCInfo); 2752 } else { 2753 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, 2754 ArgFlags, CCInfo); 2755 } 2756 2757 if (Result) { 2758#ifndef NDEBUG 2759 errs() << "Call operand #" << i << " has unhandled type " 2760 << ArgVT.getEVTString() << "\n"; 2761#endif 2762 llvm_unreachable(0); 2763 } 2764 } 2765 } else { 2766 // All arguments are treated the same. 2767 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4); 2768 } 2769 2770 // Assign locations to all of the outgoing aggregate by value arguments. 2771 SmallVector<CCValAssign, 16> ByValArgLocs; 2772 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), ByValArgLocs, 2773 *DAG.getContext()); 2774 2775 // Reserve stack space for the allocations in CCInfo. 2776 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 2777 2778 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal); 2779 2780 // Size of the linkage area, parameter list area and the part of the local 2781 // space variable where copies of aggregates which are passed by value are 2782 // stored. 2783 unsigned NumBytes = CCByValInfo.getNextStackOffset(); 2784 2785 // Calculate by how many bytes the stack has to be adjusted in case of tail 2786 // call optimization. 2787 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 2788 2789 // Adjust the stack pointer for the new arguments... 2790 // These operations are automatically eliminated by the prolog/epilog pass 2791 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2792 SDValue CallSeqStart = Chain; 2793 2794 // Load the return address and frame pointer so it can be moved somewhere else 2795 // later. 2796 SDValue LROp, FPOp; 2797 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false, 2798 dl); 2799 2800 // Set up a copy of the stack pointer for use loading and storing any 2801 // arguments that may not fit in the registers available for argument 2802 // passing. 2803 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2804 2805 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2806 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 2807 SmallVector<SDValue, 8> MemOpChains; 2808 2809 // Walk the register/memloc assignments, inserting copies/loads. 2810 for (unsigned i = 0, j = 0, e = ArgLocs.size(); 2811 i != e; 2812 ++i) { 2813 CCValAssign &VA = ArgLocs[i]; 2814 SDValue Arg = Outs[i].Val; 2815 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2816 2817 if (Flags.isByVal()) { 2818 // Argument is an aggregate which is passed by value, thus we need to 2819 // create a copy of it in the local variable space of the current stack 2820 // frame (which is the stack frame of the caller) and pass the address of 2821 // this copy to the callee. 2822 assert((j < ByValArgLocs.size()) && "Index out of bounds!"); 2823 CCValAssign &ByValVA = ByValArgLocs[j++]; 2824 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"); 2825 2826 // Memory reserved in the local variable space of the callers stack frame. 2827 unsigned LocMemOffset = ByValVA.getLocMemOffset(); 2828 2829 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2830 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2831 2832 // Create a copy of the argument in the local area of the current 2833 // stack frame. 2834 SDValue MemcpyCall = 2835 CreateCopyOfByValArgument(Arg, PtrOff, 2836 CallSeqStart.getNode()->getOperand(0), 2837 Flags, DAG, dl); 2838 2839 // This must go outside the CALLSEQ_START..END. 2840 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 2841 CallSeqStart.getNode()->getOperand(1)); 2842 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 2843 NewCallSeqStart.getNode()); 2844 Chain = CallSeqStart = NewCallSeqStart; 2845 2846 // Pass the address of the aggregate copy on the stack either in a 2847 // physical register or in the parameter list area of the current stack 2848 // frame to the callee. 2849 Arg = PtrOff; 2850 } 2851 2852 if (VA.isRegLoc()) { 2853 // Put argument in a physical register. 2854 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2855 } else { 2856 // Put argument in the parameter list area of the current stack frame. 2857 assert(VA.isMemLoc()); 2858 unsigned LocMemOffset = VA.getLocMemOffset(); 2859 2860 if (!isTailCall) { 2861 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2862 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2863 2864 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2865 PseudoSourceValue::getStack(), LocMemOffset)); 2866 } else { 2867 // Calculate and remember argument location. 2868 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset, 2869 TailCallArguments); 2870 } 2871 } 2872 } 2873 2874 if (!MemOpChains.empty()) 2875 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2876 &MemOpChains[0], MemOpChains.size()); 2877 2878 // Build a sequence of copy-to-reg nodes chained together with token chain 2879 // and flag operands which copy the outgoing args into the appropriate regs. 2880 SDValue InFlag; 2881 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2882 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2883 RegsToPass[i].second, InFlag); 2884 InFlag = Chain.getValue(1); 2885 } 2886 2887 // Set CR6 to true if this is a vararg call. 2888 if (isVarArg) { 2889 SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0); 2890 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag); 2891 InFlag = Chain.getValue(1); 2892 } 2893 2894 if (isTailCall) { 2895 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp, 2896 false, TailCallArguments); 2897 } 2898 2899 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 2900 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 2901 Ins, InVals); 2902} 2903 2904SDValue 2905PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, 2906 CallingConv::ID CallConv, bool isVarArg, 2907 bool isTailCall, 2908 const SmallVectorImpl<ISD::OutputArg> &Outs, 2909 const SmallVectorImpl<ISD::InputArg> &Ins, 2910 DebugLoc dl, SelectionDAG &DAG, 2911 SmallVectorImpl<SDValue> &InVals) { 2912 2913 unsigned NumOps = Outs.size(); 2914 2915 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2916 bool isPPC64 = PtrVT == MVT::i64; 2917 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2918 2919 MachineFunction &MF = DAG.getMachineFunction(); 2920 2921 // Mark this function as potentially containing a function that contains a 2922 // tail call. As a consequence the frame pointer will be used for dynamicalloc 2923 // and restoring the callers stack pointer in this functions epilog. This is 2924 // done because by tail calling the called function might overwrite the value 2925 // in this function's (MF) stack pointer stack slot 0(SP). 2926 if (PerformTailCallOpt && CallConv==CallingConv::Fast) 2927 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 2928 2929 unsigned nAltivecParamsAtEnd = 0; 2930 2931 // Count how many bytes are to be pushed on the stack, including the linkage 2932 // area, and parameter passing area. We start with 24/48 bytes, which is 2933 // prereserved space for [SP][CR][LR][3 x unused]. 2934 unsigned NumBytes = 2935 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv, 2936 Outs, 2937 nAltivecParamsAtEnd); 2938 2939 // Calculate by how many bytes the stack has to be adjusted in case of tail 2940 // call optimization. 2941 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 2942 2943 // To protect arguments on the stack from being clobbered in a tail call, 2944 // force all the loads to happen before doing any other lowering. 2945 if (isTailCall) 2946 Chain = DAG.getStackArgumentTokenFactor(Chain); 2947 2948 // Adjust the stack pointer for the new arguments... 2949 // These operations are automatically eliminated by the prolog/epilog pass 2950 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2951 SDValue CallSeqStart = Chain; 2952 2953 // Load the return address and frame pointer so it can be move somewhere else 2954 // later. 2955 SDValue LROp, FPOp; 2956 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 2957 dl); 2958 2959 // Set up a copy of the stack pointer for use loading and storing any 2960 // arguments that may not fit in the registers available for argument 2961 // passing. 2962 SDValue StackPtr; 2963 if (isPPC64) 2964 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2965 else 2966 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2967 2968 // Figure out which arguments are going to go in registers, and which in 2969 // memory. Also, if this is a vararg function, floating point operations 2970 // must be stored to our stack, and loaded into integer regs as well, if 2971 // any integer regs are available for argument passing. 2972 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true); 2973 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 2974 2975 static const unsigned GPR_32[] = { // 32-bit registers. 2976 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 2977 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 2978 }; 2979 static const unsigned GPR_64[] = { // 64-bit registers. 2980 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 2981 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 2982 }; 2983 static const unsigned *FPR = GetFPR(); 2984 2985 static const unsigned VR[] = { 2986 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 2987 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 2988 }; 2989 const unsigned NumGPRs = array_lengthof(GPR_32); 2990 const unsigned NumFPRs = 13; 2991 const unsigned NumVRs = array_lengthof(VR); 2992 2993 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 2994 2995 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2996 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 2997 2998 SmallVector<SDValue, 8> MemOpChains; 2999 for (unsigned i = 0; i != NumOps; ++i) { 3000 SDValue Arg = Outs[i].Val; 3001 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3002 3003 // PtrOff will be used to store the current argument to the stack if a 3004 // register cannot be found for it. 3005 SDValue PtrOff; 3006 3007 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 3008 3009 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3010 3011 // On PPC64, promote integers to 64-bit values. 3012 if (isPPC64 && Arg.getValueType() == MVT::i32) { 3013 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 3014 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3015 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 3016 } 3017 3018 // FIXME memcpy is used way more than necessary. Correctness first. 3019 if (Flags.isByVal()) { 3020 unsigned Size = Flags.getByValSize(); 3021 if (Size==1 || Size==2) { 3022 // Very small objects are passed right-justified. 3023 // Everything else is passed left-justified. 3024 EVT VT = (Size==1) ? MVT::i8 : MVT::i16; 3025 if (GPR_idx != NumGPRs) { 3026 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, 3027 NULL, 0, VT); 3028 MemOpChains.push_back(Load.getValue(1)); 3029 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3030 3031 ArgOffset += PtrByteSize; 3032 } else { 3033 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType()); 3034 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3035 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, 3036 CallSeqStart.getNode()->getOperand(0), 3037 Flags, DAG, dl); 3038 // This must go outside the CALLSEQ_START..END. 3039 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3040 CallSeqStart.getNode()->getOperand(1)); 3041 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3042 NewCallSeqStart.getNode()); 3043 Chain = CallSeqStart = NewCallSeqStart; 3044 ArgOffset += PtrByteSize; 3045 } 3046 continue; 3047 } 3048 // Copy entire object into memory. There are cases where gcc-generated 3049 // code assumes it is there, even if it could be put entirely into 3050 // registers. (This is not what the doc says.) 3051 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, 3052 CallSeqStart.getNode()->getOperand(0), 3053 Flags, DAG, dl); 3054 // This must go outside the CALLSEQ_START..END. 3055 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3056 CallSeqStart.getNode()->getOperand(1)); 3057 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode()); 3058 Chain = CallSeqStart = NewCallSeqStart; 3059 // And copy the pieces of it that fit into registers. 3060 for (unsigned j=0; j<Size; j+=PtrByteSize) { 3061 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 3062 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 3063 if (GPR_idx != NumGPRs) { 3064 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, NULL, 0); 3065 MemOpChains.push_back(Load.getValue(1)); 3066 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3067 ArgOffset += PtrByteSize; 3068 } else { 3069 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 3070 break; 3071 } 3072 } 3073 continue; 3074 } 3075 3076 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 3077 default: llvm_unreachable("Unexpected ValueType for argument!"); 3078 case MVT::i32: 3079 case MVT::i64: 3080 if (GPR_idx != NumGPRs) { 3081 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 3082 } else { 3083 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3084 isPPC64, isTailCall, false, MemOpChains, 3085 TailCallArguments, dl); 3086 } 3087 ArgOffset += PtrByteSize; 3088 break; 3089 case MVT::f32: 3090 case MVT::f64: 3091 if (FPR_idx != NumFPRs) { 3092 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 3093 3094 if (isVarArg) { 3095 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0); 3096 MemOpChains.push_back(Store); 3097 3098 // Float varargs are always shadowed in available integer registers 3099 if (GPR_idx != NumGPRs) { 3100 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0); 3101 MemOpChains.push_back(Load.getValue(1)); 3102 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3103 } 3104 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 3105 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3106 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 3107 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0); 3108 MemOpChains.push_back(Load.getValue(1)); 3109 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3110 } 3111 } else { 3112 // If we have any FPRs remaining, we may also have GPRs remaining. 3113 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 3114 // GPRs. 3115 if (GPR_idx != NumGPRs) 3116 ++GPR_idx; 3117 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 3118 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 3119 ++GPR_idx; 3120 } 3121 } else { 3122 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3123 isPPC64, isTailCall, false, MemOpChains, 3124 TailCallArguments, dl); 3125 } 3126 if (isPPC64) 3127 ArgOffset += 8; 3128 else 3129 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 3130 break; 3131 case MVT::v4f32: 3132 case MVT::v4i32: 3133 case MVT::v8i16: 3134 case MVT::v16i8: 3135 if (isVarArg) { 3136 // These go aligned on the stack, or in the corresponding R registers 3137 // when within range. The Darwin PPC ABI doc claims they also go in 3138 // V registers; in fact gcc does this only for arguments that are 3139 // prototyped, not for those that match the ... We do it for all 3140 // arguments, seems to work. 3141 while (ArgOffset % 16 !=0) { 3142 ArgOffset += PtrByteSize; 3143 if (GPR_idx != NumGPRs) 3144 GPR_idx++; 3145 } 3146 // We could elide this store in the case where the object fits 3147 // entirely in R registers. Maybe later. 3148 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 3149 DAG.getConstant(ArgOffset, PtrVT)); 3150 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0); 3151 MemOpChains.push_back(Store); 3152 if (VR_idx != NumVRs) { 3153 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0); 3154 MemOpChains.push_back(Load.getValue(1)); 3155 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 3156 } 3157 ArgOffset += 16; 3158 for (unsigned i=0; i<16; i+=PtrByteSize) { 3159 if (GPR_idx == NumGPRs) 3160 break; 3161 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 3162 DAG.getConstant(i, PtrVT)); 3163 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, NULL, 0); 3164 MemOpChains.push_back(Load.getValue(1)); 3165 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3166 } 3167 break; 3168 } 3169 3170 // Non-varargs Altivec params generally go in registers, but have 3171 // stack space allocated at the end. 3172 if (VR_idx != NumVRs) { 3173 // Doesn't have GPR space allocated. 3174 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 3175 } else if (nAltivecParamsAtEnd==0) { 3176 // We are emitting Altivec params in order. 3177 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3178 isPPC64, isTailCall, true, MemOpChains, 3179 TailCallArguments, dl); 3180 ArgOffset += 16; 3181 } 3182 break; 3183 } 3184 } 3185 // If all Altivec parameters fit in registers, as they usually do, 3186 // they get stack space following the non-Altivec parameters. We 3187 // don't track this here because nobody below needs it. 3188 // If there are more Altivec parameters than fit in registers emit 3189 // the stores here. 3190 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) { 3191 unsigned j = 0; 3192 // Offset is aligned; skip 1st 12 params which go in V registers. 3193 ArgOffset = ((ArgOffset+15)/16)*16; 3194 ArgOffset += 12*16; 3195 for (unsigned i = 0; i != NumOps; ++i) { 3196 SDValue Arg = Outs[i].Val; 3197 EVT ArgType = Arg.getValueType(); 3198 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || 3199 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { 3200 if (++j > NumVRs) { 3201 SDValue PtrOff; 3202 // We are emitting Altivec params in order. 3203 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3204 isPPC64, isTailCall, true, MemOpChains, 3205 TailCallArguments, dl); 3206 ArgOffset += 16; 3207 } 3208 } 3209 } 3210 } 3211 3212 if (!MemOpChains.empty()) 3213 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3214 &MemOpChains[0], MemOpChains.size()); 3215 3216 // Check if this is an indirect call (MTCTR/BCTRL). 3217 // See PrepareCall() for more information about calls through function 3218 // pointers in the 64-bit SVR4 ABI. 3219 if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() && 3220 !dyn_cast<GlobalAddressSDNode>(Callee) && 3221 !dyn_cast<ExternalSymbolSDNode>(Callee) && 3222 !isBLACompatibleAddress(Callee, DAG)) { 3223 // Load r2 into a virtual register and store it to the TOC save area. 3224 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); 3225 // TOC save area offset. 3226 SDValue PtrOff = DAG.getIntPtrConstant(40); 3227 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3228 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, NULL, 0); 3229 } 3230 3231 // Build a sequence of copy-to-reg nodes chained together with token chain 3232 // and flag operands which copy the outgoing args into the appropriate regs. 3233 SDValue InFlag; 3234 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3235 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3236 RegsToPass[i].second, InFlag); 3237 InFlag = Chain.getValue(1); 3238 } 3239 3240 if (isTailCall) { 3241 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp, 3242 FPOp, true, TailCallArguments); 3243 } 3244 3245 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 3246 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 3247 Ins, InVals); 3248} 3249 3250SDValue 3251PPCTargetLowering::LowerReturn(SDValue Chain, 3252 CallingConv::ID CallConv, bool isVarArg, 3253 const SmallVectorImpl<ISD::OutputArg> &Outs, 3254 DebugLoc dl, SelectionDAG &DAG) { 3255 3256 SmallVector<CCValAssign, 16> RVLocs; 3257 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 3258 RVLocs, *DAG.getContext()); 3259 CCInfo.AnalyzeReturn(Outs, RetCC_PPC); 3260 3261 // If this is the first return lowered for this function, add the regs to the 3262 // liveout set for the function. 3263 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 3264 for (unsigned i = 0; i != RVLocs.size(); ++i) 3265 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 3266 } 3267 3268 SDValue Flag; 3269 3270 // Copy the result values into the output registers. 3271 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3272 CCValAssign &VA = RVLocs[i]; 3273 assert(VA.isRegLoc() && "Can only return in registers!"); 3274 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 3275 Outs[i].Val, Flag); 3276 Flag = Chain.getValue(1); 3277 } 3278 3279 if (Flag.getNode()) 3280 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 3281 else 3282 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain); 3283} 3284 3285SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 3286 const PPCSubtarget &Subtarget) { 3287 // When we pop the dynamic allocation we need to restore the SP link. 3288 DebugLoc dl = Op.getDebugLoc(); 3289 3290 // Get the corect type for pointers. 3291 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3292 3293 // Construct the stack pointer operand. 3294 bool isPPC64 = Subtarget.isPPC64(); 3295 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; 3296 SDValue StackPtr = DAG.getRegister(SP, PtrVT); 3297 3298 // Get the operands for the STACKRESTORE. 3299 SDValue Chain = Op.getOperand(0); 3300 SDValue SaveSP = Op.getOperand(1); 3301 3302 // Load the old link SP. 3303 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0); 3304 3305 // Restore the stack pointer. 3306 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); 3307 3308 // Store the old link SP. 3309 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0); 3310} 3311 3312 3313 3314SDValue 3315PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { 3316 MachineFunction &MF = DAG.getMachineFunction(); 3317 bool isPPC64 = PPCSubTarget.isPPC64(); 3318 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 3319 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3320 3321 // Get current frame pointer save index. The users of this index will be 3322 // primarily DYNALLOC instructions. 3323 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3324 int RASI = FI->getReturnAddrSaveIndex(); 3325 3326 // If the frame pointer save index hasn't been defined yet. 3327 if (!RASI) { 3328 // Find out what the fix offset of the frame pointer save area. 3329 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI); 3330 // Allocate the frame index for frame pointer save area. 3331 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, 3332 true, false); 3333 // Save the result. 3334 FI->setReturnAddrSaveIndex(RASI); 3335 } 3336 return DAG.getFrameIndex(RASI, PtrVT); 3337} 3338 3339SDValue 3340PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { 3341 MachineFunction &MF = DAG.getMachineFunction(); 3342 bool isPPC64 = PPCSubTarget.isPPC64(); 3343 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 3344 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3345 3346 // Get current frame pointer save index. The users of this index will be 3347 // primarily DYNALLOC instructions. 3348 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3349 int FPSI = FI->getFramePointerSaveIndex(); 3350 3351 // If the frame pointer save index hasn't been defined yet. 3352 if (!FPSI) { 3353 // Find out what the fix offset of the frame pointer save area. 3354 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, 3355 isDarwinABI); 3356 3357 // Allocate the frame index for frame pointer save area. 3358 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, 3359 true, false); 3360 // Save the result. 3361 FI->setFramePointerSaveIndex(FPSI); 3362 } 3363 return DAG.getFrameIndex(FPSI, PtrVT); 3364} 3365 3366SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 3367 SelectionDAG &DAG, 3368 const PPCSubtarget &Subtarget) { 3369 // Get the inputs. 3370 SDValue Chain = Op.getOperand(0); 3371 SDValue Size = Op.getOperand(1); 3372 DebugLoc dl = Op.getDebugLoc(); 3373 3374 // Get the corect type for pointers. 3375 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3376 // Negate the size. 3377 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, 3378 DAG.getConstant(0, PtrVT), Size); 3379 // Construct a node for the frame pointer save index. 3380 SDValue FPSIdx = getFramePointerFrameIndex(DAG); 3381 // Build a DYNALLOC node. 3382 SDValue Ops[3] = { Chain, NegSize, FPSIdx }; 3383 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 3384 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3); 3385} 3386 3387/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 3388/// possible. 3389SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 3390 // Not FP? Not a fsel. 3391 if (!Op.getOperand(0).getValueType().isFloatingPoint() || 3392 !Op.getOperand(2).getValueType().isFloatingPoint()) 3393 return Op; 3394 3395 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 3396 3397 // Cannot handle SETEQ/SETNE. 3398 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op; 3399 3400 EVT ResVT = Op.getValueType(); 3401 EVT CmpVT = Op.getOperand(0).getValueType(); 3402 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3403 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); 3404 DebugLoc dl = Op.getDebugLoc(); 3405 3406 // If the RHS of the comparison is a 0.0, we don't need to do the 3407 // subtraction at all. 3408 if (isFloatingPointZero(RHS)) 3409 switch (CC) { 3410 default: break; // SETUO etc aren't handled by fsel. 3411 case ISD::SETULT: 3412 case ISD::SETLT: 3413 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 3414 case ISD::SETOGE: 3415 case ISD::SETGE: 3416 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 3417 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 3418 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); 3419 case ISD::SETUGT: 3420 case ISD::SETGT: 3421 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 3422 case ISD::SETOLE: 3423 case ISD::SETLE: 3424 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 3425 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 3426 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 3427 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); 3428 } 3429 3430 SDValue Cmp; 3431 switch (CC) { 3432 default: break; // SETUO etc aren't handled by fsel. 3433 case ISD::SETULT: 3434 case ISD::SETLT: 3435 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 3436 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3437 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3438 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 3439 case ISD::SETOGE: 3440 case ISD::SETGE: 3441 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 3442 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3443 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3444 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 3445 case ISD::SETUGT: 3446 case ISD::SETGT: 3447 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 3448 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3449 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3450 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 3451 case ISD::SETOLE: 3452 case ISD::SETLE: 3453 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 3454 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3455 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3456 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 3457 } 3458 return Op; 3459} 3460 3461// FIXME: Split this code up when LegalizeDAGTypes lands. 3462SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 3463 DebugLoc dl) { 3464 assert(Op.getOperand(0).getValueType().isFloatingPoint()); 3465 SDValue Src = Op.getOperand(0); 3466 if (Src.getValueType() == MVT::f32) 3467 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); 3468 3469 SDValue Tmp; 3470 switch (Op.getValueType().getSimpleVT().SimpleTy) { 3471 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); 3472 case MVT::i32: 3473 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : 3474 PPCISD::FCTIDZ, 3475 dl, MVT::f64, Src); 3476 break; 3477 case MVT::i64: 3478 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src); 3479 break; 3480 } 3481 3482 // Convert the FP value to an int value through memory. 3483 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); 3484 3485 // Emit a store to the stack slot. 3486 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0); 3487 3488 // Result is a load from the stack slot. If loading 4 bytes, make sure to 3489 // add in a bias. 3490 if (Op.getValueType() == MVT::i32) 3491 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, 3492 DAG.getConstant(4, FIPtr.getValueType())); 3493 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0); 3494} 3495 3496SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 3497 DebugLoc dl = Op.getDebugLoc(); 3498 // Don't handle ppc_fp128 here; let it be lowered to a libcall. 3499 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) 3500 return SDValue(); 3501 3502 if (Op.getOperand(0).getValueType() == MVT::i64) { 3503 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl, 3504 MVT::f64, Op.getOperand(0)); 3505 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); 3506 if (Op.getValueType() == MVT::f32) 3507 FP = DAG.getNode(ISD::FP_ROUND, dl, 3508 MVT::f32, FP, DAG.getIntPtrConstant(0)); 3509 return FP; 3510 } 3511 3512 assert(Op.getOperand(0).getValueType() == MVT::i32 && 3513 "Unhandled SINT_TO_FP type in custom expander!"); 3514 // Since we only generate this in 64-bit mode, we can take advantage of 3515 // 64-bit registers. In particular, sign extend the input value into the 3516 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 3517 // then lfd it and fcfid it. 3518 MachineFunction &MF = DAG.getMachineFunction(); 3519 MachineFrameInfo *FrameInfo = MF.getFrameInfo(); 3520 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false); 3521 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3522 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 3523 3524 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32, 3525 Op.getOperand(0)); 3526 3527 // STD the extended value into the stack slot. 3528 MachineMemOperand *MMO = 3529 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx), 3530 MachineMemOperand::MOStore, 0, 8, 8); 3531 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx }; 3532 SDValue Store = 3533 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other), 3534 Ops, 4, MVT::i64, MMO); 3535 // Load the value as a double. 3536 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0); 3537 3538 // FCFID it and return it. 3539 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); 3540 if (Op.getValueType() == MVT::f32) 3541 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); 3542 return FP; 3543} 3544 3545SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { 3546 DebugLoc dl = Op.getDebugLoc(); 3547 /* 3548 The rounding mode is in bits 30:31 of FPSR, and has the following 3549 settings: 3550 00 Round to nearest 3551 01 Round to 0 3552 10 Round to +inf 3553 11 Round to -inf 3554 3555 FLT_ROUNDS, on the other hand, expects the following: 3556 -1 Undefined 3557 0 Round to 0 3558 1 Round to nearest 3559 2 Round to +inf 3560 3 Round to -inf 3561 3562 To perform the conversion, we do: 3563 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 3564 */ 3565 3566 MachineFunction &MF = DAG.getMachineFunction(); 3567 EVT VT = Op.getValueType(); 3568 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3569 std::vector<EVT> NodeTys; 3570 SDValue MFFSreg, InFlag; 3571 3572 // Save FP Control Word to register 3573 NodeTys.push_back(MVT::f64); // return register 3574 NodeTys.push_back(MVT::Flag); // unused in this context 3575 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 3576 3577 // Save FP register to stack slot 3578 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 3579 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 3580 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, 3581 StackSlot, NULL, 0); 3582 3583 // Load FP Control Word from low 32 bits of stack slot. 3584 SDValue Four = DAG.getConstant(4, PtrVT); 3585 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); 3586 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0); 3587 3588 // Transform as necessary 3589 SDValue CWD1 = 3590 DAG.getNode(ISD::AND, dl, MVT::i32, 3591 CWD, DAG.getConstant(3, MVT::i32)); 3592 SDValue CWD2 = 3593 DAG.getNode(ISD::SRL, dl, MVT::i32, 3594 DAG.getNode(ISD::AND, dl, MVT::i32, 3595 DAG.getNode(ISD::XOR, dl, MVT::i32, 3596 CWD, DAG.getConstant(3, MVT::i32)), 3597 DAG.getConstant(3, MVT::i32)), 3598 DAG.getConstant(1, MVT::i32)); 3599 3600 SDValue RetVal = 3601 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); 3602 3603 return DAG.getNode((VT.getSizeInBits() < 16 ? 3604 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 3605} 3606 3607SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) { 3608 EVT VT = Op.getValueType(); 3609 unsigned BitWidth = VT.getSizeInBits(); 3610 DebugLoc dl = Op.getDebugLoc(); 3611 assert(Op.getNumOperands() == 3 && 3612 VT == Op.getOperand(1).getValueType() && 3613 "Unexpected SHL!"); 3614 3615 // Expand into a bunch of logical ops. Note that these ops 3616 // depend on the PPC behavior for oversized shift amounts. 3617 SDValue Lo = Op.getOperand(0); 3618 SDValue Hi = Op.getOperand(1); 3619 SDValue Amt = Op.getOperand(2); 3620 EVT AmtVT = Amt.getValueType(); 3621 3622 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3623 DAG.getConstant(BitWidth, AmtVT), Amt); 3624 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); 3625 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); 3626 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); 3627 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3628 DAG.getConstant(-BitWidth, AmtVT)); 3629 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); 3630 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 3631 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); 3632 SDValue OutOps[] = { OutLo, OutHi }; 3633 return DAG.getMergeValues(OutOps, 2, dl); 3634} 3635 3636SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) { 3637 EVT VT = Op.getValueType(); 3638 DebugLoc dl = Op.getDebugLoc(); 3639 unsigned BitWidth = VT.getSizeInBits(); 3640 assert(Op.getNumOperands() == 3 && 3641 VT == Op.getOperand(1).getValueType() && 3642 "Unexpected SRL!"); 3643 3644 // Expand into a bunch of logical ops. Note that these ops 3645 // depend on the PPC behavior for oversized shift amounts. 3646 SDValue Lo = Op.getOperand(0); 3647 SDValue Hi = Op.getOperand(1); 3648 SDValue Amt = Op.getOperand(2); 3649 EVT AmtVT = Amt.getValueType(); 3650 3651 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3652 DAG.getConstant(BitWidth, AmtVT), Amt); 3653 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3654 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 3655 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 3656 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3657 DAG.getConstant(-BitWidth, AmtVT)); 3658 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); 3659 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 3660 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); 3661 SDValue OutOps[] = { OutLo, OutHi }; 3662 return DAG.getMergeValues(OutOps, 2, dl); 3663} 3664 3665SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) { 3666 DebugLoc dl = Op.getDebugLoc(); 3667 EVT VT = Op.getValueType(); 3668 unsigned BitWidth = VT.getSizeInBits(); 3669 assert(Op.getNumOperands() == 3 && 3670 VT == Op.getOperand(1).getValueType() && 3671 "Unexpected SRA!"); 3672 3673 // Expand into a bunch of logical ops, followed by a select_cc. 3674 SDValue Lo = Op.getOperand(0); 3675 SDValue Hi = Op.getOperand(1); 3676 SDValue Amt = Op.getOperand(2); 3677 EVT AmtVT = Amt.getValueType(); 3678 3679 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3680 DAG.getConstant(BitWidth, AmtVT), Amt); 3681 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3682 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 3683 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 3684 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3685 DAG.getConstant(-BitWidth, AmtVT)); 3686 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); 3687 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); 3688 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), 3689 Tmp4, Tmp6, ISD::SETLE); 3690 SDValue OutOps[] = { OutLo, OutHi }; 3691 return DAG.getMergeValues(OutOps, 2, dl); 3692} 3693 3694//===----------------------------------------------------------------------===// 3695// Vector related lowering. 3696// 3697 3698/// BuildSplatI - Build a canonical splati of Val with an element size of 3699/// SplatSize. Cast the result to VT. 3700static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT, 3701 SelectionDAG &DAG, DebugLoc dl) { 3702 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 3703 3704 static const EVT VTys[] = { // canonical VT to use for each size. 3705 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 3706 }; 3707 3708 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 3709 3710 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 3711 if (Val == -1) 3712 SplatSize = 1; 3713 3714 EVT CanonicalVT = VTys[SplatSize-1]; 3715 3716 // Build a canonical splat for this value. 3717 SDValue Elt = DAG.getConstant(Val, MVT::i32); 3718 SmallVector<SDValue, 8> Ops; 3719 Ops.assign(CanonicalVT.getVectorNumElements(), Elt); 3720 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, 3721 &Ops[0], Ops.size()); 3722 return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res); 3723} 3724 3725/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 3726/// specified intrinsic ID. 3727static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, 3728 SelectionDAG &DAG, DebugLoc dl, 3729 EVT DestVT = MVT::Other) { 3730 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 3731 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 3732 DAG.getConstant(IID, MVT::i32), LHS, RHS); 3733} 3734 3735/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 3736/// specified intrinsic ID. 3737static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, 3738 SDValue Op2, SelectionDAG &DAG, 3739 DebugLoc dl, EVT DestVT = MVT::Other) { 3740 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 3741 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 3742 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 3743} 3744 3745 3746/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 3747/// amount. The result has the specified value type. 3748static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, 3749 EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3750 // Force LHS/RHS to be the right type. 3751 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS); 3752 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS); 3753 3754 int Ops[16]; 3755 for (unsigned i = 0; i != 16; ++i) 3756 Ops[i] = i + Amt; 3757 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); 3758 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T); 3759} 3760 3761// If this is a case we can't handle, return null and let the default 3762// expansion code take care of it. If we CAN select this case, and if it 3763// selects to a single instruction, return Op. Otherwise, if we can codegen 3764// this case more efficiently than a constant pool load, lower it to the 3765// sequence of ops that should be used. 3766SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { 3767 DebugLoc dl = Op.getDebugLoc(); 3768 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 3769 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR"); 3770 3771 // Check if this is a splat of a constant value. 3772 APInt APSplatBits, APSplatUndef; 3773 unsigned SplatBitSize; 3774 bool HasAnyUndefs; 3775 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize, 3776 HasAnyUndefs, 0, true) || SplatBitSize > 32) 3777 return SDValue(); 3778 3779 unsigned SplatBits = APSplatBits.getZExtValue(); 3780 unsigned SplatUndef = APSplatUndef.getZExtValue(); 3781 unsigned SplatSize = SplatBitSize / 8; 3782 3783 // First, handle single instruction cases. 3784 3785 // All zeros? 3786 if (SplatBits == 0) { 3787 // Canonicalize all zero vectors to be v4i32. 3788 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 3789 SDValue Z = DAG.getConstant(0, MVT::i32); 3790 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); 3791 Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z); 3792 } 3793 return Op; 3794 } 3795 3796 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 3797 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >> 3798 (32-SplatBitSize)); 3799 if (SextVal >= -16 && SextVal <= 15) 3800 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl); 3801 3802 3803 // Two instruction sequences. 3804 3805 // If this value is in the range [-32,30] and is even, use: 3806 // tmp = VSPLTI[bhw], result = add tmp, tmp 3807 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 3808 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl); 3809 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res); 3810 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3811 } 3812 3813 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 3814 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 3815 // for fneg/fabs. 3816 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 3817 // Make -1 and vspltisw -1: 3818 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); 3819 3820 // Make the VSLW intrinsic, computing 0x8000_0000. 3821 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 3822 OnesV, DAG, dl); 3823 3824 // xor by OnesV to invert it. 3825 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); 3826 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3827 } 3828 3829 // Check to see if this is a wide variety of vsplti*, binop self cases. 3830 static const signed char SplatCsts[] = { 3831 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 3832 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 3833 }; 3834 3835 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 3836 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 3837 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 3838 int i = SplatCsts[idx]; 3839 3840 // Figure out what shift amount will be used by altivec if shifted by i in 3841 // this splat size. 3842 unsigned TypeShiftAmt = i & (SplatBitSize-1); 3843 3844 // vsplti + shl self. 3845 if (SextVal == (i << (int)TypeShiftAmt)) { 3846 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3847 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3848 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 3849 Intrinsic::ppc_altivec_vslw 3850 }; 3851 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3852 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3853 } 3854 3855 // vsplti + srl self. 3856 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 3857 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3858 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3859 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 3860 Intrinsic::ppc_altivec_vsrw 3861 }; 3862 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3863 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3864 } 3865 3866 // vsplti + sra self. 3867 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 3868 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3869 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3870 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 3871 Intrinsic::ppc_altivec_vsraw 3872 }; 3873 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3874 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3875 } 3876 3877 // vsplti + rol self. 3878 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 3879 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 3880 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3881 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3882 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 3883 Intrinsic::ppc_altivec_vrlw 3884 }; 3885 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3886 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3887 } 3888 3889 // t = vsplti c, result = vsldoi t, t, 1 3890 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { 3891 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3892 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); 3893 } 3894 // t = vsplti c, result = vsldoi t, t, 2 3895 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { 3896 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3897 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); 3898 } 3899 // t = vsplti c, result = vsldoi t, t, 3 3900 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { 3901 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3902 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); 3903 } 3904 } 3905 3906 // Three instruction sequences. 3907 3908 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 3909 if (SextVal >= 0 && SextVal <= 31) { 3910 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl); 3911 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 3912 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS); 3913 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS); 3914 } 3915 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 3916 if (SextVal >= -31 && SextVal <= 0) { 3917 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl); 3918 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 3919 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS); 3920 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS); 3921 } 3922 3923 return SDValue(); 3924} 3925 3926/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 3927/// the specified operations to build the shuffle. 3928static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 3929 SDValue RHS, SelectionDAG &DAG, 3930 DebugLoc dl) { 3931 unsigned OpNum = (PFEntry >> 26) & 0x0F; 3932 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 3933 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 3934 3935 enum { 3936 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 3937 OP_VMRGHW, 3938 OP_VMRGLW, 3939 OP_VSPLTISW0, 3940 OP_VSPLTISW1, 3941 OP_VSPLTISW2, 3942 OP_VSPLTISW3, 3943 OP_VSLDOI4, 3944 OP_VSLDOI8, 3945 OP_VSLDOI12 3946 }; 3947 3948 if (OpNum == OP_COPY) { 3949 if (LHSID == (1*9+2)*9+3) return LHS; 3950 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 3951 return RHS; 3952 } 3953 3954 SDValue OpLHS, OpRHS; 3955 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 3956 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 3957 3958 int ShufIdxs[16]; 3959 switch (OpNum) { 3960 default: llvm_unreachable("Unknown i32 permute!"); 3961 case OP_VMRGHW: 3962 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 3963 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 3964 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 3965 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 3966 break; 3967 case OP_VMRGLW: 3968 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 3969 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 3970 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 3971 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 3972 break; 3973 case OP_VSPLTISW0: 3974 for (unsigned i = 0; i != 16; ++i) 3975 ShufIdxs[i] = (i&3)+0; 3976 break; 3977 case OP_VSPLTISW1: 3978 for (unsigned i = 0; i != 16; ++i) 3979 ShufIdxs[i] = (i&3)+4; 3980 break; 3981 case OP_VSPLTISW2: 3982 for (unsigned i = 0; i != 16; ++i) 3983 ShufIdxs[i] = (i&3)+8; 3984 break; 3985 case OP_VSPLTISW3: 3986 for (unsigned i = 0; i != 16; ++i) 3987 ShufIdxs[i] = (i&3)+12; 3988 break; 3989 case OP_VSLDOI4: 3990 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl); 3991 case OP_VSLDOI8: 3992 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl); 3993 case OP_VSLDOI12: 3994 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl); 3995 } 3996 EVT VT = OpLHS.getValueType(); 3997 OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS); 3998 OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS); 3999 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); 4000 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T); 4001} 4002 4003/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 4004/// is a shuffle we can handle in a single instruction, return it. Otherwise, 4005/// return the code it can be lowered into. Worst case, it can always be 4006/// lowered into a vperm. 4007SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 4008 SelectionDAG &DAG) { 4009 DebugLoc dl = Op.getDebugLoc(); 4010 SDValue V1 = Op.getOperand(0); 4011 SDValue V2 = Op.getOperand(1); 4012 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4013 EVT VT = Op.getValueType(); 4014 4015 // Cases that are handled by instructions that take permute immediates 4016 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 4017 // selected by the instruction selector. 4018 if (V2.getOpcode() == ISD::UNDEF) { 4019 if (PPC::isSplatShuffleMask(SVOp, 1) || 4020 PPC::isSplatShuffleMask(SVOp, 2) || 4021 PPC::isSplatShuffleMask(SVOp, 4) || 4022 PPC::isVPKUWUMShuffleMask(SVOp, true) || 4023 PPC::isVPKUHUMShuffleMask(SVOp, true) || 4024 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 || 4025 PPC::isVMRGLShuffleMask(SVOp, 1, true) || 4026 PPC::isVMRGLShuffleMask(SVOp, 2, true) || 4027 PPC::isVMRGLShuffleMask(SVOp, 4, true) || 4028 PPC::isVMRGHShuffleMask(SVOp, 1, true) || 4029 PPC::isVMRGHShuffleMask(SVOp, 2, true) || 4030 PPC::isVMRGHShuffleMask(SVOp, 4, true)) { 4031 return Op; 4032 } 4033 } 4034 4035 // Altivec has a variety of "shuffle immediates" that take two vector inputs 4036 // and produce a fixed permutation. If any of these match, do not lower to 4037 // VPERM. 4038 if (PPC::isVPKUWUMShuffleMask(SVOp, false) || 4039 PPC::isVPKUHUMShuffleMask(SVOp, false) || 4040 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 || 4041 PPC::isVMRGLShuffleMask(SVOp, 1, false) || 4042 PPC::isVMRGLShuffleMask(SVOp, 2, false) || 4043 PPC::isVMRGLShuffleMask(SVOp, 4, false) || 4044 PPC::isVMRGHShuffleMask(SVOp, 1, false) || 4045 PPC::isVMRGHShuffleMask(SVOp, 2, false) || 4046 PPC::isVMRGHShuffleMask(SVOp, 4, false)) 4047 return Op; 4048 4049 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 4050 // perfect shuffle table to emit an optimal matching sequence. 4051 SmallVector<int, 16> PermMask; 4052 SVOp->getMask(PermMask); 4053 4054 unsigned PFIndexes[4]; 4055 bool isFourElementShuffle = true; 4056 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 4057 unsigned EltNo = 8; // Start out undef. 4058 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 4059 if (PermMask[i*4+j] < 0) 4060 continue; // Undef, ignore it. 4061 4062 unsigned ByteSource = PermMask[i*4+j]; 4063 if ((ByteSource & 3) != j) { 4064 isFourElementShuffle = false; 4065 break; 4066 } 4067 4068 if (EltNo == 8) { 4069 EltNo = ByteSource/4; 4070 } else if (EltNo != ByteSource/4) { 4071 isFourElementShuffle = false; 4072 break; 4073 } 4074 } 4075 PFIndexes[i] = EltNo; 4076 } 4077 4078 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 4079 // perfect shuffle vector to determine if it is cost effective to do this as 4080 // discrete instructions, or whether we should use a vperm. 4081 if (isFourElementShuffle) { 4082 // Compute the index in the perfect shuffle table. 4083 unsigned PFTableIndex = 4084 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4085 4086 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4087 unsigned Cost = (PFEntry >> 30); 4088 4089 // Determining when to avoid vperm is tricky. Many things affect the cost 4090 // of vperm, particularly how many times the perm mask needs to be computed. 4091 // For example, if the perm mask can be hoisted out of a loop or is already 4092 // used (perhaps because there are multiple permutes with the same shuffle 4093 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 4094 // the loop requires an extra register. 4095 // 4096 // As a compromise, we only emit discrete instructions if the shuffle can be 4097 // generated in 3 or fewer operations. When we have loop information 4098 // available, if this block is within a loop, we should avoid using vperm 4099 // for 3-operation perms and use a constant pool load instead. 4100 if (Cost < 3) 4101 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 4102 } 4103 4104 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 4105 // vector that will get spilled to the constant pool. 4106 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 4107 4108 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 4109 // that it is in input element units, not in bytes. Convert now. 4110 EVT EltVT = V1.getValueType().getVectorElementType(); 4111 unsigned BytesPerElement = EltVT.getSizeInBits()/8; 4112 4113 SmallVector<SDValue, 16> ResultMask; 4114 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { 4115 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i]; 4116 4117 for (unsigned j = 0; j != BytesPerElement; ++j) 4118 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 4119 MVT::i32)); 4120 } 4121 4122 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, 4123 &ResultMask[0], ResultMask.size()); 4124 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); 4125} 4126 4127/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 4128/// altivec comparison. If it is, return true and fill in Opc/isDot with 4129/// information about the intrinsic. 4130static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, 4131 bool &isDot) { 4132 unsigned IntrinsicID = 4133 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue(); 4134 CompareOpc = -1; 4135 isDot = false; 4136 switch (IntrinsicID) { 4137 default: return false; 4138 // Comparison predicates. 4139 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 4140 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 4141 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 4142 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 4143 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 4144 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 4145 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 4146 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 4147 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 4148 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 4149 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 4150 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 4151 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 4152 4153 // Normal Comparisons. 4154 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 4155 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 4156 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 4157 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 4158 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 4159 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 4160 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 4161 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 4162 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 4163 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 4164 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 4165 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 4166 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 4167 } 4168 return true; 4169} 4170 4171/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 4172/// lower, do it, otherwise return null. 4173SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 4174 SelectionDAG &DAG) { 4175 // If this is a lowered altivec predicate compare, CompareOpc is set to the 4176 // opcode number of the comparison. 4177 DebugLoc dl = Op.getDebugLoc(); 4178 int CompareOpc; 4179 bool isDot; 4180 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 4181 return SDValue(); // Don't custom lower most intrinsics. 4182 4183 // If this is a non-dot comparison, make the VCMP node and we are done. 4184 if (!isDot) { 4185 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), 4186 Op.getOperand(1), Op.getOperand(2), 4187 DAG.getConstant(CompareOpc, MVT::i32)); 4188 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp); 4189 } 4190 4191 // Create the PPCISD altivec 'dot' comparison node. 4192 SDValue Ops[] = { 4193 Op.getOperand(2), // LHS 4194 Op.getOperand(3), // RHS 4195 DAG.getConstant(CompareOpc, MVT::i32) 4196 }; 4197 std::vector<EVT> VTs; 4198 VTs.push_back(Op.getOperand(2).getValueType()); 4199 VTs.push_back(MVT::Flag); 4200 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 4201 4202 // Now that we have the comparison, emit a copy from the CR to a GPR. 4203 // This is flagged to the above dot comparison. 4204 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32, 4205 DAG.getRegister(PPC::CR6, MVT::i32), 4206 CompNode.getValue(1)); 4207 4208 // Unpack the result based on how the target uses it. 4209 unsigned BitNo; // Bit # of CR6. 4210 bool InvertBit; // Invert result? 4211 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) { 4212 default: // Can't happen, don't crash on invalid number though. 4213 case 0: // Return the value of the EQ bit of CR6. 4214 BitNo = 0; InvertBit = false; 4215 break; 4216 case 1: // Return the inverted value of the EQ bit of CR6. 4217 BitNo = 0; InvertBit = true; 4218 break; 4219 case 2: // Return the value of the LT bit of CR6. 4220 BitNo = 2; InvertBit = false; 4221 break; 4222 case 3: // Return the inverted value of the LT bit of CR6. 4223 BitNo = 2; InvertBit = true; 4224 break; 4225 } 4226 4227 // Shift the bit into the low position. 4228 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, 4229 DAG.getConstant(8-(3-BitNo), MVT::i32)); 4230 // Isolate the bit. 4231 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, 4232 DAG.getConstant(1, MVT::i32)); 4233 4234 // If we are supposed to, toggle the bit. 4235 if (InvertBit) 4236 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, 4237 DAG.getConstant(1, MVT::i32)); 4238 return Flags; 4239} 4240 4241SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, 4242 SelectionDAG &DAG) { 4243 DebugLoc dl = Op.getDebugLoc(); 4244 // Create a stack slot that is 16-byte aligned. 4245 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 4246 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false); 4247 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4248 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 4249 4250 // Store the input value into Value#0 of the stack slot. 4251 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 4252 Op.getOperand(0), FIdx, NULL, 0); 4253 // Load it out. 4254 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0); 4255} 4256 4257SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { 4258 DebugLoc dl = Op.getDebugLoc(); 4259 if (Op.getValueType() == MVT::v4i32) { 4260 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4261 4262 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); 4263 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. 4264 4265 SDValue RHSSwap = // = vrlw RHS, 16 4266 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); 4267 4268 // Shrinkify inputs to v8i16. 4269 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS); 4270 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS); 4271 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap); 4272 4273 // Low parts multiplied together, generating 32-bit results (we ignore the 4274 // top parts). 4275 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 4276 LHS, RHS, DAG, dl, MVT::v4i32); 4277 4278 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 4279 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); 4280 // Shift the high parts up 16 bits. 4281 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, 4282 Neg16, DAG, dl); 4283 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); 4284 } else if (Op.getValueType() == MVT::v8i16) { 4285 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4286 4287 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); 4288 4289 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 4290 LHS, RHS, Zero, DAG, dl); 4291 } else if (Op.getValueType() == MVT::v16i8) { 4292 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4293 4294 // Multiply the even 8-bit parts, producing 16-bit sums. 4295 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 4296 LHS, RHS, DAG, dl, MVT::v8i16); 4297 EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts); 4298 4299 // Multiply the odd 8-bit parts, producing 16-bit sums. 4300 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 4301 LHS, RHS, DAG, dl, MVT::v8i16); 4302 OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts); 4303 4304 // Merge the results together. 4305 int Ops[16]; 4306 for (unsigned i = 0; i != 8; ++i) { 4307 Ops[i*2 ] = 2*i+1; 4308 Ops[i*2+1] = 2*i+1+16; 4309 } 4310 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); 4311 } else { 4312 llvm_unreachable("Unknown mul to lower!"); 4313 } 4314} 4315 4316/// LowerOperation - Provide custom lowering hooks for some operations. 4317/// 4318SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 4319 switch (Op.getOpcode()) { 4320 default: llvm_unreachable("Wasn't expecting to be able to lower this!"); 4321 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 4322 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 4323 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 4324 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 4325 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 4326 case ISD::SETCC: return LowerSETCC(Op, DAG); 4327 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 4328 case ISD::VASTART: 4329 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 4330 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 4331 4332 case ISD::VAARG: 4333 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 4334 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 4335 4336 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 4337 case ISD::DYNAMIC_STACKALLOC: 4338 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 4339 4340 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 4341 case ISD::FP_TO_UINT: 4342 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, 4343 Op.getDebugLoc()); 4344 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 4345 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 4346 4347 // Lower 64-bit shifts. 4348 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 4349 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 4350 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 4351 4352 // Vector-related lowering. 4353 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 4354 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 4355 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 4356 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 4357 case ISD::MUL: return LowerMUL(Op, DAG); 4358 4359 // Frame & Return address. 4360 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 4361 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 4362 } 4363 return SDValue(); 4364} 4365 4366void PPCTargetLowering::ReplaceNodeResults(SDNode *N, 4367 SmallVectorImpl<SDValue>&Results, 4368 SelectionDAG &DAG) { 4369 DebugLoc dl = N->getDebugLoc(); 4370 switch (N->getOpcode()) { 4371 default: 4372 assert(false && "Do not know how to custom type legalize this operation!"); 4373 return; 4374 case ISD::FP_ROUND_INREG: { 4375 assert(N->getValueType(0) == MVT::ppcf128); 4376 assert(N->getOperand(0).getValueType() == MVT::ppcf128); 4377 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 4378 MVT::f64, N->getOperand(0), 4379 DAG.getIntPtrConstant(0)); 4380 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 4381 MVT::f64, N->getOperand(0), 4382 DAG.getIntPtrConstant(1)); 4383 4384 // This sequence changes FPSCR to do round-to-zero, adds the two halves 4385 // of the long double, and puts FPSCR back the way it was. We do not 4386 // actually model FPSCR. 4387 std::vector<EVT> NodeTys; 4388 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg; 4389 4390 NodeTys.push_back(MVT::f64); // Return register 4391 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns 4392 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 4393 MFFSreg = Result.getValue(0); 4394 InFlag = Result.getValue(1); 4395 4396 NodeTys.clear(); 4397 NodeTys.push_back(MVT::Flag); // Returns a flag 4398 Ops[0] = DAG.getConstant(31, MVT::i32); 4399 Ops[1] = InFlag; 4400 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2); 4401 InFlag = Result.getValue(0); 4402 4403 NodeTys.clear(); 4404 NodeTys.push_back(MVT::Flag); // Returns a flag 4405 Ops[0] = DAG.getConstant(30, MVT::i32); 4406 Ops[1] = InFlag; 4407 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2); 4408 InFlag = Result.getValue(0); 4409 4410 NodeTys.clear(); 4411 NodeTys.push_back(MVT::f64); // result of add 4412 NodeTys.push_back(MVT::Flag); // Returns a flag 4413 Ops[0] = Lo; 4414 Ops[1] = Hi; 4415 Ops[2] = InFlag; 4416 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3); 4417 FPreg = Result.getValue(0); 4418 InFlag = Result.getValue(1); 4419 4420 NodeTys.clear(); 4421 NodeTys.push_back(MVT::f64); 4422 Ops[0] = DAG.getConstant(1, MVT::i32); 4423 Ops[1] = MFFSreg; 4424 Ops[2] = FPreg; 4425 Ops[3] = InFlag; 4426 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4); 4427 FPreg = Result.getValue(0); 4428 4429 // We know the low half is about to be thrown away, so just use something 4430 // convenient. 4431 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, 4432 FPreg, FPreg)); 4433 return; 4434 } 4435 case ISD::FP_TO_SINT: 4436 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl)); 4437 return; 4438 } 4439} 4440 4441 4442//===----------------------------------------------------------------------===// 4443// Other Lowering Code 4444//===----------------------------------------------------------------------===// 4445 4446MachineBasicBlock * 4447PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 4448 bool is64bit, unsigned BinOpcode) const { 4449 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4450 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4451 4452 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4453 MachineFunction *F = BB->getParent(); 4454 MachineFunction::iterator It = BB; 4455 ++It; 4456 4457 unsigned dest = MI->getOperand(0).getReg(); 4458 unsigned ptrA = MI->getOperand(1).getReg(); 4459 unsigned ptrB = MI->getOperand(2).getReg(); 4460 unsigned incr = MI->getOperand(3).getReg(); 4461 DebugLoc dl = MI->getDebugLoc(); 4462 4463 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4464 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4465 F->insert(It, loopMBB); 4466 F->insert(It, exitMBB); 4467 exitMBB->transferSuccessors(BB); 4468 4469 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4470 unsigned TmpReg = (!BinOpcode) ? incr : 4471 RegInfo.createVirtualRegister( 4472 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4473 (const TargetRegisterClass *) &PPC::GPRCRegClass); 4474 4475 // thisMBB: 4476 // ... 4477 // fallthrough --> loopMBB 4478 BB->addSuccessor(loopMBB); 4479 4480 // loopMBB: 4481 // l[wd]arx dest, ptr 4482 // add r0, dest, incr 4483 // st[wd]cx. r0, ptr 4484 // bne- loopMBB 4485 // fallthrough --> exitMBB 4486 BB = loopMBB; 4487 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4488 .addReg(ptrA).addReg(ptrB); 4489 if (BinOpcode) 4490 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); 4491 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4492 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); 4493 BuildMI(BB, dl, TII->get(PPC::BCC)) 4494 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4495 BB->addSuccessor(loopMBB); 4496 BB->addSuccessor(exitMBB); 4497 4498 // exitMBB: 4499 // ... 4500 BB = exitMBB; 4501 return BB; 4502} 4503 4504MachineBasicBlock * 4505PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, 4506 MachineBasicBlock *BB, 4507 bool is8bit, // operation 4508 unsigned BinOpcode) const { 4509 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4510 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4511 // In 64 bit mode we have to use 64 bits for addresses, even though the 4512 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address 4513 // registers without caring whether they're 32 or 64, but here we're 4514 // doing actual arithmetic on the addresses. 4515 bool is64bit = PPCSubTarget.isPPC64(); 4516 4517 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4518 MachineFunction *F = BB->getParent(); 4519 MachineFunction::iterator It = BB; 4520 ++It; 4521 4522 unsigned dest = MI->getOperand(0).getReg(); 4523 unsigned ptrA = MI->getOperand(1).getReg(); 4524 unsigned ptrB = MI->getOperand(2).getReg(); 4525 unsigned incr = MI->getOperand(3).getReg(); 4526 DebugLoc dl = MI->getDebugLoc(); 4527 4528 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4529 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4530 F->insert(It, loopMBB); 4531 F->insert(It, exitMBB); 4532 exitMBB->transferSuccessors(BB); 4533 4534 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4535 const TargetRegisterClass *RC = 4536 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4537 (const TargetRegisterClass *) &PPC::GPRCRegClass; 4538 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 4539 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 4540 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 4541 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC); 4542 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 4543 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4544 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4545 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4546 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC); 4547 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4548 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4549 unsigned Ptr1Reg; 4550 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); 4551 4552 // thisMBB: 4553 // ... 4554 // fallthrough --> loopMBB 4555 BB->addSuccessor(loopMBB); 4556 4557 // The 4-byte load must be aligned, while a char or short may be 4558 // anywhere in the word. Hence all this nasty bookkeeping code. 4559 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4560 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4561 // xori shift, shift1, 24 [16] 4562 // rlwinm ptr, ptr1, 0, 0, 29 4563 // slw incr2, incr, shift 4564 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 4565 // slw mask, mask2, shift 4566 // loopMBB: 4567 // lwarx tmpDest, ptr 4568 // add tmp, tmpDest, incr2 4569 // andc tmp2, tmpDest, mask 4570 // and tmp3, tmp, mask 4571 // or tmp4, tmp3, tmp2 4572 // stwcx. tmp4, ptr 4573 // bne- loopMBB 4574 // fallthrough --> exitMBB 4575 // srw dest, tmpDest, shift 4576 4577 if (ptrA!=PPC::R0) { 4578 Ptr1Reg = RegInfo.createVirtualRegister(RC); 4579 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 4580 .addReg(ptrA).addReg(ptrB); 4581 } else { 4582 Ptr1Reg = ptrB; 4583 } 4584 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 4585 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 4586 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 4587 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 4588 if (is64bit) 4589 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 4590 .addReg(Ptr1Reg).addImm(0).addImm(61); 4591 else 4592 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 4593 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 4594 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg) 4595 .addReg(incr).addReg(ShiftReg); 4596 if (is8bit) 4597 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 4598 else { 4599 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 4600 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535); 4601 } 4602 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 4603 .addReg(Mask2Reg).addReg(ShiftReg); 4604 4605 BB = loopMBB; 4606 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 4607 .addReg(PPC::R0).addReg(PtrReg); 4608 if (BinOpcode) 4609 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) 4610 .addReg(Incr2Reg).addReg(TmpDestReg); 4611 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) 4612 .addReg(TmpDestReg).addReg(MaskReg); 4613 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) 4614 .addReg(TmpReg).addReg(MaskReg); 4615 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) 4616 .addReg(Tmp3Reg).addReg(Tmp2Reg); 4617 BuildMI(BB, dl, TII->get(PPC::STWCX)) 4618 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg); 4619 BuildMI(BB, dl, TII->get(PPC::BCC)) 4620 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4621 BB->addSuccessor(loopMBB); 4622 BB->addSuccessor(exitMBB); 4623 4624 // exitMBB: 4625 // ... 4626 BB = exitMBB; 4627 BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg); 4628 return BB; 4629} 4630 4631MachineBasicBlock * 4632PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 4633 MachineBasicBlock *BB, 4634 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 4635 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4636 4637 // To "insert" these instructions we actually have to insert their 4638 // control-flow patterns. 4639 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4640 MachineFunction::iterator It = BB; 4641 ++It; 4642 4643 MachineFunction *F = BB->getParent(); 4644 4645 if (MI->getOpcode() == PPC::SELECT_CC_I4 || 4646 MI->getOpcode() == PPC::SELECT_CC_I8 || 4647 MI->getOpcode() == PPC::SELECT_CC_F4 || 4648 MI->getOpcode() == PPC::SELECT_CC_F8 || 4649 MI->getOpcode() == PPC::SELECT_CC_VRRC) { 4650 4651 // The incoming instruction knows the destination vreg to set, the 4652 // condition code register to branch on, the true/false values to 4653 // select between, and a branch opcode to use. 4654 4655 // thisMBB: 4656 // ... 4657 // TrueVal = ... 4658 // cmpTY ccX, r1, r2 4659 // bCC copy1MBB 4660 // fallthrough --> copy0MBB 4661 MachineBasicBlock *thisMBB = BB; 4662 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4663 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4664 unsigned SelectPred = MI->getOperand(4).getImm(); 4665 DebugLoc dl = MI->getDebugLoc(); 4666 BuildMI(BB, dl, TII->get(PPC::BCC)) 4667 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 4668 F->insert(It, copy0MBB); 4669 F->insert(It, sinkMBB); 4670 // Update machine-CFG edges by first adding all successors of the current 4671 // block to the new block which will contain the Phi node for the select. 4672 // Also inform sdisel of the edge changes. 4673 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), 4674 E = BB->succ_end(); I != E; ++I) { 4675 EM->insert(std::make_pair(*I, sinkMBB)); 4676 sinkMBB->addSuccessor(*I); 4677 } 4678 // Next, remove all successors of the current block, and add the true 4679 // and fallthrough blocks as its successors. 4680 while (!BB->succ_empty()) 4681 BB->removeSuccessor(BB->succ_begin()); 4682 // Next, add the true and fallthrough blocks as its successors. 4683 BB->addSuccessor(copy0MBB); 4684 BB->addSuccessor(sinkMBB); 4685 4686 // copy0MBB: 4687 // %FalseValue = ... 4688 // # fallthrough to sinkMBB 4689 BB = copy0MBB; 4690 4691 // Update machine-CFG edges 4692 BB->addSuccessor(sinkMBB); 4693 4694 // sinkMBB: 4695 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 4696 // ... 4697 BB = sinkMBB; 4698 BuildMI(BB, dl, TII->get(PPC::PHI), MI->getOperand(0).getReg()) 4699 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 4700 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 4701 } 4702 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) 4703 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); 4704 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) 4705 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); 4706 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) 4707 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4); 4708 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) 4709 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8); 4710 4711 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8) 4712 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); 4713 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16) 4714 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); 4715 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32) 4716 BB = EmitAtomicBinary(MI, BB, false, PPC::AND); 4717 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64) 4718 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8); 4719 4720 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8) 4721 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); 4722 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16) 4723 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); 4724 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32) 4725 BB = EmitAtomicBinary(MI, BB, false, PPC::OR); 4726 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64) 4727 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8); 4728 4729 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) 4730 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); 4731 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) 4732 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); 4733 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) 4734 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR); 4735 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) 4736 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8); 4737 4738 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) 4739 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC); 4740 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) 4741 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC); 4742 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) 4743 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC); 4744 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) 4745 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8); 4746 4747 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) 4748 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); 4749 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) 4750 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); 4751 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) 4752 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF); 4753 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) 4754 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8); 4755 4756 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8) 4757 BB = EmitPartwordAtomicBinary(MI, BB, true, 0); 4758 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16) 4759 BB = EmitPartwordAtomicBinary(MI, BB, false, 0); 4760 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32) 4761 BB = EmitAtomicBinary(MI, BB, false, 0); 4762 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64) 4763 BB = EmitAtomicBinary(MI, BB, true, 0); 4764 4765 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || 4766 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) { 4767 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; 4768 4769 unsigned dest = MI->getOperand(0).getReg(); 4770 unsigned ptrA = MI->getOperand(1).getReg(); 4771 unsigned ptrB = MI->getOperand(2).getReg(); 4772 unsigned oldval = MI->getOperand(3).getReg(); 4773 unsigned newval = MI->getOperand(4).getReg(); 4774 DebugLoc dl = MI->getDebugLoc(); 4775 4776 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 4777 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 4778 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 4779 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4780 F->insert(It, loop1MBB); 4781 F->insert(It, loop2MBB); 4782 F->insert(It, midMBB); 4783 F->insert(It, exitMBB); 4784 exitMBB->transferSuccessors(BB); 4785 4786 // thisMBB: 4787 // ... 4788 // fallthrough --> loopMBB 4789 BB->addSuccessor(loop1MBB); 4790 4791 // loop1MBB: 4792 // l[wd]arx dest, ptr 4793 // cmp[wd] dest, oldval 4794 // bne- midMBB 4795 // loop2MBB: 4796 // st[wd]cx. newval, ptr 4797 // bne- loopMBB 4798 // b exitBB 4799 // midMBB: 4800 // st[wd]cx. dest, ptr 4801 // exitBB: 4802 BB = loop1MBB; 4803 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4804 .addReg(ptrA).addReg(ptrB); 4805 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) 4806 .addReg(oldval).addReg(dest); 4807 BuildMI(BB, dl, TII->get(PPC::BCC)) 4808 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 4809 BB->addSuccessor(loop2MBB); 4810 BB->addSuccessor(midMBB); 4811 4812 BB = loop2MBB; 4813 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4814 .addReg(newval).addReg(ptrA).addReg(ptrB); 4815 BuildMI(BB, dl, TII->get(PPC::BCC)) 4816 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 4817 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 4818 BB->addSuccessor(loop1MBB); 4819 BB->addSuccessor(exitMBB); 4820 4821 BB = midMBB; 4822 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4823 .addReg(dest).addReg(ptrA).addReg(ptrB); 4824 BB->addSuccessor(exitMBB); 4825 4826 // exitMBB: 4827 // ... 4828 BB = exitMBB; 4829 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || 4830 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { 4831 // We must use 64-bit registers for addresses when targeting 64-bit, 4832 // since we're actually doing arithmetic on them. Other registers 4833 // can be 32-bit. 4834 bool is64bit = PPCSubTarget.isPPC64(); 4835 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; 4836 4837 unsigned dest = MI->getOperand(0).getReg(); 4838 unsigned ptrA = MI->getOperand(1).getReg(); 4839 unsigned ptrB = MI->getOperand(2).getReg(); 4840 unsigned oldval = MI->getOperand(3).getReg(); 4841 unsigned newval = MI->getOperand(4).getReg(); 4842 DebugLoc dl = MI->getDebugLoc(); 4843 4844 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 4845 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 4846 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 4847 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4848 F->insert(It, loop1MBB); 4849 F->insert(It, loop2MBB); 4850 F->insert(It, midMBB); 4851 F->insert(It, exitMBB); 4852 exitMBB->transferSuccessors(BB); 4853 4854 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4855 const TargetRegisterClass *RC = 4856 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4857 (const TargetRegisterClass *) &PPC::GPRCRegClass; 4858 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 4859 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 4860 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 4861 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC); 4862 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC); 4863 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC); 4864 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC); 4865 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 4866 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4867 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4868 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4869 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4870 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4871 unsigned Ptr1Reg; 4872 unsigned TmpReg = RegInfo.createVirtualRegister(RC); 4873 // thisMBB: 4874 // ... 4875 // fallthrough --> loopMBB 4876 BB->addSuccessor(loop1MBB); 4877 4878 // The 4-byte load must be aligned, while a char or short may be 4879 // anywhere in the word. Hence all this nasty bookkeeping code. 4880 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4881 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4882 // xori shift, shift1, 24 [16] 4883 // rlwinm ptr, ptr1, 0, 0, 29 4884 // slw newval2, newval, shift 4885 // slw oldval2, oldval,shift 4886 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 4887 // slw mask, mask2, shift 4888 // and newval3, newval2, mask 4889 // and oldval3, oldval2, mask 4890 // loop1MBB: 4891 // lwarx tmpDest, ptr 4892 // and tmp, tmpDest, mask 4893 // cmpw tmp, oldval3 4894 // bne- midMBB 4895 // loop2MBB: 4896 // andc tmp2, tmpDest, mask 4897 // or tmp4, tmp2, newval3 4898 // stwcx. tmp4, ptr 4899 // bne- loop1MBB 4900 // b exitBB 4901 // midMBB: 4902 // stwcx. tmpDest, ptr 4903 // exitBB: 4904 // srw dest, tmpDest, shift 4905 if (ptrA!=PPC::R0) { 4906 Ptr1Reg = RegInfo.createVirtualRegister(RC); 4907 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 4908 .addReg(ptrA).addReg(ptrB); 4909 } else { 4910 Ptr1Reg = ptrB; 4911 } 4912 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 4913 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 4914 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 4915 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 4916 if (is64bit) 4917 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 4918 .addReg(Ptr1Reg).addImm(0).addImm(61); 4919 else 4920 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 4921 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 4922 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) 4923 .addReg(newval).addReg(ShiftReg); 4924 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) 4925 .addReg(oldval).addReg(ShiftReg); 4926 if (is8bit) 4927 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 4928 else { 4929 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 4930 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) 4931 .addReg(Mask3Reg).addImm(65535); 4932 } 4933 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 4934 .addReg(Mask2Reg).addReg(ShiftReg); 4935 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg) 4936 .addReg(NewVal2Reg).addReg(MaskReg); 4937 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg) 4938 .addReg(OldVal2Reg).addReg(MaskReg); 4939 4940 BB = loop1MBB; 4941 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 4942 .addReg(PPC::R0).addReg(PtrReg); 4943 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) 4944 .addReg(TmpDestReg).addReg(MaskReg); 4945 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0) 4946 .addReg(TmpReg).addReg(OldVal3Reg); 4947 BuildMI(BB, dl, TII->get(PPC::BCC)) 4948 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 4949 BB->addSuccessor(loop2MBB); 4950 BB->addSuccessor(midMBB); 4951 4952 BB = loop2MBB; 4953 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg) 4954 .addReg(TmpDestReg).addReg(MaskReg); 4955 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg) 4956 .addReg(Tmp2Reg).addReg(NewVal3Reg); 4957 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg) 4958 .addReg(PPC::R0).addReg(PtrReg); 4959 BuildMI(BB, dl, TII->get(PPC::BCC)) 4960 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 4961 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 4962 BB->addSuccessor(loop1MBB); 4963 BB->addSuccessor(exitMBB); 4964 4965 BB = midMBB; 4966 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg) 4967 .addReg(PPC::R0).addReg(PtrReg); 4968 BB->addSuccessor(exitMBB); 4969 4970 // exitMBB: 4971 // ... 4972 BB = exitMBB; 4973 BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg); 4974 } else { 4975 llvm_unreachable("Unexpected instr type to insert"); 4976 } 4977 4978 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 4979 return BB; 4980} 4981 4982//===----------------------------------------------------------------------===// 4983// Target Optimization Hooks 4984//===----------------------------------------------------------------------===// 4985 4986SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, 4987 DAGCombinerInfo &DCI) const { 4988 TargetMachine &TM = getTargetMachine(); 4989 SelectionDAG &DAG = DCI.DAG; 4990 DebugLoc dl = N->getDebugLoc(); 4991 switch (N->getOpcode()) { 4992 default: break; 4993 case PPCISD::SHL: 4994 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 4995 if (C->getZExtValue() == 0) // 0 << V -> 0. 4996 return N->getOperand(0); 4997 } 4998 break; 4999 case PPCISD::SRL: 5000 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5001 if (C->getZExtValue() == 0) // 0 >>u V -> 0. 5002 return N->getOperand(0); 5003 } 5004 break; 5005 case PPCISD::SRA: 5006 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5007 if (C->getZExtValue() == 0 || // 0 >>s V -> 0. 5008 C->isAllOnesValue()) // -1 >>s V -> -1. 5009 return N->getOperand(0); 5010 } 5011 break; 5012 5013 case ISD::SINT_TO_FP: 5014 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 5015 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 5016 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 5017 // We allow the src/dst to be either f32/f64, but the intermediate 5018 // type must be i64. 5019 if (N->getOperand(0).getValueType() == MVT::i64 && 5020 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 5021 SDValue Val = N->getOperand(0).getOperand(0); 5022 if (Val.getValueType() == MVT::f32) { 5023 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 5024 DCI.AddToWorklist(Val.getNode()); 5025 } 5026 5027 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val); 5028 DCI.AddToWorklist(Val.getNode()); 5029 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val); 5030 DCI.AddToWorklist(Val.getNode()); 5031 if (N->getValueType(0) == MVT::f32) { 5032 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val, 5033 DAG.getIntPtrConstant(0)); 5034 DCI.AddToWorklist(Val.getNode()); 5035 } 5036 return Val; 5037 } else if (N->getOperand(0).getValueType() == MVT::i32) { 5038 // If the intermediate type is i32, we can avoid the load/store here 5039 // too. 5040 } 5041 } 5042 } 5043 break; 5044 case ISD::STORE: 5045 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 5046 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 5047 !cast<StoreSDNode>(N)->isTruncatingStore() && 5048 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 5049 N->getOperand(1).getValueType() == MVT::i32 && 5050 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 5051 SDValue Val = N->getOperand(1).getOperand(0); 5052 if (Val.getValueType() == MVT::f32) { 5053 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 5054 DCI.AddToWorklist(Val.getNode()); 5055 } 5056 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); 5057 DCI.AddToWorklist(Val.getNode()); 5058 5059 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val, 5060 N->getOperand(2), N->getOperand(3)); 5061 DCI.AddToWorklist(Val.getNode()); 5062 return Val; 5063 } 5064 5065 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 5066 if (cast<StoreSDNode>(N)->isUnindexed() && 5067 N->getOperand(1).getOpcode() == ISD::BSWAP && 5068 N->getOperand(1).getNode()->hasOneUse() && 5069 (N->getOperand(1).getValueType() == MVT::i32 || 5070 N->getOperand(1).getValueType() == MVT::i16)) { 5071 SDValue BSwapOp = N->getOperand(1).getOperand(0); 5072 // Do an any-extend to 32-bits if this is a half-word input. 5073 if (BSwapOp.getValueType() == MVT::i16) 5074 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); 5075 5076 SDValue Ops[] = { 5077 N->getOperand(0), BSwapOp, N->getOperand(2), 5078 DAG.getValueType(N->getOperand(1).getValueType()) 5079 }; 5080 return 5081 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), 5082 Ops, array_lengthof(Ops), 5083 cast<StoreSDNode>(N)->getMemoryVT(), 5084 cast<StoreSDNode>(N)->getMemOperand()); 5085 } 5086 break; 5087 case ISD::BSWAP: 5088 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 5089 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) && 5090 N->getOperand(0).hasOneUse() && 5091 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 5092 SDValue Load = N->getOperand(0); 5093 LoadSDNode *LD = cast<LoadSDNode>(Load); 5094 // Create the byte-swapping load. 5095 SDValue Ops[] = { 5096 LD->getChain(), // Chain 5097 LD->getBasePtr(), // Ptr 5098 DAG.getValueType(N->getValueType(0)) // VT 5099 }; 5100 SDValue BSLoad = 5101 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl, 5102 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3, 5103 LD->getMemoryVT(), LD->getMemOperand()); 5104 5105 // If this is an i16 load, insert the truncate. 5106 SDValue ResVal = BSLoad; 5107 if (N->getValueType(0) == MVT::i16) 5108 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); 5109 5110 // First, combine the bswap away. This makes the value produced by the 5111 // load dead. 5112 DCI.CombineTo(N, ResVal); 5113 5114 // Next, combine the load away, we give it a bogus result value but a real 5115 // chain result. The result value is dead because the bswap is dead. 5116 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1)); 5117 5118 // Return N so it doesn't get rechecked! 5119 return SDValue(N, 0); 5120 } 5121 5122 break; 5123 case PPCISD::VCMP: { 5124 // If a VCMPo node already exists with exactly the same operands as this 5125 // node, use its result instead of this node (VCMPo computes both a CR6 and 5126 // a normal output). 5127 // 5128 if (!N->getOperand(0).hasOneUse() && 5129 !N->getOperand(1).hasOneUse() && 5130 !N->getOperand(2).hasOneUse()) { 5131 5132 // Scan all of the users of the LHS, looking for VCMPo's that match. 5133 SDNode *VCMPoNode = 0; 5134 5135 SDNode *LHSN = N->getOperand(0).getNode(); 5136 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 5137 UI != E; ++UI) 5138 if (UI->getOpcode() == PPCISD::VCMPo && 5139 UI->getOperand(1) == N->getOperand(1) && 5140 UI->getOperand(2) == N->getOperand(2) && 5141 UI->getOperand(0) == N->getOperand(0)) { 5142 VCMPoNode = *UI; 5143 break; 5144 } 5145 5146 // If there is no VCMPo node, or if the flag value has a single use, don't 5147 // transform this. 5148 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 5149 break; 5150 5151 // Look at the (necessarily single) use of the flag value. If it has a 5152 // chain, this transformation is more complex. Note that multiple things 5153 // could use the value result, which we should ignore. 5154 SDNode *FlagUser = 0; 5155 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 5156 FlagUser == 0; ++UI) { 5157 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 5158 SDNode *User = *UI; 5159 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 5160 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) { 5161 FlagUser = User; 5162 break; 5163 } 5164 } 5165 } 5166 5167 // If the user is a MFCR instruction, we know this is safe. Otherwise we 5168 // give up for right now. 5169 if (FlagUser->getOpcode() == PPCISD::MFCR) 5170 return SDValue(VCMPoNode, 0); 5171 } 5172 break; 5173 } 5174 case ISD::BR_CC: { 5175 // If this is a branch on an altivec predicate comparison, lower this so 5176 // that we don't have to do a MFCR: instead, branch directly on CR6. This 5177 // lowering is done pre-legalize, because the legalizer lowers the predicate 5178 // compare down to code that is difficult to reassemble. 5179 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 5180 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 5181 int CompareOpc; 5182 bool isDot; 5183 5184 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 5185 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 5186 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 5187 assert(isDot && "Can't compare against a vector result!"); 5188 5189 // If this is a comparison against something other than 0/1, then we know 5190 // that the condition is never/always true. 5191 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue(); 5192 if (Val != 0 && Val != 1) { 5193 if (CC == ISD::SETEQ) // Cond never true, remove branch. 5194 return N->getOperand(0); 5195 // Always !=, turn it into an unconditional branch. 5196 return DAG.getNode(ISD::BR, dl, MVT::Other, 5197 N->getOperand(0), N->getOperand(4)); 5198 } 5199 5200 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 5201 5202 // Create the PPCISD altivec 'dot' comparison node. 5203 std::vector<EVT> VTs; 5204 SDValue Ops[] = { 5205 LHS.getOperand(2), // LHS of compare 5206 LHS.getOperand(3), // RHS of compare 5207 DAG.getConstant(CompareOpc, MVT::i32) 5208 }; 5209 VTs.push_back(LHS.getOperand(2).getValueType()); 5210 VTs.push_back(MVT::Flag); 5211 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 5212 5213 // Unpack the result based on how the target uses it. 5214 PPC::Predicate CompOpc; 5215 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) { 5216 default: // Can't happen, don't crash on invalid number though. 5217 case 0: // Branch on the value of the EQ bit of CR6. 5218 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 5219 break; 5220 case 1: // Branch on the inverted value of the EQ bit of CR6. 5221 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 5222 break; 5223 case 2: // Branch on the value of the LT bit of CR6. 5224 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 5225 break; 5226 case 3: // Branch on the inverted value of the LT bit of CR6. 5227 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 5228 break; 5229 } 5230 5231 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), 5232 DAG.getConstant(CompOpc, MVT::i32), 5233 DAG.getRegister(PPC::CR6, MVT::i32), 5234 N->getOperand(4), CompNode.getValue(1)); 5235 } 5236 break; 5237 } 5238 } 5239 5240 return SDValue(); 5241} 5242 5243//===----------------------------------------------------------------------===// 5244// Inline Assembly Support 5245//===----------------------------------------------------------------------===// 5246 5247void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 5248 const APInt &Mask, 5249 APInt &KnownZero, 5250 APInt &KnownOne, 5251 const SelectionDAG &DAG, 5252 unsigned Depth) const { 5253 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 5254 switch (Op.getOpcode()) { 5255 default: break; 5256 case PPCISD::LBRX: { 5257 // lhbrx is known to have the top bits cleared out. 5258 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) 5259 KnownZero = 0xFFFF0000; 5260 break; 5261 } 5262 case ISD::INTRINSIC_WO_CHAIN: { 5263 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) { 5264 default: break; 5265 case Intrinsic::ppc_altivec_vcmpbfp_p: 5266 case Intrinsic::ppc_altivec_vcmpeqfp_p: 5267 case Intrinsic::ppc_altivec_vcmpequb_p: 5268 case Intrinsic::ppc_altivec_vcmpequh_p: 5269 case Intrinsic::ppc_altivec_vcmpequw_p: 5270 case Intrinsic::ppc_altivec_vcmpgefp_p: 5271 case Intrinsic::ppc_altivec_vcmpgtfp_p: 5272 case Intrinsic::ppc_altivec_vcmpgtsb_p: 5273 case Intrinsic::ppc_altivec_vcmpgtsh_p: 5274 case Intrinsic::ppc_altivec_vcmpgtsw_p: 5275 case Intrinsic::ppc_altivec_vcmpgtub_p: 5276 case Intrinsic::ppc_altivec_vcmpgtuh_p: 5277 case Intrinsic::ppc_altivec_vcmpgtuw_p: 5278 KnownZero = ~1U; // All bits but the low one are known to be zero. 5279 break; 5280 } 5281 } 5282 } 5283} 5284 5285 5286/// getConstraintType - Given a constraint, return the type of 5287/// constraint it is for this target. 5288PPCTargetLowering::ConstraintType 5289PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 5290 if (Constraint.size() == 1) { 5291 switch (Constraint[0]) { 5292 default: break; 5293 case 'b': 5294 case 'r': 5295 case 'f': 5296 case 'v': 5297 case 'y': 5298 return C_RegisterClass; 5299 } 5300 } 5301 return TargetLowering::getConstraintType(Constraint); 5302} 5303 5304std::pair<unsigned, const TargetRegisterClass*> 5305PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 5306 EVT VT) const { 5307 if (Constraint.size() == 1) { 5308 // GCC RS6000 Constraint Letters 5309 switch (Constraint[0]) { 5310 case 'b': // R1-R31 5311 case 'r': // R0-R31 5312 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 5313 return std::make_pair(0U, PPC::G8RCRegisterClass); 5314 return std::make_pair(0U, PPC::GPRCRegisterClass); 5315 case 'f': 5316 if (VT == MVT::f32) 5317 return std::make_pair(0U, PPC::F4RCRegisterClass); 5318 else if (VT == MVT::f64) 5319 return std::make_pair(0U, PPC::F8RCRegisterClass); 5320 break; 5321 case 'v': 5322 return std::make_pair(0U, PPC::VRRCRegisterClass); 5323 case 'y': // crrc 5324 return std::make_pair(0U, PPC::CRRCRegisterClass); 5325 } 5326 } 5327 5328 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 5329} 5330 5331 5332/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 5333/// vector. If it is invalid, don't add anything to Ops. If hasMemory is true 5334/// it means one of the asm constraint of the inline asm instruction being 5335/// processed is 'm'. 5336void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter, 5337 bool hasMemory, 5338 std::vector<SDValue>&Ops, 5339 SelectionDAG &DAG) const { 5340 SDValue Result(0,0); 5341 switch (Letter) { 5342 default: break; 5343 case 'I': 5344 case 'J': 5345 case 'K': 5346 case 'L': 5347 case 'M': 5348 case 'N': 5349 case 'O': 5350 case 'P': { 5351 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 5352 if (!CST) return; // Must be an immediate to match. 5353 unsigned Value = CST->getZExtValue(); 5354 switch (Letter) { 5355 default: llvm_unreachable("Unknown constraint letter!"); 5356 case 'I': // "I" is a signed 16-bit constant. 5357 if ((short)Value == (int)Value) 5358 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5359 break; 5360 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 5361 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 5362 if ((short)Value == 0) 5363 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5364 break; 5365 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 5366 if ((Value >> 16) == 0) 5367 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5368 break; 5369 case 'M': // "M" is a constant that is greater than 31. 5370 if (Value > 31) 5371 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5372 break; 5373 case 'N': // "N" is a positive constant that is an exact power of two. 5374 if ((int)Value > 0 && isPowerOf2_32(Value)) 5375 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5376 break; 5377 case 'O': // "O" is the constant zero. 5378 if (Value == 0) 5379 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5380 break; 5381 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 5382 if ((short)-Value == (int)-Value) 5383 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5384 break; 5385 } 5386 break; 5387 } 5388 } 5389 5390 if (Result.getNode()) { 5391 Ops.push_back(Result); 5392 return; 5393 } 5394 5395 // Handle standard constraint letters. 5396 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, hasMemory, Ops, DAG); 5397} 5398 5399// isLegalAddressingMode - Return true if the addressing mode represented 5400// by AM is legal for this target, for a load/store of the specified type. 5401bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 5402 const Type *Ty) const { 5403 // FIXME: PPC does not allow r+i addressing modes for vectors! 5404 5405 // PPC allows a sign-extended 16-bit immediate field. 5406 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 5407 return false; 5408 5409 // No global is ever allowed as a base. 5410 if (AM.BaseGV) 5411 return false; 5412 5413 // PPC only support r+r, 5414 switch (AM.Scale) { 5415 case 0: // "r+i" or just "i", depending on HasBaseReg. 5416 break; 5417 case 1: 5418 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 5419 return false; 5420 // Otherwise we have r+r or r+i. 5421 break; 5422 case 2: 5423 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 5424 return false; 5425 // Allow 2*r as r+r. 5426 break; 5427 default: 5428 // No other scales are supported. 5429 return false; 5430 } 5431 5432 return true; 5433} 5434 5435/// isLegalAddressImmediate - Return true if the integer value can be used 5436/// as the offset of the target addressing mode for load / store of the 5437/// given type. 5438bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{ 5439 // PPC allows a sign-extended 16-bit immediate field. 5440 return (V > -(1 << 16) && V < (1 << 16)-1); 5441} 5442 5443bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 5444 return false; 5445} 5446 5447SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 5448 DebugLoc dl = Op.getDebugLoc(); 5449 // Depths > 0 not supported yet! 5450 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) 5451 return SDValue(); 5452 5453 MachineFunction &MF = DAG.getMachineFunction(); 5454 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 5455 5456 // Just load the return address off the stack. 5457 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); 5458 5459 // Make sure the function really does not optimize away the store of the RA 5460 // to the stack. 5461 FuncInfo->setLRStoreRequired(); 5462 return DAG.getLoad(getPointerTy(), dl, 5463 DAG.getEntryNode(), RetAddrFI, NULL, 0); 5464} 5465 5466SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 5467 DebugLoc dl = Op.getDebugLoc(); 5468 // Depths > 0 not supported yet! 5469 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) 5470 return SDValue(); 5471 5472 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 5473 bool isPPC64 = PtrVT == MVT::i64; 5474 5475 MachineFunction &MF = DAG.getMachineFunction(); 5476 MachineFrameInfo *MFI = MF.getFrameInfo(); 5477 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects()) 5478 && MFI->getStackSize(); 5479 5480 if (isPPC64) 5481 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1, 5482 MVT::i64); 5483 else 5484 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1, 5485 MVT::i32); 5486} 5487 5488bool 5489PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 5490 // The PowerPC target isn't yet aware of offsets. 5491 return false; 5492} 5493 5494EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align, 5495 bool isSrcConst, bool isSrcStr, 5496 SelectionDAG &DAG) const { 5497 if (this->PPCSubTarget.isPPC64()) { 5498 return MVT::i64; 5499 } else { 5500 return MVT::i32; 5501 } 5502} 5503