PPCISelLowering.cpp revision b10308e440c80dd6ffb4b478f741ff7e5f30cb48
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPredicates.h" 17#include "PPCTargetMachine.h" 18#include "PPCPerfectShuffle.h" 19#include "llvm/ADT/VectorExtras.h" 20#include "llvm/Analysis/ScalarEvolutionExpressions.h" 21#include "llvm/CodeGen/MachineFrameInfo.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineInstrBuilder.h" 24#include "llvm/CodeGen/SelectionDAG.h" 25#include "llvm/CodeGen/SSARegMap.h" 26#include "llvm/Constants.h" 27#include "llvm/Function.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/Support/MathExtras.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/Support/CommandLine.h" 32using namespace llvm; 33 34static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc"); 35 36PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 37 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { 38 39 setPow2DivIsCheap(); 40 41 // Use _setjmp/_longjmp instead of setjmp/longjmp. 42 setUseUnderscoreSetJmp(true); 43 setUseUnderscoreLongJmp(true); 44 45 // Set up the register classes. 46 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 47 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 48 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 49 50 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 51 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand); 52 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); 53 54 // PowerPC does not have truncstore for i1. 55 setStoreXAction(MVT::i1, Promote); 56 57 // PowerPC has pre-inc load and store's. 58 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 59 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 60 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 61 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 62 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 63 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 64 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 65 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 66 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 67 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 68 69 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 70 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 71 72 // PowerPC has no intrinsics for these particular operations 73 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 74 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 75 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 76 77 // PowerPC has no SREM/UREM instructions 78 setOperationAction(ISD::SREM, MVT::i32, Expand); 79 setOperationAction(ISD::UREM, MVT::i32, Expand); 80 setOperationAction(ISD::SREM, MVT::i64, Expand); 81 setOperationAction(ISD::UREM, MVT::i64, Expand); 82 83 // We don't support sin/cos/sqrt/fmod 84 setOperationAction(ISD::FSIN , MVT::f64, Expand); 85 setOperationAction(ISD::FCOS , MVT::f64, Expand); 86 setOperationAction(ISD::FREM , MVT::f64, Expand); 87 setOperationAction(ISD::FSIN , MVT::f32, Expand); 88 setOperationAction(ISD::FCOS , MVT::f32, Expand); 89 setOperationAction(ISD::FREM , MVT::f32, Expand); 90 91 // If we're enabling GP optimizations, use hardware square root 92 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 93 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 94 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 95 } 96 97 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 98 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 99 100 // PowerPC does not have BSWAP, CTPOP or CTTZ 101 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 102 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 103 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 104 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 105 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 106 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 107 108 // PowerPC does not have ROTR 109 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 110 111 // PowerPC does not have Select 112 setOperationAction(ISD::SELECT, MVT::i32, Expand); 113 setOperationAction(ISD::SELECT, MVT::i64, Expand); 114 setOperationAction(ISD::SELECT, MVT::f32, Expand); 115 setOperationAction(ISD::SELECT, MVT::f64, Expand); 116 117 // PowerPC wants to turn select_cc of FP into fsel when possible. 118 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 119 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 120 121 // PowerPC wants to optimize integer setcc a bit 122 setOperationAction(ISD::SETCC, MVT::i32, Custom); 123 124 // PowerPC does not have BRCOND which requires SetCC 125 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 126 127 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 128 129 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 130 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 131 132 // PowerPC does not have [U|S]INT_TO_FP 133 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 134 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 135 136 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 137 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 138 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 139 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 140 141 // We cannot sextinreg(i1). Expand to shifts. 142 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 143 144 145 // Support label based line numbers. 146 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 147 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 148 // FIXME - use subtarget debug flags 149 if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) 150 setOperationAction(ISD::LABEL, MVT::Other, Expand); 151 152 // We want to legalize GlobalAddress and ConstantPool nodes into the 153 // appropriate instructions to materialize the address. 154 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 155 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 156 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 157 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 158 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 159 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 160 161 // RET must be custom lowered, to meet ABI requirements 162 setOperationAction(ISD::RET , MVT::Other, Custom); 163 164 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 165 setOperationAction(ISD::VASTART , MVT::Other, Custom); 166 167 // Use the default implementation. 168 setOperationAction(ISD::VAARG , MVT::Other, Expand); 169 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 170 setOperationAction(ISD::VAEND , MVT::Other, Expand); 171 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 172 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 173 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 174 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 175 176 // We want to custom lower some of our intrinsics. 177 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 178 179 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 180 // They also have instructions for converting between i64 and fp. 181 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 182 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 183 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 184 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 185 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 186 187 // FIXME: disable this lowered code. This generates 64-bit register values, 188 // and we don't model the fact that the top part is clobbered by calls. We 189 // need to flag these together so that the value isn't live across a call. 190 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 191 192 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 193 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 194 } else { 195 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 196 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 197 } 198 199 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 200 // 64 bit PowerPC implementations can support i64 types directly 201 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 202 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 203 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 204 } else { 205 // 32 bit PowerPC wants to expand i64 shifts itself. 206 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 207 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 208 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 209 } 210 211 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 212 // First set operation action for all vector types to expand. Then we 213 // will selectively turn on ones that can be effectively codegen'd. 214 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 215 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 216 // add/sub are legal for all supported vector VT's. 217 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); 218 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); 219 220 // We promote all shuffles to v16i8. 221 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); 222 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); 223 224 // We promote all non-typed operations to v4i32. 225 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote); 226 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32); 227 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote); 228 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32); 229 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote); 230 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32); 231 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote); 232 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32); 233 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); 234 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32); 235 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote); 236 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32); 237 238 // No other operations are legal. 239 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); 240 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); 241 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); 242 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); 243 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); 244 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); 245 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 246 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 247 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); 248 249 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); 250 } 251 252 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 253 // with merges, splats, etc. 254 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 255 256 setOperationAction(ISD::AND , MVT::v4i32, Legal); 257 setOperationAction(ISD::OR , MVT::v4i32, Legal); 258 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 259 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 260 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 261 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 262 263 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 264 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 265 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 266 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 267 268 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 269 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 270 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 271 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 272 273 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 274 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 275 276 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 277 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 278 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 279 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 280 } 281 282 setSetCCResultType(MVT::i32); 283 setShiftAmountType(MVT::i32); 284 setSetCCResultContents(ZeroOrOneSetCCResult); 285 286 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) 287 setStackPointerRegisterToSaveRestore(PPC::X1); 288 else 289 setStackPointerRegisterToSaveRestore(PPC::R1); 290 291 // We have target-specific dag combine patterns for the following nodes: 292 setTargetDAGCombine(ISD::SINT_TO_FP); 293 setTargetDAGCombine(ISD::STORE); 294 setTargetDAGCombine(ISD::BR_CC); 295 setTargetDAGCombine(ISD::BSWAP); 296 297 computeRegisterProperties(); 298} 299 300const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 301 switch (Opcode) { 302 default: return 0; 303 case PPCISD::FSEL: return "PPCISD::FSEL"; 304 case PPCISD::FCFID: return "PPCISD::FCFID"; 305 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 306 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 307 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 308 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 309 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 310 case PPCISD::VPERM: return "PPCISD::VPERM"; 311 case PPCISD::Hi: return "PPCISD::Hi"; 312 case PPCISD::Lo: return "PPCISD::Lo"; 313 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 314 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 315 case PPCISD::SRL: return "PPCISD::SRL"; 316 case PPCISD::SRA: return "PPCISD::SRA"; 317 case PPCISD::SHL: return "PPCISD::SHL"; 318 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 319 case PPCISD::STD_32: return "PPCISD::STD_32"; 320 case PPCISD::CALL: return "PPCISD::CALL"; 321 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 322 case PPCISD::BCTRL: return "PPCISD::BCTRL"; 323 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 324 case PPCISD::MFCR: return "PPCISD::MFCR"; 325 case PPCISD::VCMP: return "PPCISD::VCMP"; 326 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 327 case PPCISD::LBRX: return "PPCISD::LBRX"; 328 case PPCISD::STBRX: return "PPCISD::STBRX"; 329 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 330 } 331} 332 333//===----------------------------------------------------------------------===// 334// Node matching predicates, for use by the tblgen matching code. 335//===----------------------------------------------------------------------===// 336 337/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 338static bool isFloatingPointZero(SDOperand Op) { 339 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 340 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 341 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { 342 // Maybe this has already been legalized into the constant pool? 343 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 344 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 345 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 346 } 347 return false; 348} 349 350/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 351/// true if Op is undef or if it matches the specified value. 352static bool isConstantOrUndef(SDOperand Op, unsigned Val) { 353 return Op.getOpcode() == ISD::UNDEF || 354 cast<ConstantSDNode>(Op)->getValue() == Val; 355} 356 357/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 358/// VPKUHUM instruction. 359bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { 360 if (!isUnary) { 361 for (unsigned i = 0; i != 16; ++i) 362 if (!isConstantOrUndef(N->getOperand(i), i*2+1)) 363 return false; 364 } else { 365 for (unsigned i = 0; i != 8; ++i) 366 if (!isConstantOrUndef(N->getOperand(i), i*2+1) || 367 !isConstantOrUndef(N->getOperand(i+8), i*2+1)) 368 return false; 369 } 370 return true; 371} 372 373/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 374/// VPKUWUM instruction. 375bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { 376 if (!isUnary) { 377 for (unsigned i = 0; i != 16; i += 2) 378 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 379 !isConstantOrUndef(N->getOperand(i+1), i*2+3)) 380 return false; 381 } else { 382 for (unsigned i = 0; i != 8; i += 2) 383 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 384 !isConstantOrUndef(N->getOperand(i+1), i*2+3) || 385 !isConstantOrUndef(N->getOperand(i+8), i*2+2) || 386 !isConstantOrUndef(N->getOperand(i+9), i*2+3)) 387 return false; 388 } 389 return true; 390} 391 392/// isVMerge - Common function, used to match vmrg* shuffles. 393/// 394static bool isVMerge(SDNode *N, unsigned UnitSize, 395 unsigned LHSStart, unsigned RHSStart) { 396 assert(N->getOpcode() == ISD::BUILD_VECTOR && 397 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 398 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 399 "Unsupported merge size!"); 400 401 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 402 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 403 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), 404 LHSStart+j+i*UnitSize) || 405 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), 406 RHSStart+j+i*UnitSize)) 407 return false; 408 } 409 return true; 410} 411 412/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 413/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 414bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 415 if (!isUnary) 416 return isVMerge(N, UnitSize, 8, 24); 417 return isVMerge(N, UnitSize, 8, 8); 418} 419 420/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 421/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 422bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 423 if (!isUnary) 424 return isVMerge(N, UnitSize, 0, 16); 425 return isVMerge(N, UnitSize, 0, 0); 426} 427 428 429/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 430/// amount, otherwise return -1. 431int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 432 assert(N->getOpcode() == ISD::BUILD_VECTOR && 433 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 434 // Find the first non-undef value in the shuffle mask. 435 unsigned i; 436 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) 437 /*search*/; 438 439 if (i == 16) return -1; // all undef. 440 441 // Otherwise, check to see if the rest of the elements are consequtively 442 // numbered from this value. 443 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue(); 444 if (ShiftAmt < i) return -1; 445 ShiftAmt -= i; 446 447 if (!isUnary) { 448 // Check the rest of the elements to see if they are consequtive. 449 for (++i; i != 16; ++i) 450 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) 451 return -1; 452 } else { 453 // Check the rest of the elements to see if they are consequtive. 454 for (++i; i != 16; ++i) 455 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) 456 return -1; 457 } 458 459 return ShiftAmt; 460} 461 462/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 463/// specifies a splat of a single element that is suitable for input to 464/// VSPLTB/VSPLTH/VSPLTW. 465bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { 466 assert(N->getOpcode() == ISD::BUILD_VECTOR && 467 N->getNumOperands() == 16 && 468 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 469 470 // This is a splat operation if each element of the permute is the same, and 471 // if the value doesn't reference the second vector. 472 unsigned ElementBase = 0; 473 SDOperand Elt = N->getOperand(0); 474 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) 475 ElementBase = EltV->getValue(); 476 else 477 return false; // FIXME: Handle UNDEF elements too! 478 479 if (cast<ConstantSDNode>(Elt)->getValue() >= 16) 480 return false; 481 482 // Check that they are consequtive. 483 for (unsigned i = 1; i != EltSize; ++i) { 484 if (!isa<ConstantSDNode>(N->getOperand(i)) || 485 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase) 486 return false; 487 } 488 489 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); 490 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 491 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 492 assert(isa<ConstantSDNode>(N->getOperand(i)) && 493 "Invalid VECTOR_SHUFFLE mask!"); 494 for (unsigned j = 0; j != EltSize; ++j) 495 if (N->getOperand(i+j) != N->getOperand(j)) 496 return false; 497 } 498 499 return true; 500} 501 502/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 503/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 504unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 505 assert(isSplatShuffleMask(N, EltSize)); 506 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize; 507} 508 509/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 510/// by using a vspltis[bhw] instruction of the specified element size, return 511/// the constant being splatted. The ByteSize field indicates the number of 512/// bytes of each element [124] -> [bhw]. 513SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 514 SDOperand OpVal(0, 0); 515 516 // If ByteSize of the splat is bigger than the element size of the 517 // build_vector, then we have a case where we are checking for a splat where 518 // multiple elements of the buildvector are folded together into a single 519 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 520 unsigned EltSize = 16/N->getNumOperands(); 521 if (EltSize < ByteSize) { 522 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 523 SDOperand UniquedVals[4]; 524 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 525 526 // See if all of the elements in the buildvector agree across. 527 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 528 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 529 // If the element isn't a constant, bail fully out. 530 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand(); 531 532 533 if (UniquedVals[i&(Multiple-1)].Val == 0) 534 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 535 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 536 return SDOperand(); // no match. 537 } 538 539 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 540 // either constant or undef values that are identical for each chunk. See 541 // if these chunks can form into a larger vspltis*. 542 543 // Check to see if all of the leading entries are either 0 or -1. If 544 // neither, then this won't fit into the immediate field. 545 bool LeadingZero = true; 546 bool LeadingOnes = true; 547 for (unsigned i = 0; i != Multiple-1; ++i) { 548 if (UniquedVals[i].Val == 0) continue; // Must have been undefs. 549 550 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 551 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 552 } 553 // Finally, check the least significant entry. 554 if (LeadingZero) { 555 if (UniquedVals[Multiple-1].Val == 0) 556 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 557 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue(); 558 if (Val < 16) 559 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 560 } 561 if (LeadingOnes) { 562 if (UniquedVals[Multiple-1].Val == 0) 563 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 564 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended(); 565 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 566 return DAG.getTargetConstant(Val, MVT::i32); 567 } 568 569 return SDOperand(); 570 } 571 572 // Check to see if this buildvec has a single non-undef value in its elements. 573 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 574 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 575 if (OpVal.Val == 0) 576 OpVal = N->getOperand(i); 577 else if (OpVal != N->getOperand(i)) 578 return SDOperand(); 579 } 580 581 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def. 582 583 unsigned ValSizeInBytes = 0; 584 uint64_t Value = 0; 585 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 586 Value = CN->getValue(); 587 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8; 588 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 589 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 590 Value = FloatToBits(CN->getValue()); 591 ValSizeInBytes = 4; 592 } 593 594 // If the splat value is larger than the element value, then we can never do 595 // this splat. The only case that we could fit the replicated bits into our 596 // immediate field for would be zero, and we prefer to use vxor for it. 597 if (ValSizeInBytes < ByteSize) return SDOperand(); 598 599 // If the element value is larger than the splat value, cut it in half and 600 // check to see if the two halves are equal. Continue doing this until we 601 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 602 while (ValSizeInBytes > ByteSize) { 603 ValSizeInBytes >>= 1; 604 605 // If the top half equals the bottom half, we're still ok. 606 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 607 (Value & ((1 << (8*ValSizeInBytes))-1))) 608 return SDOperand(); 609 } 610 611 // Properly sign extend the value. 612 int ShAmt = (4-ByteSize)*8; 613 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 614 615 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 616 if (MaskVal == 0) return SDOperand(); 617 618 // Finally, if this value fits in a 5 bit sext field, return it 619 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 620 return DAG.getTargetConstant(MaskVal, MVT::i32); 621 return SDOperand(); 622} 623 624//===----------------------------------------------------------------------===// 625// Addressing Mode Selection 626//===----------------------------------------------------------------------===// 627 628/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 629/// or 64-bit immediate, and if the value can be accurately represented as a 630/// sign extension from a 16-bit value. If so, this returns true and the 631/// immediate. 632static bool isIntS16Immediate(SDNode *N, short &Imm) { 633 if (N->getOpcode() != ISD::Constant) 634 return false; 635 636 Imm = (short)cast<ConstantSDNode>(N)->getValue(); 637 if (N->getValueType(0) == MVT::i32) 638 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue(); 639 else 640 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue(); 641} 642static bool isIntS16Immediate(SDOperand Op, short &Imm) { 643 return isIntS16Immediate(Op.Val, Imm); 644} 645 646 647/// SelectAddressRegReg - Given the specified addressed, check to see if it 648/// can be represented as an indexed [r+r] operation. Returns false if it 649/// can be more efficiently represented with [r+imm]. 650bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base, 651 SDOperand &Index, 652 SelectionDAG &DAG) { 653 short imm = 0; 654 if (N.getOpcode() == ISD::ADD) { 655 if (isIntS16Immediate(N.getOperand(1), imm)) 656 return false; // r+i 657 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 658 return false; // r+i 659 660 Base = N.getOperand(0); 661 Index = N.getOperand(1); 662 return true; 663 } else if (N.getOpcode() == ISD::OR) { 664 if (isIntS16Immediate(N.getOperand(1), imm)) 665 return false; // r+i can fold it if we can. 666 667 // If this is an or of disjoint bitfields, we can codegen this as an add 668 // (for better address arithmetic) if the LHS and RHS of the OR are provably 669 // disjoint. 670 uint64_t LHSKnownZero, LHSKnownOne; 671 uint64_t RHSKnownZero, RHSKnownOne; 672 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 673 674 if (LHSKnownZero) { 675 ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne); 676 // If all of the bits are known zero on the LHS or RHS, the add won't 677 // carry. 678 if ((LHSKnownZero | RHSKnownZero) == ~0U) { 679 Base = N.getOperand(0); 680 Index = N.getOperand(1); 681 return true; 682 } 683 } 684 } 685 686 return false; 687} 688 689/// Returns true if the address N can be represented by a base register plus 690/// a signed 16-bit displacement [r+imm], and if it is not better 691/// represented as reg+reg. 692bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp, 693 SDOperand &Base, SelectionDAG &DAG){ 694 // If this can be more profitably realized as r+r, fail. 695 if (SelectAddressRegReg(N, Disp, Base, DAG)) 696 return false; 697 698 if (N.getOpcode() == ISD::ADD) { 699 short imm = 0; 700 if (isIntS16Immediate(N.getOperand(1), imm)) { 701 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 702 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 703 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 704 } else { 705 Base = N.getOperand(0); 706 } 707 return true; // [r+i] 708 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 709 // Match LOAD (ADD (X, Lo(G))). 710 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 711 && "Cannot handle constant offsets yet!"); 712 Disp = N.getOperand(1).getOperand(0); // The global address. 713 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 714 Disp.getOpcode() == ISD::TargetConstantPool || 715 Disp.getOpcode() == ISD::TargetJumpTable); 716 Base = N.getOperand(0); 717 return true; // [&g+r] 718 } 719 } else if (N.getOpcode() == ISD::OR) { 720 short imm = 0; 721 if (isIntS16Immediate(N.getOperand(1), imm)) { 722 // If this is an or of disjoint bitfields, we can codegen this as an add 723 // (for better address arithmetic) if the LHS and RHS of the OR are 724 // provably disjoint. 725 uint64_t LHSKnownZero, LHSKnownOne; 726 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 727 if ((LHSKnownZero|~(unsigned)imm) == ~0U) { 728 // If all of the bits are known zero on the LHS or RHS, the add won't 729 // carry. 730 Base = N.getOperand(0); 731 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 732 return true; 733 } 734 } 735 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 736 // Loading from a constant address. 737 738 // If this address fits entirely in a 16-bit sext immediate field, codegen 739 // this as "d, 0" 740 short Imm; 741 if (isIntS16Immediate(CN, Imm)) { 742 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 743 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 744 return true; 745 } 746 747 // FIXME: Handle small sext constant offsets in PPC64 mode also! 748 if (CN->getValueType(0) == MVT::i32) { 749 int Addr = (int)CN->getValue(); 750 751 // Otherwise, break this down into an LIS + disp. 752 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 753 Base = DAG.getConstant(Addr - (signed short)Addr, MVT::i32); 754 return true; 755 } 756 } 757 758 Disp = DAG.getTargetConstant(0, getPointerTy()); 759 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 760 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 761 else 762 Base = N; 763 return true; // [r+0] 764} 765 766/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 767/// represented as an indexed [r+r] operation. 768bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, 769 SDOperand &Index, 770 SelectionDAG &DAG) { 771 // Check to see if we can easily represent this as an [r+r] address. This 772 // will fail if it thinks that the address is more profitably represented as 773 // reg+imm, e.g. where imm = 0. 774 if (SelectAddressRegReg(N, Base, Index, DAG)) 775 return true; 776 777 // If the operand is an addition, always emit this as [r+r], since this is 778 // better (for code size, and execution, as the memop does the add for free) 779 // than emitting an explicit add. 780 if (N.getOpcode() == ISD::ADD) { 781 Base = N.getOperand(0); 782 Index = N.getOperand(1); 783 return true; 784 } 785 786 // Otherwise, do it the hard way, using R0 as the base register. 787 Base = DAG.getRegister(PPC::R0, N.getValueType()); 788 Index = N; 789 return true; 790} 791 792/// SelectAddressRegImmShift - Returns true if the address N can be 793/// represented by a base register plus a signed 14-bit displacement 794/// [r+imm*4]. Suitable for use by STD and friends. 795bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, 796 SDOperand &Base, 797 SelectionDAG &DAG) { 798 // If this can be more profitably realized as r+r, fail. 799 if (SelectAddressRegReg(N, Disp, Base, DAG)) 800 return false; 801 802 if (N.getOpcode() == ISD::ADD) { 803 short imm = 0; 804 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 805 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 806 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 807 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 808 } else { 809 Base = N.getOperand(0); 810 } 811 return true; // [r+i] 812 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 813 // Match LOAD (ADD (X, Lo(G))). 814 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 815 && "Cannot handle constant offsets yet!"); 816 Disp = N.getOperand(1).getOperand(0); // The global address. 817 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 818 Disp.getOpcode() == ISD::TargetConstantPool || 819 Disp.getOpcode() == ISD::TargetJumpTable); 820 Base = N.getOperand(0); 821 return true; // [&g+r] 822 } 823 } else if (N.getOpcode() == ISD::OR) { 824 short imm = 0; 825 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 826 // If this is an or of disjoint bitfields, we can codegen this as an add 827 // (for better address arithmetic) if the LHS and RHS of the OR are 828 // provably disjoint. 829 uint64_t LHSKnownZero, LHSKnownOne; 830 ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 831 if ((LHSKnownZero|~(unsigned)imm) == ~0U) { 832 // If all of the bits are known zero on the LHS or RHS, the add won't 833 // carry. 834 Base = N.getOperand(0); 835 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 836 return true; 837 } 838 } 839 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 840 // Loading from a constant address. 841 842 // If this address fits entirely in a 14-bit sext immediate field, codegen 843 // this as "d, 0" 844 short Imm; 845 if (isIntS16Immediate(CN, Imm)) { 846 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 847 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 848 return true; 849 } 850 851 // FIXME: Handle small sext constant offsets in PPC64 mode also! 852 if (CN->getValueType(0) == MVT::i32) { 853 int Addr = (int)CN->getValue(); 854 855 // Otherwise, break this down into an LIS + disp. 856 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 857 Base = DAG.getConstant(Addr - (signed short)Addr, MVT::i32); 858 return true; 859 } 860 } 861 862 Disp = DAG.getTargetConstant(0, getPointerTy()); 863 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 864 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 865 else 866 Base = N; 867 return true; // [r+0] 868} 869 870 871/// getPreIndexedAddressParts - returns true by value, base pointer and 872/// offset pointer and addressing mode by reference if the node's address 873/// can be legally represented as pre-indexed load / store address. 874bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 875 SDOperand &Offset, 876 ISD::MemIndexedMode &AM, 877 SelectionDAG &DAG) { 878 // Disabled by default for now. 879 if (!EnablePPCPreinc) return false; 880 881 SDOperand Ptr; 882 MVT::ValueType VT; 883 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 884 Ptr = LD->getBasePtr(); 885 VT = LD->getLoadedVT(); 886 887 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 888 ST = ST; 889 Ptr = ST->getBasePtr(); 890 VT = ST->getStoredVT(); 891 } else 892 return false; 893 894 // PowerPC doesn't have preinc load/store instructions for vectors. 895 if (MVT::isVector(VT)) 896 return false; 897 898 // TODO: Check reg+reg first. 899 900 // LDU/STU use reg+imm*4, others use reg+imm. 901 if (VT != MVT::i64) { 902 // reg + imm 903 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 904 return false; 905 } else { 906 // reg + imm * 4. 907 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 908 return false; 909 } 910 911 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 912 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 913 // sext i32 to i64 when addr mode is r+i. 914 if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 && 915 LD->getExtensionType() == ISD::SEXTLOAD && 916 isa<ConstantSDNode>(Offset)) 917 return false; 918 } 919 920 AM = ISD::PRE_INC; 921 return true; 922} 923 924//===----------------------------------------------------------------------===// 925// LowerOperation implementation 926//===----------------------------------------------------------------------===// 927 928static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 929 MVT::ValueType PtrVT = Op.getValueType(); 930 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 931 Constant *C = CP->getConstVal(); 932 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 933 SDOperand Zero = DAG.getConstant(0, PtrVT); 934 935 const TargetMachine &TM = DAG.getTarget(); 936 937 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); 938 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); 939 940 // If this is a non-darwin platform, we don't support non-static relo models 941 // yet. 942 if (TM.getRelocationModel() == Reloc::Static || 943 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 944 // Generate non-pic code that has direct accesses to the constant pool. 945 // The address of the global is just (hi(&g)+lo(&g)). 946 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 947 } 948 949 if (TM.getRelocationModel() == Reloc::PIC_) { 950 // With PIC, the first instruction is actually "GR+hi(&G)". 951 Hi = DAG.getNode(ISD::ADD, PtrVT, 952 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 953 } 954 955 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 956 return Lo; 957} 958 959static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { 960 MVT::ValueType PtrVT = Op.getValueType(); 961 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 962 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 963 SDOperand Zero = DAG.getConstant(0, PtrVT); 964 965 const TargetMachine &TM = DAG.getTarget(); 966 967 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); 968 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); 969 970 // If this is a non-darwin platform, we don't support non-static relo models 971 // yet. 972 if (TM.getRelocationModel() == Reloc::Static || 973 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 974 // Generate non-pic code that has direct accesses to the constant pool. 975 // The address of the global is just (hi(&g)+lo(&g)). 976 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 977 } 978 979 if (TM.getRelocationModel() == Reloc::PIC_) { 980 // With PIC, the first instruction is actually "GR+hi(&G)". 981 Hi = DAG.getNode(ISD::ADD, PtrVT, 982 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 983 } 984 985 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 986 return Lo; 987} 988 989static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { 990 MVT::ValueType PtrVT = Op.getValueType(); 991 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 992 GlobalValue *GV = GSDN->getGlobal(); 993 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); 994 SDOperand Zero = DAG.getConstant(0, PtrVT); 995 996 const TargetMachine &TM = DAG.getTarget(); 997 998 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); 999 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); 1000 1001 // If this is a non-darwin platform, we don't support non-static relo models 1002 // yet. 1003 if (TM.getRelocationModel() == Reloc::Static || 1004 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1005 // Generate non-pic code that has direct accesses to globals. 1006 // The address of the global is just (hi(&g)+lo(&g)). 1007 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1008 } 1009 1010 if (TM.getRelocationModel() == Reloc::PIC_) { 1011 // With PIC, the first instruction is actually "GR+hi(&G)". 1012 Hi = DAG.getNode(ISD::ADD, PtrVT, 1013 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1014 } 1015 1016 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1017 1018 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV)) 1019 return Lo; 1020 1021 // If the global is weak or external, we have to go through the lazy 1022 // resolution stub. 1023 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); 1024} 1025 1026static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) { 1027 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1028 1029 // If we're comparing for equality to zero, expose the fact that this is 1030 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1031 // fold the new nodes. 1032 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1033 if (C->isNullValue() && CC == ISD::SETEQ) { 1034 MVT::ValueType VT = Op.getOperand(0).getValueType(); 1035 SDOperand Zext = Op.getOperand(0); 1036 if (VT < MVT::i32) { 1037 VT = MVT::i32; 1038 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); 1039 } 1040 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); 1041 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); 1042 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, 1043 DAG.getConstant(Log2b, MVT::i32)); 1044 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); 1045 } 1046 // Leave comparisons against 0 and -1 alone for now, since they're usually 1047 // optimized. FIXME: revisit this when we can custom lower all setcc 1048 // optimizations. 1049 if (C->isAllOnesValue() || C->isNullValue()) 1050 return SDOperand(); 1051 } 1052 1053 // If we have an integer seteq/setne, turn it into a compare against zero 1054 // by xor'ing the rhs with the lhs, which is faster than setting a 1055 // condition register, reading it back out, and masking the correct bit. The 1056 // normal approach here uses sub to do this instead of xor. Using xor exposes 1057 // the result to other bit-twiddling opportunities. 1058 MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); 1059 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1060 MVT::ValueType VT = Op.getValueType(); 1061 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), 1062 Op.getOperand(1)); 1063 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); 1064 } 1065 return SDOperand(); 1066} 1067 1068static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 1069 unsigned VarArgsFrameIndex) { 1070 // vastart just stores the address of the VarArgsFrameIndex slot into the 1071 // memory location argument. 1072 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1073 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1074 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 1075 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), 1076 SV->getOffset()); 1077} 1078 1079static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, 1080 int &VarArgsFrameIndex) { 1081 // TODO: add description of PPC stack frame format, or at least some docs. 1082 // 1083 MachineFunction &MF = DAG.getMachineFunction(); 1084 MachineFrameInfo *MFI = MF.getFrameInfo(); 1085 SSARegMap *RegMap = MF.getSSARegMap(); 1086 SmallVector<SDOperand, 8> ArgValues; 1087 SDOperand Root = Op.getOperand(0); 1088 1089 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1090 bool isPPC64 = PtrVT == MVT::i64; 1091 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1092 1093 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64); 1094 1095 static const unsigned GPR_32[] = { // 32-bit registers. 1096 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1097 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1098 }; 1099 static const unsigned GPR_64[] = { // 64-bit registers. 1100 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1101 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1102 }; 1103 static const unsigned FPR[] = { 1104 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1105 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1106 }; 1107 static const unsigned VR[] = { 1108 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1109 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1110 }; 1111 1112 const unsigned Num_GPR_Regs = sizeof(GPR_32)/sizeof(GPR_32[0]); 1113 const unsigned Num_FPR_Regs = sizeof(FPR)/sizeof(FPR[0]); 1114 const unsigned Num_VR_Regs = sizeof( VR)/sizeof( VR[0]); 1115 1116 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1117 1118 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1119 1120 // Add DAG nodes to load the arguments or copy them out of registers. On 1121 // entry to a function on PPC, the arguments start after the linkage area, 1122 // although the first ones are often in registers. 1123 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { 1124 SDOperand ArgVal; 1125 bool needsLoad = false; 1126 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); 1127 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; 1128 unsigned ArgSize = ObjSize; 1129 1130 unsigned CurArgOffset = ArgOffset; 1131 switch (ObjectVT) { 1132 default: assert(0 && "Unhandled argument type!"); 1133 case MVT::i32: 1134 // All int arguments reserve stack space. 1135 ArgOffset += PtrByteSize; 1136 1137 if (GPR_idx != Num_GPR_Regs) { 1138 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1139 MF.addLiveIn(GPR[GPR_idx], VReg); 1140 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1141 ++GPR_idx; 1142 } else { 1143 needsLoad = true; 1144 ArgSize = PtrByteSize; 1145 } 1146 break; 1147 case MVT::i64: // PPC64 1148 // All int arguments reserve stack space. 1149 ArgOffset += 8; 1150 1151 if (GPR_idx != Num_GPR_Regs) { 1152 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass); 1153 MF.addLiveIn(GPR[GPR_idx], VReg); 1154 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); 1155 ++GPR_idx; 1156 } else { 1157 needsLoad = true; 1158 } 1159 break; 1160 case MVT::f32: 1161 case MVT::f64: 1162 // All FP arguments reserve stack space. 1163 ArgOffset += isPPC64 ? 8 : ObjSize; 1164 1165 // Every 4 bytes of argument space consumes one of the GPRs available for 1166 // argument passing. 1167 if (GPR_idx != Num_GPR_Regs) { 1168 ++GPR_idx; 1169 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 1170 ++GPR_idx; 1171 } 1172 if (FPR_idx != Num_FPR_Regs) { 1173 unsigned VReg; 1174 if (ObjectVT == MVT::f32) 1175 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); 1176 else 1177 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 1178 MF.addLiveIn(FPR[FPR_idx], VReg); 1179 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1180 ++FPR_idx; 1181 } else { 1182 needsLoad = true; 1183 } 1184 break; 1185 case MVT::v4f32: 1186 case MVT::v4i32: 1187 case MVT::v8i16: 1188 case MVT::v16i8: 1189 // Note that vector arguments in registers don't reserve stack space. 1190 if (VR_idx != Num_VR_Regs) { 1191 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass); 1192 MF.addLiveIn(VR[VR_idx], VReg); 1193 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1194 ++VR_idx; 1195 } else { 1196 // This should be simple, but requires getting 16-byte aligned stack 1197 // values. 1198 assert(0 && "Loading VR argument not implemented yet!"); 1199 needsLoad = true; 1200 } 1201 break; 1202 } 1203 1204 // We need to load the argument to a virtual register if we determined above 1205 // that we ran out of physical registers of the appropriate type 1206 if (needsLoad) { 1207 // If the argument is actually used, emit a load from the right stack 1208 // slot. 1209 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { 1210 int FI = MFI->CreateFixedObject(ObjSize, 1211 CurArgOffset + (ArgSize - ObjSize)); 1212 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); 1213 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 1214 } else { 1215 // Don't emit a dead load. 1216 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT); 1217 } 1218 } 1219 1220 ArgValues.push_back(ArgVal); 1221 } 1222 1223 // If the function takes variable number of arguments, make a frame index for 1224 // the start of the first vararg value... for expansion of llvm.va_start. 1225 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1226 if (isVarArg) { 1227 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, 1228 ArgOffset); 1229 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1230 // If this function is vararg, store any remaining integer argument regs 1231 // to their spots on the stack so that they may be loaded by deferencing the 1232 // result of va_next. 1233 SmallVector<SDOperand, 8> MemOps; 1234 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 1235 unsigned VReg; 1236 if (isPPC64) 1237 VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass); 1238 else 1239 VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1240 1241 MF.addLiveIn(GPR[GPR_idx], VReg); 1242 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 1243 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1244 MemOps.push_back(Store); 1245 // Increment the address by four for the next argument to store 1246 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); 1247 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1248 } 1249 if (!MemOps.empty()) 1250 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); 1251 } 1252 1253 ArgValues.push_back(Root); 1254 1255 // Return the new list of results. 1256 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 1257 Op.Val->value_end()); 1258 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); 1259} 1260 1261/// isCallCompatibleAddress - Return the immediate to use if the specified 1262/// 32-bit value is representable in the immediate field of a BxA instruction. 1263static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) { 1264 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1265 if (!C) return 0; 1266 1267 int Addr = C->getValue(); 1268 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 1269 (Addr << 6 >> 6) != Addr) 1270 return 0; // Top 6 bits have to be sext of immediate. 1271 1272 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val; 1273} 1274 1275static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { 1276 SDOperand Chain = Op.getOperand(0); 1277 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1278 SDOperand Callee = Op.getOperand(4); 1279 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 1280 1281 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1282 bool isPPC64 = PtrVT == MVT::i64; 1283 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1284 1285 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in 1286 // SelectExpr to use to put the arguments in the appropriate registers. 1287 std::vector<SDOperand> args_to_use; 1288 1289 // Count how many bytes are to be pushed on the stack, including the linkage 1290 // area, and parameter passing area. We start with 24/48 bytes, which is 1291 // prereserved space for [SP][CR][LR][3 x unused]. 1292 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64); 1293 1294 // Add up all the space actually used. 1295 for (unsigned i = 0; i != NumOps; ++i) { 1296 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8; 1297 ArgSize = std::max(ArgSize, PtrByteSize); 1298 NumBytes += ArgSize; 1299 } 1300 1301 // The prolog code of the callee may store up to 8 GPR argument registers to 1302 // the stack, allowing va_start to index over them in memory if its varargs. 1303 // Because we cannot tell if this is needed on the caller side, we have to 1304 // conservatively assume that it is needed. As such, make sure we have at 1305 // least enough stack space for the caller to store the 8 GPRs. 1306 NumBytes = std::max(NumBytes, PPCFrameInfo::getMinCallFrameSize(isPPC64)); 1307 1308 // Adjust the stack pointer for the new arguments... 1309 // These operations are automatically eliminated by the prolog/epilog pass 1310 Chain = DAG.getCALLSEQ_START(Chain, 1311 DAG.getConstant(NumBytes, PtrVT)); 1312 1313 // Set up a copy of the stack pointer for use loading and storing any 1314 // arguments that may not fit in the registers available for argument 1315 // passing. 1316 SDOperand StackPtr; 1317 if (isPPC64) 1318 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 1319 else 1320 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 1321 1322 // Figure out which arguments are going to go in registers, and which in 1323 // memory. Also, if this is a vararg function, floating point operations 1324 // must be stored to our stack, and loaded into integer regs as well, if 1325 // any integer regs are available for argument passing. 1326 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64); 1327 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1328 1329 static const unsigned GPR_32[] = { // 32-bit registers. 1330 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1331 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1332 }; 1333 static const unsigned GPR_64[] = { // 64-bit registers. 1334 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1335 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1336 }; 1337 static const unsigned FPR[] = { 1338 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1339 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1340 }; 1341 static const unsigned VR[] = { 1342 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1343 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1344 }; 1345 const unsigned NumGPRs = sizeof(GPR_32)/sizeof(GPR_32[0]); 1346 const unsigned NumFPRs = sizeof(FPR)/sizeof(FPR[0]); 1347 const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]); 1348 1349 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1350 1351 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 1352 SmallVector<SDOperand, 8> MemOpChains; 1353 for (unsigned i = 0; i != NumOps; ++i) { 1354 SDOperand Arg = Op.getOperand(5+2*i); 1355 1356 // PtrOff will be used to store the current argument to the stack if a 1357 // register cannot be found for it. 1358 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 1359 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); 1360 1361 // On PPC64, promote integers to 64-bit values. 1362 if (isPPC64 && Arg.getValueType() == MVT::i32) { 1363 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue(); 1364 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 1365 1366 Arg = DAG.getNode(ExtOp, MVT::i64, Arg); 1367 } 1368 1369 switch (Arg.getValueType()) { 1370 default: assert(0 && "Unexpected ValueType for argument!"); 1371 case MVT::i32: 1372 case MVT::i64: 1373 if (GPR_idx != NumGPRs) { 1374 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 1375 } else { 1376 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1377 } 1378 ArgOffset += PtrByteSize; 1379 break; 1380 case MVT::f32: 1381 case MVT::f64: 1382 if (isVarArg && isPPC64) { 1383 // Float varargs need to be promoted to double. 1384 if (Arg.getValueType() == MVT::f32) 1385 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg); 1386 } 1387 1388 if (FPR_idx != NumFPRs) { 1389 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 1390 1391 if (isVarArg) { 1392 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); 1393 MemOpChains.push_back(Store); 1394 1395 // Float varargs are always shadowed in available integer registers 1396 if (GPR_idx != NumGPRs) { 1397 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1398 MemOpChains.push_back(Load.getValue(1)); 1399 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 1400 } 1401 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 1402 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 1403 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); 1404 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1405 MemOpChains.push_back(Load.getValue(1)); 1406 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 1407 } 1408 } else { 1409 // If we have any FPRs remaining, we may also have GPRs remaining. 1410 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 1411 // GPRs. 1412 if (GPR_idx != NumGPRs) 1413 ++GPR_idx; 1414 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64) 1415 ++GPR_idx; 1416 } 1417 } else { 1418 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1419 } 1420 if (isPPC64) 1421 ArgOffset += 8; 1422 else 1423 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 1424 break; 1425 case MVT::v4f32: 1426 case MVT::v4i32: 1427 case MVT::v8i16: 1428 case MVT::v16i8: 1429 assert(!isVarArg && "Don't support passing vectors to varargs yet!"); 1430 assert(VR_idx != NumVRs && 1431 "Don't support passing more than 12 vector args yet!"); 1432 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 1433 break; 1434 } 1435 } 1436 if (!MemOpChains.empty()) 1437 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1438 &MemOpChains[0], MemOpChains.size()); 1439 1440 // Build a sequence of copy-to-reg nodes chained together with token chain 1441 // and flag operands which copy the outgoing args into the appropriate regs. 1442 SDOperand InFlag; 1443 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1444 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1445 InFlag); 1446 InFlag = Chain.getValue(1); 1447 } 1448 1449 std::vector<MVT::ValueType> NodeTys; 1450 NodeTys.push_back(MVT::Other); // Returns a chain 1451 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 1452 1453 SmallVector<SDOperand, 8> Ops; 1454 unsigned CallOpc = PPCISD::CALL; 1455 1456 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1457 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1458 // node so that legalize doesn't hack it. 1459 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1460 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); 1461 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 1462 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); 1463 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) 1464 // If this is an absolute destination address, use the munged value. 1465 Callee = SDOperand(Dest, 0); 1466 else { 1467 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 1468 // to do the call, we can't use PPCISD::CALL. 1469 SDOperand MTCTROps[] = {Chain, Callee, InFlag}; 1470 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0)); 1471 InFlag = Chain.getValue(1); 1472 1473 // Copy the callee address into R12 on darwin. 1474 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag); 1475 InFlag = Chain.getValue(1); 1476 1477 NodeTys.clear(); 1478 NodeTys.push_back(MVT::Other); 1479 NodeTys.push_back(MVT::Flag); 1480 Ops.push_back(Chain); 1481 CallOpc = PPCISD::BCTRL; 1482 Callee.Val = 0; 1483 } 1484 1485 // If this is a direct call, pass the chain and the callee. 1486 if (Callee.Val) { 1487 Ops.push_back(Chain); 1488 Ops.push_back(Callee); 1489 } 1490 1491 // Add argument registers to the end of the list so that they are known live 1492 // into the call. 1493 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1494 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1495 RegsToPass[i].second.getValueType())); 1496 1497 if (InFlag.Val) 1498 Ops.push_back(InFlag); 1499 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 1500 InFlag = Chain.getValue(1); 1501 1502 SDOperand ResultVals[3]; 1503 unsigned NumResults = 0; 1504 NodeTys.clear(); 1505 1506 // If the call has results, copy the values out of the ret val registers. 1507 switch (Op.Val->getValueType(0)) { 1508 default: assert(0 && "Unexpected ret value!"); 1509 case MVT::Other: break; 1510 case MVT::i32: 1511 if (Op.Val->getValueType(1) == MVT::i32) { 1512 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1); 1513 ResultVals[0] = Chain.getValue(0); 1514 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, 1515 Chain.getValue(2)).getValue(1); 1516 ResultVals[1] = Chain.getValue(0); 1517 NumResults = 2; 1518 NodeTys.push_back(MVT::i32); 1519 } else { 1520 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); 1521 ResultVals[0] = Chain.getValue(0); 1522 NumResults = 1; 1523 } 1524 NodeTys.push_back(MVT::i32); 1525 break; 1526 case MVT::i64: 1527 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1); 1528 ResultVals[0] = Chain.getValue(0); 1529 NumResults = 1; 1530 NodeTys.push_back(MVT::i64); 1531 break; 1532 case MVT::f32: 1533 case MVT::f64: 1534 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0), 1535 InFlag).getValue(1); 1536 ResultVals[0] = Chain.getValue(0); 1537 NumResults = 1; 1538 NodeTys.push_back(Op.Val->getValueType(0)); 1539 break; 1540 case MVT::v4f32: 1541 case MVT::v4i32: 1542 case MVT::v8i16: 1543 case MVT::v16i8: 1544 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0), 1545 InFlag).getValue(1); 1546 ResultVals[0] = Chain.getValue(0); 1547 NumResults = 1; 1548 NodeTys.push_back(Op.Val->getValueType(0)); 1549 break; 1550 } 1551 1552 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 1553 DAG.getConstant(NumBytes, PtrVT)); 1554 NodeTys.push_back(MVT::Other); 1555 1556 // If the function returns void, just return the chain. 1557 if (NumResults == 0) 1558 return Chain; 1559 1560 // Otherwise, merge everything together with a MERGE_VALUES node. 1561 ResultVals[NumResults++] = Chain; 1562 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, 1563 ResultVals, NumResults); 1564 return Res.getValue(Op.ResNo); 1565} 1566 1567static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { 1568 SDOperand Copy; 1569 switch(Op.getNumOperands()) { 1570 default: 1571 assert(0 && "Do not know how to return this many arguments!"); 1572 abort(); 1573 case 1: 1574 return SDOperand(); // ret void is legal 1575 case 3: { 1576 MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); 1577 unsigned ArgReg; 1578 if (ArgVT == MVT::i32) { 1579 ArgReg = PPC::R3; 1580 } else if (ArgVT == MVT::i64) { 1581 ArgReg = PPC::X3; 1582 } else if (MVT::isVector(ArgVT)) { 1583 ArgReg = PPC::V2; 1584 } else { 1585 assert(MVT::isFloatingPoint(ArgVT)); 1586 ArgReg = PPC::F1; 1587 } 1588 1589 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 1590 SDOperand()); 1591 1592 // If we haven't noted the R3/F1 are live out, do so now. 1593 if (DAG.getMachineFunction().liveout_empty()) 1594 DAG.getMachineFunction().addLiveOut(ArgReg); 1595 break; 1596 } 1597 case 5: 1598 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3), 1599 SDOperand()); 1600 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1)); 1601 // If we haven't noted the R3+R4 are live out, do so now. 1602 if (DAG.getMachineFunction().liveout_empty()) { 1603 DAG.getMachineFunction().addLiveOut(PPC::R3); 1604 DAG.getMachineFunction().addLiveOut(PPC::R4); 1605 } 1606 break; 1607 } 1608 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 1609} 1610 1611static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, 1612 const PPCSubtarget &Subtarget) { 1613 // When we pop the dynamic allocation we need to restore the SP link. 1614 1615 // Get the corect type for pointers. 1616 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1617 1618 // Construct the stack pointer operand. 1619 bool IsPPC64 = Subtarget.isPPC64(); 1620 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1; 1621 SDOperand StackPtr = DAG.getRegister(SP, PtrVT); 1622 1623 // Get the operands for the STACKRESTORE. 1624 SDOperand Chain = Op.getOperand(0); 1625 SDOperand SaveSP = Op.getOperand(1); 1626 1627 // Load the old link SP. 1628 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0); 1629 1630 // Restore the stack pointer. 1631 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP); 1632 1633 // Store the old link SP. 1634 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0); 1635} 1636 1637static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG, 1638 const PPCSubtarget &Subtarget) { 1639 MachineFunction &MF = DAG.getMachineFunction(); 1640 bool IsPPC64 = Subtarget.isPPC64(); 1641 1642 // Get current frame pointer save index. The users of this index will be 1643 // primarily DYNALLOC instructions. 1644 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1645 int FPSI = FI->getFramePointerSaveIndex(); 1646 1647 // If the frame pointer save index hasn't been defined yet. 1648 if (!FPSI) { 1649 // Find out what the fix offset of the frame pointer save area. 1650 int Offset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64); 1651 // Allocate the frame index for frame pointer save area. 1652 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, Offset); 1653 // Save the result. 1654 FI->setFramePointerSaveIndex(FPSI); 1655 } 1656 1657 // Get the inputs. 1658 SDOperand Chain = Op.getOperand(0); 1659 SDOperand Size = Op.getOperand(1); 1660 1661 // Get the corect type for pointers. 1662 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1663 // Negate the size. 1664 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT, 1665 DAG.getConstant(0, PtrVT), Size); 1666 // Construct a node for the frame pointer save index. 1667 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT); 1668 // Build a DYNALLOC node. 1669 SDOperand Ops[3] = { Chain, NegSize, FPSIdx }; 1670 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 1671 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3); 1672} 1673 1674 1675/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 1676/// possible. 1677static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { 1678 // Not FP? Not a fsel. 1679 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 1680 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 1681 return SDOperand(); 1682 1683 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1684 1685 // Cannot handle SETEQ/SETNE. 1686 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand(); 1687 1688 MVT::ValueType ResVT = Op.getValueType(); 1689 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 1690 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 1691 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 1692 1693 // If the RHS of the comparison is a 0.0, we don't need to do the 1694 // subtraction at all. 1695 if (isFloatingPointZero(RHS)) 1696 switch (CC) { 1697 default: break; // SETUO etc aren't handled by fsel. 1698 case ISD::SETULT: 1699 case ISD::SETOLT: 1700 case ISD::SETLT: 1701 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 1702 case ISD::SETUGE: 1703 case ISD::SETOGE: 1704 case ISD::SETGE: 1705 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 1706 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 1707 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 1708 case ISD::SETUGT: 1709 case ISD::SETOGT: 1710 case ISD::SETGT: 1711 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 1712 case ISD::SETULE: 1713 case ISD::SETOLE: 1714 case ISD::SETLE: 1715 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 1716 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 1717 return DAG.getNode(PPCISD::FSEL, ResVT, 1718 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 1719 } 1720 1721 SDOperand Cmp; 1722 switch (CC) { 1723 default: break; // SETUO etc aren't handled by fsel. 1724 case ISD::SETULT: 1725 case ISD::SETOLT: 1726 case ISD::SETLT: 1727 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 1728 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 1729 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 1730 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 1731 case ISD::SETUGE: 1732 case ISD::SETOGE: 1733 case ISD::SETGE: 1734 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 1735 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 1736 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 1737 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 1738 case ISD::SETUGT: 1739 case ISD::SETOGT: 1740 case ISD::SETGT: 1741 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 1742 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 1743 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 1744 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 1745 case ISD::SETULE: 1746 case ISD::SETOLE: 1747 case ISD::SETLE: 1748 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 1749 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 1750 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 1751 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 1752 } 1753 return SDOperand(); 1754} 1755 1756static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 1757 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 1758 SDOperand Src = Op.getOperand(0); 1759 if (Src.getValueType() == MVT::f32) 1760 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 1761 1762 SDOperand Tmp; 1763 switch (Op.getValueType()) { 1764 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 1765 case MVT::i32: 1766 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 1767 break; 1768 case MVT::i64: 1769 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 1770 break; 1771 } 1772 1773 // Convert the FP value to an int value through memory. 1774 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp); 1775 if (Op.getValueType() == MVT::i32) 1776 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits); 1777 return Bits; 1778} 1779 1780static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 1781 if (Op.getOperand(0).getValueType() == MVT::i64) { 1782 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 1783 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 1784 if (Op.getValueType() == MVT::f32) 1785 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 1786 return FP; 1787 } 1788 1789 assert(Op.getOperand(0).getValueType() == MVT::i32 && 1790 "Unhandled SINT_TO_FP type in custom expander!"); 1791 // Since we only generate this in 64-bit mode, we can take advantage of 1792 // 64-bit registers. In particular, sign extend the input value into the 1793 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 1794 // then lfd it and fcfid it. 1795 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 1796 int FrameIdx = FrameInfo->CreateStackObject(8, 8); 1797 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1798 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 1799 1800 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, 1801 Op.getOperand(0)); 1802 1803 // STD the extended value into the stack slot. 1804 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, 1805 DAG.getEntryNode(), Ext64, FIdx, 1806 DAG.getSrcValue(NULL)); 1807 // Load the value as a double. 1808 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); 1809 1810 // FCFID it and return it. 1811 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); 1812 if (Op.getValueType() == MVT::f32) 1813 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 1814 return FP; 1815} 1816 1817static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { 1818 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 1819 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 1820 1821 // Expand into a bunch of logical ops. Note that these ops 1822 // depend on the PPC behavior for oversized shift amounts. 1823 SDOperand Lo = Op.getOperand(0); 1824 SDOperand Hi = Op.getOperand(1); 1825 SDOperand Amt = Op.getOperand(2); 1826 1827 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 1828 DAG.getConstant(32, MVT::i32), Amt); 1829 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); 1830 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); 1831 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 1832 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 1833 DAG.getConstant(-32U, MVT::i32)); 1834 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); 1835 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 1836 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); 1837 SDOperand OutOps[] = { OutLo, OutHi }; 1838 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 1839 OutOps, 2); 1840} 1841 1842static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { 1843 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 1844 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!"); 1845 1846 // Otherwise, expand into a bunch of logical ops. Note that these ops 1847 // depend on the PPC behavior for oversized shift amounts. 1848 SDOperand Lo = Op.getOperand(0); 1849 SDOperand Hi = Op.getOperand(1); 1850 SDOperand Amt = Op.getOperand(2); 1851 1852 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 1853 DAG.getConstant(32, MVT::i32), Amt); 1854 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 1855 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 1856 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 1857 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 1858 DAG.getConstant(-32U, MVT::i32)); 1859 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); 1860 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 1861 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); 1862 SDOperand OutOps[] = { OutLo, OutHi }; 1863 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 1864 OutOps, 2); 1865} 1866 1867static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { 1868 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 1869 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 1870 1871 // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 1872 SDOperand Lo = Op.getOperand(0); 1873 SDOperand Hi = Op.getOperand(1); 1874 SDOperand Amt = Op.getOperand(2); 1875 1876 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 1877 DAG.getConstant(32, MVT::i32), Amt); 1878 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 1879 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 1880 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 1881 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 1882 DAG.getConstant(-32U, MVT::i32)); 1883 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); 1884 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); 1885 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 1886 Tmp4, Tmp6, ISD::SETLE); 1887 SDOperand OutOps[] = { OutLo, OutHi }; 1888 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 1889 OutOps, 2); 1890} 1891 1892//===----------------------------------------------------------------------===// 1893// Vector related lowering. 1894// 1895 1896// If this is a vector of constants or undefs, get the bits. A bit in 1897// UndefBits is set if the corresponding element of the vector is an 1898// ISD::UNDEF value. For undefs, the corresponding VectorBits values are 1899// zero. Return true if this is not an array of constants, false if it is. 1900// 1901static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], 1902 uint64_t UndefBits[2]) { 1903 // Start with zero'd results. 1904 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; 1905 1906 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType()); 1907 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 1908 SDOperand OpVal = BV->getOperand(i); 1909 1910 unsigned PartNo = i >= e/2; // In the upper 128 bits? 1911 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. 1912 1913 uint64_t EltBits = 0; 1914 if (OpVal.getOpcode() == ISD::UNDEF) { 1915 uint64_t EltUndefBits = ~0U >> (32-EltBitSize); 1916 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); 1917 continue; 1918 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 1919 EltBits = CN->getValue() & (~0U >> (32-EltBitSize)); 1920 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 1921 assert(CN->getValueType(0) == MVT::f32 && 1922 "Only one legal FP vector type!"); 1923 EltBits = FloatToBits(CN->getValue()); 1924 } else { 1925 // Nonconstant element. 1926 return true; 1927 } 1928 1929 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); 1930 } 1931 1932 //printf("%llx %llx %llx %llx\n", 1933 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); 1934 return false; 1935} 1936 1937// If this is a splat (repetition) of a value across the whole vector, return 1938// the smallest size that splats it. For example, "0x01010101010101..." is a 1939// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 1940// SplatSize = 1 byte. 1941static bool isConstantSplat(const uint64_t Bits128[2], 1942 const uint64_t Undef128[2], 1943 unsigned &SplatBits, unsigned &SplatUndef, 1944 unsigned &SplatSize) { 1945 1946 // Don't let undefs prevent splats from matching. See if the top 64-bits are 1947 // the same as the lower 64-bits, ignoring undefs. 1948 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0])) 1949 return false; // Can't be a splat if two pieces don't match. 1950 1951 uint64_t Bits64 = Bits128[0] | Bits128[1]; 1952 uint64_t Undef64 = Undef128[0] & Undef128[1]; 1953 1954 // Check that the top 32-bits are the same as the lower 32-bits, ignoring 1955 // undefs. 1956 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64)) 1957 return false; // Can't be a splat if two pieces don't match. 1958 1959 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32); 1960 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32); 1961 1962 // If the top 16-bits are different than the lower 16-bits, ignoring 1963 // undefs, we have an i32 splat. 1964 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) { 1965 SplatBits = Bits32; 1966 SplatUndef = Undef32; 1967 SplatSize = 4; 1968 return true; 1969 } 1970 1971 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16); 1972 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16); 1973 1974 // If the top 8-bits are different than the lower 8-bits, ignoring 1975 // undefs, we have an i16 splat. 1976 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) { 1977 SplatBits = Bits16; 1978 SplatUndef = Undef16; 1979 SplatSize = 2; 1980 return true; 1981 } 1982 1983 // Otherwise, we have an 8-bit splat. 1984 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); 1985 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); 1986 SplatSize = 1; 1987 return true; 1988} 1989 1990/// BuildSplatI - Build a canonical splati of Val with an element size of 1991/// SplatSize. Cast the result to VT. 1992static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT, 1993 SelectionDAG &DAG) { 1994 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 1995 1996 static const MVT::ValueType VTys[] = { // canonical VT to use for each size. 1997 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 1998 }; 1999 2000 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 2001 2002 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 2003 if (Val == -1) 2004 SplatSize = 1; 2005 2006 MVT::ValueType CanonicalVT = VTys[SplatSize-1]; 2007 2008 // Build a canonical splat for this value. 2009 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT)); 2010 SmallVector<SDOperand, 8> Ops; 2011 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt); 2012 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, 2013 &Ops[0], Ops.size()); 2014 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res); 2015} 2016 2017/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 2018/// specified intrinsic ID. 2019static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS, 2020 SelectionDAG &DAG, 2021 MVT::ValueType DestVT = MVT::Other) { 2022 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 2023 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 2024 DAG.getConstant(IID, MVT::i32), LHS, RHS); 2025} 2026 2027/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 2028/// specified intrinsic ID. 2029static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1, 2030 SDOperand Op2, SelectionDAG &DAG, 2031 MVT::ValueType DestVT = MVT::Other) { 2032 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 2033 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 2034 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 2035} 2036 2037 2038/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 2039/// amount. The result has the specified value type. 2040static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt, 2041 MVT::ValueType VT, SelectionDAG &DAG) { 2042 // Force LHS/RHS to be the right type. 2043 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); 2044 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); 2045 2046 SDOperand Ops[16]; 2047 for (unsigned i = 0; i != 16; ++i) 2048 Ops[i] = DAG.getConstant(i+Amt, MVT::i32); 2049 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, 2050 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16)); 2051 return DAG.getNode(ISD::BIT_CONVERT, VT, T); 2052} 2053 2054// If this is a case we can't handle, return null and let the default 2055// expansion code take care of it. If we CAN select this case, and if it 2056// selects to a single instruction, return Op. Otherwise, if we can codegen 2057// this case more efficiently than a constant pool load, lower it to the 2058// sequence of ops that should be used. 2059static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2060 // If this is a vector of constants or undefs, get the bits. A bit in 2061 // UndefBits is set if the corresponding element of the vector is an 2062 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are 2063 // zero. 2064 uint64_t VectorBits[2]; 2065 uint64_t UndefBits[2]; 2066 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) 2067 return SDOperand(); // Not a constant vector. 2068 2069 // If this is a splat (repetition) of a value across the whole vector, return 2070 // the smallest size that splats it. For example, "0x01010101010101..." is a 2071 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 2072 // SplatSize = 1 byte. 2073 unsigned SplatBits, SplatUndef, SplatSize; 2074 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){ 2075 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0; 2076 2077 // First, handle single instruction cases. 2078 2079 // All zeros? 2080 if (SplatBits == 0) { 2081 // Canonicalize all zero vectors to be v4i32. 2082 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 2083 SDOperand Z = DAG.getConstant(0, MVT::i32); 2084 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); 2085 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); 2086 } 2087 return Op; 2088 } 2089 2090 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 2091 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); 2092 if (SextVal >= -16 && SextVal <= 15) 2093 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG); 2094 2095 2096 // Two instruction sequences. 2097 2098 // If this value is in the range [-32,30] and is even, use: 2099 // tmp = VSPLTI[bhw], result = add tmp, tmp 2100 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 2101 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG); 2102 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op); 2103 } 2104 2105 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 2106 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 2107 // for fneg/fabs. 2108 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 2109 // Make -1 and vspltisw -1: 2110 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); 2111 2112 // Make the VSLW intrinsic, computing 0x8000_0000. 2113 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 2114 OnesV, DAG); 2115 2116 // xor by OnesV to invert it. 2117 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); 2118 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2119 } 2120 2121 // Check to see if this is a wide variety of vsplti*, binop self cases. 2122 unsigned SplatBitSize = SplatSize*8; 2123 static const char SplatCsts[] = { 2124 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 2125 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 2126 }; 2127 2128 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){ 2129 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 2130 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 2131 int i = SplatCsts[idx]; 2132 2133 // Figure out what shift amount will be used by altivec if shifted by i in 2134 // this splat size. 2135 unsigned TypeShiftAmt = i & (SplatBitSize-1); 2136 2137 // vsplti + shl self. 2138 if (SextVal == (i << (int)TypeShiftAmt)) { 2139 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2140 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2141 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 2142 Intrinsic::ppc_altivec_vslw 2143 }; 2144 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2145 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2146 } 2147 2148 // vsplti + srl self. 2149 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2150 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2151 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2152 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 2153 Intrinsic::ppc_altivec_vsrw 2154 }; 2155 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2156 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2157 } 2158 2159 // vsplti + sra self. 2160 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2161 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2162 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2163 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 2164 Intrinsic::ppc_altivec_vsraw 2165 }; 2166 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2167 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2168 } 2169 2170 // vsplti + rol self. 2171 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 2172 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 2173 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2174 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2175 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 2176 Intrinsic::ppc_altivec_vrlw 2177 }; 2178 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2179 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2180 } 2181 2182 // t = vsplti c, result = vsldoi t, t, 1 2183 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { 2184 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2185 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG); 2186 } 2187 // t = vsplti c, result = vsldoi t, t, 2 2188 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { 2189 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2190 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG); 2191 } 2192 // t = vsplti c, result = vsldoi t, t, 3 2193 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { 2194 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2195 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG); 2196 } 2197 } 2198 2199 // Three instruction sequences. 2200 2201 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 2202 if (SextVal >= 0 && SextVal <= 31) { 2203 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG); 2204 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 2205 LHS = DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS); 2206 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 2207 } 2208 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 2209 if (SextVal >= -31 && SextVal <= 0) { 2210 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG); 2211 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 2212 LHS = DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS); 2213 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 2214 } 2215 } 2216 2217 return SDOperand(); 2218} 2219 2220/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 2221/// the specified operations to build the shuffle. 2222static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, 2223 SDOperand RHS, SelectionDAG &DAG) { 2224 unsigned OpNum = (PFEntry >> 26) & 0x0F; 2225 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 2226 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 2227 2228 enum { 2229 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 2230 OP_VMRGHW, 2231 OP_VMRGLW, 2232 OP_VSPLTISW0, 2233 OP_VSPLTISW1, 2234 OP_VSPLTISW2, 2235 OP_VSPLTISW3, 2236 OP_VSLDOI4, 2237 OP_VSLDOI8, 2238 OP_VSLDOI12 2239 }; 2240 2241 if (OpNum == OP_COPY) { 2242 if (LHSID == (1*9+2)*9+3) return LHS; 2243 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 2244 return RHS; 2245 } 2246 2247 SDOperand OpLHS, OpRHS; 2248 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG); 2249 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG); 2250 2251 unsigned ShufIdxs[16]; 2252 switch (OpNum) { 2253 default: assert(0 && "Unknown i32 permute!"); 2254 case OP_VMRGHW: 2255 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 2256 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 2257 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 2258 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 2259 break; 2260 case OP_VMRGLW: 2261 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 2262 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 2263 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 2264 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 2265 break; 2266 case OP_VSPLTISW0: 2267 for (unsigned i = 0; i != 16; ++i) 2268 ShufIdxs[i] = (i&3)+0; 2269 break; 2270 case OP_VSPLTISW1: 2271 for (unsigned i = 0; i != 16; ++i) 2272 ShufIdxs[i] = (i&3)+4; 2273 break; 2274 case OP_VSPLTISW2: 2275 for (unsigned i = 0; i != 16; ++i) 2276 ShufIdxs[i] = (i&3)+8; 2277 break; 2278 case OP_VSPLTISW3: 2279 for (unsigned i = 0; i != 16; ++i) 2280 ShufIdxs[i] = (i&3)+12; 2281 break; 2282 case OP_VSLDOI4: 2283 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG); 2284 case OP_VSLDOI8: 2285 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG); 2286 case OP_VSLDOI12: 2287 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); 2288 } 2289 SDOperand Ops[16]; 2290 for (unsigned i = 0; i != 16; ++i) 2291 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32); 2292 2293 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS, 2294 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 2295} 2296 2297/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 2298/// is a shuffle we can handle in a single instruction, return it. Otherwise, 2299/// return the code it can be lowered into. Worst case, it can always be 2300/// lowered into a vperm. 2301static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { 2302 SDOperand V1 = Op.getOperand(0); 2303 SDOperand V2 = Op.getOperand(1); 2304 SDOperand PermMask = Op.getOperand(2); 2305 2306 // Cases that are handled by instructions that take permute immediates 2307 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 2308 // selected by the instruction selector. 2309 if (V2.getOpcode() == ISD::UNDEF) { 2310 if (PPC::isSplatShuffleMask(PermMask.Val, 1) || 2311 PPC::isSplatShuffleMask(PermMask.Val, 2) || 2312 PPC::isSplatShuffleMask(PermMask.Val, 4) || 2313 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || 2314 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || 2315 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || 2316 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || 2317 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || 2318 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || 2319 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || 2320 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || 2321 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { 2322 return Op; 2323 } 2324 } 2325 2326 // Altivec has a variety of "shuffle immediates" that take two vector inputs 2327 // and produce a fixed permutation. If any of these match, do not lower to 2328 // VPERM. 2329 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || 2330 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || 2331 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || 2332 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || 2333 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || 2334 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || 2335 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || 2336 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || 2337 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) 2338 return Op; 2339 2340 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 2341 // perfect shuffle table to emit an optimal matching sequence. 2342 unsigned PFIndexes[4]; 2343 bool isFourElementShuffle = true; 2344 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 2345 unsigned EltNo = 8; // Start out undef. 2346 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 2347 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF) 2348 continue; // Undef, ignore it. 2349 2350 unsigned ByteSource = 2351 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue(); 2352 if ((ByteSource & 3) != j) { 2353 isFourElementShuffle = false; 2354 break; 2355 } 2356 2357 if (EltNo == 8) { 2358 EltNo = ByteSource/4; 2359 } else if (EltNo != ByteSource/4) { 2360 isFourElementShuffle = false; 2361 break; 2362 } 2363 } 2364 PFIndexes[i] = EltNo; 2365 } 2366 2367 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 2368 // perfect shuffle vector to determine if it is cost effective to do this as 2369 // discrete instructions, or whether we should use a vperm. 2370 if (isFourElementShuffle) { 2371 // Compute the index in the perfect shuffle table. 2372 unsigned PFTableIndex = 2373 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 2374 2375 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 2376 unsigned Cost = (PFEntry >> 30); 2377 2378 // Determining when to avoid vperm is tricky. Many things affect the cost 2379 // of vperm, particularly how many times the perm mask needs to be computed. 2380 // For example, if the perm mask can be hoisted out of a loop or is already 2381 // used (perhaps because there are multiple permutes with the same shuffle 2382 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 2383 // the loop requires an extra register. 2384 // 2385 // As a compromise, we only emit discrete instructions if the shuffle can be 2386 // generated in 3 or fewer operations. When we have loop information 2387 // available, if this block is within a loop, we should avoid using vperm 2388 // for 3-operation perms and use a constant pool load instead. 2389 if (Cost < 3) 2390 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG); 2391 } 2392 2393 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 2394 // vector that will get spilled to the constant pool. 2395 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 2396 2397 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 2398 // that it is in input element units, not in bytes. Convert now. 2399 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType()); 2400 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; 2401 2402 SmallVector<SDOperand, 16> ResultMask; 2403 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { 2404 unsigned SrcElt; 2405 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) 2406 SrcElt = 0; 2407 else 2408 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue(); 2409 2410 for (unsigned j = 0; j != BytesPerElement; ++j) 2411 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 2412 MVT::i8)); 2413 } 2414 2415 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, 2416 &ResultMask[0], ResultMask.size()); 2417 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); 2418} 2419 2420/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 2421/// altivec comparison. If it is, return true and fill in Opc/isDot with 2422/// information about the intrinsic. 2423static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc, 2424 bool &isDot) { 2425 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue(); 2426 CompareOpc = -1; 2427 isDot = false; 2428 switch (IntrinsicID) { 2429 default: return false; 2430 // Comparison predicates. 2431 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 2432 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 2433 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 2434 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 2435 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 2436 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 2437 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 2438 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 2439 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 2440 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 2441 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 2442 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 2443 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 2444 2445 // Normal Comparisons. 2446 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 2447 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 2448 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 2449 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 2450 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 2451 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 2452 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 2453 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 2454 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 2455 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 2456 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 2457 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 2458 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 2459 } 2460 return true; 2461} 2462 2463/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 2464/// lower, do it, otherwise return null. 2465static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { 2466 // If this is a lowered altivec predicate compare, CompareOpc is set to the 2467 // opcode number of the comparison. 2468 int CompareOpc; 2469 bool isDot; 2470 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 2471 return SDOperand(); // Don't custom lower most intrinsics. 2472 2473 // If this is a non-dot comparison, make the VCMP node and we are done. 2474 if (!isDot) { 2475 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), 2476 Op.getOperand(1), Op.getOperand(2), 2477 DAG.getConstant(CompareOpc, MVT::i32)); 2478 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); 2479 } 2480 2481 // Create the PPCISD altivec 'dot' comparison node. 2482 SDOperand Ops[] = { 2483 Op.getOperand(2), // LHS 2484 Op.getOperand(3), // RHS 2485 DAG.getConstant(CompareOpc, MVT::i32) 2486 }; 2487 std::vector<MVT::ValueType> VTs; 2488 VTs.push_back(Op.getOperand(2).getValueType()); 2489 VTs.push_back(MVT::Flag); 2490 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 2491 2492 // Now that we have the comparison, emit a copy from the CR to a GPR. 2493 // This is flagged to the above dot comparison. 2494 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, 2495 DAG.getRegister(PPC::CR6, MVT::i32), 2496 CompNode.getValue(1)); 2497 2498 // Unpack the result based on how the target uses it. 2499 unsigned BitNo; // Bit # of CR6. 2500 bool InvertBit; // Invert result? 2501 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { 2502 default: // Can't happen, don't crash on invalid number though. 2503 case 0: // Return the value of the EQ bit of CR6. 2504 BitNo = 0; InvertBit = false; 2505 break; 2506 case 1: // Return the inverted value of the EQ bit of CR6. 2507 BitNo = 0; InvertBit = true; 2508 break; 2509 case 2: // Return the value of the LT bit of CR6. 2510 BitNo = 2; InvertBit = false; 2511 break; 2512 case 3: // Return the inverted value of the LT bit of CR6. 2513 BitNo = 2; InvertBit = true; 2514 break; 2515 } 2516 2517 // Shift the bit into the low position. 2518 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, 2519 DAG.getConstant(8-(3-BitNo), MVT::i32)); 2520 // Isolate the bit. 2521 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, 2522 DAG.getConstant(1, MVT::i32)); 2523 2524 // If we are supposed to, toggle the bit. 2525 if (InvertBit) 2526 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, 2527 DAG.getConstant(1, MVT::i32)); 2528 return Flags; 2529} 2530 2531static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2532 // Create a stack slot that is 16-byte aligned. 2533 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2534 int FrameIdx = FrameInfo->CreateStackObject(16, 16); 2535 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2536 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2537 2538 // Store the input value into Value#0 of the stack slot. 2539 SDOperand Store = DAG.getStore(DAG.getEntryNode(), 2540 Op.getOperand(0), FIdx, NULL, 0); 2541 // Load it out. 2542 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); 2543} 2544 2545static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { 2546 if (Op.getValueType() == MVT::v4i32) { 2547 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2548 2549 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); 2550 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. 2551 2552 SDOperand RHSSwap = // = vrlw RHS, 16 2553 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG); 2554 2555 // Shrinkify inputs to v8i16. 2556 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS); 2557 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS); 2558 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap); 2559 2560 // Low parts multiplied together, generating 32-bit results (we ignore the 2561 // top parts). 2562 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 2563 LHS, RHS, DAG, MVT::v4i32); 2564 2565 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 2566 LHS, RHSSwap, Zero, DAG, MVT::v4i32); 2567 // Shift the high parts up 16 bits. 2568 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG); 2569 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd); 2570 } else if (Op.getValueType() == MVT::v8i16) { 2571 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2572 2573 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); 2574 2575 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 2576 LHS, RHS, Zero, DAG); 2577 } else if (Op.getValueType() == MVT::v16i8) { 2578 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2579 2580 // Multiply the even 8-bit parts, producing 16-bit sums. 2581 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 2582 LHS, RHS, DAG, MVT::v8i16); 2583 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts); 2584 2585 // Multiply the odd 8-bit parts, producing 16-bit sums. 2586 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 2587 LHS, RHS, DAG, MVT::v8i16); 2588 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); 2589 2590 // Merge the results together. 2591 SDOperand Ops[16]; 2592 for (unsigned i = 0; i != 8; ++i) { 2593 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); 2594 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); 2595 } 2596 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts, 2597 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 2598 } else { 2599 assert(0 && "Unknown mul to lower!"); 2600 abort(); 2601 } 2602} 2603 2604/// LowerOperation - Provide custom lowering hooks for some operations. 2605/// 2606SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 2607 switch (Op.getOpcode()) { 2608 default: assert(0 && "Wasn't expecting to be able to lower this!"); 2609 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 2610 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 2611 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 2612 case ISD::SETCC: return LowerSETCC(Op, DAG); 2613 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); 2614 case ISD::FORMAL_ARGUMENTS: 2615 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex); 2616 case ISD::CALL: return LowerCALL(Op, DAG); 2617 case ISD::RET: return LowerRET(Op, DAG); 2618 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 2619 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG, 2620 PPCSubTarget); 2621 2622 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 2623 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 2624 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 2625 2626 // Lower 64-bit shifts. 2627 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 2628 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 2629 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 2630 2631 // Vector-related lowering. 2632 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 2633 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 2634 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 2635 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 2636 case ISD::MUL: return LowerMUL(Op, DAG); 2637 } 2638 return SDOperand(); 2639} 2640 2641//===----------------------------------------------------------------------===// 2642// Other Lowering Code 2643//===----------------------------------------------------------------------===// 2644 2645MachineBasicBlock * 2646PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 2647 MachineBasicBlock *BB) { 2648 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2649 assert((MI->getOpcode() == PPC::SELECT_CC_I4 || 2650 MI->getOpcode() == PPC::SELECT_CC_I8 || 2651 MI->getOpcode() == PPC::SELECT_CC_F4 || 2652 MI->getOpcode() == PPC::SELECT_CC_F8 || 2653 MI->getOpcode() == PPC::SELECT_CC_VRRC) && 2654 "Unexpected instr type to insert"); 2655 2656 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 2657 // control-flow pattern. The incoming instruction knows the destination vreg 2658 // to set, the condition code register to branch on, the true/false values to 2659 // select between, and a branch opcode to use. 2660 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2661 ilist<MachineBasicBlock>::iterator It = BB; 2662 ++It; 2663 2664 // thisMBB: 2665 // ... 2666 // TrueVal = ... 2667 // cmpTY ccX, r1, r2 2668 // bCC copy1MBB 2669 // fallthrough --> copy0MBB 2670 MachineBasicBlock *thisMBB = BB; 2671 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 2672 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 2673 unsigned SelectPred = MI->getOperand(4).getImm(); 2674 BuildMI(BB, TII->get(PPC::BCC)) 2675 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 2676 MachineFunction *F = BB->getParent(); 2677 F->getBasicBlockList().insert(It, copy0MBB); 2678 F->getBasicBlockList().insert(It, sinkMBB); 2679 // Update machine-CFG edges by first adding all successors of the current 2680 // block to the new block which will contain the Phi node for the select. 2681 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 2682 e = BB->succ_end(); i != e; ++i) 2683 sinkMBB->addSuccessor(*i); 2684 // Next, remove all successors of the current block, and add the true 2685 // and fallthrough blocks as its successors. 2686 while(!BB->succ_empty()) 2687 BB->removeSuccessor(BB->succ_begin()); 2688 BB->addSuccessor(copy0MBB); 2689 BB->addSuccessor(sinkMBB); 2690 2691 // copy0MBB: 2692 // %FalseValue = ... 2693 // # fallthrough to sinkMBB 2694 BB = copy0MBB; 2695 2696 // Update machine-CFG edges 2697 BB->addSuccessor(sinkMBB); 2698 2699 // sinkMBB: 2700 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 2701 // ... 2702 BB = sinkMBB; 2703 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg()) 2704 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 2705 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 2706 2707 delete MI; // The pseudo instruction is gone now. 2708 return BB; 2709} 2710 2711//===----------------------------------------------------------------------===// 2712// Target Optimization Hooks 2713//===----------------------------------------------------------------------===// 2714 2715SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, 2716 DAGCombinerInfo &DCI) const { 2717 TargetMachine &TM = getTargetMachine(); 2718 SelectionDAG &DAG = DCI.DAG; 2719 switch (N->getOpcode()) { 2720 default: break; 2721 case PPCISD::SHL: 2722 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 2723 if (C->getValue() == 0) // 0 << V -> 0. 2724 return N->getOperand(0); 2725 } 2726 break; 2727 case PPCISD::SRL: 2728 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 2729 if (C->getValue() == 0) // 0 >>u V -> 0. 2730 return N->getOperand(0); 2731 } 2732 break; 2733 case PPCISD::SRA: 2734 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 2735 if (C->getValue() == 0 || // 0 >>s V -> 0. 2736 C->isAllOnesValue()) // -1 >>s V -> -1. 2737 return N->getOperand(0); 2738 } 2739 break; 2740 2741 case ISD::SINT_TO_FP: 2742 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 2743 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 2744 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 2745 // We allow the src/dst to be either f32/f64, but the intermediate 2746 // type must be i64. 2747 if (N->getOperand(0).getValueType() == MVT::i64) { 2748 SDOperand Val = N->getOperand(0).getOperand(0); 2749 if (Val.getValueType() == MVT::f32) { 2750 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 2751 DCI.AddToWorklist(Val.Val); 2752 } 2753 2754 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); 2755 DCI.AddToWorklist(Val.Val); 2756 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); 2757 DCI.AddToWorklist(Val.Val); 2758 if (N->getValueType(0) == MVT::f32) { 2759 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val); 2760 DCI.AddToWorklist(Val.Val); 2761 } 2762 return Val; 2763 } else if (N->getOperand(0).getValueType() == MVT::i32) { 2764 // If the intermediate type is i32, we can avoid the load/store here 2765 // too. 2766 } 2767 } 2768 } 2769 break; 2770 case ISD::STORE: 2771 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 2772 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 2773 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 2774 N->getOperand(1).getValueType() == MVT::i32) { 2775 SDOperand Val = N->getOperand(1).getOperand(0); 2776 if (Val.getValueType() == MVT::f32) { 2777 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 2778 DCI.AddToWorklist(Val.Val); 2779 } 2780 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); 2781 DCI.AddToWorklist(Val.Val); 2782 2783 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, 2784 N->getOperand(2), N->getOperand(3)); 2785 DCI.AddToWorklist(Val.Val); 2786 return Val; 2787 } 2788 2789 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 2790 if (N->getOperand(1).getOpcode() == ISD::BSWAP && 2791 N->getOperand(1).Val->hasOneUse() && 2792 (N->getOperand(1).getValueType() == MVT::i32 || 2793 N->getOperand(1).getValueType() == MVT::i16)) { 2794 SDOperand BSwapOp = N->getOperand(1).getOperand(0); 2795 // Do an any-extend to 32-bits if this is a half-word input. 2796 if (BSwapOp.getValueType() == MVT::i16) 2797 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp); 2798 2799 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp, 2800 N->getOperand(2), N->getOperand(3), 2801 DAG.getValueType(N->getOperand(1).getValueType())); 2802 } 2803 break; 2804 case ISD::BSWAP: 2805 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 2806 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) && 2807 N->getOperand(0).hasOneUse() && 2808 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 2809 SDOperand Load = N->getOperand(0); 2810 LoadSDNode *LD = cast<LoadSDNode>(Load); 2811 // Create the byte-swapping load. 2812 std::vector<MVT::ValueType> VTs; 2813 VTs.push_back(MVT::i32); 2814 VTs.push_back(MVT::Other); 2815 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset()); 2816 SDOperand Ops[] = { 2817 LD->getChain(), // Chain 2818 LD->getBasePtr(), // Ptr 2819 SV, // SrcValue 2820 DAG.getValueType(N->getValueType(0)) // VT 2821 }; 2822 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); 2823 2824 // If this is an i16 load, insert the truncate. 2825 SDOperand ResVal = BSLoad; 2826 if (N->getValueType(0) == MVT::i16) 2827 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad); 2828 2829 // First, combine the bswap away. This makes the value produced by the 2830 // load dead. 2831 DCI.CombineTo(N, ResVal); 2832 2833 // Next, combine the load away, we give it a bogus result value but a real 2834 // chain result. The result value is dead because the bswap is dead. 2835 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1)); 2836 2837 // Return N so it doesn't get rechecked! 2838 return SDOperand(N, 0); 2839 } 2840 2841 break; 2842 case PPCISD::VCMP: { 2843 // If a VCMPo node already exists with exactly the same operands as this 2844 // node, use its result instead of this node (VCMPo computes both a CR6 and 2845 // a normal output). 2846 // 2847 if (!N->getOperand(0).hasOneUse() && 2848 !N->getOperand(1).hasOneUse() && 2849 !N->getOperand(2).hasOneUse()) { 2850 2851 // Scan all of the users of the LHS, looking for VCMPo's that match. 2852 SDNode *VCMPoNode = 0; 2853 2854 SDNode *LHSN = N->getOperand(0).Val; 2855 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 2856 UI != E; ++UI) 2857 if ((*UI)->getOpcode() == PPCISD::VCMPo && 2858 (*UI)->getOperand(1) == N->getOperand(1) && 2859 (*UI)->getOperand(2) == N->getOperand(2) && 2860 (*UI)->getOperand(0) == N->getOperand(0)) { 2861 VCMPoNode = *UI; 2862 break; 2863 } 2864 2865 // If there is no VCMPo node, or if the flag value has a single use, don't 2866 // transform this. 2867 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 2868 break; 2869 2870 // Look at the (necessarily single) use of the flag value. If it has a 2871 // chain, this transformation is more complex. Note that multiple things 2872 // could use the value result, which we should ignore. 2873 SDNode *FlagUser = 0; 2874 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 2875 FlagUser == 0; ++UI) { 2876 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 2877 SDNode *User = *UI; 2878 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2879 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) { 2880 FlagUser = User; 2881 break; 2882 } 2883 } 2884 } 2885 2886 // If the user is a MFCR instruction, we know this is safe. Otherwise we 2887 // give up for right now. 2888 if (FlagUser->getOpcode() == PPCISD::MFCR) 2889 return SDOperand(VCMPoNode, 0); 2890 } 2891 break; 2892 } 2893 case ISD::BR_CC: { 2894 // If this is a branch on an altivec predicate comparison, lower this so 2895 // that we don't have to do a MFCR: instead, branch directly on CR6. This 2896 // lowering is done pre-legalize, because the legalizer lowers the predicate 2897 // compare down to code that is difficult to reassemble. 2898 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2899 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3); 2900 int CompareOpc; 2901 bool isDot; 2902 2903 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 2904 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 2905 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 2906 assert(isDot && "Can't compare against a vector result!"); 2907 2908 // If this is a comparison against something other than 0/1, then we know 2909 // that the condition is never/always true. 2910 unsigned Val = cast<ConstantSDNode>(RHS)->getValue(); 2911 if (Val != 0 && Val != 1) { 2912 if (CC == ISD::SETEQ) // Cond never true, remove branch. 2913 return N->getOperand(0); 2914 // Always !=, turn it into an unconditional branch. 2915 return DAG.getNode(ISD::BR, MVT::Other, 2916 N->getOperand(0), N->getOperand(4)); 2917 } 2918 2919 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 2920 2921 // Create the PPCISD altivec 'dot' comparison node. 2922 std::vector<MVT::ValueType> VTs; 2923 SDOperand Ops[] = { 2924 LHS.getOperand(2), // LHS of compare 2925 LHS.getOperand(3), // RHS of compare 2926 DAG.getConstant(CompareOpc, MVT::i32) 2927 }; 2928 VTs.push_back(LHS.getOperand(2).getValueType()); 2929 VTs.push_back(MVT::Flag); 2930 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 2931 2932 // Unpack the result based on how the target uses it. 2933 PPC::Predicate CompOpc; 2934 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) { 2935 default: // Can't happen, don't crash on invalid number though. 2936 case 0: // Branch on the value of the EQ bit of CR6. 2937 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 2938 break; 2939 case 1: // Branch on the inverted value of the EQ bit of CR6. 2940 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 2941 break; 2942 case 2: // Branch on the value of the LT bit of CR6. 2943 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 2944 break; 2945 case 3: // Branch on the inverted value of the LT bit of CR6. 2946 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 2947 break; 2948 } 2949 2950 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), 2951 DAG.getConstant(CompOpc, MVT::i32), 2952 DAG.getRegister(PPC::CR6, MVT::i32), 2953 N->getOperand(4), CompNode.getValue(1)); 2954 } 2955 break; 2956 } 2957 } 2958 2959 return SDOperand(); 2960} 2961 2962//===----------------------------------------------------------------------===// 2963// Inline Assembly Support 2964//===----------------------------------------------------------------------===// 2965 2966void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 2967 uint64_t Mask, 2968 uint64_t &KnownZero, 2969 uint64_t &KnownOne, 2970 unsigned Depth) const { 2971 KnownZero = 0; 2972 KnownOne = 0; 2973 switch (Op.getOpcode()) { 2974 default: break; 2975 case PPCISD::LBRX: { 2976 // lhbrx is known to have the top bits cleared out. 2977 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16) 2978 KnownZero = 0xFFFF0000; 2979 break; 2980 } 2981 case ISD::INTRINSIC_WO_CHAIN: { 2982 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) { 2983 default: break; 2984 case Intrinsic::ppc_altivec_vcmpbfp_p: 2985 case Intrinsic::ppc_altivec_vcmpeqfp_p: 2986 case Intrinsic::ppc_altivec_vcmpequb_p: 2987 case Intrinsic::ppc_altivec_vcmpequh_p: 2988 case Intrinsic::ppc_altivec_vcmpequw_p: 2989 case Intrinsic::ppc_altivec_vcmpgefp_p: 2990 case Intrinsic::ppc_altivec_vcmpgtfp_p: 2991 case Intrinsic::ppc_altivec_vcmpgtsb_p: 2992 case Intrinsic::ppc_altivec_vcmpgtsh_p: 2993 case Intrinsic::ppc_altivec_vcmpgtsw_p: 2994 case Intrinsic::ppc_altivec_vcmpgtub_p: 2995 case Intrinsic::ppc_altivec_vcmpgtuh_p: 2996 case Intrinsic::ppc_altivec_vcmpgtuw_p: 2997 KnownZero = ~1U; // All bits but the low one are known to be zero. 2998 break; 2999 } 3000 } 3001 } 3002} 3003 3004 3005/// getConstraintType - Given a constraint letter, return the type of 3006/// constraint it is for this target. 3007PPCTargetLowering::ConstraintType 3008PPCTargetLowering::getConstraintType(char ConstraintLetter) const { 3009 switch (ConstraintLetter) { 3010 default: break; 3011 case 'b': 3012 case 'r': 3013 case 'f': 3014 case 'v': 3015 case 'y': 3016 return C_RegisterClass; 3017 } 3018 return TargetLowering::getConstraintType(ConstraintLetter); 3019} 3020 3021std::pair<unsigned, const TargetRegisterClass*> 3022PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 3023 MVT::ValueType VT) const { 3024 if (Constraint.size() == 1) { 3025 // GCC RS6000 Constraint Letters 3026 switch (Constraint[0]) { 3027 case 'b': // R1-R31 3028 case 'r': // R0-R31 3029 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 3030 return std::make_pair(0U, PPC::G8RCRegisterClass); 3031 return std::make_pair(0U, PPC::GPRCRegisterClass); 3032 case 'f': 3033 if (VT == MVT::f32) 3034 return std::make_pair(0U, PPC::F4RCRegisterClass); 3035 else if (VT == MVT::f64) 3036 return std::make_pair(0U, PPC::F8RCRegisterClass); 3037 break; 3038 case 'v': 3039 return std::make_pair(0U, PPC::VRRCRegisterClass); 3040 case 'y': // crrc 3041 return std::make_pair(0U, PPC::CRRCRegisterClass); 3042 } 3043 } 3044 3045 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3046} 3047 3048 3049// isOperandValidForConstraint 3050SDOperand PPCTargetLowering:: 3051isOperandValidForConstraint(SDOperand Op, char Letter, SelectionDAG &DAG) { 3052 switch (Letter) { 3053 default: break; 3054 case 'I': 3055 case 'J': 3056 case 'K': 3057 case 'L': 3058 case 'M': 3059 case 'N': 3060 case 'O': 3061 case 'P': { 3062 if (!isa<ConstantSDNode>(Op)) return SDOperand(0,0);// Must be an immediate. 3063 unsigned Value = cast<ConstantSDNode>(Op)->getValue(); 3064 switch (Letter) { 3065 default: assert(0 && "Unknown constraint letter!"); 3066 case 'I': // "I" is a signed 16-bit constant. 3067 if ((short)Value == (int)Value) return Op; 3068 break; 3069 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 3070 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 3071 if ((short)Value == 0) return Op; 3072 break; 3073 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 3074 if ((Value >> 16) == 0) return Op; 3075 break; 3076 case 'M': // "M" is a constant that is greater than 31. 3077 if (Value > 31) return Op; 3078 break; 3079 case 'N': // "N" is a positive constant that is an exact power of two. 3080 if ((int)Value > 0 && isPowerOf2_32(Value)) return Op; 3081 break; 3082 case 'O': // "O" is the constant zero. 3083 if (Value == 0) return Op; 3084 break; 3085 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 3086 if ((short)-Value == (int)-Value) return Op; 3087 break; 3088 } 3089 break; 3090 } 3091 } 3092 3093 // Handle standard constraint letters. 3094 return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG); 3095} 3096 3097/// isLegalAddressImmediate - Return true if the integer value can be used 3098/// as the offset of the target addressing mode. 3099bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const { 3100 // PPC allows a sign-extended 16-bit immediate field. 3101 return (V > -(1 << 16) && V < (1 << 16)-1); 3102} 3103 3104bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 3105 return TargetLowering::isLegalAddressImmediate(GV); 3106} 3107