PPCISelLowering.cpp revision b453e16855f347e300f1dc0cd0dfbdd65c27b0d2
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "MCTargetDesc/PPCPredicates.h" 16#include "PPCMachineFunctionInfo.h" 17#include "PPCPerfectShuffle.h" 18#include "PPCTargetMachine.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/CallingConv.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/SelectionDAG.h" 27#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 28#include "llvm/Constants.h" 29#include "llvm/DerivedTypes.h" 30#include "llvm/Function.h" 31#include "llvm/Intrinsics.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/Target/TargetOptions.h" 37using namespace llvm; 38 39static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 40 CCValAssign::LocInfo &LocInfo, 41 ISD::ArgFlagsTy &ArgFlags, 42 CCState &State); 43static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 44 MVT &LocVT, 45 CCValAssign::LocInfo &LocInfo, 46 ISD::ArgFlagsTy &ArgFlags, 47 CCState &State); 48static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 49 MVT &LocVT, 50 CCValAssign::LocInfo &LocInfo, 51 ISD::ArgFlagsTy &ArgFlags, 52 CCState &State); 53 54static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc", 55cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden); 56 57static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref", 58cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden); 59 60static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) { 61 if (TM.getSubtargetImpl()->isDarwin()) 62 return new TargetLoweringObjectFileMachO(); 63 64 return new TargetLoweringObjectFileELF(); 65} 66 67PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) { 69 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>(); 70 71 setPow2DivIsCheap(); 72 73 // Use _setjmp/_longjmp instead of setjmp/longjmp. 74 setUseUnderscoreSetJmp(true); 75 setUseUnderscoreLongJmp(true); 76 77 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all 78 // arguments are at least 4/8 bytes aligned. 79 bool isPPC64 = Subtarget->isPPC64(); 80 setMinStackArgumentAlignment(isPPC64 ? 8:4); 81 82 // Set up the register classes. 83 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); 84 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); 85 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); 86 87 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 88 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 90 91 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 92 93 // PowerPC has pre-inc load and store's. 94 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 95 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 96 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 97 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 98 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 99 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 100 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 101 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 102 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 103 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 104 105 // This is used in the ppcf128->int sequence. Note it has different semantics 106 // from FP_ROUND: that rounds to nearest, this rounds to zero. 107 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 108 109 // We do not currently implement these libm ops for PowerPC. 110 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand); 111 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); 112 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand); 113 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand); 114 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand); 115 116 // PowerPC has no SREM/UREM instructions 117 setOperationAction(ISD::SREM, MVT::i32, Expand); 118 setOperationAction(ISD::UREM, MVT::i32, Expand); 119 setOperationAction(ISD::SREM, MVT::i64, Expand); 120 setOperationAction(ISD::UREM, MVT::i64, Expand); 121 122 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 123 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 124 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 125 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 126 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 127 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 128 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 129 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 130 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 131 132 // We don't support sin/cos/sqrt/fmod/pow 133 setOperationAction(ISD::FSIN , MVT::f64, Expand); 134 setOperationAction(ISD::FCOS , MVT::f64, Expand); 135 setOperationAction(ISD::FREM , MVT::f64, Expand); 136 setOperationAction(ISD::FPOW , MVT::f64, Expand); 137 setOperationAction(ISD::FMA , MVT::f64, Legal); 138 setOperationAction(ISD::FSIN , MVT::f32, Expand); 139 setOperationAction(ISD::FCOS , MVT::f32, Expand); 140 setOperationAction(ISD::FREM , MVT::f32, Expand); 141 setOperationAction(ISD::FPOW , MVT::f32, Expand); 142 setOperationAction(ISD::FMA , MVT::f32, Legal); 143 144 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 145 146 // If we're enabling GP optimizations, use hardware square root 147 if (!Subtarget->hasFSQRT()) { 148 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 149 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 150 } 151 152 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 153 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 154 155 // PowerPC does not have BSWAP, CTPOP or CTTZ 156 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 157 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 158 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 159 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 160 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 161 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 162 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 163 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 164 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 165 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 166 167 // PowerPC does not have ROTR 168 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 169 setOperationAction(ISD::ROTR, MVT::i64 , Expand); 170 171 // PowerPC does not have Select 172 setOperationAction(ISD::SELECT, MVT::i32, Expand); 173 setOperationAction(ISD::SELECT, MVT::i64, Expand); 174 setOperationAction(ISD::SELECT, MVT::f32, Expand); 175 setOperationAction(ISD::SELECT, MVT::f64, Expand); 176 177 // PowerPC wants to turn select_cc of FP into fsel when possible. 178 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 179 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 180 181 // PowerPC wants to optimize integer setcc a bit 182 setOperationAction(ISD::SETCC, MVT::i32, Custom); 183 184 // PowerPC does not have BRCOND which requires SetCC 185 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 186 187 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 188 189 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 190 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 191 192 // PowerPC does not have [U|S]INT_TO_FP 193 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 194 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 195 196 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 197 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 198 setOperationAction(ISD::BITCAST, MVT::i64, Expand); 199 setOperationAction(ISD::BITCAST, MVT::f64, Expand); 200 201 // We cannot sextinreg(i1). Expand to shifts. 202 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 203 204 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 205 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 206 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 207 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 208 209 210 // We want to legalize GlobalAddress and ConstantPool nodes into the 211 // appropriate instructions to materialize the address. 212 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 213 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 214 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 215 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 216 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 217 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 218 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 219 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 220 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 221 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 222 223 // TRAP is legal. 224 setOperationAction(ISD::TRAP, MVT::Other, Legal); 225 226 // TRAMPOLINE is custom lowered. 227 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 228 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 229 230 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 231 setOperationAction(ISD::VASTART , MVT::Other, Custom); 232 233 if (Subtarget->isSVR4ABI()) { 234 if (isPPC64) { 235 // VAARG always uses double-word chunks, so promote anything smaller. 236 setOperationAction(ISD::VAARG, MVT::i1, Promote); 237 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64); 238 setOperationAction(ISD::VAARG, MVT::i8, Promote); 239 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64); 240 setOperationAction(ISD::VAARG, MVT::i16, Promote); 241 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64); 242 setOperationAction(ISD::VAARG, MVT::i32, Promote); 243 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64); 244 setOperationAction(ISD::VAARG, MVT::Other, Expand); 245 } else { 246 // VAARG is custom lowered with the 32-bit SVR4 ABI. 247 setOperationAction(ISD::VAARG, MVT::Other, Custom); 248 setOperationAction(ISD::VAARG, MVT::i64, Custom); 249 } 250 } else 251 setOperationAction(ISD::VAARG, MVT::Other, Expand); 252 253 // Use the default implementation. 254 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 255 setOperationAction(ISD::VAEND , MVT::Other, Expand); 256 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 257 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 258 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 259 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 260 261 // We want to custom lower some of our intrinsics. 262 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 263 264 // Comparisons that require checking two conditions. 265 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 266 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); 267 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); 268 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); 269 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); 270 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); 271 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 272 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 273 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 274 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 275 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); 276 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); 277 278 if (Subtarget->has64BitSupport()) { 279 // They also have instructions for converting between i64 and fp. 280 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 281 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 282 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 283 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 284 // This is just the low 32 bits of a (signed) fp->i64 conversion. 285 // We cannot do this with Promote because i64 is not a legal type. 286 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 287 288 // FIXME: disable this lowered code. This generates 64-bit register values, 289 // and we don't model the fact that the top part is clobbered by calls. We 290 // need to flag these together so that the value isn't live across a call. 291 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 292 } else { 293 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 294 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 295 } 296 297 if (Subtarget->use64BitRegs()) { 298 // 64-bit PowerPC implementations can support i64 types directly 299 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); 300 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 301 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 302 // 64-bit PowerPC wants to expand i128 shifts itself. 303 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 304 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 305 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 306 } else { 307 // 32-bit PowerPC wants to expand i64 shifts itself. 308 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 309 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 310 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 311 } 312 313 if (Subtarget->hasAltivec()) { 314 // First set operation action for all vector types to expand. Then we 315 // will selectively turn on ones that can be effectively codegen'd. 316 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 317 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 318 MVT::SimpleValueType VT = (MVT::SimpleValueType)i; 319 320 // add/sub are legal for all supported vector VT's. 321 setOperationAction(ISD::ADD , VT, Legal); 322 setOperationAction(ISD::SUB , VT, Legal); 323 324 // We promote all shuffles to v16i8. 325 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 326 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 327 328 // We promote all non-typed operations to v4i32. 329 setOperationAction(ISD::AND , VT, Promote); 330 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 331 setOperationAction(ISD::OR , VT, Promote); 332 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 333 setOperationAction(ISD::XOR , VT, Promote); 334 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 335 setOperationAction(ISD::LOAD , VT, Promote); 336 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 337 setOperationAction(ISD::SELECT, VT, Promote); 338 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 339 setOperationAction(ISD::STORE, VT, Promote); 340 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 341 342 // No other operations are legal. 343 setOperationAction(ISD::MUL , VT, Expand); 344 setOperationAction(ISD::SDIV, VT, Expand); 345 setOperationAction(ISD::SREM, VT, Expand); 346 setOperationAction(ISD::UDIV, VT, Expand); 347 setOperationAction(ISD::UREM, VT, Expand); 348 setOperationAction(ISD::FDIV, VT, Expand); 349 setOperationAction(ISD::FNEG, VT, Expand); 350 setOperationAction(ISD::FSQRT, VT, Expand); 351 setOperationAction(ISD::FLOG, VT, Expand); 352 setOperationAction(ISD::FLOG10, VT, Expand); 353 setOperationAction(ISD::FLOG2, VT, Expand); 354 setOperationAction(ISD::FEXP, VT, Expand); 355 setOperationAction(ISD::FEXP2, VT, Expand); 356 setOperationAction(ISD::FSIN, VT, Expand); 357 setOperationAction(ISD::FCOS, VT, Expand); 358 setOperationAction(ISD::FABS, VT, Expand); 359 setOperationAction(ISD::FPOWI, VT, Expand); 360 setOperationAction(ISD::FFLOOR, VT, Expand); 361 setOperationAction(ISD::FCEIL, VT, Expand); 362 setOperationAction(ISD::FTRUNC, VT, Expand); 363 setOperationAction(ISD::FRINT, VT, Expand); 364 setOperationAction(ISD::FNEARBYINT, VT, Expand); 365 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); 366 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 367 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); 368 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 369 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 370 setOperationAction(ISD::UDIVREM, VT, Expand); 371 setOperationAction(ISD::SDIVREM, VT, Expand); 372 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); 373 setOperationAction(ISD::FPOW, VT, Expand); 374 setOperationAction(ISD::CTPOP, VT, Expand); 375 setOperationAction(ISD::CTLZ, VT, Expand); 376 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); 377 setOperationAction(ISD::CTTZ, VT, Expand); 378 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); 379 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); 380 381 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 382 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) { 383 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j; 384 setTruncStoreAction(VT, InnerVT, Expand); 385 } 386 setLoadExtAction(ISD::SEXTLOAD, VT, Expand); 387 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand); 388 setLoadExtAction(ISD::EXTLOAD, VT, Expand); 389 } 390 391 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 392 // with merges, splats, etc. 393 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 394 395 setOperationAction(ISD::AND , MVT::v4i32, Legal); 396 setOperationAction(ISD::OR , MVT::v4i32, Legal); 397 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 398 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 399 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 400 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 401 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 402 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal); 403 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 404 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); 405 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); 406 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); 407 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); 408 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); 409 410 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); 411 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); 412 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); 413 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass); 414 415 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 416 setOperationAction(ISD::FMA, MVT::v4f32, Legal); 417 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 418 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 419 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 420 421 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 422 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 423 424 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 425 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 426 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 427 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 428 429 // Altivec does not contain unordered floating-point compare instructions 430 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand); 431 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand); 432 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand); 433 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand); 434 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand); 435 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand); 436 } 437 438 if (Subtarget->has64BitSupport()) { 439 setOperationAction(ISD::PREFETCH, MVT::Other, Legal); 440 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal); 441 } 442 443 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 444 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 445 446 setBooleanContents(ZeroOrOneBooleanContent); 447 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 448 449 if (isPPC64) { 450 setStackPointerRegisterToSaveRestore(PPC::X1); 451 setExceptionPointerRegister(PPC::X3); 452 setExceptionSelectorRegister(PPC::X4); 453 } else { 454 setStackPointerRegisterToSaveRestore(PPC::R1); 455 setExceptionPointerRegister(PPC::R3); 456 setExceptionSelectorRegister(PPC::R4); 457 } 458 459 // We have target-specific dag combine patterns for the following nodes: 460 setTargetDAGCombine(ISD::SINT_TO_FP); 461 setTargetDAGCombine(ISD::STORE); 462 setTargetDAGCombine(ISD::BR_CC); 463 setTargetDAGCombine(ISD::BSWAP); 464 465 // Darwin long double math library functions have $LDBL128 appended. 466 if (Subtarget->isDarwin()) { 467 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 468 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 469 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 470 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 471 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 472 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128"); 473 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128"); 474 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128"); 475 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128"); 476 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128"); 477 } 478 479 setMinFunctionAlignment(2); 480 if (PPCSubTarget.isDarwin()) 481 setPrefFunctionAlignment(4); 482 483 if (isPPC64 && Subtarget->isJITCodeModel()) 484 // Temporary workaround for the inability of PPC64 JIT to handle jump 485 // tables. 486 setSupportJumpTables(false); 487 488 setInsertFencesForAtomic(true); 489 490 setSchedulingPreference(Sched::Hybrid); 491 492 computeRegisterProperties(); 493 494 // The Freescale cores does better with aggressive inlining of memcpy and 495 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores). 496 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc || 497 Subtarget->getDarwinDirective() == PPC::DIR_E5500) { 498 maxStoresPerMemset = 32; 499 maxStoresPerMemsetOptSize = 16; 500 maxStoresPerMemcpy = 32; 501 maxStoresPerMemcpyOptSize = 8; 502 maxStoresPerMemmove = 32; 503 maxStoresPerMemmoveOptSize = 8; 504 505 setPrefFunctionAlignment(4); 506 benefitFromCodePlacementOpt = true; 507 } 508} 509 510/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 511/// function arguments in the caller parameter area. 512unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const { 513 const TargetMachine &TM = getTargetMachine(); 514 // Darwin passes everything on 4 byte boundary. 515 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) 516 return 4; 517 518 // 16byte and wider vectors are passed on 16byte boundary. 519 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) 520 if (VTy->getBitWidth() >= 128) 521 return 16; 522 523 // The rest is 8 on PPC64 and 4 on PPC32 boundary. 524 if (PPCSubTarget.isPPC64()) 525 return 8; 526 527 return 4; 528} 529 530const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 531 switch (Opcode) { 532 default: return 0; 533 case PPCISD::FSEL: return "PPCISD::FSEL"; 534 case PPCISD::FCFID: return "PPCISD::FCFID"; 535 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 536 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 537 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 538 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 539 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 540 case PPCISD::VPERM: return "PPCISD::VPERM"; 541 case PPCISD::Hi: return "PPCISD::Hi"; 542 case PPCISD::Lo: return "PPCISD::Lo"; 543 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY"; 544 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE"; 545 case PPCISD::LOAD: return "PPCISD::LOAD"; 546 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC"; 547 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 548 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 549 case PPCISD::SRL: return "PPCISD::SRL"; 550 case PPCISD::SRA: return "PPCISD::SRA"; 551 case PPCISD::SHL: return "PPCISD::SHL"; 552 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 553 case PPCISD::STD_32: return "PPCISD::STD_32"; 554 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4"; 555 case PPCISD::CALL_NOP_SVR4: return "PPCISD::CALL_NOP_SVR4"; 556 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin"; 557 case PPCISD::NOP: return "PPCISD::NOP"; 558 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 559 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin"; 560 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4"; 561 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 562 case PPCISD::MFCR: return "PPCISD::MFCR"; 563 case PPCISD::VCMP: return "PPCISD::VCMP"; 564 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 565 case PPCISD::LBRX: return "PPCISD::LBRX"; 566 case PPCISD::STBRX: return "PPCISD::STBRX"; 567 case PPCISD::LARX: return "PPCISD::LARX"; 568 case PPCISD::STCX: return "PPCISD::STCX"; 569 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 570 case PPCISD::MFFS: return "PPCISD::MFFS"; 571 case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; 572 case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; 573 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 574 case PPCISD::MTFSF: return "PPCISD::MTFSF"; 575 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; 576 case PPCISD::CR6SET: return "PPCISD::CR6SET"; 577 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET"; 578 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA"; 579 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L"; 580 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L"; 581 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA"; 582 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L"; 583 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS"; 584 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA"; 585 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L"; 586 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR"; 587 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA"; 588 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L"; 589 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR"; 590 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA"; 591 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L"; 592 } 593} 594 595EVT PPCTargetLowering::getSetCCResultType(EVT VT) const { 596 if (!VT.isVector()) 597 return MVT::i32; 598 return VT.changeVectorElementTypeToInteger(); 599} 600 601//===----------------------------------------------------------------------===// 602// Node matching predicates, for use by the tblgen matching code. 603//===----------------------------------------------------------------------===// 604 605/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 606static bool isFloatingPointZero(SDValue Op) { 607 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 608 return CFP->getValueAPF().isZero(); 609 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 610 // Maybe this has already been legalized into the constant pool? 611 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 612 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 613 return CFP->getValueAPF().isZero(); 614 } 615 return false; 616} 617 618/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 619/// true if Op is undef or if it matches the specified value. 620static bool isConstantOrUndef(int Op, int Val) { 621 return Op < 0 || Op == Val; 622} 623 624/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 625/// VPKUHUM instruction. 626bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 627 if (!isUnary) { 628 for (unsigned i = 0; i != 16; ++i) 629 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1)) 630 return false; 631 } else { 632 for (unsigned i = 0; i != 8; ++i) 633 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) || 634 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1)) 635 return false; 636 } 637 return true; 638} 639 640/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 641/// VPKUWUM instruction. 642bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 643 if (!isUnary) { 644 for (unsigned i = 0; i != 16; i += 2) 645 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 646 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3)) 647 return false; 648 } else { 649 for (unsigned i = 0; i != 8; i += 2) 650 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 651 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) || 652 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) || 653 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3)) 654 return false; 655 } 656 return true; 657} 658 659/// isVMerge - Common function, used to match vmrg* shuffles. 660/// 661static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, 662 unsigned LHSStart, unsigned RHSStart) { 663 assert(N->getValueType(0) == MVT::v16i8 && 664 "PPC only supports shuffles by bytes!"); 665 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 666 "Unsupported merge size!"); 667 668 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 669 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 670 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j), 671 LHSStart+j+i*UnitSize) || 672 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j), 673 RHSStart+j+i*UnitSize)) 674 return false; 675 } 676 return true; 677} 678 679/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 680/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 681bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 682 bool isUnary) { 683 if (!isUnary) 684 return isVMerge(N, UnitSize, 8, 24); 685 return isVMerge(N, UnitSize, 8, 8); 686} 687 688/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 689/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 690bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 691 bool isUnary) { 692 if (!isUnary) 693 return isVMerge(N, UnitSize, 0, 16); 694 return isVMerge(N, UnitSize, 0, 0); 695} 696 697 698/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 699/// amount, otherwise return -1. 700int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 701 assert(N->getValueType(0) == MVT::v16i8 && 702 "PPC only supports shuffles by bytes!"); 703 704 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 705 706 // Find the first non-undef value in the shuffle mask. 707 unsigned i; 708 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i) 709 /*search*/; 710 711 if (i == 16) return -1; // all undef. 712 713 // Otherwise, check to see if the rest of the elements are consecutively 714 // numbered from this value. 715 unsigned ShiftAmt = SVOp->getMaskElt(i); 716 if (ShiftAmt < i) return -1; 717 ShiftAmt -= i; 718 719 if (!isUnary) { 720 // Check the rest of the elements to see if they are consecutive. 721 for (++i; i != 16; ++i) 722 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) 723 return -1; 724 } else { 725 // Check the rest of the elements to see if they are consecutive. 726 for (++i; i != 16; ++i) 727 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) 728 return -1; 729 } 730 return ShiftAmt; 731} 732 733/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 734/// specifies a splat of a single element that is suitable for input to 735/// VSPLTB/VSPLTH/VSPLTW. 736bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { 737 assert(N->getValueType(0) == MVT::v16i8 && 738 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 739 740 // This is a splat operation if each element of the permute is the same, and 741 // if the value doesn't reference the second vector. 742 unsigned ElementBase = N->getMaskElt(0); 743 744 // FIXME: Handle UNDEF elements too! 745 if (ElementBase >= 16) 746 return false; 747 748 // Check that the indices are consecutive, in the case of a multi-byte element 749 // splatted with a v16i8 mask. 750 for (unsigned i = 1; i != EltSize; ++i) 751 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase)) 752 return false; 753 754 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 755 if (N->getMaskElt(i) < 0) continue; 756 for (unsigned j = 0; j != EltSize; ++j) 757 if (N->getMaskElt(i+j) != N->getMaskElt(j)) 758 return false; 759 } 760 return true; 761} 762 763/// isAllNegativeZeroVector - Returns true if all elements of build_vector 764/// are -0.0. 765bool PPC::isAllNegativeZeroVector(SDNode *N) { 766 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N); 767 768 APInt APVal, APUndef; 769 unsigned BitSize; 770 bool HasAnyUndefs; 771 772 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true)) 773 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 774 return CFP->getValueAPF().isNegZero(); 775 776 return false; 777} 778 779/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 780/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 781unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 782 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 783 assert(isSplatShuffleMask(SVOp, EltSize)); 784 return SVOp->getMaskElt(0) / EltSize; 785} 786 787/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 788/// by using a vspltis[bhw] instruction of the specified element size, return 789/// the constant being splatted. The ByteSize field indicates the number of 790/// bytes of each element [124] -> [bhw]. 791SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 792 SDValue OpVal(0, 0); 793 794 // If ByteSize of the splat is bigger than the element size of the 795 // build_vector, then we have a case where we are checking for a splat where 796 // multiple elements of the buildvector are folded together into a single 797 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 798 unsigned EltSize = 16/N->getNumOperands(); 799 if (EltSize < ByteSize) { 800 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 801 SDValue UniquedVals[4]; 802 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 803 804 // See if all of the elements in the buildvector agree across. 805 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 806 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 807 // If the element isn't a constant, bail fully out. 808 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue(); 809 810 811 if (UniquedVals[i&(Multiple-1)].getNode() == 0) 812 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 813 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 814 return SDValue(); // no match. 815 } 816 817 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 818 // either constant or undef values that are identical for each chunk. See 819 // if these chunks can form into a larger vspltis*. 820 821 // Check to see if all of the leading entries are either 0 or -1. If 822 // neither, then this won't fit into the immediate field. 823 bool LeadingZero = true; 824 bool LeadingOnes = true; 825 for (unsigned i = 0; i != Multiple-1; ++i) { 826 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs. 827 828 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 829 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 830 } 831 // Finally, check the least significant entry. 832 if (LeadingZero) { 833 if (UniquedVals[Multiple-1].getNode() == 0) 834 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 835 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue(); 836 if (Val < 16) 837 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 838 } 839 if (LeadingOnes) { 840 if (UniquedVals[Multiple-1].getNode() == 0) 841 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 842 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue(); 843 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 844 return DAG.getTargetConstant(Val, MVT::i32); 845 } 846 847 return SDValue(); 848 } 849 850 // Check to see if this buildvec has a single non-undef value in its elements. 851 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 852 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 853 if (OpVal.getNode() == 0) 854 OpVal = N->getOperand(i); 855 else if (OpVal != N->getOperand(i)) 856 return SDValue(); 857 } 858 859 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def. 860 861 unsigned ValSizeInBytes = EltSize; 862 uint64_t Value = 0; 863 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 864 Value = CN->getZExtValue(); 865 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 866 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 867 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 868 } 869 870 // If the splat value is larger than the element value, then we can never do 871 // this splat. The only case that we could fit the replicated bits into our 872 // immediate field for would be zero, and we prefer to use vxor for it. 873 if (ValSizeInBytes < ByteSize) return SDValue(); 874 875 // If the element value is larger than the splat value, cut it in half and 876 // check to see if the two halves are equal. Continue doing this until we 877 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 878 while (ValSizeInBytes > ByteSize) { 879 ValSizeInBytes >>= 1; 880 881 // If the top half equals the bottom half, we're still ok. 882 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 883 (Value & ((1 << (8*ValSizeInBytes))-1))) 884 return SDValue(); 885 } 886 887 // Properly sign extend the value. 888 int MaskVal = SignExtend32(Value, ByteSize * 8); 889 890 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 891 if (MaskVal == 0) return SDValue(); 892 893 // Finally, if this value fits in a 5 bit sext field, return it 894 if (SignExtend32<5>(MaskVal) == MaskVal) 895 return DAG.getTargetConstant(MaskVal, MVT::i32); 896 return SDValue(); 897} 898 899//===----------------------------------------------------------------------===// 900// Addressing Mode Selection 901//===----------------------------------------------------------------------===// 902 903/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 904/// or 64-bit immediate, and if the value can be accurately represented as a 905/// sign extension from a 16-bit value. If so, this returns true and the 906/// immediate. 907static bool isIntS16Immediate(SDNode *N, short &Imm) { 908 if (N->getOpcode() != ISD::Constant) 909 return false; 910 911 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 912 if (N->getValueType(0) == MVT::i32) 913 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 914 else 915 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 916} 917static bool isIntS16Immediate(SDValue Op, short &Imm) { 918 return isIntS16Immediate(Op.getNode(), Imm); 919} 920 921 922/// SelectAddressRegReg - Given the specified addressed, check to see if it 923/// can be represented as an indexed [r+r] operation. Returns false if it 924/// can be more efficiently represented with [r+imm]. 925bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, 926 SDValue &Index, 927 SelectionDAG &DAG) const { 928 short imm = 0; 929 if (N.getOpcode() == ISD::ADD) { 930 if (isIntS16Immediate(N.getOperand(1), imm)) 931 return false; // r+i 932 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 933 return false; // r+i 934 935 Base = N.getOperand(0); 936 Index = N.getOperand(1); 937 return true; 938 } else if (N.getOpcode() == ISD::OR) { 939 if (isIntS16Immediate(N.getOperand(1), imm)) 940 return false; // r+i can fold it if we can. 941 942 // If this is an or of disjoint bitfields, we can codegen this as an add 943 // (for better address arithmetic) if the LHS and RHS of the OR are provably 944 // disjoint. 945 APInt LHSKnownZero, LHSKnownOne; 946 APInt RHSKnownZero, RHSKnownOne; 947 DAG.ComputeMaskedBits(N.getOperand(0), 948 LHSKnownZero, LHSKnownOne); 949 950 if (LHSKnownZero.getBoolValue()) { 951 DAG.ComputeMaskedBits(N.getOperand(1), 952 RHSKnownZero, RHSKnownOne); 953 // If all of the bits are known zero on the LHS or RHS, the add won't 954 // carry. 955 if (~(LHSKnownZero | RHSKnownZero) == 0) { 956 Base = N.getOperand(0); 957 Index = N.getOperand(1); 958 return true; 959 } 960 } 961 } 962 963 return false; 964} 965 966/// Returns true if the address N can be represented by a base register plus 967/// a signed 16-bit displacement [r+imm], and if it is not better 968/// represented as reg+reg. 969bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, 970 SDValue &Base, 971 SelectionDAG &DAG) const { 972 // FIXME dl should come from parent load or store, not from address 973 DebugLoc dl = N.getDebugLoc(); 974 // If this can be more profitably realized as r+r, fail. 975 if (SelectAddressRegReg(N, Disp, Base, DAG)) 976 return false; 977 978 if (N.getOpcode() == ISD::ADD) { 979 short imm = 0; 980 if (isIntS16Immediate(N.getOperand(1), imm)) { 981 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 982 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 983 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 984 } else { 985 Base = N.getOperand(0); 986 } 987 return true; // [r+i] 988 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 989 // Match LOAD (ADD (X, Lo(G))). 990 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 991 && "Cannot handle constant offsets yet!"); 992 Disp = N.getOperand(1).getOperand(0); // The global address. 993 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 994 Disp.getOpcode() == ISD::TargetGlobalTLSAddress || 995 Disp.getOpcode() == ISD::TargetConstantPool || 996 Disp.getOpcode() == ISD::TargetJumpTable); 997 Base = N.getOperand(0); 998 return true; // [&g+r] 999 } 1000 } else if (N.getOpcode() == ISD::OR) { 1001 short imm = 0; 1002 if (isIntS16Immediate(N.getOperand(1), imm)) { 1003 // If this is an or of disjoint bitfields, we can codegen this as an add 1004 // (for better address arithmetic) if the LHS and RHS of the OR are 1005 // provably disjoint. 1006 APInt LHSKnownZero, LHSKnownOne; 1007 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne); 1008 1009 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 1010 // If all of the bits are known zero on the LHS or RHS, the add won't 1011 // carry. 1012 Base = N.getOperand(0); 1013 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 1014 return true; 1015 } 1016 } 1017 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 1018 // Loading from a constant address. 1019 1020 // If this address fits entirely in a 16-bit sext immediate field, codegen 1021 // this as "d, 0" 1022 short Imm; 1023 if (isIntS16Immediate(CN, Imm)) { 1024 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 1025 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 1026 CN->getValueType(0)); 1027 return true; 1028 } 1029 1030 // Handle 32-bit sext immediates with LIS + addr mode. 1031 if (CN->getValueType(0) == MVT::i32 || 1032 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 1033 int Addr = (int)CN->getZExtValue(); 1034 1035 // Otherwise, break this down into an LIS + disp. 1036 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 1037 1038 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 1039 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1040 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); 1041 return true; 1042 } 1043 } 1044 1045 Disp = DAG.getTargetConstant(0, getPointerTy()); 1046 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1047 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1048 else 1049 Base = N; 1050 return true; // [r+0] 1051} 1052 1053/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 1054/// represented as an indexed [r+r] operation. 1055bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, 1056 SDValue &Index, 1057 SelectionDAG &DAG) const { 1058 // Check to see if we can easily represent this as an [r+r] address. This 1059 // will fail if it thinks that the address is more profitably represented as 1060 // reg+imm, e.g. where imm = 0. 1061 if (SelectAddressRegReg(N, Base, Index, DAG)) 1062 return true; 1063 1064 // If the operand is an addition, always emit this as [r+r], since this is 1065 // better (for code size, and execution, as the memop does the add for free) 1066 // than emitting an explicit add. 1067 if (N.getOpcode() == ISD::ADD) { 1068 Base = N.getOperand(0); 1069 Index = N.getOperand(1); 1070 return true; 1071 } 1072 1073 // Otherwise, do it the hard way, using R0 as the base register. 1074 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 1075 N.getValueType()); 1076 Index = N; 1077 return true; 1078} 1079 1080/// SelectAddressRegImmShift - Returns true if the address N can be 1081/// represented by a base register plus a signed 14-bit displacement 1082/// [r+imm*4]. Suitable for use by STD and friends. 1083bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, 1084 SDValue &Base, 1085 SelectionDAG &DAG) const { 1086 // FIXME dl should come from the parent load or store, not the address 1087 DebugLoc dl = N.getDebugLoc(); 1088 // If this can be more profitably realized as r+r, fail. 1089 if (SelectAddressRegReg(N, Disp, Base, DAG)) 1090 return false; 1091 1092 if (N.getOpcode() == ISD::ADD) { 1093 short imm = 0; 1094 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 1095 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 1096 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 1097 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1098 } else { 1099 Base = N.getOperand(0); 1100 } 1101 return true; // [r+i] 1102 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 1103 // Match LOAD (ADD (X, Lo(G))). 1104 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 1105 && "Cannot handle constant offsets yet!"); 1106 Disp = N.getOperand(1).getOperand(0); // The global address. 1107 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 1108 Disp.getOpcode() == ISD::TargetConstantPool || 1109 Disp.getOpcode() == ISD::TargetJumpTable); 1110 Base = N.getOperand(0); 1111 return true; // [&g+r] 1112 } 1113 } else if (N.getOpcode() == ISD::OR) { 1114 short imm = 0; 1115 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 1116 // If this is an or of disjoint bitfields, we can codegen this as an add 1117 // (for better address arithmetic) if the LHS and RHS of the OR are 1118 // provably disjoint. 1119 APInt LHSKnownZero, LHSKnownOne; 1120 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne); 1121 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 1122 // If all of the bits are known zero on the LHS or RHS, the add won't 1123 // carry. 1124 Base = N.getOperand(0); 1125 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 1126 return true; 1127 } 1128 } 1129 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 1130 // Loading from a constant address. Verify low two bits are clear. 1131 if ((CN->getZExtValue() & 3) == 0) { 1132 // If this address fits entirely in a 14-bit sext immediate field, codegen 1133 // this as "d, 0" 1134 short Imm; 1135 if (isIntS16Immediate(CN, Imm)) { 1136 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 1137 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 1138 CN->getValueType(0)); 1139 return true; 1140 } 1141 1142 // Fold the low-part of 32-bit absolute addresses into addr mode. 1143 if (CN->getValueType(0) == MVT::i32 || 1144 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 1145 int Addr = (int)CN->getZExtValue(); 1146 1147 // Otherwise, break this down into an LIS + disp. 1148 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 1149 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 1150 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1151 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0); 1152 return true; 1153 } 1154 } 1155 } 1156 1157 Disp = DAG.getTargetConstant(0, getPointerTy()); 1158 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1159 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1160 else 1161 Base = N; 1162 return true; // [r+0] 1163} 1164 1165 1166/// getPreIndexedAddressParts - returns true by value, base pointer and 1167/// offset pointer and addressing mode by reference if the node's address 1168/// can be legally represented as pre-indexed load / store address. 1169bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1170 SDValue &Offset, 1171 ISD::MemIndexedMode &AM, 1172 SelectionDAG &DAG) const { 1173 if (DisablePPCPreinc) return false; 1174 1175 SDValue Ptr; 1176 EVT VT; 1177 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1178 Ptr = LD->getBasePtr(); 1179 VT = LD->getMemoryVT(); 1180 1181 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1182 Ptr = ST->getBasePtr(); 1183 VT = ST->getMemoryVT(); 1184 } else 1185 return false; 1186 1187 // PowerPC doesn't have preinc load/store instructions for vectors. 1188 if (VT.isVector()) 1189 return false; 1190 1191 if (SelectAddressRegReg(Ptr, Offset, Base, DAG)) { 1192 AM = ISD::PRE_INC; 1193 return true; 1194 } 1195 1196 // LDU/STU use reg+imm*4, others use reg+imm. 1197 if (VT != MVT::i64) { 1198 // reg + imm 1199 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 1200 return false; 1201 } else { 1202 // reg + imm * 4. 1203 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 1204 return false; 1205 } 1206 1207 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1208 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 1209 // sext i32 to i64 when addr mode is r+i. 1210 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 1211 LD->getExtensionType() == ISD::SEXTLOAD && 1212 isa<ConstantSDNode>(Offset)) 1213 return false; 1214 } 1215 1216 AM = ISD::PRE_INC; 1217 return true; 1218} 1219 1220//===----------------------------------------------------------------------===// 1221// LowerOperation implementation 1222//===----------------------------------------------------------------------===// 1223 1224/// GetLabelAccessInfo - Return true if we should reference labels using a 1225/// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags. 1226static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags, 1227 unsigned &LoOpFlags, const GlobalValue *GV = 0) { 1228 HiOpFlags = PPCII::MO_HA16; 1229 LoOpFlags = PPCII::MO_LO16; 1230 1231 // Don't use the pic base if not in PIC relocation model. Or if we are on a 1232 // non-darwin platform. We don't support PIC on other platforms yet. 1233 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ && 1234 TM.getSubtarget<PPCSubtarget>().isDarwin(); 1235 if (isPIC) { 1236 HiOpFlags |= PPCII::MO_PIC_FLAG; 1237 LoOpFlags |= PPCII::MO_PIC_FLAG; 1238 } 1239 1240 // If this is a reference to a global value that requires a non-lazy-ptr, make 1241 // sure that instruction lowering adds it. 1242 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) { 1243 HiOpFlags |= PPCII::MO_NLP_FLAG; 1244 LoOpFlags |= PPCII::MO_NLP_FLAG; 1245 1246 if (GV->hasHiddenVisibility()) { 1247 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; 1248 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; 1249 } 1250 } 1251 1252 return isPIC; 1253} 1254 1255static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, 1256 SelectionDAG &DAG) { 1257 EVT PtrVT = HiPart.getValueType(); 1258 SDValue Zero = DAG.getConstant(0, PtrVT); 1259 DebugLoc DL = HiPart.getDebugLoc(); 1260 1261 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero); 1262 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero); 1263 1264 // With PIC, the first instruction is actually "GR+hi(&G)". 1265 if (isPIC) 1266 Hi = DAG.getNode(ISD::ADD, DL, PtrVT, 1267 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi); 1268 1269 // Generate non-pic code that has direct accesses to the constant pool. 1270 // The address of the global is just (hi(&g)+lo(&g)). 1271 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1272} 1273 1274SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, 1275 SelectionDAG &DAG) const { 1276 EVT PtrVT = Op.getValueType(); 1277 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1278 const Constant *C = CP->getConstVal(); 1279 1280 // 64-bit SVR4 ABI code is always position-independent. 1281 // The actual address of the GlobalValue is stored in the TOC. 1282 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1283 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0); 1284 return DAG.getNode(PPCISD::TOC_ENTRY, CP->getDebugLoc(), MVT::i64, GA, 1285 DAG.getRegister(PPC::X2, MVT::i64)); 1286 } 1287 1288 unsigned MOHiFlag, MOLoFlag; 1289 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1290 SDValue CPIHi = 1291 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag); 1292 SDValue CPILo = 1293 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag); 1294 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG); 1295} 1296 1297SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 1298 EVT PtrVT = Op.getValueType(); 1299 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1300 1301 // 64-bit SVR4 ABI code is always position-independent. 1302 // The actual address of the GlobalValue is stored in the TOC. 1303 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1304 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1305 return DAG.getNode(PPCISD::TOC_ENTRY, JT->getDebugLoc(), MVT::i64, GA, 1306 DAG.getRegister(PPC::X2, MVT::i64)); 1307 } 1308 1309 unsigned MOHiFlag, MOLoFlag; 1310 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1311 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag); 1312 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag); 1313 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG); 1314} 1315 1316SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, 1317 SelectionDAG &DAG) const { 1318 EVT PtrVT = Op.getValueType(); 1319 1320 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1321 1322 unsigned MOHiFlag, MOLoFlag; 1323 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1324 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag); 1325 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag); 1326 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG); 1327} 1328 1329SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, 1330 SelectionDAG &DAG) const { 1331 1332 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1333 DebugLoc dl = GA->getDebugLoc(); 1334 const GlobalValue *GV = GA->getGlobal(); 1335 EVT PtrVT = getPointerTy(); 1336 bool is64bit = PPCSubTarget.isPPC64(); 1337 1338 TLSModel::Model Model = getTargetMachine().getTLSModel(GV); 1339 1340 if (Model == TLSModel::LocalExec) { 1341 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1342 PPCII::MO_TPREL16_HA); 1343 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1344 PPCII::MO_TPREL16_LO); 1345 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2, 1346 is64bit ? MVT::i64 : MVT::i32); 1347 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg); 1348 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi); 1349 } 1350 1351 if (!is64bit) 1352 llvm_unreachable("only local-exec is currently supported for ppc32"); 1353 1354 if (Model == TLSModel::InitialExec) { 1355 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0); 1356 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); 1357 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl, 1358 PtrVT, GOTReg, TGA); 1359 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl, 1360 PtrVT, TGA, TPOffsetHi); 1361 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGA); 1362 } 1363 1364 if (Model == TLSModel::GeneralDynamic) { 1365 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0); 1366 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); 1367 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT, 1368 GOTReg, TGA); 1369 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT, 1370 GOTEntryHi, TGA); 1371 1372 // We need a chain node, and don't have one handy. The underlying 1373 // call has no side effects, so using the function entry node 1374 // suffices. 1375 SDValue Chain = DAG.getEntryNode(); 1376 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry); 1377 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64); 1378 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl, 1379 PtrVT, ParmReg, TGA); 1380 // The return value from GET_TLS_ADDR really is in X3 already, but 1381 // some hacks are needed here to tie everything together. The extra 1382 // copies dissolve during subsequent transforms. 1383 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr); 1384 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT); 1385 } 1386 1387 if (Model == TLSModel::LocalDynamic) { 1388 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0); 1389 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); 1390 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT, 1391 GOTReg, TGA); 1392 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT, 1393 GOTEntryHi, TGA); 1394 1395 // We need a chain node, and don't have one handy. The underlying 1396 // call has no side effects, so using the function entry node 1397 // suffices. 1398 SDValue Chain = DAG.getEntryNode(); 1399 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry); 1400 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64); 1401 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl, 1402 PtrVT, ParmReg, TGA); 1403 // The return value from GET_TLSLD_ADDR really is in X3 already, but 1404 // some hacks are needed here to tie everything together. The extra 1405 // copies dissolve during subsequent transforms. 1406 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr); 1407 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT, 1408 Chain, ParmReg, TGA); 1409 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA); 1410 } 1411 1412 llvm_unreachable("Unknown TLS model!"); 1413} 1414 1415SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, 1416 SelectionDAG &DAG) const { 1417 EVT PtrVT = Op.getValueType(); 1418 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1419 DebugLoc DL = GSDN->getDebugLoc(); 1420 const GlobalValue *GV = GSDN->getGlobal(); 1421 1422 // 64-bit SVR4 ABI code is always position-independent. 1423 // The actual address of the GlobalValue is stored in the TOC. 1424 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1425 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset()); 1426 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA, 1427 DAG.getRegister(PPC::X2, MVT::i64)); 1428 } 1429 1430 unsigned MOHiFlag, MOLoFlag; 1431 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV); 1432 1433 SDValue GAHi = 1434 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag); 1435 SDValue GALo = 1436 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag); 1437 1438 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG); 1439 1440 // If the global reference is actually to a non-lazy-pointer, we have to do an 1441 // extra load to get the address of the global. 1442 if (MOHiFlag & PPCII::MO_NLP_FLAG) 1443 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(), 1444 false, false, false, 0); 1445 return Ptr; 1446} 1447 1448SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1449 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1450 DebugLoc dl = Op.getDebugLoc(); 1451 1452 // If we're comparing for equality to zero, expose the fact that this is 1453 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1454 // fold the new nodes. 1455 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1456 if (C->isNullValue() && CC == ISD::SETEQ) { 1457 EVT VT = Op.getOperand(0).getValueType(); 1458 SDValue Zext = Op.getOperand(0); 1459 if (VT.bitsLT(MVT::i32)) { 1460 VT = MVT::i32; 1461 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); 1462 } 1463 unsigned Log2b = Log2_32(VT.getSizeInBits()); 1464 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); 1465 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, 1466 DAG.getConstant(Log2b, MVT::i32)); 1467 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); 1468 } 1469 // Leave comparisons against 0 and -1 alone for now, since they're usually 1470 // optimized. FIXME: revisit this when we can custom lower all setcc 1471 // optimizations. 1472 if (C->isAllOnesValue() || C->isNullValue()) 1473 return SDValue(); 1474 } 1475 1476 // If we have an integer seteq/setne, turn it into a compare against zero 1477 // by xor'ing the rhs with the lhs, which is faster than setting a 1478 // condition register, reading it back out, and masking the correct bit. The 1479 // normal approach here uses sub to do this instead of xor. Using xor exposes 1480 // the result to other bit-twiddling opportunities. 1481 EVT LHSVT = Op.getOperand(0).getValueType(); 1482 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1483 EVT VT = Op.getValueType(); 1484 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), 1485 Op.getOperand(1)); 1486 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); 1487 } 1488 return SDValue(); 1489} 1490 1491SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, 1492 const PPCSubtarget &Subtarget) const { 1493 SDNode *Node = Op.getNode(); 1494 EVT VT = Node->getValueType(0); 1495 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1496 SDValue InChain = Node->getOperand(0); 1497 SDValue VAListPtr = Node->getOperand(1); 1498 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1499 DebugLoc dl = Node->getDebugLoc(); 1500 1501 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); 1502 1503 // gpr_index 1504 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, 1505 VAListPtr, MachinePointerInfo(SV), MVT::i8, 1506 false, false, 0); 1507 InChain = GprIndex.getValue(1); 1508 1509 if (VT == MVT::i64) { 1510 // Check if GprIndex is even 1511 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex, 1512 DAG.getConstant(1, MVT::i32)); 1513 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd, 1514 DAG.getConstant(0, MVT::i32), ISD::SETNE); 1515 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex, 1516 DAG.getConstant(1, MVT::i32)); 1517 // Align GprIndex to be even if it isn't 1518 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne, 1519 GprIndex); 1520 } 1521 1522 // fpr index is 1 byte after gpr 1523 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1524 DAG.getConstant(1, MVT::i32)); 1525 1526 // fpr 1527 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, 1528 FprPtr, MachinePointerInfo(SV), MVT::i8, 1529 false, false, 0); 1530 InChain = FprIndex.getValue(1); 1531 1532 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1533 DAG.getConstant(8, MVT::i32)); 1534 1535 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1536 DAG.getConstant(4, MVT::i32)); 1537 1538 // areas 1539 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, 1540 MachinePointerInfo(), false, false, 1541 false, 0); 1542 InChain = OverflowArea.getValue(1); 1543 1544 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, 1545 MachinePointerInfo(), false, false, 1546 false, 0); 1547 InChain = RegSaveArea.getValue(1); 1548 1549 // select overflow_area if index > 8 1550 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, 1551 DAG.getConstant(8, MVT::i32), ISD::SETLT); 1552 1553 // adjustment constant gpr_index * 4/8 1554 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32, 1555 VT.isInteger() ? GprIndex : FprIndex, 1556 DAG.getConstant(VT.isInteger() ? 4 : 8, 1557 MVT::i32)); 1558 1559 // OurReg = RegSaveArea + RegConstant 1560 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea, 1561 RegConstant); 1562 1563 // Floating types are 32 bytes into RegSaveArea 1564 if (VT.isFloatingPoint()) 1565 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg, 1566 DAG.getConstant(32, MVT::i32)); 1567 1568 // increase {f,g}pr_index by 1 (or 2 if VT is i64) 1569 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32, 1570 VT.isInteger() ? GprIndex : FprIndex, 1571 DAG.getConstant(VT == MVT::i64 ? 2 : 1, 1572 MVT::i32)); 1573 1574 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1, 1575 VT.isInteger() ? VAListPtr : FprPtr, 1576 MachinePointerInfo(SV), 1577 MVT::i8, false, false, 0); 1578 1579 // determine if we should load from reg_save_area or overflow_area 1580 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea); 1581 1582 // increase overflow_area by 4/8 if gpr/fpr > 8 1583 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea, 1584 DAG.getConstant(VT.isInteger() ? 4 : 8, 1585 MVT::i32)); 1586 1587 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea, 1588 OverflowAreaPlusN); 1589 1590 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, 1591 OverflowAreaPtr, 1592 MachinePointerInfo(), 1593 MVT::i32, false, false, 0); 1594 1595 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(), 1596 false, false, false, 0); 1597} 1598 1599SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 1600 SelectionDAG &DAG) const { 1601 return Op.getOperand(0); 1602} 1603 1604SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 1605 SelectionDAG &DAG) const { 1606 SDValue Chain = Op.getOperand(0); 1607 SDValue Trmp = Op.getOperand(1); // trampoline 1608 SDValue FPtr = Op.getOperand(2); // nested function 1609 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 1610 DebugLoc dl = Op.getDebugLoc(); 1611 1612 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1613 bool isPPC64 = (PtrVT == MVT::i64); 1614 Type *IntPtrTy = 1615 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType( 1616 *DAG.getContext()); 1617 1618 TargetLowering::ArgListTy Args; 1619 TargetLowering::ArgListEntry Entry; 1620 1621 Entry.Ty = IntPtrTy; 1622 Entry.Node = Trmp; Args.push_back(Entry); 1623 1624 // TrampSize == (isPPC64 ? 48 : 40); 1625 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, 1626 isPPC64 ? MVT::i64 : MVT::i32); 1627 Args.push_back(Entry); 1628 1629 Entry.Node = FPtr; Args.push_back(Entry); 1630 Entry.Node = Nest; Args.push_back(Entry); 1631 1632 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) 1633 TargetLowering::CallLoweringInfo CLI(Chain, 1634 Type::getVoidTy(*DAG.getContext()), 1635 false, false, false, false, 0, 1636 CallingConv::C, 1637 /*isTailCall=*/false, 1638 /*doesNotRet=*/false, 1639 /*isReturnValueUsed=*/true, 1640 DAG.getExternalSymbol("__trampoline_setup", PtrVT), 1641 Args, DAG, dl); 1642 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1643 1644 return CallResult.second; 1645} 1646 1647SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, 1648 const PPCSubtarget &Subtarget) const { 1649 MachineFunction &MF = DAG.getMachineFunction(); 1650 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1651 1652 DebugLoc dl = Op.getDebugLoc(); 1653 1654 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) { 1655 // vastart just stores the address of the VarArgsFrameIndex slot into the 1656 // memory location argument. 1657 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1658 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1659 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1660 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 1661 MachinePointerInfo(SV), 1662 false, false, 0); 1663 } 1664 1665 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct. 1666 // We suppose the given va_list is already allocated. 1667 // 1668 // typedef struct { 1669 // char gpr; /* index into the array of 8 GPRs 1670 // * stored in the register save area 1671 // * gpr=0 corresponds to r3, 1672 // * gpr=1 to r4, etc. 1673 // */ 1674 // char fpr; /* index into the array of 8 FPRs 1675 // * stored in the register save area 1676 // * fpr=0 corresponds to f1, 1677 // * fpr=1 to f2, etc. 1678 // */ 1679 // char *overflow_arg_area; 1680 // /* location on stack that holds 1681 // * the next overflow argument 1682 // */ 1683 // char *reg_save_area; 1684 // /* where r3:r10 and f1:f8 (if saved) 1685 // * are stored 1686 // */ 1687 // } va_list[1]; 1688 1689 1690 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32); 1691 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32); 1692 1693 1694 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1695 1696 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(), 1697 PtrVT); 1698 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1699 PtrVT); 1700 1701 uint64_t FrameOffset = PtrVT.getSizeInBits()/8; 1702 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1703 1704 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; 1705 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1706 1707 uint64_t FPROffset = 1; 1708 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1709 1710 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1711 1712 // Store first byte : number of int regs 1713 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, 1714 Op.getOperand(1), 1715 MachinePointerInfo(SV), 1716 MVT::i8, false, false, 0); 1717 uint64_t nextOffset = FPROffset; 1718 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), 1719 ConstFPROffset); 1720 1721 // Store second byte : number of float regs 1722 SDValue secondStore = 1723 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, 1724 MachinePointerInfo(SV, nextOffset), MVT::i8, 1725 false, false, 0); 1726 nextOffset += StackOffset; 1727 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); 1728 1729 // Store second word : arguments given on stack 1730 SDValue thirdStore = 1731 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, 1732 MachinePointerInfo(SV, nextOffset), 1733 false, false, 0); 1734 nextOffset += FrameOffset; 1735 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset); 1736 1737 // Store third word : arguments given in registers 1738 return DAG.getStore(thirdStore, dl, FR, nextPtr, 1739 MachinePointerInfo(SV, nextOffset), 1740 false, false, 0); 1741 1742} 1743 1744#include "PPCGenCallingConv.inc" 1745 1746static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 1747 CCValAssign::LocInfo &LocInfo, 1748 ISD::ArgFlagsTy &ArgFlags, 1749 CCState &State) { 1750 return true; 1751} 1752 1753static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 1754 MVT &LocVT, 1755 CCValAssign::LocInfo &LocInfo, 1756 ISD::ArgFlagsTy &ArgFlags, 1757 CCState &State) { 1758 static const uint16_t ArgRegs[] = { 1759 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1760 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1761 }; 1762 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1763 1764 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1765 1766 // Skip one register if the first unallocated register has an even register 1767 // number and there are still argument registers available which have not been 1768 // allocated yet. RegNum is actually an index into ArgRegs, which means we 1769 // need to skip a register if RegNum is odd. 1770 if (RegNum != NumArgRegs && RegNum % 2 == 1) { 1771 State.AllocateReg(ArgRegs[RegNum]); 1772 } 1773 1774 // Always return false here, as this function only makes sure that the first 1775 // unallocated register has an odd register number and does not actually 1776 // allocate a register for the current argument. 1777 return false; 1778} 1779 1780static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 1781 MVT &LocVT, 1782 CCValAssign::LocInfo &LocInfo, 1783 ISD::ArgFlagsTy &ArgFlags, 1784 CCState &State) { 1785 static const uint16_t ArgRegs[] = { 1786 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1787 PPC::F8 1788 }; 1789 1790 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1791 1792 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1793 1794 // If there is only one Floating-point register left we need to put both f64 1795 // values of a split ppc_fp128 value on the stack. 1796 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { 1797 State.AllocateReg(ArgRegs[RegNum]); 1798 } 1799 1800 // Always return false here, as this function only makes sure that the two f64 1801 // values a ppc_fp128 value is split into are both passed in registers or both 1802 // passed on the stack and does not actually allocate a register for the 1803 // current argument. 1804 return false; 1805} 1806 1807/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1808/// on Darwin. 1809static const uint16_t *GetFPR() { 1810 static const uint16_t FPR[] = { 1811 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1812 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1813 }; 1814 1815 return FPR; 1816} 1817 1818/// CalculateStackSlotSize - Calculates the size reserved for this argument on 1819/// the stack. 1820static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, 1821 unsigned PtrByteSize) { 1822 unsigned ArgSize = ArgVT.getSizeInBits()/8; 1823 if (Flags.isByVal()) 1824 ArgSize = Flags.getByValSize(); 1825 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1826 1827 return ArgSize; 1828} 1829 1830SDValue 1831PPCTargetLowering::LowerFormalArguments(SDValue Chain, 1832 CallingConv::ID CallConv, bool isVarArg, 1833 const SmallVectorImpl<ISD::InputArg> 1834 &Ins, 1835 DebugLoc dl, SelectionDAG &DAG, 1836 SmallVectorImpl<SDValue> &InVals) 1837 const { 1838 if (PPCSubTarget.isSVR4ABI()) { 1839 if (PPCSubTarget.isPPC64()) 1840 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins, 1841 dl, DAG, InVals); 1842 else 1843 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins, 1844 dl, DAG, InVals); 1845 } else { 1846 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, 1847 dl, DAG, InVals); 1848 } 1849} 1850 1851SDValue 1852PPCTargetLowering::LowerFormalArguments_32SVR4( 1853 SDValue Chain, 1854 CallingConv::ID CallConv, bool isVarArg, 1855 const SmallVectorImpl<ISD::InputArg> 1856 &Ins, 1857 DebugLoc dl, SelectionDAG &DAG, 1858 SmallVectorImpl<SDValue> &InVals) const { 1859 1860 // 32-bit SVR4 ABI Stack Frame Layout: 1861 // +-----------------------------------+ 1862 // +--> | Back chain | 1863 // | +-----------------------------------+ 1864 // | | Floating-point register save area | 1865 // | +-----------------------------------+ 1866 // | | General register save area | 1867 // | +-----------------------------------+ 1868 // | | CR save word | 1869 // | +-----------------------------------+ 1870 // | | VRSAVE save word | 1871 // | +-----------------------------------+ 1872 // | | Alignment padding | 1873 // | +-----------------------------------+ 1874 // | | Vector register save area | 1875 // | +-----------------------------------+ 1876 // | | Local variable space | 1877 // | +-----------------------------------+ 1878 // | | Parameter list area | 1879 // | +-----------------------------------+ 1880 // | | LR save word | 1881 // | +-----------------------------------+ 1882 // SP--> +--- | Back chain | 1883 // +-----------------------------------+ 1884 // 1885 // Specifications: 1886 // System V Application Binary Interface PowerPC Processor Supplement 1887 // AltiVec Technology Programming Interface Manual 1888 1889 MachineFunction &MF = DAG.getMachineFunction(); 1890 MachineFrameInfo *MFI = MF.getFrameInfo(); 1891 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1892 1893 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1894 // Potential tail calls could cause overwriting of argument stack slots. 1895 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt && 1896 (CallConv == CallingConv::Fast)); 1897 unsigned PtrByteSize = 4; 1898 1899 // Assign locations to all of the incoming arguments. 1900 SmallVector<CCValAssign, 16> ArgLocs; 1901 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1902 getTargetMachine(), ArgLocs, *DAG.getContext()); 1903 1904 // Reserve space for the linkage area on the stack. 1905 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); 1906 1907 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4); 1908 1909 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1910 CCValAssign &VA = ArgLocs[i]; 1911 1912 // Arguments stored in registers. 1913 if (VA.isRegLoc()) { 1914 const TargetRegisterClass *RC; 1915 EVT ValVT = VA.getValVT(); 1916 1917 switch (ValVT.getSimpleVT().SimpleTy) { 1918 default: 1919 llvm_unreachable("ValVT not supported by formal arguments Lowering"); 1920 case MVT::i32: 1921 RC = &PPC::GPRCRegClass; 1922 break; 1923 case MVT::f32: 1924 RC = &PPC::F4RCRegClass; 1925 break; 1926 case MVT::f64: 1927 RC = &PPC::F8RCRegClass; 1928 break; 1929 case MVT::v16i8: 1930 case MVT::v8i16: 1931 case MVT::v4i32: 1932 case MVT::v4f32: 1933 RC = &PPC::VRRCRegClass; 1934 break; 1935 } 1936 1937 // Transform the arguments stored in physical registers into virtual ones. 1938 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1939 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT); 1940 1941 InVals.push_back(ArgValue); 1942 } else { 1943 // Argument stored in memory. 1944 assert(VA.isMemLoc()); 1945 1946 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; 1947 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), 1948 isImmutable); 1949 1950 // Create load nodes to retrieve arguments from the stack. 1951 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1952 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 1953 MachinePointerInfo(), 1954 false, false, false, 0)); 1955 } 1956 } 1957 1958 // Assign locations to all of the incoming aggregate by value arguments. 1959 // Aggregates passed by value are stored in the local variable space of the 1960 // caller's stack frame, right above the parameter list area. 1961 SmallVector<CCValAssign, 16> ByValArgLocs; 1962 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1963 getTargetMachine(), ByValArgLocs, *DAG.getContext()); 1964 1965 // Reserve stack space for the allocations in CCInfo. 1966 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 1967 1968 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal); 1969 1970 // Area that is at least reserved in the caller of this function. 1971 unsigned MinReservedArea = CCByValInfo.getNextStackOffset(); 1972 1973 // Set the size that is at least reserved in caller of this function. Tail 1974 // call optimized function's reserved stack space needs to be aligned so that 1975 // taking the difference between two stack areas will result in an aligned 1976 // stack. 1977 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1978 1979 MinReservedArea = 1980 std::max(MinReservedArea, 1981 PPCFrameLowering::getMinCallFrameSize(false, false)); 1982 1983 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> 1984 getStackAlignment(); 1985 unsigned AlignMask = TargetAlign-1; 1986 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 1987 1988 FI->setMinReservedArea(MinReservedArea); 1989 1990 SmallVector<SDValue, 8> MemOps; 1991 1992 // If the function takes variable number of arguments, make a frame index for 1993 // the start of the first vararg value... for expansion of llvm.va_start. 1994 if (isVarArg) { 1995 static const uint16_t GPArgRegs[] = { 1996 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1997 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1998 }; 1999 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs); 2000 2001 static const uint16_t FPArgRegs[] = { 2002 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 2003 PPC::F8 2004 }; 2005 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs); 2006 2007 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs, 2008 NumGPArgRegs)); 2009 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs, 2010 NumFPArgRegs)); 2011 2012 // Make room for NumGPArgRegs and NumFPArgRegs. 2013 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 + 2014 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8; 2015 2016 FuncInfo->setVarArgsStackOffset( 2017 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2018 CCInfo.getNextStackOffset(), true)); 2019 2020 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false)); 2021 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2022 2023 // The fixed integer arguments of a variadic function are stored to the 2024 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing 2025 // the result of va_next. 2026 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) { 2027 // Get an existing live-in vreg, or add a new one. 2028 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); 2029 if (!VReg) 2030 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); 2031 2032 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2033 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2034 MachinePointerInfo(), false, false, 0); 2035 MemOps.push_back(Store); 2036 // Increment the address by four for the next argument to store 2037 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2038 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2039 } 2040 2041 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6 2042 // is set. 2043 // The double arguments are stored to the VarArgsFrameIndex 2044 // on the stack. 2045 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) { 2046 // Get an existing live-in vreg, or add a new one. 2047 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); 2048 if (!VReg) 2049 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); 2050 2051 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); 2052 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2053 MachinePointerInfo(), false, false, 0); 2054 MemOps.push_back(Store); 2055 // Increment the address by eight for the next argument to store 2056 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8, 2057 PtrVT); 2058 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2059 } 2060 } 2061 2062 if (!MemOps.empty()) 2063 Chain = DAG.getNode(ISD::TokenFactor, dl, 2064 MVT::Other, &MemOps[0], MemOps.size()); 2065 2066 return Chain; 2067} 2068 2069// PPC64 passes i8, i16, and i32 values in i64 registers. Promote 2070// value to MVT::i64 and then truncate to the correct register size. 2071SDValue 2072PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, 2073 SelectionDAG &DAG, SDValue ArgVal, 2074 DebugLoc dl) const { 2075 if (Flags.isSExt()) 2076 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, 2077 DAG.getValueType(ObjectVT)); 2078 else if (Flags.isZExt()) 2079 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, 2080 DAG.getValueType(ObjectVT)); 2081 2082 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); 2083} 2084 2085// Set the size that is at least reserved in caller of this function. Tail 2086// call optimized functions' reserved stack space needs to be aligned so that 2087// taking the difference between two stack areas will result in an aligned 2088// stack. 2089void 2090PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG, 2091 unsigned nAltivecParamsAtEnd, 2092 unsigned MinReservedArea, 2093 bool isPPC64) const { 2094 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2095 // Add the Altivec parameters at the end, if needed. 2096 if (nAltivecParamsAtEnd) { 2097 MinReservedArea = ((MinReservedArea+15)/16)*16; 2098 MinReservedArea += 16*nAltivecParamsAtEnd; 2099 } 2100 MinReservedArea = 2101 std::max(MinReservedArea, 2102 PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); 2103 unsigned TargetAlign 2104 = DAG.getMachineFunction().getTarget().getFrameLowering()-> 2105 getStackAlignment(); 2106 unsigned AlignMask = TargetAlign-1; 2107 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 2108 FI->setMinReservedArea(MinReservedArea); 2109} 2110 2111SDValue 2112PPCTargetLowering::LowerFormalArguments_64SVR4( 2113 SDValue Chain, 2114 CallingConv::ID CallConv, bool isVarArg, 2115 const SmallVectorImpl<ISD::InputArg> 2116 &Ins, 2117 DebugLoc dl, SelectionDAG &DAG, 2118 SmallVectorImpl<SDValue> &InVals) const { 2119 // TODO: add description of PPC stack frame format, or at least some docs. 2120 // 2121 MachineFunction &MF = DAG.getMachineFunction(); 2122 MachineFrameInfo *MFI = MF.getFrameInfo(); 2123 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 2124 2125 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2126 // Potential tail calls could cause overwriting of argument stack slots. 2127 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt && 2128 (CallConv == CallingConv::Fast)); 2129 unsigned PtrByteSize = 8; 2130 2131 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true); 2132 // Area that is at least reserved in caller of this function. 2133 unsigned MinReservedArea = ArgOffset; 2134 2135 static const uint16_t GPR[] = { 2136 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 2137 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 2138 }; 2139 2140 static const uint16_t *FPR = GetFPR(); 2141 2142 static const uint16_t VR[] = { 2143 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 2144 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 2145 }; 2146 2147 const unsigned Num_GPR_Regs = array_lengthof(GPR); 2148 const unsigned Num_FPR_Regs = 13; 2149 const unsigned Num_VR_Regs = array_lengthof(VR); 2150 2151 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 2152 2153 // Add DAG nodes to load the arguments or copy them out of registers. On 2154 // entry to a function on PPC, the arguments start after the linkage area, 2155 // although the first ones are often in registers. 2156 2157 SmallVector<SDValue, 8> MemOps; 2158 unsigned nAltivecParamsAtEnd = 0; 2159 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin(); 2160 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo, ++FuncArg) { 2161 SDValue ArgVal; 2162 bool needsLoad = false; 2163 EVT ObjectVT = Ins[ArgNo].VT; 2164 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 2165 unsigned ArgSize = ObjSize; 2166 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 2167 2168 unsigned CurArgOffset = ArgOffset; 2169 2170 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 2171 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 2172 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 2173 if (isVarArg) { 2174 MinReservedArea = ((MinReservedArea+15)/16)*16; 2175 MinReservedArea += CalculateStackSlotSize(ObjectVT, 2176 Flags, 2177 PtrByteSize); 2178 } else 2179 nAltivecParamsAtEnd++; 2180 } else 2181 // Calculate min reserved area. 2182 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 2183 Flags, 2184 PtrByteSize); 2185 2186 // FIXME the codegen can be much improved in some cases. 2187 // We do not have to keep everything in memory. 2188 if (Flags.isByVal()) { 2189 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 2190 ObjSize = Flags.getByValSize(); 2191 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 2192 // Empty aggregate parameters do not take up registers. Examples: 2193 // struct { } a; 2194 // union { } b; 2195 // int c[0]; 2196 // etc. However, we have to provide a place-holder in InVals, so 2197 // pretend we have an 8-byte item at the current address for that 2198 // purpose. 2199 if (!ObjSize) { 2200 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2201 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2202 InVals.push_back(FIN); 2203 continue; 2204 } 2205 // All aggregates smaller than 8 bytes must be passed right-justified. 2206 if (ObjSize < PtrByteSize) 2207 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize); 2208 // The value of the object is its address. 2209 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true); 2210 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2211 InVals.push_back(FIN); 2212 2213 if (ObjSize < 8) { 2214 if (GPR_idx != Num_GPR_Regs) { 2215 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2216 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2217 SDValue Store; 2218 2219 if (ObjSize==1 || ObjSize==2 || ObjSize==4) { 2220 EVT ObjType = (ObjSize == 1 ? MVT::i8 : 2221 (ObjSize == 2 ? MVT::i16 : MVT::i32)); 2222 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 2223 MachinePointerInfo(FuncArg, CurArgOffset), 2224 ObjType, false, false, 0); 2225 } else { 2226 // For sizes that don't fit a truncating store (3, 5, 6, 7), 2227 // store the whole register as-is to the parameter save area 2228 // slot. The address of the parameter was already calculated 2229 // above (InVals.push_back(FIN)) to be the right-justified 2230 // offset within the slot. For this store, we need a new 2231 // frame index that points at the beginning of the slot. 2232 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2233 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2234 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2235 MachinePointerInfo(FuncArg, ArgOffset), 2236 false, false, 0); 2237 } 2238 2239 MemOps.push_back(Store); 2240 ++GPR_idx; 2241 } 2242 // Whether we copied from a register or not, advance the offset 2243 // into the parameter save area by a full doubleword. 2244 ArgOffset += PtrByteSize; 2245 continue; 2246 } 2247 2248 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 2249 // Store whatever pieces of the object are in registers 2250 // to memory. ArgOffset will be the address of the beginning 2251 // of the object. 2252 if (GPR_idx != Num_GPR_Regs) { 2253 unsigned VReg; 2254 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2255 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2256 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2257 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2258 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2259 MachinePointerInfo(FuncArg, ArgOffset), 2260 false, false, 0); 2261 MemOps.push_back(Store); 2262 ++GPR_idx; 2263 ArgOffset += PtrByteSize; 2264 } else { 2265 ArgOffset += ArgSize - j; 2266 break; 2267 } 2268 } 2269 continue; 2270 } 2271 2272 switch (ObjectVT.getSimpleVT().SimpleTy) { 2273 default: llvm_unreachable("Unhandled argument type!"); 2274 case MVT::i32: 2275 case MVT::i64: 2276 if (GPR_idx != Num_GPR_Regs) { 2277 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2278 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2279 2280 if (ObjectVT == MVT::i32) 2281 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 2282 // value to MVT::i64 and then truncate to the correct register size. 2283 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl); 2284 2285 ++GPR_idx; 2286 } else { 2287 needsLoad = true; 2288 ArgSize = PtrByteSize; 2289 } 2290 ArgOffset += 8; 2291 break; 2292 2293 case MVT::f32: 2294 case MVT::f64: 2295 // Every 8 bytes of argument space consumes one of the GPRs available for 2296 // argument passing. 2297 if (GPR_idx != Num_GPR_Regs) { 2298 ++GPR_idx; 2299 } 2300 if (FPR_idx != Num_FPR_Regs) { 2301 unsigned VReg; 2302 2303 if (ObjectVT == MVT::f32) 2304 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 2305 else 2306 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 2307 2308 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2309 ++FPR_idx; 2310 } else { 2311 needsLoad = true; 2312 ArgSize = PtrByteSize; 2313 } 2314 2315 ArgOffset += 8; 2316 break; 2317 case MVT::v4f32: 2318 case MVT::v4i32: 2319 case MVT::v8i16: 2320 case MVT::v16i8: 2321 // Note that vector arguments in registers don't reserve stack space, 2322 // except in varargs functions. 2323 if (VR_idx != Num_VR_Regs) { 2324 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 2325 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2326 if (isVarArg) { 2327 while ((ArgOffset % 16) != 0) { 2328 ArgOffset += PtrByteSize; 2329 if (GPR_idx != Num_GPR_Regs) 2330 GPR_idx++; 2331 } 2332 ArgOffset += 16; 2333 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 2334 } 2335 ++VR_idx; 2336 } else { 2337 // Vectors are aligned. 2338 ArgOffset = ((ArgOffset+15)/16)*16; 2339 CurArgOffset = ArgOffset; 2340 ArgOffset += 16; 2341 needsLoad = true; 2342 } 2343 break; 2344 } 2345 2346 // We need to load the argument to a virtual register if we determined 2347 // above that we ran out of physical registers of the appropriate type. 2348 if (needsLoad) { 2349 int FI = MFI->CreateFixedObject(ObjSize, 2350 CurArgOffset + (ArgSize - ObjSize), 2351 isImmutable); 2352 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2353 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), 2354 false, false, false, 0); 2355 } 2356 2357 InVals.push_back(ArgVal); 2358 } 2359 2360 // Set the size that is at least reserved in caller of this function. Tail 2361 // call optimized functions' reserved stack space needs to be aligned so that 2362 // taking the difference between two stack areas will result in an aligned 2363 // stack. 2364 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true); 2365 2366 // If the function takes variable number of arguments, make a frame index for 2367 // the start of the first vararg value... for expansion of llvm.va_start. 2368 if (isVarArg) { 2369 int Depth = ArgOffset; 2370 2371 FuncInfo->setVarArgsFrameIndex( 2372 MFI->CreateFixedObject(PtrByteSize, Depth, true)); 2373 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2374 2375 // If this function is vararg, store any remaining integer argument regs 2376 // to their spots on the stack so that they may be loaded by deferencing the 2377 // result of va_next. 2378 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2379 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2380 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2381 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2382 MachinePointerInfo(), false, false, 0); 2383 MemOps.push_back(Store); 2384 // Increment the address by four for the next argument to store 2385 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT); 2386 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2387 } 2388 } 2389 2390 if (!MemOps.empty()) 2391 Chain = DAG.getNode(ISD::TokenFactor, dl, 2392 MVT::Other, &MemOps[0], MemOps.size()); 2393 2394 return Chain; 2395} 2396 2397SDValue 2398PPCTargetLowering::LowerFormalArguments_Darwin( 2399 SDValue Chain, 2400 CallingConv::ID CallConv, bool isVarArg, 2401 const SmallVectorImpl<ISD::InputArg> 2402 &Ins, 2403 DebugLoc dl, SelectionDAG &DAG, 2404 SmallVectorImpl<SDValue> &InVals) const { 2405 // TODO: add description of PPC stack frame format, or at least some docs. 2406 // 2407 MachineFunction &MF = DAG.getMachineFunction(); 2408 MachineFrameInfo *MFI = MF.getFrameInfo(); 2409 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 2410 2411 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2412 bool isPPC64 = PtrVT == MVT::i64; 2413 // Potential tail calls could cause overwriting of argument stack slots. 2414 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt && 2415 (CallConv == CallingConv::Fast)); 2416 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2417 2418 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); 2419 // Area that is at least reserved in caller of this function. 2420 unsigned MinReservedArea = ArgOffset; 2421 2422 static const uint16_t GPR_32[] = { // 32-bit registers. 2423 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 2424 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 2425 }; 2426 static const uint16_t GPR_64[] = { // 64-bit registers. 2427 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 2428 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 2429 }; 2430 2431 static const uint16_t *FPR = GetFPR(); 2432 2433 static const uint16_t VR[] = { 2434 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 2435 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 2436 }; 2437 2438 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 2439 const unsigned Num_FPR_Regs = 13; 2440 const unsigned Num_VR_Regs = array_lengthof( VR); 2441 2442 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 2443 2444 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32; 2445 2446 // In 32-bit non-varargs functions, the stack space for vectors is after the 2447 // stack space for non-vectors. We do not use this space unless we have 2448 // too many vectors to fit in registers, something that only occurs in 2449 // constructed examples:), but we have to walk the arglist to figure 2450 // that out...for the pathological case, compute VecArgOffset as the 2451 // start of the vector parameter area. Computing VecArgOffset is the 2452 // entire point of the following loop. 2453 unsigned VecArgOffset = ArgOffset; 2454 if (!isVarArg && !isPPC64) { 2455 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; 2456 ++ArgNo) { 2457 EVT ObjectVT = Ins[ArgNo].VT; 2458 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 2459 2460 if (Flags.isByVal()) { 2461 // ObjSize is the true size, ArgSize rounded up to multiple of regs. 2462 unsigned ObjSize = Flags.getByValSize(); 2463 unsigned ArgSize = 2464 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 2465 VecArgOffset += ArgSize; 2466 continue; 2467 } 2468 2469 switch(ObjectVT.getSimpleVT().SimpleTy) { 2470 default: llvm_unreachable("Unhandled argument type!"); 2471 case MVT::i32: 2472 case MVT::f32: 2473 VecArgOffset += 4; 2474 break; 2475 case MVT::i64: // PPC64 2476 case MVT::f64: 2477 // FIXME: We are guaranteed to be !isPPC64 at this point. 2478 // Does MVT::i64 apply? 2479 VecArgOffset += 8; 2480 break; 2481 case MVT::v4f32: 2482 case MVT::v4i32: 2483 case MVT::v8i16: 2484 case MVT::v16i8: 2485 // Nothing to do, we're only looking at Nonvector args here. 2486 break; 2487 } 2488 } 2489 } 2490 // We've found where the vector parameter area in memory is. Skip the 2491 // first 12 parameters; these don't use that memory. 2492 VecArgOffset = ((VecArgOffset+15)/16)*16; 2493 VecArgOffset += 12*16; 2494 2495 // Add DAG nodes to load the arguments or copy them out of registers. On 2496 // entry to a function on PPC, the arguments start after the linkage area, 2497 // although the first ones are often in registers. 2498 2499 SmallVector<SDValue, 8> MemOps; 2500 unsigned nAltivecParamsAtEnd = 0; 2501 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin(); 2502 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo, ++FuncArg) { 2503 SDValue ArgVal; 2504 bool needsLoad = false; 2505 EVT ObjectVT = Ins[ArgNo].VT; 2506 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 2507 unsigned ArgSize = ObjSize; 2508 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 2509 2510 unsigned CurArgOffset = ArgOffset; 2511 2512 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 2513 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 2514 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 2515 if (isVarArg || isPPC64) { 2516 MinReservedArea = ((MinReservedArea+15)/16)*16; 2517 MinReservedArea += CalculateStackSlotSize(ObjectVT, 2518 Flags, 2519 PtrByteSize); 2520 } else nAltivecParamsAtEnd++; 2521 } else 2522 // Calculate min reserved area. 2523 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 2524 Flags, 2525 PtrByteSize); 2526 2527 // FIXME the codegen can be much improved in some cases. 2528 // We do not have to keep everything in memory. 2529 if (Flags.isByVal()) { 2530 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 2531 ObjSize = Flags.getByValSize(); 2532 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 2533 // Objects of size 1 and 2 are right justified, everything else is 2534 // left justified. This means the memory address is adjusted forwards. 2535 if (ObjSize==1 || ObjSize==2) { 2536 CurArgOffset = CurArgOffset + (4 - ObjSize); 2537 } 2538 // The value of the object is its address. 2539 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true); 2540 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2541 InVals.push_back(FIN); 2542 if (ObjSize==1 || ObjSize==2) { 2543 if (GPR_idx != Num_GPR_Regs) { 2544 unsigned VReg; 2545 if (isPPC64) 2546 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2547 else 2548 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2549 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2550 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16; 2551 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 2552 MachinePointerInfo(FuncArg, 2553 CurArgOffset), 2554 ObjType, false, false, 0); 2555 MemOps.push_back(Store); 2556 ++GPR_idx; 2557 } 2558 2559 ArgOffset += PtrByteSize; 2560 2561 continue; 2562 } 2563 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 2564 // Store whatever pieces of the object are in registers 2565 // to memory. ArgOffset will be the address of the beginning 2566 // of the object. 2567 if (GPR_idx != Num_GPR_Regs) { 2568 unsigned VReg; 2569 if (isPPC64) 2570 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2571 else 2572 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2573 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2574 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2575 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2576 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2577 MachinePointerInfo(FuncArg, ArgOffset), 2578 false, false, 0); 2579 MemOps.push_back(Store); 2580 ++GPR_idx; 2581 ArgOffset += PtrByteSize; 2582 } else { 2583 ArgOffset += ArgSize - (ArgOffset-CurArgOffset); 2584 break; 2585 } 2586 } 2587 continue; 2588 } 2589 2590 switch (ObjectVT.getSimpleVT().SimpleTy) { 2591 default: llvm_unreachable("Unhandled argument type!"); 2592 case MVT::i32: 2593 if (!isPPC64) { 2594 if (GPR_idx != Num_GPR_Regs) { 2595 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2596 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2597 ++GPR_idx; 2598 } else { 2599 needsLoad = true; 2600 ArgSize = PtrByteSize; 2601 } 2602 // All int arguments reserve stack space in the Darwin ABI. 2603 ArgOffset += PtrByteSize; 2604 break; 2605 } 2606 // FALLTHROUGH 2607 case MVT::i64: // PPC64 2608 if (GPR_idx != Num_GPR_Regs) { 2609 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2610 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2611 2612 if (ObjectVT == MVT::i32) 2613 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 2614 // value to MVT::i64 and then truncate to the correct register size. 2615 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl); 2616 2617 ++GPR_idx; 2618 } else { 2619 needsLoad = true; 2620 ArgSize = PtrByteSize; 2621 } 2622 // All int arguments reserve stack space in the Darwin ABI. 2623 ArgOffset += 8; 2624 break; 2625 2626 case MVT::f32: 2627 case MVT::f64: 2628 // Every 4 bytes of argument space consumes one of the GPRs available for 2629 // argument passing. 2630 if (GPR_idx != Num_GPR_Regs) { 2631 ++GPR_idx; 2632 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 2633 ++GPR_idx; 2634 } 2635 if (FPR_idx != Num_FPR_Regs) { 2636 unsigned VReg; 2637 2638 if (ObjectVT == MVT::f32) 2639 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 2640 else 2641 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 2642 2643 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2644 ++FPR_idx; 2645 } else { 2646 needsLoad = true; 2647 } 2648 2649 // All FP arguments reserve stack space in the Darwin ABI. 2650 ArgOffset += isPPC64 ? 8 : ObjSize; 2651 break; 2652 case MVT::v4f32: 2653 case MVT::v4i32: 2654 case MVT::v8i16: 2655 case MVT::v16i8: 2656 // Note that vector arguments in registers don't reserve stack space, 2657 // except in varargs functions. 2658 if (VR_idx != Num_VR_Regs) { 2659 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 2660 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2661 if (isVarArg) { 2662 while ((ArgOffset % 16) != 0) { 2663 ArgOffset += PtrByteSize; 2664 if (GPR_idx != Num_GPR_Regs) 2665 GPR_idx++; 2666 } 2667 ArgOffset += 16; 2668 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 2669 } 2670 ++VR_idx; 2671 } else { 2672 if (!isVarArg && !isPPC64) { 2673 // Vectors go after all the nonvectors. 2674 CurArgOffset = VecArgOffset; 2675 VecArgOffset += 16; 2676 } else { 2677 // Vectors are aligned. 2678 ArgOffset = ((ArgOffset+15)/16)*16; 2679 CurArgOffset = ArgOffset; 2680 ArgOffset += 16; 2681 } 2682 needsLoad = true; 2683 } 2684 break; 2685 } 2686 2687 // We need to load the argument to a virtual register if we determined above 2688 // that we ran out of physical registers of the appropriate type. 2689 if (needsLoad) { 2690 int FI = MFI->CreateFixedObject(ObjSize, 2691 CurArgOffset + (ArgSize - ObjSize), 2692 isImmutable); 2693 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2694 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), 2695 false, false, false, 0); 2696 } 2697 2698 InVals.push_back(ArgVal); 2699 } 2700 2701 // Set the size that is at least reserved in caller of this function. Tail 2702 // call optimized functions' reserved stack space needs to be aligned so that 2703 // taking the difference between two stack areas will result in an aligned 2704 // stack. 2705 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64); 2706 2707 // If the function takes variable number of arguments, make a frame index for 2708 // the start of the first vararg value... for expansion of llvm.va_start. 2709 if (isVarArg) { 2710 int Depth = ArgOffset; 2711 2712 FuncInfo->setVarArgsFrameIndex( 2713 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2714 Depth, true)); 2715 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2716 2717 // If this function is vararg, store any remaining integer argument regs 2718 // to their spots on the stack so that they may be loaded by deferencing the 2719 // result of va_next. 2720 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2721 unsigned VReg; 2722 2723 if (isPPC64) 2724 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2725 else 2726 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2727 2728 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2729 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2730 MachinePointerInfo(), false, false, 0); 2731 MemOps.push_back(Store); 2732 // Increment the address by four for the next argument to store 2733 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2734 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2735 } 2736 } 2737 2738 if (!MemOps.empty()) 2739 Chain = DAG.getNode(ISD::TokenFactor, dl, 2740 MVT::Other, &MemOps[0], MemOps.size()); 2741 2742 return Chain; 2743} 2744 2745/// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus 2746/// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI. 2747static unsigned 2748CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, 2749 bool isPPC64, 2750 bool isVarArg, 2751 unsigned CC, 2752 const SmallVectorImpl<ISD::OutputArg> 2753 &Outs, 2754 const SmallVectorImpl<SDValue> &OutVals, 2755 unsigned &nAltivecParamsAtEnd) { 2756 // Count how many bytes are to be pushed on the stack, including the linkage 2757 // area, and parameter passing area. We start with 24/48 bytes, which is 2758 // prereserved space for [SP][CR][LR][3 x unused]. 2759 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true); 2760 unsigned NumOps = Outs.size(); 2761 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2762 2763 // Add up all the space actually used. 2764 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually 2765 // they all go in registers, but we must reserve stack space for them for 2766 // possible use by the caller. In varargs or 64-bit calls, parameters are 2767 // assigned stack space in order, with padding so Altivec parameters are 2768 // 16-byte aligned. 2769 nAltivecParamsAtEnd = 0; 2770 for (unsigned i = 0; i != NumOps; ++i) { 2771 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2772 EVT ArgVT = Outs[i].VT; 2773 // Varargs Altivec parameters are padded to a 16 byte boundary. 2774 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 2775 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { 2776 if (!isVarArg && !isPPC64) { 2777 // Non-varargs Altivec parameters go after all the non-Altivec 2778 // parameters; handle those later so we know how much padding we need. 2779 nAltivecParamsAtEnd++; 2780 continue; 2781 } 2782 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. 2783 NumBytes = ((NumBytes+15)/16)*16; 2784 } 2785 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); 2786 } 2787 2788 // Allow for Altivec parameters at the end, if needed. 2789 if (nAltivecParamsAtEnd) { 2790 NumBytes = ((NumBytes+15)/16)*16; 2791 NumBytes += 16*nAltivecParamsAtEnd; 2792 } 2793 2794 // The prolog code of the callee may store up to 8 GPR argument registers to 2795 // the stack, allowing va_start to index over them in memory if its varargs. 2796 // Because we cannot tell if this is needed on the caller side, we have to 2797 // conservatively assume that it is needed. As such, make sure we have at 2798 // least enough stack space for the caller to store the 8 GPRs. 2799 NumBytes = std::max(NumBytes, 2800 PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); 2801 2802 // Tail call needs the stack to be aligned. 2803 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){ 2804 unsigned TargetAlign = DAG.getMachineFunction().getTarget(). 2805 getFrameLowering()->getStackAlignment(); 2806 unsigned AlignMask = TargetAlign-1; 2807 NumBytes = (NumBytes + AlignMask) & ~AlignMask; 2808 } 2809 2810 return NumBytes; 2811} 2812 2813/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be 2814/// adjusted to accommodate the arguments for the tailcall. 2815static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, 2816 unsigned ParamSize) { 2817 2818 if (!isTailCall) return 0; 2819 2820 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>(); 2821 unsigned CallerMinReservedArea = FI->getMinReservedArea(); 2822 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize; 2823 // Remember only if the new adjustement is bigger. 2824 if (SPDiff < FI->getTailCallSPDelta()) 2825 FI->setTailCallSPDelta(SPDiff); 2826 2827 return SPDiff; 2828} 2829 2830/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2831/// for tail call optimization. Targets which want to do tail call 2832/// optimization should implement this function. 2833bool 2834PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2835 CallingConv::ID CalleeCC, 2836 bool isVarArg, 2837 const SmallVectorImpl<ISD::InputArg> &Ins, 2838 SelectionDAG& DAG) const { 2839 if (!getTargetMachine().Options.GuaranteedTailCallOpt) 2840 return false; 2841 2842 // Variable argument functions are not supported. 2843 if (isVarArg) 2844 return false; 2845 2846 MachineFunction &MF = DAG.getMachineFunction(); 2847 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv(); 2848 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 2849 // Functions containing by val parameters are not supported. 2850 for (unsigned i = 0; i != Ins.size(); i++) { 2851 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2852 if (Flags.isByVal()) return false; 2853 } 2854 2855 // Non PIC/GOT tail calls are supported. 2856 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 2857 return true; 2858 2859 // At the moment we can only do local tail calls (in same module, hidden 2860 // or protected) if we are generating PIC. 2861 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2862 return G->getGlobal()->hasHiddenVisibility() 2863 || G->getGlobal()->hasProtectedVisibility(); 2864 } 2865 2866 return false; 2867} 2868 2869/// isCallCompatibleAddress - Return the immediate to use if the specified 2870/// 32-bit value is representable in the immediate field of a BxA instruction. 2871static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { 2872 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2873 if (!C) return 0; 2874 2875 int Addr = C->getZExtValue(); 2876 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 2877 SignExtend32<26>(Addr) != Addr) 2878 return 0; // Top 6 bits have to be sext of immediate. 2879 2880 return DAG.getConstant((int)C->getZExtValue() >> 2, 2881 DAG.getTargetLoweringInfo().getPointerTy()).getNode(); 2882} 2883 2884namespace { 2885 2886struct TailCallArgumentInfo { 2887 SDValue Arg; 2888 SDValue FrameIdxOp; 2889 int FrameIdx; 2890 2891 TailCallArgumentInfo() : FrameIdx(0) {} 2892}; 2893 2894} 2895 2896/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. 2897static void 2898StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, 2899 SDValue Chain, 2900 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, 2901 SmallVector<SDValue, 8> &MemOpChains, 2902 DebugLoc dl) { 2903 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { 2904 SDValue Arg = TailCallArgs[i].Arg; 2905 SDValue FIN = TailCallArgs[i].FrameIdxOp; 2906 int FI = TailCallArgs[i].FrameIdx; 2907 // Store relative to framepointer. 2908 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN, 2909 MachinePointerInfo::getFixedStack(FI), 2910 false, false, 0)); 2911 } 2912} 2913 2914/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to 2915/// the appropriate stack slot for the tail call optimized function call. 2916static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, 2917 MachineFunction &MF, 2918 SDValue Chain, 2919 SDValue OldRetAddr, 2920 SDValue OldFP, 2921 int SPDiff, 2922 bool isPPC64, 2923 bool isDarwinABI, 2924 DebugLoc dl) { 2925 if (SPDiff) { 2926 // Calculate the new stack slot for the return address. 2927 int SlotSize = isPPC64 ? 8 : 4; 2928 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64, 2929 isDarwinABI); 2930 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, 2931 NewRetAddrLoc, true); 2932 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2933 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); 2934 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, 2935 MachinePointerInfo::getFixedStack(NewRetAddr), 2936 false, false, 0); 2937 2938 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack 2939 // slot as the FP is never overwritten. 2940 if (isDarwinABI) { 2941 int NewFPLoc = 2942 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 2943 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc, 2944 true); 2945 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); 2946 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, 2947 MachinePointerInfo::getFixedStack(NewFPIdx), 2948 false, false, 0); 2949 } 2950 } 2951 return Chain; 2952} 2953 2954/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate 2955/// the position of the argument. 2956static void 2957CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, 2958 SDValue Arg, int SPDiff, unsigned ArgOffset, 2959 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 2960 int Offset = ArgOffset + SPDiff; 2961 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; 2962 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2963 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2964 SDValue FIN = DAG.getFrameIndex(FI, VT); 2965 TailCallArgumentInfo Info; 2966 Info.Arg = Arg; 2967 Info.FrameIdxOp = FIN; 2968 Info.FrameIdx = FI; 2969 TailCallArguments.push_back(Info); 2970} 2971 2972/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address 2973/// stack slot. Returns the chain as result and the loaded frame pointers in 2974/// LROpOut/FPOpout. Used when tail calling. 2975SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 2976 int SPDiff, 2977 SDValue Chain, 2978 SDValue &LROpOut, 2979 SDValue &FPOpOut, 2980 bool isDarwinABI, 2981 DebugLoc dl) const { 2982 if (SPDiff) { 2983 // Load the LR and FP stack slot for later adjusting. 2984 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; 2985 LROpOut = getReturnAddrFrameIndex(DAG); 2986 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(), 2987 false, false, false, 0); 2988 Chain = SDValue(LROpOut.getNode(), 1); 2989 2990 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack 2991 // slot as the FP is never overwritten. 2992 if (isDarwinABI) { 2993 FPOpOut = getFramePointerFrameIndex(DAG); 2994 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(), 2995 false, false, false, 0); 2996 Chain = SDValue(FPOpOut.getNode(), 1); 2997 } 2998 } 2999 return Chain; 3000} 3001 3002/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 3003/// by "Src" to address "Dst" of size "Size". Alignment information is 3004/// specified by the specific parameter attribute. The copy will be passed as 3005/// a byval function parameter. 3006/// Sometimes what we are copying is the end of a larger object, the part that 3007/// does not fit in registers. 3008static SDValue 3009CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 3010 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 3011 DebugLoc dl) { 3012 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 3013 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 3014 false, false, MachinePointerInfo(0), 3015 MachinePointerInfo(0)); 3016} 3017 3018/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of 3019/// tail calls. 3020static void 3021LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, 3022 SDValue Arg, SDValue PtrOff, int SPDiff, 3023 unsigned ArgOffset, bool isPPC64, bool isTailCall, 3024 bool isVector, SmallVector<SDValue, 8> &MemOpChains, 3025 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments, 3026 DebugLoc dl) { 3027 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3028 if (!isTailCall) { 3029 if (isVector) { 3030 SDValue StackPtr; 3031 if (isPPC64) 3032 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 3033 else 3034 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 3035 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 3036 DAG.getConstant(ArgOffset, PtrVT)); 3037 } 3038 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 3039 MachinePointerInfo(), false, false, 0)); 3040 // Calculate and remember argument location. 3041 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, 3042 TailCallArguments); 3043} 3044 3045static 3046void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, 3047 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, 3048 SDValue LROp, SDValue FPOp, bool isDarwinABI, 3049 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) { 3050 MachineFunction &MF = DAG.getMachineFunction(); 3051 3052 // Emit a sequence of copyto/copyfrom virtual registers for arguments that 3053 // might overwrite each other in case of tail call optimization. 3054 SmallVector<SDValue, 8> MemOpChains2; 3055 // Do not flag preceding copytoreg stuff together with the following stuff. 3056 InFlag = SDValue(); 3057 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, 3058 MemOpChains2, dl); 3059 if (!MemOpChains2.empty()) 3060 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3061 &MemOpChains2[0], MemOpChains2.size()); 3062 3063 // Store the return address to the appropriate stack slot. 3064 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, 3065 isPPC64, isDarwinABI, dl); 3066 3067 // Emit callseq_end just before tailcall node. 3068 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 3069 DAG.getIntPtrConstant(0, true), InFlag); 3070 InFlag = Chain.getValue(1); 3071} 3072 3073static 3074unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, 3075 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall, 3076 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 3077 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys, 3078 const PPCSubtarget &PPCSubTarget) { 3079 3080 bool isPPC64 = PPCSubTarget.isPPC64(); 3081 bool isSVR4ABI = PPCSubTarget.isSVR4ABI(); 3082 3083 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3084 NodeTys.push_back(MVT::Other); // Returns a chain 3085 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use. 3086 3087 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin; 3088 3089 bool needIndirectCall = true; 3090 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) { 3091 // If this is an absolute destination address, use the munged value. 3092 Callee = SDValue(Dest, 0); 3093 needIndirectCall = false; 3094 } 3095 3096 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3097 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201 3098 // Use indirect calls for ALL functions calls in JIT mode, since the 3099 // far-call stubs may be outside relocation limits for a BL instruction. 3100 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) { 3101 unsigned OpFlags = 0; 3102 if (DAG.getTarget().getRelocationModel() != Reloc::Static && 3103 (PPCSubTarget.getTargetTriple().isMacOSX() && 3104 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) && 3105 (G->getGlobal()->isDeclaration() || 3106 G->getGlobal()->isWeakForLinker())) { 3107 // PC-relative references to external symbols should go through $stub, 3108 // unless we're building with the leopard linker or later, which 3109 // automatically synthesizes these stubs. 3110 OpFlags = PPCII::MO_DARWIN_STUB; 3111 } 3112 3113 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, 3114 // every direct call is) turn it into a TargetGlobalAddress / 3115 // TargetExternalSymbol node so that legalize doesn't hack it. 3116 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 3117 Callee.getValueType(), 3118 0, OpFlags); 3119 needIndirectCall = false; 3120 } 3121 } 3122 3123 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3124 unsigned char OpFlags = 0; 3125 3126 if (DAG.getTarget().getRelocationModel() != Reloc::Static && 3127 (PPCSubTarget.getTargetTriple().isMacOSX() && 3128 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) { 3129 // PC-relative references to external symbols should go through $stub, 3130 // unless we're building with the leopard linker or later, which 3131 // automatically synthesizes these stubs. 3132 OpFlags = PPCII::MO_DARWIN_STUB; 3133 } 3134 3135 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(), 3136 OpFlags); 3137 needIndirectCall = false; 3138 } 3139 3140 if (needIndirectCall) { 3141 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 3142 // to do the call, we can't use PPCISD::CALL. 3143 SDValue MTCTROps[] = {Chain, Callee, InFlag}; 3144 3145 if (isSVR4ABI && isPPC64) { 3146 // Function pointers in the 64-bit SVR4 ABI do not point to the function 3147 // entry point, but to the function descriptor (the function entry point 3148 // address is part of the function descriptor though). 3149 // The function descriptor is a three doubleword structure with the 3150 // following fields: function entry point, TOC base address and 3151 // environment pointer. 3152 // Thus for a call through a function pointer, the following actions need 3153 // to be performed: 3154 // 1. Save the TOC of the caller in the TOC save area of its stack 3155 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()). 3156 // 2. Load the address of the function entry point from the function 3157 // descriptor. 3158 // 3. Load the TOC of the callee from the function descriptor into r2. 3159 // 4. Load the environment pointer from the function descriptor into 3160 // r11. 3161 // 5. Branch to the function entry point address. 3162 // 6. On return of the callee, the TOC of the caller needs to be 3163 // restored (this is done in FinishCall()). 3164 // 3165 // All those operations are flagged together to ensure that no other 3166 // operations can be scheduled in between. E.g. without flagging the 3167 // operations together, a TOC access in the caller could be scheduled 3168 // between the load of the callee TOC and the branch to the callee, which 3169 // results in the TOC access going through the TOC of the callee instead 3170 // of going through the TOC of the caller, which leads to incorrect code. 3171 3172 // Load the address of the function entry point from the function 3173 // descriptor. 3174 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue); 3175 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps, 3176 InFlag.getNode() ? 3 : 2); 3177 Chain = LoadFuncPtr.getValue(1); 3178 InFlag = LoadFuncPtr.getValue(2); 3179 3180 // Load environment pointer into r11. 3181 // Offset of the environment pointer within the function descriptor. 3182 SDValue PtrOff = DAG.getIntPtrConstant(16); 3183 3184 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff); 3185 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr, 3186 InFlag); 3187 Chain = LoadEnvPtr.getValue(1); 3188 InFlag = LoadEnvPtr.getValue(2); 3189 3190 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr, 3191 InFlag); 3192 Chain = EnvVal.getValue(0); 3193 InFlag = EnvVal.getValue(1); 3194 3195 // Load TOC of the callee into r2. We are using a target-specific load 3196 // with r2 hard coded, because the result of a target-independent load 3197 // would never go directly into r2, since r2 is a reserved register (which 3198 // prevents the register allocator from allocating it), resulting in an 3199 // additional register being allocated and an unnecessary move instruction 3200 // being generated. 3201 VTs = DAG.getVTList(MVT::Other, MVT::Glue); 3202 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, 3203 Callee, InFlag); 3204 Chain = LoadTOCPtr.getValue(0); 3205 InFlag = LoadTOCPtr.getValue(1); 3206 3207 MTCTROps[0] = Chain; 3208 MTCTROps[1] = LoadFuncPtr; 3209 MTCTROps[2] = InFlag; 3210 } 3211 3212 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps, 3213 2 + (InFlag.getNode() != 0)); 3214 InFlag = Chain.getValue(1); 3215 3216 NodeTys.clear(); 3217 NodeTys.push_back(MVT::Other); 3218 NodeTys.push_back(MVT::Glue); 3219 Ops.push_back(Chain); 3220 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin; 3221 Callee.setNode(0); 3222 // Add CTR register as callee so a bctr can be emitted later. 3223 if (isTailCall) 3224 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT)); 3225 } 3226 3227 // If this is a direct call, pass the chain and the callee. 3228 if (Callee.getNode()) { 3229 Ops.push_back(Chain); 3230 Ops.push_back(Callee); 3231 } 3232 // If this is a tail call add stack pointer delta. 3233 if (isTailCall) 3234 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); 3235 3236 // Add argument registers to the end of the list so that they are known live 3237 // into the call. 3238 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 3239 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 3240 RegsToPass[i].second.getValueType())); 3241 3242 return CallOpc; 3243} 3244 3245static 3246bool isLocalCall(const SDValue &Callee) 3247{ 3248 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 3249 return !G->getGlobal()->isDeclaration() && 3250 !G->getGlobal()->isWeakForLinker(); 3251 return false; 3252} 3253 3254SDValue 3255PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 3256 CallingConv::ID CallConv, bool isVarArg, 3257 const SmallVectorImpl<ISD::InputArg> &Ins, 3258 DebugLoc dl, SelectionDAG &DAG, 3259 SmallVectorImpl<SDValue> &InVals) const { 3260 3261 SmallVector<CCValAssign, 16> RVLocs; 3262 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3263 getTargetMachine(), RVLocs, *DAG.getContext()); 3264 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC); 3265 3266 // Copy all of the result registers out of their specified physreg. 3267 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 3268 CCValAssign &VA = RVLocs[i]; 3269 assert(VA.isRegLoc() && "Can only return in registers!"); 3270 3271 SDValue Val = DAG.getCopyFromReg(Chain, dl, 3272 VA.getLocReg(), VA.getLocVT(), InFlag); 3273 Chain = Val.getValue(1); 3274 InFlag = Val.getValue(2); 3275 3276 switch (VA.getLocInfo()) { 3277 default: llvm_unreachable("Unknown loc info!"); 3278 case CCValAssign::Full: break; 3279 case CCValAssign::AExt: 3280 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); 3281 break; 3282 case CCValAssign::ZExt: 3283 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val, 3284 DAG.getValueType(VA.getValVT())); 3285 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); 3286 break; 3287 case CCValAssign::SExt: 3288 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val, 3289 DAG.getValueType(VA.getValVT())); 3290 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); 3291 break; 3292 } 3293 3294 InVals.push_back(Val); 3295 } 3296 3297 return Chain; 3298} 3299 3300SDValue 3301PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl, 3302 bool isTailCall, bool isVarArg, 3303 SelectionDAG &DAG, 3304 SmallVector<std::pair<unsigned, SDValue>, 8> 3305 &RegsToPass, 3306 SDValue InFlag, SDValue Chain, 3307 SDValue &Callee, 3308 int SPDiff, unsigned NumBytes, 3309 const SmallVectorImpl<ISD::InputArg> &Ins, 3310 SmallVectorImpl<SDValue> &InVals) const { 3311 std::vector<EVT> NodeTys; 3312 SmallVector<SDValue, 8> Ops; 3313 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff, 3314 isTailCall, RegsToPass, Ops, NodeTys, 3315 PPCSubTarget); 3316 3317 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls 3318 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) 3319 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32)); 3320 3321 // When performing tail call optimization the callee pops its arguments off 3322 // the stack. Account for this here so these bytes can be pushed back on in 3323 // PPCRegisterInfo::eliminateCallFramePseudoInstr. 3324 int BytesCalleePops = 3325 (CallConv == CallingConv::Fast && 3326 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0; 3327 3328 // Add a register mask operand representing the call-preserved registers. 3329 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 3330 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 3331 assert(Mask && "Missing call preserved mask for calling convention"); 3332 Ops.push_back(DAG.getRegisterMask(Mask)); 3333 3334 if (InFlag.getNode()) 3335 Ops.push_back(InFlag); 3336 3337 // Emit tail call. 3338 if (isTailCall) { 3339 // If this is the first return lowered for this function, add the regs 3340 // to the liveout set for the function. 3341 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 3342 SmallVector<CCValAssign, 16> RVLocs; 3343 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3344 getTargetMachine(), RVLocs, *DAG.getContext()); 3345 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC); 3346 for (unsigned i = 0; i != RVLocs.size(); ++i) 3347 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 3348 } 3349 3350 assert(((Callee.getOpcode() == ISD::Register && 3351 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || 3352 Callee.getOpcode() == ISD::TargetExternalSymbol || 3353 Callee.getOpcode() == ISD::TargetGlobalAddress || 3354 isa<ConstantSDNode>(Callee)) && 3355 "Expecting an global address, external symbol, absolute value or register"); 3356 3357 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size()); 3358 } 3359 3360 // Add a NOP immediately after the branch instruction when using the 64-bit 3361 // SVR4 ABI. At link time, if caller and callee are in a different module and 3362 // thus have a different TOC, the call will be replaced with a call to a stub 3363 // function which saves the current TOC, loads the TOC of the callee and 3364 // branches to the callee. The NOP will be replaced with a load instruction 3365 // which restores the TOC of the caller from the TOC save slot of the current 3366 // stack frame. If caller and callee belong to the same module (and have the 3367 // same TOC), the NOP will remain unchanged. 3368 3369 bool needsTOCRestore = false; 3370 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) { 3371 if (CallOpc == PPCISD::BCTRL_SVR4) { 3372 // This is a call through a function pointer. 3373 // Restore the caller TOC from the save area into R2. 3374 // See PrepareCall() for more information about calls through function 3375 // pointers in the 64-bit SVR4 ABI. 3376 // We are using a target-specific load with r2 hard coded, because the 3377 // result of a target-independent load would never go directly into r2, 3378 // since r2 is a reserved register (which prevents the register allocator 3379 // from allocating it), resulting in an additional register being 3380 // allocated and an unnecessary move instruction being generated. 3381 needsTOCRestore = true; 3382 } else if ((CallOpc == PPCISD::CALL_SVR4) && !isLocalCall(Callee)) { 3383 // Otherwise insert NOP for non-local calls. 3384 CallOpc = PPCISD::CALL_NOP_SVR4; 3385 } 3386 } 3387 3388 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 3389 InFlag = Chain.getValue(1); 3390 3391 if (needsTOCRestore) { 3392 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); 3393 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag); 3394 InFlag = Chain.getValue(1); 3395 } 3396 3397 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 3398 DAG.getIntPtrConstant(BytesCalleePops, true), 3399 InFlag); 3400 if (!Ins.empty()) 3401 InFlag = Chain.getValue(1); 3402 3403 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 3404 Ins, dl, DAG, InVals); 3405} 3406 3407SDValue 3408PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 3409 SmallVectorImpl<SDValue> &InVals) const { 3410 SelectionDAG &DAG = CLI.DAG; 3411 DebugLoc &dl = CLI.DL; 3412 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 3413 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 3414 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 3415 SDValue Chain = CLI.Chain; 3416 SDValue Callee = CLI.Callee; 3417 bool &isTailCall = CLI.IsTailCall; 3418 CallingConv::ID CallConv = CLI.CallConv; 3419 bool isVarArg = CLI.IsVarArg; 3420 3421 if (isTailCall) 3422 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, 3423 Ins, DAG); 3424 3425 if (PPCSubTarget.isSVR4ABI()) { 3426 if (PPCSubTarget.isPPC64()) 3427 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg, 3428 isTailCall, Outs, OutVals, Ins, 3429 dl, DAG, InVals); 3430 else 3431 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg, 3432 isTailCall, Outs, OutVals, Ins, 3433 dl, DAG, InVals); 3434 } 3435 3436 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg, 3437 isTailCall, Outs, OutVals, Ins, 3438 dl, DAG, InVals); 3439} 3440 3441SDValue 3442PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee, 3443 CallingConv::ID CallConv, bool isVarArg, 3444 bool isTailCall, 3445 const SmallVectorImpl<ISD::OutputArg> &Outs, 3446 const SmallVectorImpl<SDValue> &OutVals, 3447 const SmallVectorImpl<ISD::InputArg> &Ins, 3448 DebugLoc dl, SelectionDAG &DAG, 3449 SmallVectorImpl<SDValue> &InVals) const { 3450 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description 3451 // of the 32-bit SVR4 ABI stack frame layout. 3452 3453 assert((CallConv == CallingConv::C || 3454 CallConv == CallingConv::Fast) && "Unknown calling convention!"); 3455 3456 unsigned PtrByteSize = 4; 3457 3458 MachineFunction &MF = DAG.getMachineFunction(); 3459 3460 // Mark this function as potentially containing a function that contains a 3461 // tail call. As a consequence the frame pointer will be used for dynamicalloc 3462 // and restoring the callers stack pointer in this functions epilog. This is 3463 // done because by tail calling the called function might overwrite the value 3464 // in this function's (MF) stack pointer stack slot 0(SP). 3465 if (getTargetMachine().Options.GuaranteedTailCallOpt && 3466 CallConv == CallingConv::Fast) 3467 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 3468 3469 // Count how many bytes are to be pushed on the stack, including the linkage 3470 // area, parameter list area and the part of the local variable space which 3471 // contains copies of aggregates which are passed by value. 3472 3473 // Assign locations to all of the outgoing arguments. 3474 SmallVector<CCValAssign, 16> ArgLocs; 3475 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3476 getTargetMachine(), ArgLocs, *DAG.getContext()); 3477 3478 // Reserve space for the linkage area on the stack. 3479 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); 3480 3481 if (isVarArg) { 3482 // Handle fixed and variable vector arguments differently. 3483 // Fixed vector arguments go into registers as long as registers are 3484 // available. Variable vector arguments always go into memory. 3485 unsigned NumArgs = Outs.size(); 3486 3487 for (unsigned i = 0; i != NumArgs; ++i) { 3488 MVT ArgVT = Outs[i].VT; 3489 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 3490 bool Result; 3491 3492 if (Outs[i].IsFixed) { 3493 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, 3494 CCInfo); 3495 } else { 3496 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, 3497 ArgFlags, CCInfo); 3498 } 3499 3500 if (Result) { 3501#ifndef NDEBUG 3502 errs() << "Call operand #" << i << " has unhandled type " 3503 << EVT(ArgVT).getEVTString() << "\n"; 3504#endif 3505 llvm_unreachable(0); 3506 } 3507 } 3508 } else { 3509 // All arguments are treated the same. 3510 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4); 3511 } 3512 3513 // Assign locations to all of the outgoing aggregate by value arguments. 3514 SmallVector<CCValAssign, 16> ByValArgLocs; 3515 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3516 getTargetMachine(), ByValArgLocs, *DAG.getContext()); 3517 3518 // Reserve stack space for the allocations in CCInfo. 3519 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 3520 3521 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal); 3522 3523 // Size of the linkage area, parameter list area and the part of the local 3524 // space variable where copies of aggregates which are passed by value are 3525 // stored. 3526 unsigned NumBytes = CCByValInfo.getNextStackOffset(); 3527 3528 // Calculate by how many bytes the stack has to be adjusted in case of tail 3529 // call optimization. 3530 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 3531 3532 // Adjust the stack pointer for the new arguments... 3533 // These operations are automatically eliminated by the prolog/epilog pass 3534 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 3535 SDValue CallSeqStart = Chain; 3536 3537 // Load the return address and frame pointer so it can be moved somewhere else 3538 // later. 3539 SDValue LROp, FPOp; 3540 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false, 3541 dl); 3542 3543 // Set up a copy of the stack pointer for use loading and storing any 3544 // arguments that may not fit in the registers available for argument 3545 // passing. 3546 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 3547 3548 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3549 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3550 SmallVector<SDValue, 8> MemOpChains; 3551 3552 bool seenFloatArg = false; 3553 // Walk the register/memloc assignments, inserting copies/loads. 3554 for (unsigned i = 0, j = 0, e = ArgLocs.size(); 3555 i != e; 3556 ++i) { 3557 CCValAssign &VA = ArgLocs[i]; 3558 SDValue Arg = OutVals[i]; 3559 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3560 3561 if (Flags.isByVal()) { 3562 // Argument is an aggregate which is passed by value, thus we need to 3563 // create a copy of it in the local variable space of the current stack 3564 // frame (which is the stack frame of the caller) and pass the address of 3565 // this copy to the callee. 3566 assert((j < ByValArgLocs.size()) && "Index out of bounds!"); 3567 CCValAssign &ByValVA = ByValArgLocs[j++]; 3568 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"); 3569 3570 // Memory reserved in the local variable space of the callers stack frame. 3571 unsigned LocMemOffset = ByValVA.getLocMemOffset(); 3572 3573 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 3574 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 3575 3576 // Create a copy of the argument in the local area of the current 3577 // stack frame. 3578 SDValue MemcpyCall = 3579 CreateCopyOfByValArgument(Arg, PtrOff, 3580 CallSeqStart.getNode()->getOperand(0), 3581 Flags, DAG, dl); 3582 3583 // This must go outside the CALLSEQ_START..END. 3584 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3585 CallSeqStart.getNode()->getOperand(1)); 3586 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3587 NewCallSeqStart.getNode()); 3588 Chain = CallSeqStart = NewCallSeqStart; 3589 3590 // Pass the address of the aggregate copy on the stack either in a 3591 // physical register or in the parameter list area of the current stack 3592 // frame to the callee. 3593 Arg = PtrOff; 3594 } 3595 3596 if (VA.isRegLoc()) { 3597 seenFloatArg |= VA.getLocVT().isFloatingPoint(); 3598 // Put argument in a physical register. 3599 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3600 } else { 3601 // Put argument in the parameter list area of the current stack frame. 3602 assert(VA.isMemLoc()); 3603 unsigned LocMemOffset = VA.getLocMemOffset(); 3604 3605 if (!isTailCall) { 3606 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 3607 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 3608 3609 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 3610 MachinePointerInfo(), 3611 false, false, 0)); 3612 } else { 3613 // Calculate and remember argument location. 3614 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset, 3615 TailCallArguments); 3616 } 3617 } 3618 } 3619 3620 if (!MemOpChains.empty()) 3621 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3622 &MemOpChains[0], MemOpChains.size()); 3623 3624 // Build a sequence of copy-to-reg nodes chained together with token chain 3625 // and flag operands which copy the outgoing args into the appropriate regs. 3626 SDValue InFlag; 3627 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3628 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3629 RegsToPass[i].second, InFlag); 3630 InFlag = Chain.getValue(1); 3631 } 3632 3633 // Set CR bit 6 to true if this is a vararg call with floating args passed in 3634 // registers. 3635 if (isVarArg) { 3636 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); 3637 SDValue Ops[] = { Chain, InFlag }; 3638 3639 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET, 3640 dl, VTs, Ops, InFlag.getNode() ? 2 : 1); 3641 3642 InFlag = Chain.getValue(1); 3643 } 3644 3645 if (isTailCall) 3646 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp, 3647 false, TailCallArguments); 3648 3649 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 3650 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 3651 Ins, InVals); 3652} 3653 3654// Copy an argument into memory, being careful to do this outside the 3655// call sequence for the call to which the argument belongs. 3656SDValue 3657PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 3658 SDValue CallSeqStart, 3659 ISD::ArgFlagsTy Flags, 3660 SelectionDAG &DAG, 3661 DebugLoc dl) const { 3662 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, 3663 CallSeqStart.getNode()->getOperand(0), 3664 Flags, DAG, dl); 3665 // The MEMCPY must go outside the CALLSEQ_START..END. 3666 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3667 CallSeqStart.getNode()->getOperand(1)); 3668 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3669 NewCallSeqStart.getNode()); 3670 return NewCallSeqStart; 3671} 3672 3673SDValue 3674PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee, 3675 CallingConv::ID CallConv, bool isVarArg, 3676 bool isTailCall, 3677 const SmallVectorImpl<ISD::OutputArg> &Outs, 3678 const SmallVectorImpl<SDValue> &OutVals, 3679 const SmallVectorImpl<ISD::InputArg> &Ins, 3680 DebugLoc dl, SelectionDAG &DAG, 3681 SmallVectorImpl<SDValue> &InVals) const { 3682 3683 unsigned NumOps = Outs.size(); 3684 3685 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3686 unsigned PtrByteSize = 8; 3687 3688 MachineFunction &MF = DAG.getMachineFunction(); 3689 3690 // Mark this function as potentially containing a function that contains a 3691 // tail call. As a consequence the frame pointer will be used for dynamicalloc 3692 // and restoring the callers stack pointer in this functions epilog. This is 3693 // done because by tail calling the called function might overwrite the value 3694 // in this function's (MF) stack pointer stack slot 0(SP). 3695 if (getTargetMachine().Options.GuaranteedTailCallOpt && 3696 CallConv == CallingConv::Fast) 3697 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 3698 3699 unsigned nAltivecParamsAtEnd = 0; 3700 3701 // Count how many bytes are to be pushed on the stack, including the linkage 3702 // area, and parameter passing area. We start with at least 48 bytes, which 3703 // is reserved space for [SP][CR][LR][3 x unused]. 3704 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result 3705 // of this call. 3706 unsigned NumBytes = 3707 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv, 3708 Outs, OutVals, nAltivecParamsAtEnd); 3709 3710 // Calculate by how many bytes the stack has to be adjusted in case of tail 3711 // call optimization. 3712 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 3713 3714 // To protect arguments on the stack from being clobbered in a tail call, 3715 // force all the loads to happen before doing any other lowering. 3716 if (isTailCall) 3717 Chain = DAG.getStackArgumentTokenFactor(Chain); 3718 3719 // Adjust the stack pointer for the new arguments... 3720 // These operations are automatically eliminated by the prolog/epilog pass 3721 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 3722 SDValue CallSeqStart = Chain; 3723 3724 // Load the return address and frame pointer so it can be move somewhere else 3725 // later. 3726 SDValue LROp, FPOp; 3727 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 3728 dl); 3729 3730 // Set up a copy of the stack pointer for use loading and storing any 3731 // arguments that may not fit in the registers available for argument 3732 // passing. 3733 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 3734 3735 // Figure out which arguments are going to go in registers, and which in 3736 // memory. Also, if this is a vararg function, floating point operations 3737 // must be stored to our stack, and loaded into integer regs as well, if 3738 // any integer regs are available for argument passing. 3739 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true); 3740 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 3741 3742 static const uint16_t GPR[] = { 3743 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 3744 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 3745 }; 3746 static const uint16_t *FPR = GetFPR(); 3747 3748 static const uint16_t VR[] = { 3749 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 3750 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 3751 }; 3752 const unsigned NumGPRs = array_lengthof(GPR); 3753 const unsigned NumFPRs = 13; 3754 const unsigned NumVRs = array_lengthof(VR); 3755 3756 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3757 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3758 3759 SmallVector<SDValue, 8> MemOpChains; 3760 for (unsigned i = 0; i != NumOps; ++i) { 3761 SDValue Arg = OutVals[i]; 3762 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3763 3764 // PtrOff will be used to store the current argument to the stack if a 3765 // register cannot be found for it. 3766 SDValue PtrOff; 3767 3768 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 3769 3770 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3771 3772 // Promote integers to 64-bit values. 3773 if (Arg.getValueType() == MVT::i32) { 3774 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 3775 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3776 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 3777 } 3778 3779 // FIXME memcpy is used way more than necessary. Correctness first. 3780 // Note: "by value" is code for passing a structure by value, not 3781 // basic types. 3782 if (Flags.isByVal()) { 3783 // Note: Size includes alignment padding, so 3784 // struct x { short a; char b; } 3785 // will have Size = 4. With #pragma pack(1), it will have Size = 3. 3786 // These are the proper values we need for right-justifying the 3787 // aggregate in a parameter register. 3788 unsigned Size = Flags.getByValSize(); 3789 3790 // An empty aggregate parameter takes up no storage and no 3791 // registers. 3792 if (Size == 0) 3793 continue; 3794 3795 // All aggregates smaller than 8 bytes must be passed right-justified. 3796 if (Size==1 || Size==2 || Size==4) { 3797 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32); 3798 if (GPR_idx != NumGPRs) { 3799 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, 3800 MachinePointerInfo(), VT, 3801 false, false, 0); 3802 MemOpChains.push_back(Load.getValue(1)); 3803 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3804 3805 ArgOffset += PtrByteSize; 3806 continue; 3807 } 3808 } 3809 3810 if (GPR_idx == NumGPRs && Size < 8) { 3811 SDValue Const = DAG.getConstant(PtrByteSize - Size, 3812 PtrOff.getValueType()); 3813 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3814 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, 3815 CallSeqStart, 3816 Flags, DAG, dl); 3817 ArgOffset += PtrByteSize; 3818 continue; 3819 } 3820 // Copy entire object into memory. There are cases where gcc-generated 3821 // code assumes it is there, even if it could be put entirely into 3822 // registers. (This is not what the doc says.) 3823 3824 // FIXME: The above statement is likely due to a misunderstanding of the 3825 // documents. All arguments must be copied into the parameter area BY 3826 // THE CALLEE in the event that the callee takes the address of any 3827 // formal argument. That has not yet been implemented. However, it is 3828 // reasonable to use the stack area as a staging area for the register 3829 // load. 3830 3831 // Skip this for small aggregates, as we will use the same slot for a 3832 // right-justified copy, below. 3833 if (Size >= 8) 3834 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff, 3835 CallSeqStart, 3836 Flags, DAG, dl); 3837 3838 // When a register is available, pass a small aggregate right-justified. 3839 if (Size < 8 && GPR_idx != NumGPRs) { 3840 // The easiest way to get this right-justified in a register 3841 // is to copy the structure into the rightmost portion of a 3842 // local variable slot, then load the whole slot into the 3843 // register. 3844 // FIXME: The memcpy seems to produce pretty awful code for 3845 // small aggregates, particularly for packed ones. 3846 // FIXME: It would be preferable to use the slot in the 3847 // parameter save area instead of a new local variable. 3848 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType()); 3849 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3850 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, 3851 CallSeqStart, 3852 Flags, DAG, dl); 3853 3854 // Load the slot into the register. 3855 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff, 3856 MachinePointerInfo(), 3857 false, false, false, 0); 3858 MemOpChains.push_back(Load.getValue(1)); 3859 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3860 3861 // Done with this argument. 3862 ArgOffset += PtrByteSize; 3863 continue; 3864 } 3865 3866 // For aggregates larger than PtrByteSize, copy the pieces of the 3867 // object that fit into registers from the parameter save area. 3868 for (unsigned j=0; j<Size; j+=PtrByteSize) { 3869 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 3870 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 3871 if (GPR_idx != NumGPRs) { 3872 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 3873 MachinePointerInfo(), 3874 false, false, false, 0); 3875 MemOpChains.push_back(Load.getValue(1)); 3876 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3877 ArgOffset += PtrByteSize; 3878 } else { 3879 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 3880 break; 3881 } 3882 } 3883 continue; 3884 } 3885 3886 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 3887 default: llvm_unreachable("Unexpected ValueType for argument!"); 3888 case MVT::i32: 3889 case MVT::i64: 3890 if (GPR_idx != NumGPRs) { 3891 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 3892 } else { 3893 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3894 true, isTailCall, false, MemOpChains, 3895 TailCallArguments, dl); 3896 } 3897 ArgOffset += PtrByteSize; 3898 break; 3899 case MVT::f32: 3900 case MVT::f64: 3901 if (FPR_idx != NumFPRs) { 3902 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 3903 3904 if (isVarArg) { 3905 // A single float or an aggregate containing only a single float 3906 // must be passed right-justified in the stack doubleword, and 3907 // in the GPR, if one is available. 3908 SDValue StoreOff; 3909 if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) { 3910 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3911 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 3912 } else 3913 StoreOff = PtrOff; 3914 3915 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff, 3916 MachinePointerInfo(), false, false, 0); 3917 MemOpChains.push_back(Store); 3918 3919 // Float varargs are always shadowed in available integer registers 3920 if (GPR_idx != NumGPRs) { 3921 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 3922 MachinePointerInfo(), false, false, 3923 false, 0); 3924 MemOpChains.push_back(Load.getValue(1)); 3925 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3926 } 3927 } else if (GPR_idx != NumGPRs) 3928 // If we have any FPRs remaining, we may also have GPRs remaining. 3929 ++GPR_idx; 3930 } else { 3931 // Single-precision floating-point values are mapped to the 3932 // second (rightmost) word of the stack doubleword. 3933 if (Arg.getValueType() == MVT::f32) { 3934 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3935 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 3936 } 3937 3938 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3939 true, isTailCall, false, MemOpChains, 3940 TailCallArguments, dl); 3941 } 3942 ArgOffset += 8; 3943 break; 3944 case MVT::v4f32: 3945 case MVT::v4i32: 3946 case MVT::v8i16: 3947 case MVT::v16i8: 3948 if (isVarArg) { 3949 // These go aligned on the stack, or in the corresponding R registers 3950 // when within range. The Darwin PPC ABI doc claims they also go in 3951 // V registers; in fact gcc does this only for arguments that are 3952 // prototyped, not for those that match the ... We do it for all 3953 // arguments, seems to work. 3954 while (ArgOffset % 16 !=0) { 3955 ArgOffset += PtrByteSize; 3956 if (GPR_idx != NumGPRs) 3957 GPR_idx++; 3958 } 3959 // We could elide this store in the case where the object fits 3960 // entirely in R registers. Maybe later. 3961 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 3962 DAG.getConstant(ArgOffset, PtrVT)); 3963 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 3964 MachinePointerInfo(), false, false, 0); 3965 MemOpChains.push_back(Store); 3966 if (VR_idx != NumVRs) { 3967 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, 3968 MachinePointerInfo(), 3969 false, false, false, 0); 3970 MemOpChains.push_back(Load.getValue(1)); 3971 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 3972 } 3973 ArgOffset += 16; 3974 for (unsigned i=0; i<16; i+=PtrByteSize) { 3975 if (GPR_idx == NumGPRs) 3976 break; 3977 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 3978 DAG.getConstant(i, PtrVT)); 3979 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(), 3980 false, false, false, 0); 3981 MemOpChains.push_back(Load.getValue(1)); 3982 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3983 } 3984 break; 3985 } 3986 3987 // Non-varargs Altivec params generally go in registers, but have 3988 // stack space allocated at the end. 3989 if (VR_idx != NumVRs) { 3990 // Doesn't have GPR space allocated. 3991 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 3992 } else { 3993 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3994 true, isTailCall, true, MemOpChains, 3995 TailCallArguments, dl); 3996 ArgOffset += 16; 3997 } 3998 break; 3999 } 4000 } 4001 4002 if (!MemOpChains.empty()) 4003 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 4004 &MemOpChains[0], MemOpChains.size()); 4005 4006 // Check if this is an indirect call (MTCTR/BCTRL). 4007 // See PrepareCall() for more information about calls through function 4008 // pointers in the 64-bit SVR4 ABI. 4009 if (!isTailCall && 4010 !dyn_cast<GlobalAddressSDNode>(Callee) && 4011 !dyn_cast<ExternalSymbolSDNode>(Callee) && 4012 !isBLACompatibleAddress(Callee, DAG)) { 4013 // Load r2 into a virtual register and store it to the TOC save area. 4014 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); 4015 // TOC save area offset. 4016 SDValue PtrOff = DAG.getIntPtrConstant(40); 4017 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 4018 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(), 4019 false, false, 0); 4020 // R12 must contain the address of an indirect callee. This does not 4021 // mean the MTCTR instruction must use R12; it's easier to model this 4022 // as an extra parameter, so do that. 4023 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee)); 4024 } 4025 4026 // Build a sequence of copy-to-reg nodes chained together with token chain 4027 // and flag operands which copy the outgoing args into the appropriate regs. 4028 SDValue InFlag; 4029 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 4030 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 4031 RegsToPass[i].second, InFlag); 4032 InFlag = Chain.getValue(1); 4033 } 4034 4035 if (isTailCall) 4036 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp, 4037 FPOp, true, TailCallArguments); 4038 4039 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 4040 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 4041 Ins, InVals); 4042} 4043 4044SDValue 4045PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, 4046 CallingConv::ID CallConv, bool isVarArg, 4047 bool isTailCall, 4048 const SmallVectorImpl<ISD::OutputArg> &Outs, 4049 const SmallVectorImpl<SDValue> &OutVals, 4050 const SmallVectorImpl<ISD::InputArg> &Ins, 4051 DebugLoc dl, SelectionDAG &DAG, 4052 SmallVectorImpl<SDValue> &InVals) const { 4053 4054 unsigned NumOps = Outs.size(); 4055 4056 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4057 bool isPPC64 = PtrVT == MVT::i64; 4058 unsigned PtrByteSize = isPPC64 ? 8 : 4; 4059 4060 MachineFunction &MF = DAG.getMachineFunction(); 4061 4062 // Mark this function as potentially containing a function that contains a 4063 // tail call. As a consequence the frame pointer will be used for dynamicalloc 4064 // and restoring the callers stack pointer in this functions epilog. This is 4065 // done because by tail calling the called function might overwrite the value 4066 // in this function's (MF) stack pointer stack slot 0(SP). 4067 if (getTargetMachine().Options.GuaranteedTailCallOpt && 4068 CallConv == CallingConv::Fast) 4069 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 4070 4071 unsigned nAltivecParamsAtEnd = 0; 4072 4073 // Count how many bytes are to be pushed on the stack, including the linkage 4074 // area, and parameter passing area. We start with 24/48 bytes, which is 4075 // prereserved space for [SP][CR][LR][3 x unused]. 4076 unsigned NumBytes = 4077 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv, 4078 Outs, OutVals, 4079 nAltivecParamsAtEnd); 4080 4081 // Calculate by how many bytes the stack has to be adjusted in case of tail 4082 // call optimization. 4083 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 4084 4085 // To protect arguments on the stack from being clobbered in a tail call, 4086 // force all the loads to happen before doing any other lowering. 4087 if (isTailCall) 4088 Chain = DAG.getStackArgumentTokenFactor(Chain); 4089 4090 // Adjust the stack pointer for the new arguments... 4091 // These operations are automatically eliminated by the prolog/epilog pass 4092 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 4093 SDValue CallSeqStart = Chain; 4094 4095 // Load the return address and frame pointer so it can be move somewhere else 4096 // later. 4097 SDValue LROp, FPOp; 4098 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 4099 dl); 4100 4101 // Set up a copy of the stack pointer for use loading and storing any 4102 // arguments that may not fit in the registers available for argument 4103 // passing. 4104 SDValue StackPtr; 4105 if (isPPC64) 4106 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 4107 else 4108 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 4109 4110 // Figure out which arguments are going to go in registers, and which in 4111 // memory. Also, if this is a vararg function, floating point operations 4112 // must be stored to our stack, and loaded into integer regs as well, if 4113 // any integer regs are available for argument passing. 4114 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); 4115 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 4116 4117 static const uint16_t GPR_32[] = { // 32-bit registers. 4118 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 4119 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 4120 }; 4121 static const uint16_t GPR_64[] = { // 64-bit registers. 4122 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 4123 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 4124 }; 4125 static const uint16_t *FPR = GetFPR(); 4126 4127 static const uint16_t VR[] = { 4128 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 4129 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 4130 }; 4131 const unsigned NumGPRs = array_lengthof(GPR_32); 4132 const unsigned NumFPRs = 13; 4133 const unsigned NumVRs = array_lengthof(VR); 4134 4135 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32; 4136 4137 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 4138 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 4139 4140 SmallVector<SDValue, 8> MemOpChains; 4141 for (unsigned i = 0; i != NumOps; ++i) { 4142 SDValue Arg = OutVals[i]; 4143 ISD::ArgFlagsTy Flags = Outs[i].Flags; 4144 4145 // PtrOff will be used to store the current argument to the stack if a 4146 // register cannot be found for it. 4147 SDValue PtrOff; 4148 4149 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 4150 4151 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 4152 4153 // On PPC64, promote integers to 64-bit values. 4154 if (isPPC64 && Arg.getValueType() == MVT::i32) { 4155 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 4156 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 4157 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 4158 } 4159 4160 // FIXME memcpy is used way more than necessary. Correctness first. 4161 // Note: "by value" is code for passing a structure by value, not 4162 // basic types. 4163 if (Flags.isByVal()) { 4164 unsigned Size = Flags.getByValSize(); 4165 // Very small objects are passed right-justified. Everything else is 4166 // passed left-justified. 4167 if (Size==1 || Size==2) { 4168 EVT VT = (Size==1) ? MVT::i8 : MVT::i16; 4169 if (GPR_idx != NumGPRs) { 4170 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, 4171 MachinePointerInfo(), VT, 4172 false, false, 0); 4173 MemOpChains.push_back(Load.getValue(1)); 4174 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4175 4176 ArgOffset += PtrByteSize; 4177 } else { 4178 SDValue Const = DAG.getConstant(PtrByteSize - Size, 4179 PtrOff.getValueType()); 4180 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 4181 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, 4182 CallSeqStart, 4183 Flags, DAG, dl); 4184 ArgOffset += PtrByteSize; 4185 } 4186 continue; 4187 } 4188 // Copy entire object into memory. There are cases where gcc-generated 4189 // code assumes it is there, even if it could be put entirely into 4190 // registers. (This is not what the doc says.) 4191 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff, 4192 CallSeqStart, 4193 Flags, DAG, dl); 4194 4195 // For small aggregates (Darwin only) and aggregates >= PtrByteSize, 4196 // copy the pieces of the object that fit into registers from the 4197 // parameter save area. 4198 for (unsigned j=0; j<Size; j+=PtrByteSize) { 4199 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 4200 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 4201 if (GPR_idx != NumGPRs) { 4202 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 4203 MachinePointerInfo(), 4204 false, false, false, 0); 4205 MemOpChains.push_back(Load.getValue(1)); 4206 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4207 ArgOffset += PtrByteSize; 4208 } else { 4209 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 4210 break; 4211 } 4212 } 4213 continue; 4214 } 4215 4216 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 4217 default: llvm_unreachable("Unexpected ValueType for argument!"); 4218 case MVT::i32: 4219 case MVT::i64: 4220 if (GPR_idx != NumGPRs) { 4221 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 4222 } else { 4223 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4224 isPPC64, isTailCall, false, MemOpChains, 4225 TailCallArguments, dl); 4226 } 4227 ArgOffset += PtrByteSize; 4228 break; 4229 case MVT::f32: 4230 case MVT::f64: 4231 if (FPR_idx != NumFPRs) { 4232 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 4233 4234 if (isVarArg) { 4235 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 4236 MachinePointerInfo(), false, false, 0); 4237 MemOpChains.push_back(Store); 4238 4239 // Float varargs are always shadowed in available integer registers 4240 if (GPR_idx != NumGPRs) { 4241 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 4242 MachinePointerInfo(), false, false, 4243 false, 0); 4244 MemOpChains.push_back(Load.getValue(1)); 4245 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4246 } 4247 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 4248 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 4249 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 4250 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 4251 MachinePointerInfo(), 4252 false, false, false, 0); 4253 MemOpChains.push_back(Load.getValue(1)); 4254 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4255 } 4256 } else { 4257 // If we have any FPRs remaining, we may also have GPRs remaining. 4258 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 4259 // GPRs. 4260 if (GPR_idx != NumGPRs) 4261 ++GPR_idx; 4262 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 4263 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 4264 ++GPR_idx; 4265 } 4266 } else 4267 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4268 isPPC64, isTailCall, false, MemOpChains, 4269 TailCallArguments, dl); 4270 if (isPPC64) 4271 ArgOffset += 8; 4272 else 4273 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 4274 break; 4275 case MVT::v4f32: 4276 case MVT::v4i32: 4277 case MVT::v8i16: 4278 case MVT::v16i8: 4279 if (isVarArg) { 4280 // These go aligned on the stack, or in the corresponding R registers 4281 // when within range. The Darwin PPC ABI doc claims they also go in 4282 // V registers; in fact gcc does this only for arguments that are 4283 // prototyped, not for those that match the ... We do it for all 4284 // arguments, seems to work. 4285 while (ArgOffset % 16 !=0) { 4286 ArgOffset += PtrByteSize; 4287 if (GPR_idx != NumGPRs) 4288 GPR_idx++; 4289 } 4290 // We could elide this store in the case where the object fits 4291 // entirely in R registers. Maybe later. 4292 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 4293 DAG.getConstant(ArgOffset, PtrVT)); 4294 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 4295 MachinePointerInfo(), false, false, 0); 4296 MemOpChains.push_back(Store); 4297 if (VR_idx != NumVRs) { 4298 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, 4299 MachinePointerInfo(), 4300 false, false, false, 0); 4301 MemOpChains.push_back(Load.getValue(1)); 4302 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 4303 } 4304 ArgOffset += 16; 4305 for (unsigned i=0; i<16; i+=PtrByteSize) { 4306 if (GPR_idx == NumGPRs) 4307 break; 4308 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 4309 DAG.getConstant(i, PtrVT)); 4310 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(), 4311 false, false, false, 0); 4312 MemOpChains.push_back(Load.getValue(1)); 4313 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4314 } 4315 break; 4316 } 4317 4318 // Non-varargs Altivec params generally go in registers, but have 4319 // stack space allocated at the end. 4320 if (VR_idx != NumVRs) { 4321 // Doesn't have GPR space allocated. 4322 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 4323 } else if (nAltivecParamsAtEnd==0) { 4324 // We are emitting Altivec params in order. 4325 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4326 isPPC64, isTailCall, true, MemOpChains, 4327 TailCallArguments, dl); 4328 ArgOffset += 16; 4329 } 4330 break; 4331 } 4332 } 4333 // If all Altivec parameters fit in registers, as they usually do, 4334 // they get stack space following the non-Altivec parameters. We 4335 // don't track this here because nobody below needs it. 4336 // If there are more Altivec parameters than fit in registers emit 4337 // the stores here. 4338 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) { 4339 unsigned j = 0; 4340 // Offset is aligned; skip 1st 12 params which go in V registers. 4341 ArgOffset = ((ArgOffset+15)/16)*16; 4342 ArgOffset += 12*16; 4343 for (unsigned i = 0; i != NumOps; ++i) { 4344 SDValue Arg = OutVals[i]; 4345 EVT ArgType = Outs[i].VT; 4346 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || 4347 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { 4348 if (++j > NumVRs) { 4349 SDValue PtrOff; 4350 // We are emitting Altivec params in order. 4351 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4352 isPPC64, isTailCall, true, MemOpChains, 4353 TailCallArguments, dl); 4354 ArgOffset += 16; 4355 } 4356 } 4357 } 4358 } 4359 4360 if (!MemOpChains.empty()) 4361 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 4362 &MemOpChains[0], MemOpChains.size()); 4363 4364 // On Darwin, R12 must contain the address of an indirect callee. This does 4365 // not mean the MTCTR instruction must use R12; it's easier to model this as 4366 // an extra parameter, so do that. 4367 if (!isTailCall && 4368 !dyn_cast<GlobalAddressSDNode>(Callee) && 4369 !dyn_cast<ExternalSymbolSDNode>(Callee) && 4370 !isBLACompatibleAddress(Callee, DAG)) 4371 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 : 4372 PPC::R12), Callee)); 4373 4374 // Build a sequence of copy-to-reg nodes chained together with token chain 4375 // and flag operands which copy the outgoing args into the appropriate regs. 4376 SDValue InFlag; 4377 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 4378 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 4379 RegsToPass[i].second, InFlag); 4380 InFlag = Chain.getValue(1); 4381 } 4382 4383 if (isTailCall) 4384 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp, 4385 FPOp, true, TailCallArguments); 4386 4387 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 4388 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 4389 Ins, InVals); 4390} 4391 4392bool 4393PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 4394 MachineFunction &MF, bool isVarArg, 4395 const SmallVectorImpl<ISD::OutputArg> &Outs, 4396 LLVMContext &Context) const { 4397 SmallVector<CCValAssign, 16> RVLocs; 4398 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 4399 RVLocs, Context); 4400 return CCInfo.CheckReturn(Outs, RetCC_PPC); 4401} 4402 4403SDValue 4404PPCTargetLowering::LowerReturn(SDValue Chain, 4405 CallingConv::ID CallConv, bool isVarArg, 4406 const SmallVectorImpl<ISD::OutputArg> &Outs, 4407 const SmallVectorImpl<SDValue> &OutVals, 4408 DebugLoc dl, SelectionDAG &DAG) const { 4409 4410 SmallVector<CCValAssign, 16> RVLocs; 4411 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 4412 getTargetMachine(), RVLocs, *DAG.getContext()); 4413 CCInfo.AnalyzeReturn(Outs, RetCC_PPC); 4414 4415 // If this is the first return lowered for this function, add the regs to the 4416 // liveout set for the function. 4417 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 4418 for (unsigned i = 0; i != RVLocs.size(); ++i) 4419 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 4420 } 4421 4422 SDValue Flag; 4423 4424 // Copy the result values into the output registers. 4425 for (unsigned i = 0; i != RVLocs.size(); ++i) { 4426 CCValAssign &VA = RVLocs[i]; 4427 assert(VA.isRegLoc() && "Can only return in registers!"); 4428 4429 SDValue Arg = OutVals[i]; 4430 4431 switch (VA.getLocInfo()) { 4432 default: llvm_unreachable("Unknown loc info!"); 4433 case CCValAssign::Full: break; 4434 case CCValAssign::AExt: 4435 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 4436 break; 4437 case CCValAssign::ZExt: 4438 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 4439 break; 4440 case CCValAssign::SExt: 4441 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 4442 break; 4443 } 4444 4445 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 4446 Flag = Chain.getValue(1); 4447 } 4448 4449 if (Flag.getNode()) 4450 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 4451 else 4452 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain); 4453} 4454 4455SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 4456 const PPCSubtarget &Subtarget) const { 4457 // When we pop the dynamic allocation we need to restore the SP link. 4458 DebugLoc dl = Op.getDebugLoc(); 4459 4460 // Get the corect type for pointers. 4461 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4462 4463 // Construct the stack pointer operand. 4464 bool isPPC64 = Subtarget.isPPC64(); 4465 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; 4466 SDValue StackPtr = DAG.getRegister(SP, PtrVT); 4467 4468 // Get the operands for the STACKRESTORE. 4469 SDValue Chain = Op.getOperand(0); 4470 SDValue SaveSP = Op.getOperand(1); 4471 4472 // Load the old link SP. 4473 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, 4474 MachinePointerInfo(), 4475 false, false, false, 0); 4476 4477 // Restore the stack pointer. 4478 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); 4479 4480 // Store the old link SP. 4481 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(), 4482 false, false, 0); 4483} 4484 4485 4486 4487SDValue 4488PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { 4489 MachineFunction &MF = DAG.getMachineFunction(); 4490 bool isPPC64 = PPCSubTarget.isPPC64(); 4491 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 4492 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4493 4494 // Get current frame pointer save index. The users of this index will be 4495 // primarily DYNALLOC instructions. 4496 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 4497 int RASI = FI->getReturnAddrSaveIndex(); 4498 4499 // If the frame pointer save index hasn't been defined yet. 4500 if (!RASI) { 4501 // Find out what the fix offset of the frame pointer save area. 4502 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 4503 // Allocate the frame index for frame pointer save area. 4504 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true); 4505 // Save the result. 4506 FI->setReturnAddrSaveIndex(RASI); 4507 } 4508 return DAG.getFrameIndex(RASI, PtrVT); 4509} 4510 4511SDValue 4512PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { 4513 MachineFunction &MF = DAG.getMachineFunction(); 4514 bool isPPC64 = PPCSubTarget.isPPC64(); 4515 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 4516 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4517 4518 // Get current frame pointer save index. The users of this index will be 4519 // primarily DYNALLOC instructions. 4520 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 4521 int FPSI = FI->getFramePointerSaveIndex(); 4522 4523 // If the frame pointer save index hasn't been defined yet. 4524 if (!FPSI) { 4525 // Find out what the fix offset of the frame pointer save area. 4526 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, 4527 isDarwinABI); 4528 4529 // Allocate the frame index for frame pointer save area. 4530 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 4531 // Save the result. 4532 FI->setFramePointerSaveIndex(FPSI); 4533 } 4534 return DAG.getFrameIndex(FPSI, PtrVT); 4535} 4536 4537SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 4538 SelectionDAG &DAG, 4539 const PPCSubtarget &Subtarget) const { 4540 // Get the inputs. 4541 SDValue Chain = Op.getOperand(0); 4542 SDValue Size = Op.getOperand(1); 4543 DebugLoc dl = Op.getDebugLoc(); 4544 4545 // Get the corect type for pointers. 4546 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4547 // Negate the size. 4548 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, 4549 DAG.getConstant(0, PtrVT), Size); 4550 // Construct a node for the frame pointer save index. 4551 SDValue FPSIdx = getFramePointerFrameIndex(DAG); 4552 // Build a DYNALLOC node. 4553 SDValue Ops[3] = { Chain, NegSize, FPSIdx }; 4554 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 4555 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3); 4556} 4557 4558/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 4559/// possible. 4560SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 4561 // Not FP? Not a fsel. 4562 if (!Op.getOperand(0).getValueType().isFloatingPoint() || 4563 !Op.getOperand(2).getValueType().isFloatingPoint()) 4564 return Op; 4565 4566 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 4567 4568 // Cannot handle SETEQ/SETNE. 4569 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op; 4570 4571 EVT ResVT = Op.getValueType(); 4572 EVT CmpVT = Op.getOperand(0).getValueType(); 4573 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4574 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); 4575 DebugLoc dl = Op.getDebugLoc(); 4576 4577 // If the RHS of the comparison is a 0.0, we don't need to do the 4578 // subtraction at all. 4579 if (isFloatingPointZero(RHS)) 4580 switch (CC) { 4581 default: break; // SETUO etc aren't handled by fsel. 4582 case ISD::SETULT: 4583 case ISD::SETLT: 4584 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 4585 case ISD::SETOGE: 4586 case ISD::SETGE: 4587 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 4588 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 4589 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); 4590 case ISD::SETUGT: 4591 case ISD::SETGT: 4592 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 4593 case ISD::SETOLE: 4594 case ISD::SETLE: 4595 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 4596 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 4597 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 4598 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); 4599 } 4600 4601 SDValue Cmp; 4602 switch (CC) { 4603 default: break; // SETUO etc aren't handled by fsel. 4604 case ISD::SETULT: 4605 case ISD::SETLT: 4606 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 4607 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4608 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4609 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 4610 case ISD::SETOGE: 4611 case ISD::SETGE: 4612 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 4613 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4614 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4615 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 4616 case ISD::SETUGT: 4617 case ISD::SETGT: 4618 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 4619 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4620 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4621 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 4622 case ISD::SETOLE: 4623 case ISD::SETLE: 4624 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 4625 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4626 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4627 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 4628 } 4629 return Op; 4630} 4631 4632// FIXME: Split this code up when LegalizeDAGTypes lands. 4633SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 4634 DebugLoc dl) const { 4635 assert(Op.getOperand(0).getValueType().isFloatingPoint()); 4636 SDValue Src = Op.getOperand(0); 4637 if (Src.getValueType() == MVT::f32) 4638 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); 4639 4640 SDValue Tmp; 4641 switch (Op.getValueType().getSimpleVT().SimpleTy) { 4642 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); 4643 case MVT::i32: 4644 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : 4645 PPCISD::FCTIDZ, 4646 dl, MVT::f64, Src); 4647 break; 4648 case MVT::i64: 4649 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src); 4650 break; 4651 } 4652 4653 // Convert the FP value to an int value through memory. 4654 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); 4655 4656 // Emit a store to the stack slot. 4657 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, 4658 MachinePointerInfo(), false, false, 0); 4659 4660 // Result is a load from the stack slot. If loading 4 bytes, make sure to 4661 // add in a bias. 4662 if (Op.getValueType() == MVT::i32) 4663 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, 4664 DAG.getConstant(4, FIPtr.getValueType())); 4665 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(), 4666 false, false, false, 0); 4667} 4668 4669SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, 4670 SelectionDAG &DAG) const { 4671 DebugLoc dl = Op.getDebugLoc(); 4672 // Don't handle ppc_fp128 here; let it be lowered to a libcall. 4673 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) 4674 return SDValue(); 4675 4676 if (Op.getOperand(0).getValueType() == MVT::i64) { 4677 SDValue SINT = Op.getOperand(0); 4678 // When converting to single-precision, we actually need to convert 4679 // to double-precision first and then round to single-precision. 4680 // To avoid double-rounding effects during that operation, we have 4681 // to prepare the input operand. Bits that might be truncated when 4682 // converting to double-precision are replaced by a bit that won't 4683 // be lost at this stage, but is below the single-precision rounding 4684 // position. 4685 // 4686 // However, if -enable-unsafe-fp-math is in effect, accept double 4687 // rounding to avoid the extra overhead. 4688 if (Op.getValueType() == MVT::f32 && 4689 !DAG.getTarget().Options.UnsafeFPMath) { 4690 4691 // Twiddle input to make sure the low 11 bits are zero. (If this 4692 // is the case, we are guaranteed the value will fit into the 53 bit 4693 // mantissa of an IEEE double-precision value without rounding.) 4694 // If any of those low 11 bits were not zero originally, make sure 4695 // bit 12 (value 2048) is set instead, so that the final rounding 4696 // to single-precision gets the correct result. 4697 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64, 4698 SINT, DAG.getConstant(2047, MVT::i64)); 4699 Round = DAG.getNode(ISD::ADD, dl, MVT::i64, 4700 Round, DAG.getConstant(2047, MVT::i64)); 4701 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT); 4702 Round = DAG.getNode(ISD::AND, dl, MVT::i64, 4703 Round, DAG.getConstant(-2048, MVT::i64)); 4704 4705 // However, we cannot use that value unconditionally: if the magnitude 4706 // of the input value is small, the bit-twiddling we did above might 4707 // end up visibly changing the output. Fortunately, in that case, we 4708 // don't need to twiddle bits since the original input will convert 4709 // exactly to double-precision floating-point already. Therefore, 4710 // construct a conditional to use the original value if the top 11 4711 // bits are all sign-bit copies, and use the rounded value computed 4712 // above otherwise. 4713 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64, 4714 SINT, DAG.getConstant(53, MVT::i32)); 4715 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64, 4716 Cond, DAG.getConstant(1, MVT::i64)); 4717 Cond = DAG.getSetCC(dl, MVT::i32, 4718 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT); 4719 4720 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT); 4721 } 4722 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT); 4723 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); 4724 if (Op.getValueType() == MVT::f32) 4725 FP = DAG.getNode(ISD::FP_ROUND, dl, 4726 MVT::f32, FP, DAG.getIntPtrConstant(0)); 4727 return FP; 4728 } 4729 4730 assert(Op.getOperand(0).getValueType() == MVT::i32 && 4731 "Unhandled SINT_TO_FP type in custom expander!"); 4732 // Since we only generate this in 64-bit mode, we can take advantage of 4733 // 64-bit registers. In particular, sign extend the input value into the 4734 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 4735 // then lfd it and fcfid it. 4736 MachineFunction &MF = DAG.getMachineFunction(); 4737 MachineFrameInfo *FrameInfo = MF.getFrameInfo(); 4738 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false); 4739 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4740 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 4741 4742 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32, 4743 Op.getOperand(0)); 4744 4745 // STD the extended value into the stack slot. 4746 MachineMemOperand *MMO = 4747 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 4748 MachineMemOperand::MOStore, 8, 8); 4749 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx }; 4750 SDValue Store = 4751 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other), 4752 Ops, 4, MVT::i64, MMO); 4753 // Load the value as a double. 4754 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(), 4755 false, false, false, 0); 4756 4757 // FCFID it and return it. 4758 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); 4759 if (Op.getValueType() == MVT::f32) 4760 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); 4761 return FP; 4762} 4763 4764SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 4765 SelectionDAG &DAG) const { 4766 DebugLoc dl = Op.getDebugLoc(); 4767 /* 4768 The rounding mode is in bits 30:31 of FPSR, and has the following 4769 settings: 4770 00 Round to nearest 4771 01 Round to 0 4772 10 Round to +inf 4773 11 Round to -inf 4774 4775 FLT_ROUNDS, on the other hand, expects the following: 4776 -1 Undefined 4777 0 Round to 0 4778 1 Round to nearest 4779 2 Round to +inf 4780 3 Round to -inf 4781 4782 To perform the conversion, we do: 4783 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 4784 */ 4785 4786 MachineFunction &MF = DAG.getMachineFunction(); 4787 EVT VT = Op.getValueType(); 4788 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4789 std::vector<EVT> NodeTys; 4790 SDValue MFFSreg, InFlag; 4791 4792 // Save FP Control Word to register 4793 NodeTys.push_back(MVT::f64); // return register 4794 NodeTys.push_back(MVT::Glue); // unused in this context 4795 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 4796 4797 // Save FP register to stack slot 4798 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 4799 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 4800 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, 4801 StackSlot, MachinePointerInfo(), false, false,0); 4802 4803 // Load FP Control Word from low 32 bits of stack slot. 4804 SDValue Four = DAG.getConstant(4, PtrVT); 4805 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); 4806 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(), 4807 false, false, false, 0); 4808 4809 // Transform as necessary 4810 SDValue CWD1 = 4811 DAG.getNode(ISD::AND, dl, MVT::i32, 4812 CWD, DAG.getConstant(3, MVT::i32)); 4813 SDValue CWD2 = 4814 DAG.getNode(ISD::SRL, dl, MVT::i32, 4815 DAG.getNode(ISD::AND, dl, MVT::i32, 4816 DAG.getNode(ISD::XOR, dl, MVT::i32, 4817 CWD, DAG.getConstant(3, MVT::i32)), 4818 DAG.getConstant(3, MVT::i32)), 4819 DAG.getConstant(1, MVT::i32)); 4820 4821 SDValue RetVal = 4822 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); 4823 4824 return DAG.getNode((VT.getSizeInBits() < 16 ? 4825 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 4826} 4827 4828SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const { 4829 EVT VT = Op.getValueType(); 4830 unsigned BitWidth = VT.getSizeInBits(); 4831 DebugLoc dl = Op.getDebugLoc(); 4832 assert(Op.getNumOperands() == 3 && 4833 VT == Op.getOperand(1).getValueType() && 4834 "Unexpected SHL!"); 4835 4836 // Expand into a bunch of logical ops. Note that these ops 4837 // depend on the PPC behavior for oversized shift amounts. 4838 SDValue Lo = Op.getOperand(0); 4839 SDValue Hi = Op.getOperand(1); 4840 SDValue Amt = Op.getOperand(2); 4841 EVT AmtVT = Amt.getValueType(); 4842 4843 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 4844 DAG.getConstant(BitWidth, AmtVT), Amt); 4845 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); 4846 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); 4847 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); 4848 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 4849 DAG.getConstant(-BitWidth, AmtVT)); 4850 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); 4851 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 4852 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); 4853 SDValue OutOps[] = { OutLo, OutHi }; 4854 return DAG.getMergeValues(OutOps, 2, dl); 4855} 4856 4857SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const { 4858 EVT VT = Op.getValueType(); 4859 DebugLoc dl = Op.getDebugLoc(); 4860 unsigned BitWidth = VT.getSizeInBits(); 4861 assert(Op.getNumOperands() == 3 && 4862 VT == Op.getOperand(1).getValueType() && 4863 "Unexpected SRL!"); 4864 4865 // Expand into a bunch of logical ops. Note that these ops 4866 // depend on the PPC behavior for oversized shift amounts. 4867 SDValue Lo = Op.getOperand(0); 4868 SDValue Hi = Op.getOperand(1); 4869 SDValue Amt = Op.getOperand(2); 4870 EVT AmtVT = Amt.getValueType(); 4871 4872 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 4873 DAG.getConstant(BitWidth, AmtVT), Amt); 4874 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 4875 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 4876 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 4877 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 4878 DAG.getConstant(-BitWidth, AmtVT)); 4879 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); 4880 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 4881 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); 4882 SDValue OutOps[] = { OutLo, OutHi }; 4883 return DAG.getMergeValues(OutOps, 2, dl); 4884} 4885 4886SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const { 4887 DebugLoc dl = Op.getDebugLoc(); 4888 EVT VT = Op.getValueType(); 4889 unsigned BitWidth = VT.getSizeInBits(); 4890 assert(Op.getNumOperands() == 3 && 4891 VT == Op.getOperand(1).getValueType() && 4892 "Unexpected SRA!"); 4893 4894 // Expand into a bunch of logical ops, followed by a select_cc. 4895 SDValue Lo = Op.getOperand(0); 4896 SDValue Hi = Op.getOperand(1); 4897 SDValue Amt = Op.getOperand(2); 4898 EVT AmtVT = Amt.getValueType(); 4899 4900 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 4901 DAG.getConstant(BitWidth, AmtVT), Amt); 4902 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 4903 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 4904 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 4905 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 4906 DAG.getConstant(-BitWidth, AmtVT)); 4907 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); 4908 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); 4909 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), 4910 Tmp4, Tmp6, ISD::SETLE); 4911 SDValue OutOps[] = { OutLo, OutHi }; 4912 return DAG.getMergeValues(OutOps, 2, dl); 4913} 4914 4915//===----------------------------------------------------------------------===// 4916// Vector related lowering. 4917// 4918 4919/// BuildSplatI - Build a canonical splati of Val with an element size of 4920/// SplatSize. Cast the result to VT. 4921static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT, 4922 SelectionDAG &DAG, DebugLoc dl) { 4923 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 4924 4925 static const EVT VTys[] = { // canonical VT to use for each size. 4926 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 4927 }; 4928 4929 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 4930 4931 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 4932 if (Val == -1) 4933 SplatSize = 1; 4934 4935 EVT CanonicalVT = VTys[SplatSize-1]; 4936 4937 // Build a canonical splat for this value. 4938 SDValue Elt = DAG.getConstant(Val, MVT::i32); 4939 SmallVector<SDValue, 8> Ops; 4940 Ops.assign(CanonicalVT.getVectorNumElements(), Elt); 4941 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, 4942 &Ops[0], Ops.size()); 4943 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res); 4944} 4945 4946/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 4947/// specified intrinsic ID. 4948static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, 4949 SelectionDAG &DAG, DebugLoc dl, 4950 EVT DestVT = MVT::Other) { 4951 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 4952 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4953 DAG.getConstant(IID, MVT::i32), LHS, RHS); 4954} 4955 4956/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 4957/// specified intrinsic ID. 4958static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, 4959 SDValue Op2, SelectionDAG &DAG, 4960 DebugLoc dl, EVT DestVT = MVT::Other) { 4961 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 4962 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4963 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 4964} 4965 4966 4967/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 4968/// amount. The result has the specified value type. 4969static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, 4970 EVT VT, SelectionDAG &DAG, DebugLoc dl) { 4971 // Force LHS/RHS to be the right type. 4972 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS); 4973 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS); 4974 4975 int Ops[16]; 4976 for (unsigned i = 0; i != 16; ++i) 4977 Ops[i] = i + Amt; 4978 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); 4979 return DAG.getNode(ISD::BITCAST, dl, VT, T); 4980} 4981 4982// If this is a case we can't handle, return null and let the default 4983// expansion code take care of it. If we CAN select this case, and if it 4984// selects to a single instruction, return Op. Otherwise, if we can codegen 4985// this case more efficiently than a constant pool load, lower it to the 4986// sequence of ops that should be used. 4987SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, 4988 SelectionDAG &DAG) const { 4989 DebugLoc dl = Op.getDebugLoc(); 4990 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 4991 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR"); 4992 4993 // Check if this is a splat of a constant value. 4994 APInt APSplatBits, APSplatUndef; 4995 unsigned SplatBitSize; 4996 bool HasAnyUndefs; 4997 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize, 4998 HasAnyUndefs, 0, true) || SplatBitSize > 32) 4999 return SDValue(); 5000 5001 unsigned SplatBits = APSplatBits.getZExtValue(); 5002 unsigned SplatUndef = APSplatUndef.getZExtValue(); 5003 unsigned SplatSize = SplatBitSize / 8; 5004 5005 // First, handle single instruction cases. 5006 5007 // All zeros? 5008 if (SplatBits == 0) { 5009 // Canonicalize all zero vectors to be v4i32. 5010 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 5011 SDValue Z = DAG.getConstant(0, MVT::i32); 5012 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); 5013 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z); 5014 } 5015 return Op; 5016 } 5017 5018 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 5019 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >> 5020 (32-SplatBitSize)); 5021 if (SextVal >= -16 && SextVal <= 15) 5022 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl); 5023 5024 5025 // Two instruction sequences. 5026 5027 // If this value is in the range [-32,30] and is even, use: 5028 // tmp = VSPLTI[bhw], result = add tmp, tmp 5029 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 5030 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl); 5031 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res); 5032 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5033 } 5034 5035 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 5036 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 5037 // for fneg/fabs. 5038 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 5039 // Make -1 and vspltisw -1: 5040 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); 5041 5042 // Make the VSLW intrinsic, computing 0x8000_0000. 5043 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 5044 OnesV, DAG, dl); 5045 5046 // xor by OnesV to invert it. 5047 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); 5048 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5049 } 5050 5051 // Check to see if this is a wide variety of vsplti*, binop self cases. 5052 static const signed char SplatCsts[] = { 5053 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 5054 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 5055 }; 5056 5057 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 5058 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 5059 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 5060 int i = SplatCsts[idx]; 5061 5062 // Figure out what shift amount will be used by altivec if shifted by i in 5063 // this splat size. 5064 unsigned TypeShiftAmt = i & (SplatBitSize-1); 5065 5066 // vsplti + shl self. 5067 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) { 5068 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5069 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5070 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 5071 Intrinsic::ppc_altivec_vslw 5072 }; 5073 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5074 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5075 } 5076 5077 // vsplti + srl self. 5078 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 5079 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5080 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5081 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 5082 Intrinsic::ppc_altivec_vsrw 5083 }; 5084 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5085 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5086 } 5087 5088 // vsplti + sra self. 5089 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 5090 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5091 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5092 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 5093 Intrinsic::ppc_altivec_vsraw 5094 }; 5095 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5096 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5097 } 5098 5099 // vsplti + rol self. 5100 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 5101 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 5102 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5103 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5104 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 5105 Intrinsic::ppc_altivec_vrlw 5106 }; 5107 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5108 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5109 } 5110 5111 // t = vsplti c, result = vsldoi t, t, 1 5112 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) { 5113 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 5114 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); 5115 } 5116 // t = vsplti c, result = vsldoi t, t, 2 5117 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) { 5118 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 5119 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); 5120 } 5121 // t = vsplti c, result = vsldoi t, t, 3 5122 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) { 5123 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 5124 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); 5125 } 5126 } 5127 5128 // Three instruction sequences. 5129 5130 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 5131 if (SextVal >= 0 && SextVal <= 31) { 5132 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl); 5133 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 5134 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS); 5135 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS); 5136 } 5137 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 5138 if (SextVal >= -31 && SextVal <= 0) { 5139 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl); 5140 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 5141 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS); 5142 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS); 5143 } 5144 5145 return SDValue(); 5146} 5147 5148/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 5149/// the specified operations to build the shuffle. 5150static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 5151 SDValue RHS, SelectionDAG &DAG, 5152 DebugLoc dl) { 5153 unsigned OpNum = (PFEntry >> 26) & 0x0F; 5154 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 5155 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 5156 5157 enum { 5158 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 5159 OP_VMRGHW, 5160 OP_VMRGLW, 5161 OP_VSPLTISW0, 5162 OP_VSPLTISW1, 5163 OP_VSPLTISW2, 5164 OP_VSPLTISW3, 5165 OP_VSLDOI4, 5166 OP_VSLDOI8, 5167 OP_VSLDOI12 5168 }; 5169 5170 if (OpNum == OP_COPY) { 5171 if (LHSID == (1*9+2)*9+3) return LHS; 5172 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 5173 return RHS; 5174 } 5175 5176 SDValue OpLHS, OpRHS; 5177 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 5178 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 5179 5180 int ShufIdxs[16]; 5181 switch (OpNum) { 5182 default: llvm_unreachable("Unknown i32 permute!"); 5183 case OP_VMRGHW: 5184 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 5185 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 5186 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 5187 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 5188 break; 5189 case OP_VMRGLW: 5190 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 5191 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 5192 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 5193 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 5194 break; 5195 case OP_VSPLTISW0: 5196 for (unsigned i = 0; i != 16; ++i) 5197 ShufIdxs[i] = (i&3)+0; 5198 break; 5199 case OP_VSPLTISW1: 5200 for (unsigned i = 0; i != 16; ++i) 5201 ShufIdxs[i] = (i&3)+4; 5202 break; 5203 case OP_VSPLTISW2: 5204 for (unsigned i = 0; i != 16; ++i) 5205 ShufIdxs[i] = (i&3)+8; 5206 break; 5207 case OP_VSPLTISW3: 5208 for (unsigned i = 0; i != 16; ++i) 5209 ShufIdxs[i] = (i&3)+12; 5210 break; 5211 case OP_VSLDOI4: 5212 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl); 5213 case OP_VSLDOI8: 5214 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl); 5215 case OP_VSLDOI12: 5216 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl); 5217 } 5218 EVT VT = OpLHS.getValueType(); 5219 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS); 5220 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS); 5221 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); 5222 return DAG.getNode(ISD::BITCAST, dl, VT, T); 5223} 5224 5225/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 5226/// is a shuffle we can handle in a single instruction, return it. Otherwise, 5227/// return the code it can be lowered into. Worst case, it can always be 5228/// lowered into a vperm. 5229SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 5230 SelectionDAG &DAG) const { 5231 DebugLoc dl = Op.getDebugLoc(); 5232 SDValue V1 = Op.getOperand(0); 5233 SDValue V2 = Op.getOperand(1); 5234 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5235 EVT VT = Op.getValueType(); 5236 5237 // Cases that are handled by instructions that take permute immediates 5238 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 5239 // selected by the instruction selector. 5240 if (V2.getOpcode() == ISD::UNDEF) { 5241 if (PPC::isSplatShuffleMask(SVOp, 1) || 5242 PPC::isSplatShuffleMask(SVOp, 2) || 5243 PPC::isSplatShuffleMask(SVOp, 4) || 5244 PPC::isVPKUWUMShuffleMask(SVOp, true) || 5245 PPC::isVPKUHUMShuffleMask(SVOp, true) || 5246 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 || 5247 PPC::isVMRGLShuffleMask(SVOp, 1, true) || 5248 PPC::isVMRGLShuffleMask(SVOp, 2, true) || 5249 PPC::isVMRGLShuffleMask(SVOp, 4, true) || 5250 PPC::isVMRGHShuffleMask(SVOp, 1, true) || 5251 PPC::isVMRGHShuffleMask(SVOp, 2, true) || 5252 PPC::isVMRGHShuffleMask(SVOp, 4, true)) { 5253 return Op; 5254 } 5255 } 5256 5257 // Altivec has a variety of "shuffle immediates" that take two vector inputs 5258 // and produce a fixed permutation. If any of these match, do not lower to 5259 // VPERM. 5260 if (PPC::isVPKUWUMShuffleMask(SVOp, false) || 5261 PPC::isVPKUHUMShuffleMask(SVOp, false) || 5262 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 || 5263 PPC::isVMRGLShuffleMask(SVOp, 1, false) || 5264 PPC::isVMRGLShuffleMask(SVOp, 2, false) || 5265 PPC::isVMRGLShuffleMask(SVOp, 4, false) || 5266 PPC::isVMRGHShuffleMask(SVOp, 1, false) || 5267 PPC::isVMRGHShuffleMask(SVOp, 2, false) || 5268 PPC::isVMRGHShuffleMask(SVOp, 4, false)) 5269 return Op; 5270 5271 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 5272 // perfect shuffle table to emit an optimal matching sequence. 5273 ArrayRef<int> PermMask = SVOp->getMask(); 5274 5275 unsigned PFIndexes[4]; 5276 bool isFourElementShuffle = true; 5277 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 5278 unsigned EltNo = 8; // Start out undef. 5279 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 5280 if (PermMask[i*4+j] < 0) 5281 continue; // Undef, ignore it. 5282 5283 unsigned ByteSource = PermMask[i*4+j]; 5284 if ((ByteSource & 3) != j) { 5285 isFourElementShuffle = false; 5286 break; 5287 } 5288 5289 if (EltNo == 8) { 5290 EltNo = ByteSource/4; 5291 } else if (EltNo != ByteSource/4) { 5292 isFourElementShuffle = false; 5293 break; 5294 } 5295 } 5296 PFIndexes[i] = EltNo; 5297 } 5298 5299 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 5300 // perfect shuffle vector to determine if it is cost effective to do this as 5301 // discrete instructions, or whether we should use a vperm. 5302 if (isFourElementShuffle) { 5303 // Compute the index in the perfect shuffle table. 5304 unsigned PFTableIndex = 5305 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 5306 5307 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 5308 unsigned Cost = (PFEntry >> 30); 5309 5310 // Determining when to avoid vperm is tricky. Many things affect the cost 5311 // of vperm, particularly how many times the perm mask needs to be computed. 5312 // For example, if the perm mask can be hoisted out of a loop or is already 5313 // used (perhaps because there are multiple permutes with the same shuffle 5314 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 5315 // the loop requires an extra register. 5316 // 5317 // As a compromise, we only emit discrete instructions if the shuffle can be 5318 // generated in 3 or fewer operations. When we have loop information 5319 // available, if this block is within a loop, we should avoid using vperm 5320 // for 3-operation perms and use a constant pool load instead. 5321 if (Cost < 3) 5322 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 5323 } 5324 5325 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 5326 // vector that will get spilled to the constant pool. 5327 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 5328 5329 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 5330 // that it is in input element units, not in bytes. Convert now. 5331 EVT EltVT = V1.getValueType().getVectorElementType(); 5332 unsigned BytesPerElement = EltVT.getSizeInBits()/8; 5333 5334 SmallVector<SDValue, 16> ResultMask; 5335 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { 5336 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i]; 5337 5338 for (unsigned j = 0; j != BytesPerElement; ++j) 5339 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 5340 MVT::i32)); 5341 } 5342 5343 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, 5344 &ResultMask[0], ResultMask.size()); 5345 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); 5346} 5347 5348/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 5349/// altivec comparison. If it is, return true and fill in Opc/isDot with 5350/// information about the intrinsic. 5351static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, 5352 bool &isDot) { 5353 unsigned IntrinsicID = 5354 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue(); 5355 CompareOpc = -1; 5356 isDot = false; 5357 switch (IntrinsicID) { 5358 default: return false; 5359 // Comparison predicates. 5360 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 5361 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 5362 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 5363 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 5364 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 5365 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 5366 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 5367 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 5368 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 5369 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 5370 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 5371 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 5372 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 5373 5374 // Normal Comparisons. 5375 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 5376 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 5377 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 5378 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 5379 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 5380 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 5381 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 5382 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 5383 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 5384 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 5385 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 5386 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 5387 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 5388 } 5389 return true; 5390} 5391 5392/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 5393/// lower, do it, otherwise return null. 5394SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 5395 SelectionDAG &DAG) const { 5396 // If this is a lowered altivec predicate compare, CompareOpc is set to the 5397 // opcode number of the comparison. 5398 DebugLoc dl = Op.getDebugLoc(); 5399 int CompareOpc; 5400 bool isDot; 5401 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 5402 return SDValue(); // Don't custom lower most intrinsics. 5403 5404 // If this is a non-dot comparison, make the VCMP node and we are done. 5405 if (!isDot) { 5406 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), 5407 Op.getOperand(1), Op.getOperand(2), 5408 DAG.getConstant(CompareOpc, MVT::i32)); 5409 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp); 5410 } 5411 5412 // Create the PPCISD altivec 'dot' comparison node. 5413 SDValue Ops[] = { 5414 Op.getOperand(2), // LHS 5415 Op.getOperand(3), // RHS 5416 DAG.getConstant(CompareOpc, MVT::i32) 5417 }; 5418 std::vector<EVT> VTs; 5419 VTs.push_back(Op.getOperand(2).getValueType()); 5420 VTs.push_back(MVT::Glue); 5421 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 5422 5423 // Now that we have the comparison, emit a copy from the CR to a GPR. 5424 // This is flagged to the above dot comparison. 5425 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32, 5426 DAG.getRegister(PPC::CR6, MVT::i32), 5427 CompNode.getValue(1)); 5428 5429 // Unpack the result based on how the target uses it. 5430 unsigned BitNo; // Bit # of CR6. 5431 bool InvertBit; // Invert result? 5432 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) { 5433 default: // Can't happen, don't crash on invalid number though. 5434 case 0: // Return the value of the EQ bit of CR6. 5435 BitNo = 0; InvertBit = false; 5436 break; 5437 case 1: // Return the inverted value of the EQ bit of CR6. 5438 BitNo = 0; InvertBit = true; 5439 break; 5440 case 2: // Return the value of the LT bit of CR6. 5441 BitNo = 2; InvertBit = false; 5442 break; 5443 case 3: // Return the inverted value of the LT bit of CR6. 5444 BitNo = 2; InvertBit = true; 5445 break; 5446 } 5447 5448 // Shift the bit into the low position. 5449 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, 5450 DAG.getConstant(8-(3-BitNo), MVT::i32)); 5451 // Isolate the bit. 5452 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, 5453 DAG.getConstant(1, MVT::i32)); 5454 5455 // If we are supposed to, toggle the bit. 5456 if (InvertBit) 5457 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, 5458 DAG.getConstant(1, MVT::i32)); 5459 return Flags; 5460} 5461 5462SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, 5463 SelectionDAG &DAG) const { 5464 DebugLoc dl = Op.getDebugLoc(); 5465 // Create a stack slot that is 16-byte aligned. 5466 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 5467 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false); 5468 EVT PtrVT = getPointerTy(); 5469 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 5470 5471 // Store the input value into Value#0 of the stack slot. 5472 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 5473 Op.getOperand(0), FIdx, MachinePointerInfo(), 5474 false, false, 0); 5475 // Load it out. 5476 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(), 5477 false, false, false, 0); 5478} 5479 5480SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 5481 DebugLoc dl = Op.getDebugLoc(); 5482 if (Op.getValueType() == MVT::v4i32) { 5483 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 5484 5485 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); 5486 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. 5487 5488 SDValue RHSSwap = // = vrlw RHS, 16 5489 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); 5490 5491 // Shrinkify inputs to v8i16. 5492 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS); 5493 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS); 5494 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap); 5495 5496 // Low parts multiplied together, generating 32-bit results (we ignore the 5497 // top parts). 5498 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 5499 LHS, RHS, DAG, dl, MVT::v4i32); 5500 5501 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 5502 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); 5503 // Shift the high parts up 16 bits. 5504 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, 5505 Neg16, DAG, dl); 5506 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); 5507 } else if (Op.getValueType() == MVT::v8i16) { 5508 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 5509 5510 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); 5511 5512 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 5513 LHS, RHS, Zero, DAG, dl); 5514 } else if (Op.getValueType() == MVT::v16i8) { 5515 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 5516 5517 // Multiply the even 8-bit parts, producing 16-bit sums. 5518 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 5519 LHS, RHS, DAG, dl, MVT::v8i16); 5520 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts); 5521 5522 // Multiply the odd 8-bit parts, producing 16-bit sums. 5523 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 5524 LHS, RHS, DAG, dl, MVT::v8i16); 5525 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts); 5526 5527 // Merge the results together. 5528 int Ops[16]; 5529 for (unsigned i = 0; i != 8; ++i) { 5530 Ops[i*2 ] = 2*i+1; 5531 Ops[i*2+1] = 2*i+1+16; 5532 } 5533 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); 5534 } else { 5535 llvm_unreachable("Unknown mul to lower!"); 5536 } 5537} 5538 5539/// LowerOperation - Provide custom lowering hooks for some operations. 5540/// 5541SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 5542 switch (Op.getOpcode()) { 5543 default: llvm_unreachable("Wasn't expecting to be able to lower this!"); 5544 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 5545 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 5546 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 5547 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 5548 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 5549 case ISD::SETCC: return LowerSETCC(Op, DAG); 5550 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 5551 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 5552 case ISD::VASTART: 5553 return LowerVASTART(Op, DAG, PPCSubTarget); 5554 5555 case ISD::VAARG: 5556 return LowerVAARG(Op, DAG, PPCSubTarget); 5557 5558 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 5559 case ISD::DYNAMIC_STACKALLOC: 5560 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 5561 5562 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 5563 case ISD::FP_TO_UINT: 5564 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, 5565 Op.getDebugLoc()); 5566 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 5567 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 5568 5569 // Lower 64-bit shifts. 5570 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 5571 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 5572 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 5573 5574 // Vector-related lowering. 5575 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 5576 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 5577 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 5578 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 5579 case ISD::MUL: return LowerMUL(Op, DAG); 5580 5581 // Frame & Return address. 5582 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 5583 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 5584 } 5585} 5586 5587void PPCTargetLowering::ReplaceNodeResults(SDNode *N, 5588 SmallVectorImpl<SDValue>&Results, 5589 SelectionDAG &DAG) const { 5590 const TargetMachine &TM = getTargetMachine(); 5591 DebugLoc dl = N->getDebugLoc(); 5592 switch (N->getOpcode()) { 5593 default: 5594 llvm_unreachable("Do not know how to custom type legalize this operation!"); 5595 case ISD::VAARG: { 5596 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI() 5597 || TM.getSubtarget<PPCSubtarget>().isPPC64()) 5598 return; 5599 5600 EVT VT = N->getValueType(0); 5601 5602 if (VT == MVT::i64) { 5603 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget); 5604 5605 Results.push_back(NewNode); 5606 Results.push_back(NewNode.getValue(1)); 5607 } 5608 return; 5609 } 5610 case ISD::FP_ROUND_INREG: { 5611 assert(N->getValueType(0) == MVT::ppcf128); 5612 assert(N->getOperand(0).getValueType() == MVT::ppcf128); 5613 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 5614 MVT::f64, N->getOperand(0), 5615 DAG.getIntPtrConstant(0)); 5616 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 5617 MVT::f64, N->getOperand(0), 5618 DAG.getIntPtrConstant(1)); 5619 5620 // This sequence changes FPSCR to do round-to-zero, adds the two halves 5621 // of the long double, and puts FPSCR back the way it was. We do not 5622 // actually model FPSCR. 5623 std::vector<EVT> NodeTys; 5624 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg; 5625 5626 NodeTys.push_back(MVT::f64); // Return register 5627 NodeTys.push_back(MVT::Glue); // Returns a flag for later insns 5628 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 5629 MFFSreg = Result.getValue(0); 5630 InFlag = Result.getValue(1); 5631 5632 NodeTys.clear(); 5633 NodeTys.push_back(MVT::Glue); // Returns a flag 5634 Ops[0] = DAG.getConstant(31, MVT::i32); 5635 Ops[1] = InFlag; 5636 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2); 5637 InFlag = Result.getValue(0); 5638 5639 NodeTys.clear(); 5640 NodeTys.push_back(MVT::Glue); // Returns a flag 5641 Ops[0] = DAG.getConstant(30, MVT::i32); 5642 Ops[1] = InFlag; 5643 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2); 5644 InFlag = Result.getValue(0); 5645 5646 NodeTys.clear(); 5647 NodeTys.push_back(MVT::f64); // result of add 5648 NodeTys.push_back(MVT::Glue); // Returns a flag 5649 Ops[0] = Lo; 5650 Ops[1] = Hi; 5651 Ops[2] = InFlag; 5652 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3); 5653 FPreg = Result.getValue(0); 5654 InFlag = Result.getValue(1); 5655 5656 NodeTys.clear(); 5657 NodeTys.push_back(MVT::f64); 5658 Ops[0] = DAG.getConstant(1, MVT::i32); 5659 Ops[1] = MFFSreg; 5660 Ops[2] = FPreg; 5661 Ops[3] = InFlag; 5662 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4); 5663 FPreg = Result.getValue(0); 5664 5665 // We know the low half is about to be thrown away, so just use something 5666 // convenient. 5667 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, 5668 FPreg, FPreg)); 5669 return; 5670 } 5671 case ISD::FP_TO_SINT: 5672 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl)); 5673 return; 5674 } 5675} 5676 5677 5678//===----------------------------------------------------------------------===// 5679// Other Lowering Code 5680//===----------------------------------------------------------------------===// 5681 5682MachineBasicBlock * 5683PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 5684 bool is64bit, unsigned BinOpcode) const { 5685 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 5686 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5687 5688 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5689 MachineFunction *F = BB->getParent(); 5690 MachineFunction::iterator It = BB; 5691 ++It; 5692 5693 unsigned dest = MI->getOperand(0).getReg(); 5694 unsigned ptrA = MI->getOperand(1).getReg(); 5695 unsigned ptrB = MI->getOperand(2).getReg(); 5696 unsigned incr = MI->getOperand(3).getReg(); 5697 DebugLoc dl = MI->getDebugLoc(); 5698 5699 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 5700 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 5701 F->insert(It, loopMBB); 5702 F->insert(It, exitMBB); 5703 exitMBB->splice(exitMBB->begin(), BB, 5704 llvm::next(MachineBasicBlock::iterator(MI)), 5705 BB->end()); 5706 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5707 5708 MachineRegisterInfo &RegInfo = F->getRegInfo(); 5709 unsigned TmpReg = (!BinOpcode) ? incr : 5710 RegInfo.createVirtualRegister( 5711 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 5712 (const TargetRegisterClass *) &PPC::GPRCRegClass); 5713 5714 // thisMBB: 5715 // ... 5716 // fallthrough --> loopMBB 5717 BB->addSuccessor(loopMBB); 5718 5719 // loopMBB: 5720 // l[wd]arx dest, ptr 5721 // add r0, dest, incr 5722 // st[wd]cx. r0, ptr 5723 // bne- loopMBB 5724 // fallthrough --> exitMBB 5725 BB = loopMBB; 5726 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 5727 .addReg(ptrA).addReg(ptrB); 5728 if (BinOpcode) 5729 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); 5730 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 5731 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); 5732 BuildMI(BB, dl, TII->get(PPC::BCC)) 5733 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 5734 BB->addSuccessor(loopMBB); 5735 BB->addSuccessor(exitMBB); 5736 5737 // exitMBB: 5738 // ... 5739 BB = exitMBB; 5740 return BB; 5741} 5742 5743MachineBasicBlock * 5744PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, 5745 MachineBasicBlock *BB, 5746 bool is8bit, // operation 5747 unsigned BinOpcode) const { 5748 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 5749 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5750 // In 64 bit mode we have to use 64 bits for addresses, even though the 5751 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address 5752 // registers without caring whether they're 32 or 64, but here we're 5753 // doing actual arithmetic on the addresses. 5754 bool is64bit = PPCSubTarget.isPPC64(); 5755 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; 5756 5757 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5758 MachineFunction *F = BB->getParent(); 5759 MachineFunction::iterator It = BB; 5760 ++It; 5761 5762 unsigned dest = MI->getOperand(0).getReg(); 5763 unsigned ptrA = MI->getOperand(1).getReg(); 5764 unsigned ptrB = MI->getOperand(2).getReg(); 5765 unsigned incr = MI->getOperand(3).getReg(); 5766 DebugLoc dl = MI->getDebugLoc(); 5767 5768 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 5769 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 5770 F->insert(It, loopMBB); 5771 F->insert(It, exitMBB); 5772 exitMBB->splice(exitMBB->begin(), BB, 5773 llvm::next(MachineBasicBlock::iterator(MI)), 5774 BB->end()); 5775 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5776 5777 MachineRegisterInfo &RegInfo = F->getRegInfo(); 5778 const TargetRegisterClass *RC = 5779 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 5780 (const TargetRegisterClass *) &PPC::GPRCRegClass; 5781 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 5782 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 5783 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 5784 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC); 5785 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 5786 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 5787 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 5788 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 5789 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC); 5790 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 5791 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 5792 unsigned Ptr1Reg; 5793 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); 5794 5795 // thisMBB: 5796 // ... 5797 // fallthrough --> loopMBB 5798 BB->addSuccessor(loopMBB); 5799 5800 // The 4-byte load must be aligned, while a char or short may be 5801 // anywhere in the word. Hence all this nasty bookkeeping code. 5802 // add ptr1, ptrA, ptrB [copy if ptrA==0] 5803 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 5804 // xori shift, shift1, 24 [16] 5805 // rlwinm ptr, ptr1, 0, 0, 29 5806 // slw incr2, incr, shift 5807 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 5808 // slw mask, mask2, shift 5809 // loopMBB: 5810 // lwarx tmpDest, ptr 5811 // add tmp, tmpDest, incr2 5812 // andc tmp2, tmpDest, mask 5813 // and tmp3, tmp, mask 5814 // or tmp4, tmp3, tmp2 5815 // stwcx. tmp4, ptr 5816 // bne- loopMBB 5817 // fallthrough --> exitMBB 5818 // srw dest, tmpDest, shift 5819 if (ptrA != ZeroReg) { 5820 Ptr1Reg = RegInfo.createVirtualRegister(RC); 5821 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 5822 .addReg(ptrA).addReg(ptrB); 5823 } else { 5824 Ptr1Reg = ptrB; 5825 } 5826 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 5827 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 5828 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 5829 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 5830 if (is64bit) 5831 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 5832 .addReg(Ptr1Reg).addImm(0).addImm(61); 5833 else 5834 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 5835 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 5836 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg) 5837 .addReg(incr).addReg(ShiftReg); 5838 if (is8bit) 5839 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 5840 else { 5841 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 5842 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535); 5843 } 5844 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 5845 .addReg(Mask2Reg).addReg(ShiftReg); 5846 5847 BB = loopMBB; 5848 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 5849 .addReg(ZeroReg).addReg(PtrReg); 5850 if (BinOpcode) 5851 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) 5852 .addReg(Incr2Reg).addReg(TmpDestReg); 5853 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) 5854 .addReg(TmpDestReg).addReg(MaskReg); 5855 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) 5856 .addReg(TmpReg).addReg(MaskReg); 5857 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) 5858 .addReg(Tmp3Reg).addReg(Tmp2Reg); 5859 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 5860 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg); 5861 BuildMI(BB, dl, TII->get(PPC::BCC)) 5862 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 5863 BB->addSuccessor(loopMBB); 5864 BB->addSuccessor(exitMBB); 5865 5866 // exitMBB: 5867 // ... 5868 BB = exitMBB; 5869 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg) 5870 .addReg(ShiftReg); 5871 return BB; 5872} 5873 5874MachineBasicBlock * 5875PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 5876 MachineBasicBlock *BB) const { 5877 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5878 5879 // To "insert" these instructions we actually have to insert their 5880 // control-flow patterns. 5881 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5882 MachineFunction::iterator It = BB; 5883 ++It; 5884 5885 MachineFunction *F = BB->getParent(); 5886 5887 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 || 5888 MI->getOpcode() == PPC::SELECT_CC_I8)) { 5889 unsigned OpCode = MI->getOpcode() == PPC::SELECT_CC_I8 ? 5890 PPC::ISEL8 : PPC::ISEL; 5891 unsigned SelectPred = MI->getOperand(4).getImm(); 5892 DebugLoc dl = MI->getDebugLoc(); 5893 5894 // The SelectPred is ((BI << 5) | BO) for a BCC 5895 unsigned BO = SelectPred & 0xF; 5896 assert((BO == 12 || BO == 4) && "invalid predicate BO field for isel"); 5897 5898 unsigned TrueOpNo, FalseOpNo; 5899 if (BO == 12) { 5900 TrueOpNo = 2; 5901 FalseOpNo = 3; 5902 } else { 5903 TrueOpNo = 3; 5904 FalseOpNo = 2; 5905 SelectPred = PPC::InvertPredicate((PPC::Predicate)SelectPred); 5906 } 5907 5908 BuildMI(*BB, MI, dl, TII->get(OpCode), MI->getOperand(0).getReg()) 5909 .addReg(MI->getOperand(TrueOpNo).getReg()) 5910 .addReg(MI->getOperand(FalseOpNo).getReg()) 5911 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()); 5912 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 || 5913 MI->getOpcode() == PPC::SELECT_CC_I8 || 5914 MI->getOpcode() == PPC::SELECT_CC_F4 || 5915 MI->getOpcode() == PPC::SELECT_CC_F8 || 5916 MI->getOpcode() == PPC::SELECT_CC_VRRC) { 5917 5918 5919 // The incoming instruction knows the destination vreg to set, the 5920 // condition code register to branch on, the true/false values to 5921 // select between, and a branch opcode to use. 5922 5923 // thisMBB: 5924 // ... 5925 // TrueVal = ... 5926 // cmpTY ccX, r1, r2 5927 // bCC copy1MBB 5928 // fallthrough --> copy0MBB 5929 MachineBasicBlock *thisMBB = BB; 5930 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 5931 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 5932 unsigned SelectPred = MI->getOperand(4).getImm(); 5933 DebugLoc dl = MI->getDebugLoc(); 5934 F->insert(It, copy0MBB); 5935 F->insert(It, sinkMBB); 5936 5937 // Transfer the remainder of BB and its successor edges to sinkMBB. 5938 sinkMBB->splice(sinkMBB->begin(), BB, 5939 llvm::next(MachineBasicBlock::iterator(MI)), 5940 BB->end()); 5941 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 5942 5943 // Next, add the true and fallthrough blocks as its successors. 5944 BB->addSuccessor(copy0MBB); 5945 BB->addSuccessor(sinkMBB); 5946 5947 BuildMI(BB, dl, TII->get(PPC::BCC)) 5948 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 5949 5950 // copy0MBB: 5951 // %FalseValue = ... 5952 // # fallthrough to sinkMBB 5953 BB = copy0MBB; 5954 5955 // Update machine-CFG edges 5956 BB->addSuccessor(sinkMBB); 5957 5958 // sinkMBB: 5959 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 5960 // ... 5961 BB = sinkMBB; 5962 BuildMI(*BB, BB->begin(), dl, 5963 TII->get(PPC::PHI), MI->getOperand(0).getReg()) 5964 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 5965 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 5966 } 5967 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) 5968 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); 5969 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) 5970 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); 5971 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) 5972 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4); 5973 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) 5974 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8); 5975 5976 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8) 5977 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); 5978 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16) 5979 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); 5980 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32) 5981 BB = EmitAtomicBinary(MI, BB, false, PPC::AND); 5982 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64) 5983 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8); 5984 5985 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8) 5986 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); 5987 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16) 5988 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); 5989 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32) 5990 BB = EmitAtomicBinary(MI, BB, false, PPC::OR); 5991 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64) 5992 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8); 5993 5994 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) 5995 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); 5996 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) 5997 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); 5998 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) 5999 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR); 6000 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) 6001 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8); 6002 6003 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) 6004 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC); 6005 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) 6006 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC); 6007 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) 6008 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC); 6009 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) 6010 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8); 6011 6012 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) 6013 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); 6014 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) 6015 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); 6016 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) 6017 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF); 6018 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) 6019 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8); 6020 6021 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8) 6022 BB = EmitPartwordAtomicBinary(MI, BB, true, 0); 6023 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16) 6024 BB = EmitPartwordAtomicBinary(MI, BB, false, 0); 6025 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32) 6026 BB = EmitAtomicBinary(MI, BB, false, 0); 6027 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64) 6028 BB = EmitAtomicBinary(MI, BB, true, 0); 6029 6030 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || 6031 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) { 6032 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; 6033 6034 unsigned dest = MI->getOperand(0).getReg(); 6035 unsigned ptrA = MI->getOperand(1).getReg(); 6036 unsigned ptrB = MI->getOperand(2).getReg(); 6037 unsigned oldval = MI->getOperand(3).getReg(); 6038 unsigned newval = MI->getOperand(4).getReg(); 6039 DebugLoc dl = MI->getDebugLoc(); 6040 6041 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 6042 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 6043 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 6044 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 6045 F->insert(It, loop1MBB); 6046 F->insert(It, loop2MBB); 6047 F->insert(It, midMBB); 6048 F->insert(It, exitMBB); 6049 exitMBB->splice(exitMBB->begin(), BB, 6050 llvm::next(MachineBasicBlock::iterator(MI)), 6051 BB->end()); 6052 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 6053 6054 // thisMBB: 6055 // ... 6056 // fallthrough --> loopMBB 6057 BB->addSuccessor(loop1MBB); 6058 6059 // loop1MBB: 6060 // l[wd]arx dest, ptr 6061 // cmp[wd] dest, oldval 6062 // bne- midMBB 6063 // loop2MBB: 6064 // st[wd]cx. newval, ptr 6065 // bne- loopMBB 6066 // b exitBB 6067 // midMBB: 6068 // st[wd]cx. dest, ptr 6069 // exitBB: 6070 BB = loop1MBB; 6071 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 6072 .addReg(ptrA).addReg(ptrB); 6073 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) 6074 .addReg(oldval).addReg(dest); 6075 BuildMI(BB, dl, TII->get(PPC::BCC)) 6076 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 6077 BB->addSuccessor(loop2MBB); 6078 BB->addSuccessor(midMBB); 6079 6080 BB = loop2MBB; 6081 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 6082 .addReg(newval).addReg(ptrA).addReg(ptrB); 6083 BuildMI(BB, dl, TII->get(PPC::BCC)) 6084 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 6085 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 6086 BB->addSuccessor(loop1MBB); 6087 BB->addSuccessor(exitMBB); 6088 6089 BB = midMBB; 6090 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 6091 .addReg(dest).addReg(ptrA).addReg(ptrB); 6092 BB->addSuccessor(exitMBB); 6093 6094 // exitMBB: 6095 // ... 6096 BB = exitMBB; 6097 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || 6098 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { 6099 // We must use 64-bit registers for addresses when targeting 64-bit, 6100 // since we're actually doing arithmetic on them. Other registers 6101 // can be 32-bit. 6102 bool is64bit = PPCSubTarget.isPPC64(); 6103 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; 6104 6105 unsigned dest = MI->getOperand(0).getReg(); 6106 unsigned ptrA = MI->getOperand(1).getReg(); 6107 unsigned ptrB = MI->getOperand(2).getReg(); 6108 unsigned oldval = MI->getOperand(3).getReg(); 6109 unsigned newval = MI->getOperand(4).getReg(); 6110 DebugLoc dl = MI->getDebugLoc(); 6111 6112 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 6113 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 6114 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 6115 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 6116 F->insert(It, loop1MBB); 6117 F->insert(It, loop2MBB); 6118 F->insert(It, midMBB); 6119 F->insert(It, exitMBB); 6120 exitMBB->splice(exitMBB->begin(), BB, 6121 llvm::next(MachineBasicBlock::iterator(MI)), 6122 BB->end()); 6123 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 6124 6125 MachineRegisterInfo &RegInfo = F->getRegInfo(); 6126 const TargetRegisterClass *RC = 6127 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 6128 (const TargetRegisterClass *) &PPC::GPRCRegClass; 6129 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 6130 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 6131 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 6132 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC); 6133 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC); 6134 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC); 6135 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC); 6136 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 6137 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 6138 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 6139 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 6140 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 6141 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 6142 unsigned Ptr1Reg; 6143 unsigned TmpReg = RegInfo.createVirtualRegister(RC); 6144 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; 6145 // thisMBB: 6146 // ... 6147 // fallthrough --> loopMBB 6148 BB->addSuccessor(loop1MBB); 6149 6150 // The 4-byte load must be aligned, while a char or short may be 6151 // anywhere in the word. Hence all this nasty bookkeeping code. 6152 // add ptr1, ptrA, ptrB [copy if ptrA==0] 6153 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 6154 // xori shift, shift1, 24 [16] 6155 // rlwinm ptr, ptr1, 0, 0, 29 6156 // slw newval2, newval, shift 6157 // slw oldval2, oldval,shift 6158 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 6159 // slw mask, mask2, shift 6160 // and newval3, newval2, mask 6161 // and oldval3, oldval2, mask 6162 // loop1MBB: 6163 // lwarx tmpDest, ptr 6164 // and tmp, tmpDest, mask 6165 // cmpw tmp, oldval3 6166 // bne- midMBB 6167 // loop2MBB: 6168 // andc tmp2, tmpDest, mask 6169 // or tmp4, tmp2, newval3 6170 // stwcx. tmp4, ptr 6171 // bne- loop1MBB 6172 // b exitBB 6173 // midMBB: 6174 // stwcx. tmpDest, ptr 6175 // exitBB: 6176 // srw dest, tmpDest, shift 6177 if (ptrA != ZeroReg) { 6178 Ptr1Reg = RegInfo.createVirtualRegister(RC); 6179 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 6180 .addReg(ptrA).addReg(ptrB); 6181 } else { 6182 Ptr1Reg = ptrB; 6183 } 6184 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 6185 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 6186 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 6187 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 6188 if (is64bit) 6189 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 6190 .addReg(Ptr1Reg).addImm(0).addImm(61); 6191 else 6192 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 6193 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 6194 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) 6195 .addReg(newval).addReg(ShiftReg); 6196 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) 6197 .addReg(oldval).addReg(ShiftReg); 6198 if (is8bit) 6199 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 6200 else { 6201 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 6202 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) 6203 .addReg(Mask3Reg).addImm(65535); 6204 } 6205 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 6206 .addReg(Mask2Reg).addReg(ShiftReg); 6207 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg) 6208 .addReg(NewVal2Reg).addReg(MaskReg); 6209 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg) 6210 .addReg(OldVal2Reg).addReg(MaskReg); 6211 6212 BB = loop1MBB; 6213 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 6214 .addReg(ZeroReg).addReg(PtrReg); 6215 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) 6216 .addReg(TmpDestReg).addReg(MaskReg); 6217 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0) 6218 .addReg(TmpReg).addReg(OldVal3Reg); 6219 BuildMI(BB, dl, TII->get(PPC::BCC)) 6220 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 6221 BB->addSuccessor(loop2MBB); 6222 BB->addSuccessor(midMBB); 6223 6224 BB = loop2MBB; 6225 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg) 6226 .addReg(TmpDestReg).addReg(MaskReg); 6227 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg) 6228 .addReg(Tmp2Reg).addReg(NewVal3Reg); 6229 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg) 6230 .addReg(ZeroReg).addReg(PtrReg); 6231 BuildMI(BB, dl, TII->get(PPC::BCC)) 6232 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 6233 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 6234 BB->addSuccessor(loop1MBB); 6235 BB->addSuccessor(exitMBB); 6236 6237 BB = midMBB; 6238 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg) 6239 .addReg(ZeroReg).addReg(PtrReg); 6240 BB->addSuccessor(exitMBB); 6241 6242 // exitMBB: 6243 // ... 6244 BB = exitMBB; 6245 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg) 6246 .addReg(ShiftReg); 6247 } else { 6248 llvm_unreachable("Unexpected instr type to insert"); 6249 } 6250 6251 MI->eraseFromParent(); // The pseudo instruction is gone now. 6252 return BB; 6253} 6254 6255//===----------------------------------------------------------------------===// 6256// Target Optimization Hooks 6257//===----------------------------------------------------------------------===// 6258 6259SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, 6260 DAGCombinerInfo &DCI) const { 6261 const TargetMachine &TM = getTargetMachine(); 6262 SelectionDAG &DAG = DCI.DAG; 6263 DebugLoc dl = N->getDebugLoc(); 6264 switch (N->getOpcode()) { 6265 default: break; 6266 case PPCISD::SHL: 6267 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 6268 if (C->isNullValue()) // 0 << V -> 0. 6269 return N->getOperand(0); 6270 } 6271 break; 6272 case PPCISD::SRL: 6273 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 6274 if (C->isNullValue()) // 0 >>u V -> 0. 6275 return N->getOperand(0); 6276 } 6277 break; 6278 case PPCISD::SRA: 6279 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 6280 if (C->isNullValue() || // 0 >>s V -> 0. 6281 C->isAllOnesValue()) // -1 >>s V -> -1. 6282 return N->getOperand(0); 6283 } 6284 break; 6285 6286 case ISD::SINT_TO_FP: 6287 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 6288 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 6289 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 6290 // We allow the src/dst to be either f32/f64, but the intermediate 6291 // type must be i64. 6292 if (N->getOperand(0).getValueType() == MVT::i64 && 6293 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 6294 SDValue Val = N->getOperand(0).getOperand(0); 6295 if (Val.getValueType() == MVT::f32) { 6296 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 6297 DCI.AddToWorklist(Val.getNode()); 6298 } 6299 6300 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val); 6301 DCI.AddToWorklist(Val.getNode()); 6302 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val); 6303 DCI.AddToWorklist(Val.getNode()); 6304 if (N->getValueType(0) == MVT::f32) { 6305 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val, 6306 DAG.getIntPtrConstant(0)); 6307 DCI.AddToWorklist(Val.getNode()); 6308 } 6309 return Val; 6310 } else if (N->getOperand(0).getValueType() == MVT::i32) { 6311 // If the intermediate type is i32, we can avoid the load/store here 6312 // too. 6313 } 6314 } 6315 } 6316 break; 6317 case ISD::STORE: 6318 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 6319 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 6320 !cast<StoreSDNode>(N)->isTruncatingStore() && 6321 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 6322 N->getOperand(1).getValueType() == MVT::i32 && 6323 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 6324 SDValue Val = N->getOperand(1).getOperand(0); 6325 if (Val.getValueType() == MVT::f32) { 6326 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 6327 DCI.AddToWorklist(Val.getNode()); 6328 } 6329 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); 6330 DCI.AddToWorklist(Val.getNode()); 6331 6332 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val, 6333 N->getOperand(2), N->getOperand(3)); 6334 DCI.AddToWorklist(Val.getNode()); 6335 return Val; 6336 } 6337 6338 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 6339 if (cast<StoreSDNode>(N)->isUnindexed() && 6340 N->getOperand(1).getOpcode() == ISD::BSWAP && 6341 N->getOperand(1).getNode()->hasOneUse() && 6342 (N->getOperand(1).getValueType() == MVT::i32 || 6343 N->getOperand(1).getValueType() == MVT::i16)) { 6344 SDValue BSwapOp = N->getOperand(1).getOperand(0); 6345 // Do an any-extend to 32-bits if this is a half-word input. 6346 if (BSwapOp.getValueType() == MVT::i16) 6347 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); 6348 6349 SDValue Ops[] = { 6350 N->getOperand(0), BSwapOp, N->getOperand(2), 6351 DAG.getValueType(N->getOperand(1).getValueType()) 6352 }; 6353 return 6354 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), 6355 Ops, array_lengthof(Ops), 6356 cast<StoreSDNode>(N)->getMemoryVT(), 6357 cast<StoreSDNode>(N)->getMemOperand()); 6358 } 6359 break; 6360 case ISD::BSWAP: 6361 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 6362 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) && 6363 N->getOperand(0).hasOneUse() && 6364 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 6365 SDValue Load = N->getOperand(0); 6366 LoadSDNode *LD = cast<LoadSDNode>(Load); 6367 // Create the byte-swapping load. 6368 SDValue Ops[] = { 6369 LD->getChain(), // Chain 6370 LD->getBasePtr(), // Ptr 6371 DAG.getValueType(N->getValueType(0)) // VT 6372 }; 6373 SDValue BSLoad = 6374 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl, 6375 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3, 6376 LD->getMemoryVT(), LD->getMemOperand()); 6377 6378 // If this is an i16 load, insert the truncate. 6379 SDValue ResVal = BSLoad; 6380 if (N->getValueType(0) == MVT::i16) 6381 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); 6382 6383 // First, combine the bswap away. This makes the value produced by the 6384 // load dead. 6385 DCI.CombineTo(N, ResVal); 6386 6387 // Next, combine the load away, we give it a bogus result value but a real 6388 // chain result. The result value is dead because the bswap is dead. 6389 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1)); 6390 6391 // Return N so it doesn't get rechecked! 6392 return SDValue(N, 0); 6393 } 6394 6395 break; 6396 case PPCISD::VCMP: { 6397 // If a VCMPo node already exists with exactly the same operands as this 6398 // node, use its result instead of this node (VCMPo computes both a CR6 and 6399 // a normal output). 6400 // 6401 if (!N->getOperand(0).hasOneUse() && 6402 !N->getOperand(1).hasOneUse() && 6403 !N->getOperand(2).hasOneUse()) { 6404 6405 // Scan all of the users of the LHS, looking for VCMPo's that match. 6406 SDNode *VCMPoNode = 0; 6407 6408 SDNode *LHSN = N->getOperand(0).getNode(); 6409 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 6410 UI != E; ++UI) 6411 if (UI->getOpcode() == PPCISD::VCMPo && 6412 UI->getOperand(1) == N->getOperand(1) && 6413 UI->getOperand(2) == N->getOperand(2) && 6414 UI->getOperand(0) == N->getOperand(0)) { 6415 VCMPoNode = *UI; 6416 break; 6417 } 6418 6419 // If there is no VCMPo node, or if the flag value has a single use, don't 6420 // transform this. 6421 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 6422 break; 6423 6424 // Look at the (necessarily single) use of the flag value. If it has a 6425 // chain, this transformation is more complex. Note that multiple things 6426 // could use the value result, which we should ignore. 6427 SDNode *FlagUser = 0; 6428 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 6429 FlagUser == 0; ++UI) { 6430 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 6431 SDNode *User = *UI; 6432 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 6433 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) { 6434 FlagUser = User; 6435 break; 6436 } 6437 } 6438 } 6439 6440 // If the user is a MFCR instruction, we know this is safe. Otherwise we 6441 // give up for right now. 6442 if (FlagUser->getOpcode() == PPCISD::MFCR) 6443 return SDValue(VCMPoNode, 0); 6444 } 6445 break; 6446 } 6447 case ISD::BR_CC: { 6448 // If this is a branch on an altivec predicate comparison, lower this so 6449 // that we don't have to do a MFCR: instead, branch directly on CR6. This 6450 // lowering is done pre-legalize, because the legalizer lowers the predicate 6451 // compare down to code that is difficult to reassemble. 6452 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 6453 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 6454 int CompareOpc; 6455 bool isDot; 6456 6457 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 6458 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 6459 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 6460 assert(isDot && "Can't compare against a vector result!"); 6461 6462 // If this is a comparison against something other than 0/1, then we know 6463 // that the condition is never/always true. 6464 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue(); 6465 if (Val != 0 && Val != 1) { 6466 if (CC == ISD::SETEQ) // Cond never true, remove branch. 6467 return N->getOperand(0); 6468 // Always !=, turn it into an unconditional branch. 6469 return DAG.getNode(ISD::BR, dl, MVT::Other, 6470 N->getOperand(0), N->getOperand(4)); 6471 } 6472 6473 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 6474 6475 // Create the PPCISD altivec 'dot' comparison node. 6476 std::vector<EVT> VTs; 6477 SDValue Ops[] = { 6478 LHS.getOperand(2), // LHS of compare 6479 LHS.getOperand(3), // RHS of compare 6480 DAG.getConstant(CompareOpc, MVT::i32) 6481 }; 6482 VTs.push_back(LHS.getOperand(2).getValueType()); 6483 VTs.push_back(MVT::Glue); 6484 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 6485 6486 // Unpack the result based on how the target uses it. 6487 PPC::Predicate CompOpc; 6488 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) { 6489 default: // Can't happen, don't crash on invalid number though. 6490 case 0: // Branch on the value of the EQ bit of CR6. 6491 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 6492 break; 6493 case 1: // Branch on the inverted value of the EQ bit of CR6. 6494 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 6495 break; 6496 case 2: // Branch on the value of the LT bit of CR6. 6497 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 6498 break; 6499 case 3: // Branch on the inverted value of the LT bit of CR6. 6500 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 6501 break; 6502 } 6503 6504 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), 6505 DAG.getConstant(CompOpc, MVT::i32), 6506 DAG.getRegister(PPC::CR6, MVT::i32), 6507 N->getOperand(4), CompNode.getValue(1)); 6508 } 6509 break; 6510 } 6511 } 6512 6513 return SDValue(); 6514} 6515 6516//===----------------------------------------------------------------------===// 6517// Inline Assembly Support 6518//===----------------------------------------------------------------------===// 6519 6520void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 6521 APInt &KnownZero, 6522 APInt &KnownOne, 6523 const SelectionDAG &DAG, 6524 unsigned Depth) const { 6525 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); 6526 switch (Op.getOpcode()) { 6527 default: break; 6528 case PPCISD::LBRX: { 6529 // lhbrx is known to have the top bits cleared out. 6530 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) 6531 KnownZero = 0xFFFF0000; 6532 break; 6533 } 6534 case ISD::INTRINSIC_WO_CHAIN: { 6535 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) { 6536 default: break; 6537 case Intrinsic::ppc_altivec_vcmpbfp_p: 6538 case Intrinsic::ppc_altivec_vcmpeqfp_p: 6539 case Intrinsic::ppc_altivec_vcmpequb_p: 6540 case Intrinsic::ppc_altivec_vcmpequh_p: 6541 case Intrinsic::ppc_altivec_vcmpequw_p: 6542 case Intrinsic::ppc_altivec_vcmpgefp_p: 6543 case Intrinsic::ppc_altivec_vcmpgtfp_p: 6544 case Intrinsic::ppc_altivec_vcmpgtsb_p: 6545 case Intrinsic::ppc_altivec_vcmpgtsh_p: 6546 case Intrinsic::ppc_altivec_vcmpgtsw_p: 6547 case Intrinsic::ppc_altivec_vcmpgtub_p: 6548 case Intrinsic::ppc_altivec_vcmpgtuh_p: 6549 case Intrinsic::ppc_altivec_vcmpgtuw_p: 6550 KnownZero = ~1U; // All bits but the low one are known to be zero. 6551 break; 6552 } 6553 } 6554 } 6555} 6556 6557 6558/// getConstraintType - Given a constraint, return the type of 6559/// constraint it is for this target. 6560PPCTargetLowering::ConstraintType 6561PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 6562 if (Constraint.size() == 1) { 6563 switch (Constraint[0]) { 6564 default: break; 6565 case 'b': 6566 case 'r': 6567 case 'f': 6568 case 'v': 6569 case 'y': 6570 return C_RegisterClass; 6571 case 'Z': 6572 // FIXME: While Z does indicate a memory constraint, it specifically 6573 // indicates an r+r address (used in conjunction with the 'y' modifier 6574 // in the replacement string). Currently, we're forcing the base 6575 // register to be r0 in the asm printer (which is interpreted as zero) 6576 // and forming the complete address in the second register. This is 6577 // suboptimal. 6578 return C_Memory; 6579 } 6580 } 6581 return TargetLowering::getConstraintType(Constraint); 6582} 6583 6584/// Examine constraint type and operand type and determine a weight value. 6585/// This object must already have been set up with the operand type 6586/// and the current alternative constraint selected. 6587TargetLowering::ConstraintWeight 6588PPCTargetLowering::getSingleConstraintMatchWeight( 6589 AsmOperandInfo &info, const char *constraint) const { 6590 ConstraintWeight weight = CW_Invalid; 6591 Value *CallOperandVal = info.CallOperandVal; 6592 // If we don't have a value, we can't do a match, 6593 // but allow it at the lowest weight. 6594 if (CallOperandVal == NULL) 6595 return CW_Default; 6596 Type *type = CallOperandVal->getType(); 6597 // Look at the constraint type. 6598 switch (*constraint) { 6599 default: 6600 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 6601 break; 6602 case 'b': 6603 if (type->isIntegerTy()) 6604 weight = CW_Register; 6605 break; 6606 case 'f': 6607 if (type->isFloatTy()) 6608 weight = CW_Register; 6609 break; 6610 case 'd': 6611 if (type->isDoubleTy()) 6612 weight = CW_Register; 6613 break; 6614 case 'v': 6615 if (type->isVectorTy()) 6616 weight = CW_Register; 6617 break; 6618 case 'y': 6619 weight = CW_Register; 6620 break; 6621 case 'Z': 6622 weight = CW_Memory; 6623 break; 6624 } 6625 return weight; 6626} 6627 6628std::pair<unsigned, const TargetRegisterClass*> 6629PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 6630 EVT VT) const { 6631 if (Constraint.size() == 1) { 6632 // GCC RS6000 Constraint Letters 6633 switch (Constraint[0]) { 6634 case 'b': // R1-R31 6635 case 'r': // R0-R31 6636 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 6637 return std::make_pair(0U, &PPC::G8RCRegClass); 6638 return std::make_pair(0U, &PPC::GPRCRegClass); 6639 case 'f': 6640 if (VT == MVT::f32 || VT == MVT::i32) 6641 return std::make_pair(0U, &PPC::F4RCRegClass); 6642 if (VT == MVT::f64 || VT == MVT::i64) 6643 return std::make_pair(0U, &PPC::F8RCRegClass); 6644 break; 6645 case 'v': 6646 return std::make_pair(0U, &PPC::VRRCRegClass); 6647 case 'y': // crrc 6648 return std::make_pair(0U, &PPC::CRRCRegClass); 6649 } 6650 } 6651 6652 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 6653} 6654 6655 6656/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 6657/// vector. If it is invalid, don't add anything to Ops. 6658void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 6659 std::string &Constraint, 6660 std::vector<SDValue>&Ops, 6661 SelectionDAG &DAG) const { 6662 SDValue Result(0,0); 6663 6664 // Only support length 1 constraints. 6665 if (Constraint.length() > 1) return; 6666 6667 char Letter = Constraint[0]; 6668 switch (Letter) { 6669 default: break; 6670 case 'I': 6671 case 'J': 6672 case 'K': 6673 case 'L': 6674 case 'M': 6675 case 'N': 6676 case 'O': 6677 case 'P': { 6678 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 6679 if (!CST) return; // Must be an immediate to match. 6680 unsigned Value = CST->getZExtValue(); 6681 switch (Letter) { 6682 default: llvm_unreachable("Unknown constraint letter!"); 6683 case 'I': // "I" is a signed 16-bit constant. 6684 if ((short)Value == (int)Value) 6685 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6686 break; 6687 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 6688 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 6689 if ((short)Value == 0) 6690 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6691 break; 6692 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 6693 if ((Value >> 16) == 0) 6694 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6695 break; 6696 case 'M': // "M" is a constant that is greater than 31. 6697 if (Value > 31) 6698 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6699 break; 6700 case 'N': // "N" is a positive constant that is an exact power of two. 6701 if ((int)Value > 0 && isPowerOf2_32(Value)) 6702 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6703 break; 6704 case 'O': // "O" is the constant zero. 6705 if (Value == 0) 6706 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6707 break; 6708 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 6709 if ((short)-Value == (int)-Value) 6710 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6711 break; 6712 } 6713 break; 6714 } 6715 } 6716 6717 if (Result.getNode()) { 6718 Ops.push_back(Result); 6719 return; 6720 } 6721 6722 // Handle standard constraint letters. 6723 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 6724} 6725 6726// isLegalAddressingMode - Return true if the addressing mode represented 6727// by AM is legal for this target, for a load/store of the specified type. 6728bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 6729 Type *Ty) const { 6730 // FIXME: PPC does not allow r+i addressing modes for vectors! 6731 6732 // PPC allows a sign-extended 16-bit immediate field. 6733 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 6734 return false; 6735 6736 // No global is ever allowed as a base. 6737 if (AM.BaseGV) 6738 return false; 6739 6740 // PPC only support r+r, 6741 switch (AM.Scale) { 6742 case 0: // "r+i" or just "i", depending on HasBaseReg. 6743 break; 6744 case 1: 6745 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 6746 return false; 6747 // Otherwise we have r+r or r+i. 6748 break; 6749 case 2: 6750 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 6751 return false; 6752 // Allow 2*r as r+r. 6753 break; 6754 default: 6755 // No other scales are supported. 6756 return false; 6757 } 6758 6759 return true; 6760} 6761 6762/// isLegalAddressImmediate - Return true if the integer value can be used 6763/// as the offset of the target addressing mode for load / store of the 6764/// given type. 6765bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{ 6766 // PPC allows a sign-extended 16-bit immediate field. 6767 return (V > -(1 << 16) && V < (1 << 16)-1); 6768} 6769 6770bool PPCTargetLowering::isLegalAddressImmediate(GlobalValue* GV) const { 6771 return false; 6772} 6773 6774SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, 6775 SelectionDAG &DAG) const { 6776 MachineFunction &MF = DAG.getMachineFunction(); 6777 MachineFrameInfo *MFI = MF.getFrameInfo(); 6778 MFI->setReturnAddressIsTaken(true); 6779 6780 DebugLoc dl = Op.getDebugLoc(); 6781 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6782 6783 // Make sure the function does not optimize away the store of the RA to 6784 // the stack. 6785 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 6786 FuncInfo->setLRStoreRequired(); 6787 bool isPPC64 = PPCSubTarget.isPPC64(); 6788 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 6789 6790 if (Depth > 0) { 6791 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 6792 SDValue Offset = 6793 6794 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI), 6795 isPPC64? MVT::i64 : MVT::i32); 6796 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 6797 DAG.getNode(ISD::ADD, dl, getPointerTy(), 6798 FrameAddr, Offset), 6799 MachinePointerInfo(), false, false, false, 0); 6800 } 6801 6802 // Just load the return address off the stack. 6803 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); 6804 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 6805 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 6806} 6807 6808SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, 6809 SelectionDAG &DAG) const { 6810 DebugLoc dl = Op.getDebugLoc(); 6811 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6812 6813 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 6814 bool isPPC64 = PtrVT == MVT::i64; 6815 6816 MachineFunction &MF = DAG.getMachineFunction(); 6817 MachineFrameInfo *MFI = MF.getFrameInfo(); 6818 MFI->setFrameAddressIsTaken(true); 6819 bool is31 = (getTargetMachine().Options.DisableFramePointerElim(MF) || 6820 MFI->hasVarSizedObjects()) && 6821 MFI->getStackSize() && 6822 !MF.getFunction()->getFnAttributes(). 6823 hasAttribute(Attributes::Naked); 6824 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) : 6825 (is31 ? PPC::R31 : PPC::R1); 6826 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, 6827 PtrVT); 6828 while (Depth--) 6829 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(), 6830 FrameAddr, MachinePointerInfo(), false, false, 6831 false, 0); 6832 return FrameAddr; 6833} 6834 6835bool 6836PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 6837 // The PowerPC target isn't yet aware of offsets. 6838 return false; 6839} 6840 6841/// getOptimalMemOpType - Returns the target specific optimal type for load 6842/// and store operations as a result of memset, memcpy, and memmove 6843/// lowering. If DstAlign is zero that means it's safe to destination 6844/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 6845/// means there isn't a need to check it against alignment requirement, 6846/// probably because the source does not need to be loaded. If 'IsMemset' is 6847/// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 6848/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 6849/// source is constant so it does not need to be loaded. 6850/// It returns EVT::Other if the type should be determined using generic 6851/// target-independent logic. 6852EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, 6853 unsigned DstAlign, unsigned SrcAlign, 6854 bool IsMemset, bool ZeroMemset, 6855 bool MemcpyStrSrc, 6856 MachineFunction &MF) const { 6857 if (this->PPCSubTarget.isPPC64()) { 6858 return MVT::i64; 6859 } else { 6860 return MVT::i32; 6861 } 6862} 6863 6864/// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than 6865/// a pair of mul and add instructions. fmuladd intrinsics will be expanded to 6866/// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd 6867/// is expanded to mul + add. 6868bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const { 6869 if (!VT.isSimple()) 6870 return false; 6871 6872 switch (VT.getSimpleVT().SimpleTy) { 6873 case MVT::f32: 6874 case MVT::f64: 6875 case MVT::v4f32: 6876 return true; 6877 default: 6878 break; 6879 } 6880 6881 return false; 6882} 6883 6884Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const { 6885 if (DisableILPPref) 6886 return TargetLowering::getSchedulingPreference(N); 6887 6888 return Sched::ILP; 6889} 6890 6891