PPCISelLowering.cpp revision d752e0f7e64585839cb3a458ef52456eaebbea3c
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPerfectShuffle.h" 17#include "PPCTargetMachine.h" 18#include "MCTargetDesc/PPCPredicates.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/ADT/VectorExtras.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 29#include "llvm/CallingConv.h" 30#include "llvm/Constants.h" 31#include "llvm/Function.h" 32#include "llvm/Intrinsics.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Target/TargetOptions.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38#include "llvm/DerivedTypes.h" 39using namespace llvm; 40 41static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 42 CCValAssign::LocInfo &LocInfo, 43 ISD::ArgFlagsTy &ArgFlags, 44 CCState &State); 45static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 46 MVT &LocVT, 47 CCValAssign::LocInfo &LocInfo, 48 ISD::ArgFlagsTy &ArgFlags, 49 CCState &State); 50static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 51 MVT &LocVT, 52 CCValAssign::LocInfo &LocInfo, 53 ISD::ArgFlagsTy &ArgFlags, 54 CCState &State); 55 56static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", 57cl::desc("enable preincrement load/store generation on PPC (experimental)"), 58 cl::Hidden); 59 60static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) { 61 if (TM.getSubtargetImpl()->isDarwin()) 62 return new TargetLoweringObjectFileMachO(); 63 64 return new TargetLoweringObjectFileELF(); 65} 66 67PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) { 69 70 setPow2DivIsCheap(); 71 72 // Use _setjmp/_longjmp instead of setjmp/longjmp. 73 setUseUnderscoreSetJmp(true); 74 setUseUnderscoreLongJmp(true); 75 76 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all 77 // arguments are at least 4/8 bytes aligned. 78 setMinStackArgumentAlignment(TM.getSubtarget<PPCSubtarget>().isPPC64() ? 8:4); 79 80 // Set up the register classes. 81 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 82 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 83 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 84 85 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 86 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 87 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 88 89 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 90 91 // PowerPC has pre-inc load and store's. 92 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 93 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 94 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 95 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 96 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 97 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 98 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 99 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 100 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 101 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 102 103 // This is used in the ppcf128->int sequence. Note it has different semantics 104 // from FP_ROUND: that rounds to nearest, this rounds to zero. 105 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 106 107 // PowerPC has no SREM/UREM instructions 108 setOperationAction(ISD::SREM, MVT::i32, Expand); 109 setOperationAction(ISD::UREM, MVT::i32, Expand); 110 setOperationAction(ISD::SREM, MVT::i64, Expand); 111 setOperationAction(ISD::UREM, MVT::i64, Expand); 112 113 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 114 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 115 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 116 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 117 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 118 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 119 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 120 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 121 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 122 123 // We don't support sin/cos/sqrt/fmod/pow 124 setOperationAction(ISD::FSIN , MVT::f64, Expand); 125 setOperationAction(ISD::FCOS , MVT::f64, Expand); 126 setOperationAction(ISD::FREM , MVT::f64, Expand); 127 setOperationAction(ISD::FPOW , MVT::f64, Expand); 128 setOperationAction(ISD::FMA , MVT::f64, Expand); 129 setOperationAction(ISD::FSIN , MVT::f32, Expand); 130 setOperationAction(ISD::FCOS , MVT::f32, Expand); 131 setOperationAction(ISD::FREM , MVT::f32, Expand); 132 setOperationAction(ISD::FPOW , MVT::f32, Expand); 133 setOperationAction(ISD::FMA , MVT::f32, Expand); 134 135 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 136 137 // If we're enabling GP optimizations, use hardware square root 138 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 139 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 140 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 141 } 142 143 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 144 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 145 146 // PowerPC does not have BSWAP, CTPOP or CTTZ 147 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 148 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 149 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 150 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 151 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 152 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 153 154 // PowerPC does not have ROTR 155 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 156 setOperationAction(ISD::ROTR, MVT::i64 , Expand); 157 158 // PowerPC does not have Select 159 setOperationAction(ISD::SELECT, MVT::i32, Expand); 160 setOperationAction(ISD::SELECT, MVT::i64, Expand); 161 setOperationAction(ISD::SELECT, MVT::f32, Expand); 162 setOperationAction(ISD::SELECT, MVT::f64, Expand); 163 164 // PowerPC wants to turn select_cc of FP into fsel when possible. 165 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 166 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 167 168 // PowerPC wants to optimize integer setcc a bit 169 setOperationAction(ISD::SETCC, MVT::i32, Custom); 170 171 // PowerPC does not have BRCOND which requires SetCC 172 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 173 174 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 175 176 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 177 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 178 179 // PowerPC does not have [U|S]INT_TO_FP 180 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 181 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 182 183 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 184 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 185 setOperationAction(ISD::BITCAST, MVT::i64, Expand); 186 setOperationAction(ISD::BITCAST, MVT::f64, Expand); 187 188 // We cannot sextinreg(i1). Expand to shifts. 189 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 190 191 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 192 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 193 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 194 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 195 196 197 // We want to legalize GlobalAddress and ConstantPool nodes into the 198 // appropriate instructions to materialize the address. 199 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 200 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 201 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 202 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 203 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 204 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 205 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 206 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 207 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 208 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 209 210 // TRAP is legal. 211 setOperationAction(ISD::TRAP, MVT::Other, Legal); 212 213 // TRAMPOLINE is custom lowered. 214 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 215 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 216 217 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 218 setOperationAction(ISD::VASTART , MVT::Other, Custom); 219 220 // VAARG is custom lowered with the 32-bit SVR4 ABI. 221 if (TM.getSubtarget<PPCSubtarget>().isSVR4ABI() 222 && !TM.getSubtarget<PPCSubtarget>().isPPC64()) { 223 setOperationAction(ISD::VAARG, MVT::Other, Custom); 224 setOperationAction(ISD::VAARG, MVT::i64, Custom); 225 } else 226 setOperationAction(ISD::VAARG, MVT::Other, Expand); 227 228 // Use the default implementation. 229 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 230 setOperationAction(ISD::VAEND , MVT::Other, Expand); 231 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 232 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 233 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 234 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 235 236 // We want to custom lower some of our intrinsics. 237 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 238 239 // Comparisons that require checking two conditions. 240 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 241 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); 242 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); 243 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); 244 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); 245 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); 246 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 247 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 248 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 249 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 250 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); 251 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); 252 253 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 254 // They also have instructions for converting between i64 and fp. 255 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 256 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 257 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 258 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 259 // This is just the low 32 bits of a (signed) fp->i64 conversion. 260 // We cannot do this with Promote because i64 is not a legal type. 261 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 262 263 // FIXME: disable this lowered code. This generates 64-bit register values, 264 // and we don't model the fact that the top part is clobbered by calls. We 265 // need to flag these together so that the value isn't live across a call. 266 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 267 } else { 268 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 269 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 270 } 271 272 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 273 // 64-bit PowerPC implementations can support i64 types directly 274 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 275 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 276 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 277 // 64-bit PowerPC wants to expand i128 shifts itself. 278 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 279 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 280 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 281 } else { 282 // 32-bit PowerPC wants to expand i64 shifts itself. 283 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 284 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 285 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 286 } 287 288 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 289 // First set operation action for all vector types to expand. Then we 290 // will selectively turn on ones that can be effectively codegen'd. 291 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 292 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 293 MVT::SimpleValueType VT = (MVT::SimpleValueType)i; 294 295 // add/sub are legal for all supported vector VT's. 296 setOperationAction(ISD::ADD , VT, Legal); 297 setOperationAction(ISD::SUB , VT, Legal); 298 299 // We promote all shuffles to v16i8. 300 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 301 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 302 303 // We promote all non-typed operations to v4i32. 304 setOperationAction(ISD::AND , VT, Promote); 305 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 306 setOperationAction(ISD::OR , VT, Promote); 307 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 308 setOperationAction(ISD::XOR , VT, Promote); 309 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 310 setOperationAction(ISD::LOAD , VT, Promote); 311 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 312 setOperationAction(ISD::SELECT, VT, Promote); 313 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 314 setOperationAction(ISD::STORE, VT, Promote); 315 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 316 317 // No other operations are legal. 318 setOperationAction(ISD::MUL , VT, Expand); 319 setOperationAction(ISD::SDIV, VT, Expand); 320 setOperationAction(ISD::SREM, VT, Expand); 321 setOperationAction(ISD::UDIV, VT, Expand); 322 setOperationAction(ISD::UREM, VT, Expand); 323 setOperationAction(ISD::FDIV, VT, Expand); 324 setOperationAction(ISD::FNEG, VT, Expand); 325 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); 326 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 327 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); 328 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 329 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 330 setOperationAction(ISD::UDIVREM, VT, Expand); 331 setOperationAction(ISD::SDIVREM, VT, Expand); 332 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); 333 setOperationAction(ISD::FPOW, VT, Expand); 334 setOperationAction(ISD::CTPOP, VT, Expand); 335 setOperationAction(ISD::CTLZ, VT, Expand); 336 setOperationAction(ISD::CTTZ, VT, Expand); 337 } 338 339 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 340 // with merges, splats, etc. 341 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 342 343 setOperationAction(ISD::AND , MVT::v4i32, Legal); 344 setOperationAction(ISD::OR , MVT::v4i32, Legal); 345 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 346 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 347 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 348 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 349 350 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 351 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 352 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 353 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 354 355 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 356 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 357 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 358 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 359 360 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 361 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 362 363 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 364 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 365 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 366 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 367 } 368 369 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 370 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 371 372 setBooleanContents(ZeroOrOneBooleanContent); 373 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 374 375 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 376 setStackPointerRegisterToSaveRestore(PPC::X1); 377 setExceptionPointerRegister(PPC::X3); 378 setExceptionSelectorRegister(PPC::X4); 379 } else { 380 setStackPointerRegisterToSaveRestore(PPC::R1); 381 setExceptionPointerRegister(PPC::R3); 382 setExceptionSelectorRegister(PPC::R4); 383 } 384 385 // We have target-specific dag combine patterns for the following nodes: 386 setTargetDAGCombine(ISD::SINT_TO_FP); 387 setTargetDAGCombine(ISD::STORE); 388 setTargetDAGCombine(ISD::BR_CC); 389 setTargetDAGCombine(ISD::BSWAP); 390 391 // Darwin long double math library functions have $LDBL128 appended. 392 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) { 393 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 394 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 395 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 396 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 397 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 398 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128"); 399 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128"); 400 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128"); 401 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128"); 402 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128"); 403 } 404 405 setMinFunctionAlignment(2); 406 if (PPCSubTarget.isDarwin()) 407 setPrefFunctionAlignment(4); 408 409 setInsertFencesForAtomic(true); 410 411 computeRegisterProperties(); 412} 413 414/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 415/// function arguments in the caller parameter area. 416unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const { 417 const TargetMachine &TM = getTargetMachine(); 418 // Darwin passes everything on 4 byte boundary. 419 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) 420 return 4; 421 // FIXME SVR4 TBD 422 return 4; 423} 424 425const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 426 switch (Opcode) { 427 default: return 0; 428 case PPCISD::FSEL: return "PPCISD::FSEL"; 429 case PPCISD::FCFID: return "PPCISD::FCFID"; 430 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 431 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 432 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 433 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 434 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 435 case PPCISD::VPERM: return "PPCISD::VPERM"; 436 case PPCISD::Hi: return "PPCISD::Hi"; 437 case PPCISD::Lo: return "PPCISD::Lo"; 438 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY"; 439 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE"; 440 case PPCISD::LOAD: return "PPCISD::LOAD"; 441 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC"; 442 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 443 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 444 case PPCISD::SRL: return "PPCISD::SRL"; 445 case PPCISD::SRA: return "PPCISD::SRA"; 446 case PPCISD::SHL: return "PPCISD::SHL"; 447 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 448 case PPCISD::STD_32: return "PPCISD::STD_32"; 449 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4"; 450 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin"; 451 case PPCISD::NOP: return "PPCISD::NOP"; 452 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 453 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin"; 454 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4"; 455 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 456 case PPCISD::MFCR: return "PPCISD::MFCR"; 457 case PPCISD::VCMP: return "PPCISD::VCMP"; 458 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 459 case PPCISD::LBRX: return "PPCISD::LBRX"; 460 case PPCISD::STBRX: return "PPCISD::STBRX"; 461 case PPCISD::LARX: return "PPCISD::LARX"; 462 case PPCISD::STCX: return "PPCISD::STCX"; 463 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 464 case PPCISD::MFFS: return "PPCISD::MFFS"; 465 case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; 466 case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; 467 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 468 case PPCISD::MTFSF: return "PPCISD::MTFSF"; 469 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; 470 } 471} 472 473EVT PPCTargetLowering::getSetCCResultType(EVT VT) const { 474 return MVT::i32; 475} 476 477//===----------------------------------------------------------------------===// 478// Node matching predicates, for use by the tblgen matching code. 479//===----------------------------------------------------------------------===// 480 481/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 482static bool isFloatingPointZero(SDValue Op) { 483 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 484 return CFP->getValueAPF().isZero(); 485 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 486 // Maybe this has already been legalized into the constant pool? 487 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 488 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 489 return CFP->getValueAPF().isZero(); 490 } 491 return false; 492} 493 494/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 495/// true if Op is undef or if it matches the specified value. 496static bool isConstantOrUndef(int Op, int Val) { 497 return Op < 0 || Op == Val; 498} 499 500/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 501/// VPKUHUM instruction. 502bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 503 if (!isUnary) { 504 for (unsigned i = 0; i != 16; ++i) 505 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1)) 506 return false; 507 } else { 508 for (unsigned i = 0; i != 8; ++i) 509 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) || 510 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1)) 511 return false; 512 } 513 return true; 514} 515 516/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 517/// VPKUWUM instruction. 518bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 519 if (!isUnary) { 520 for (unsigned i = 0; i != 16; i += 2) 521 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 522 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3)) 523 return false; 524 } else { 525 for (unsigned i = 0; i != 8; i += 2) 526 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 527 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) || 528 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) || 529 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3)) 530 return false; 531 } 532 return true; 533} 534 535/// isVMerge - Common function, used to match vmrg* shuffles. 536/// 537static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, 538 unsigned LHSStart, unsigned RHSStart) { 539 assert(N->getValueType(0) == MVT::v16i8 && 540 "PPC only supports shuffles by bytes!"); 541 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 542 "Unsupported merge size!"); 543 544 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 545 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 546 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j), 547 LHSStart+j+i*UnitSize) || 548 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j), 549 RHSStart+j+i*UnitSize)) 550 return false; 551 } 552 return true; 553} 554 555/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 556/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 557bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 558 bool isUnary) { 559 if (!isUnary) 560 return isVMerge(N, UnitSize, 8, 24); 561 return isVMerge(N, UnitSize, 8, 8); 562} 563 564/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 565/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 566bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 567 bool isUnary) { 568 if (!isUnary) 569 return isVMerge(N, UnitSize, 0, 16); 570 return isVMerge(N, UnitSize, 0, 0); 571} 572 573 574/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 575/// amount, otherwise return -1. 576int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 577 assert(N->getValueType(0) == MVT::v16i8 && 578 "PPC only supports shuffles by bytes!"); 579 580 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 581 582 // Find the first non-undef value in the shuffle mask. 583 unsigned i; 584 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i) 585 /*search*/; 586 587 if (i == 16) return -1; // all undef. 588 589 // Otherwise, check to see if the rest of the elements are consecutively 590 // numbered from this value. 591 unsigned ShiftAmt = SVOp->getMaskElt(i); 592 if (ShiftAmt < i) return -1; 593 ShiftAmt -= i; 594 595 if (!isUnary) { 596 // Check the rest of the elements to see if they are consecutive. 597 for (++i; i != 16; ++i) 598 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) 599 return -1; 600 } else { 601 // Check the rest of the elements to see if they are consecutive. 602 for (++i; i != 16; ++i) 603 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) 604 return -1; 605 } 606 return ShiftAmt; 607} 608 609/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 610/// specifies a splat of a single element that is suitable for input to 611/// VSPLTB/VSPLTH/VSPLTW. 612bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { 613 assert(N->getValueType(0) == MVT::v16i8 && 614 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 615 616 // This is a splat operation if each element of the permute is the same, and 617 // if the value doesn't reference the second vector. 618 unsigned ElementBase = N->getMaskElt(0); 619 620 // FIXME: Handle UNDEF elements too! 621 if (ElementBase >= 16) 622 return false; 623 624 // Check that the indices are consecutive, in the case of a multi-byte element 625 // splatted with a v16i8 mask. 626 for (unsigned i = 1; i != EltSize; ++i) 627 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase)) 628 return false; 629 630 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 631 if (N->getMaskElt(i) < 0) continue; 632 for (unsigned j = 0; j != EltSize; ++j) 633 if (N->getMaskElt(i+j) != N->getMaskElt(j)) 634 return false; 635 } 636 return true; 637} 638 639/// isAllNegativeZeroVector - Returns true if all elements of build_vector 640/// are -0.0. 641bool PPC::isAllNegativeZeroVector(SDNode *N) { 642 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N); 643 644 APInt APVal, APUndef; 645 unsigned BitSize; 646 bool HasAnyUndefs; 647 648 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true)) 649 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 650 return CFP->getValueAPF().isNegZero(); 651 652 return false; 653} 654 655/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 656/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 657unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 658 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 659 assert(isSplatShuffleMask(SVOp, EltSize)); 660 return SVOp->getMaskElt(0) / EltSize; 661} 662 663/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 664/// by using a vspltis[bhw] instruction of the specified element size, return 665/// the constant being splatted. The ByteSize field indicates the number of 666/// bytes of each element [124] -> [bhw]. 667SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 668 SDValue OpVal(0, 0); 669 670 // If ByteSize of the splat is bigger than the element size of the 671 // build_vector, then we have a case where we are checking for a splat where 672 // multiple elements of the buildvector are folded together into a single 673 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 674 unsigned EltSize = 16/N->getNumOperands(); 675 if (EltSize < ByteSize) { 676 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 677 SDValue UniquedVals[4]; 678 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 679 680 // See if all of the elements in the buildvector agree across. 681 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 682 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 683 // If the element isn't a constant, bail fully out. 684 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue(); 685 686 687 if (UniquedVals[i&(Multiple-1)].getNode() == 0) 688 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 689 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 690 return SDValue(); // no match. 691 } 692 693 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 694 // either constant or undef values that are identical for each chunk. See 695 // if these chunks can form into a larger vspltis*. 696 697 // Check to see if all of the leading entries are either 0 or -1. If 698 // neither, then this won't fit into the immediate field. 699 bool LeadingZero = true; 700 bool LeadingOnes = true; 701 for (unsigned i = 0; i != Multiple-1; ++i) { 702 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs. 703 704 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 705 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 706 } 707 // Finally, check the least significant entry. 708 if (LeadingZero) { 709 if (UniquedVals[Multiple-1].getNode() == 0) 710 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 711 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue(); 712 if (Val < 16) 713 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 714 } 715 if (LeadingOnes) { 716 if (UniquedVals[Multiple-1].getNode() == 0) 717 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 718 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue(); 719 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 720 return DAG.getTargetConstant(Val, MVT::i32); 721 } 722 723 return SDValue(); 724 } 725 726 // Check to see if this buildvec has a single non-undef value in its elements. 727 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 728 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 729 if (OpVal.getNode() == 0) 730 OpVal = N->getOperand(i); 731 else if (OpVal != N->getOperand(i)) 732 return SDValue(); 733 } 734 735 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def. 736 737 unsigned ValSizeInBytes = EltSize; 738 uint64_t Value = 0; 739 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 740 Value = CN->getZExtValue(); 741 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 742 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 743 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 744 } 745 746 // If the splat value is larger than the element value, then we can never do 747 // this splat. The only case that we could fit the replicated bits into our 748 // immediate field for would be zero, and we prefer to use vxor for it. 749 if (ValSizeInBytes < ByteSize) return SDValue(); 750 751 // If the element value is larger than the splat value, cut it in half and 752 // check to see if the two halves are equal. Continue doing this until we 753 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 754 while (ValSizeInBytes > ByteSize) { 755 ValSizeInBytes >>= 1; 756 757 // If the top half equals the bottom half, we're still ok. 758 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 759 (Value & ((1 << (8*ValSizeInBytes))-1))) 760 return SDValue(); 761 } 762 763 // Properly sign extend the value. 764 int ShAmt = (4-ByteSize)*8; 765 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 766 767 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 768 if (MaskVal == 0) return SDValue(); 769 770 // Finally, if this value fits in a 5 bit sext field, return it 771 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 772 return DAG.getTargetConstant(MaskVal, MVT::i32); 773 return SDValue(); 774} 775 776//===----------------------------------------------------------------------===// 777// Addressing Mode Selection 778//===----------------------------------------------------------------------===// 779 780/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 781/// or 64-bit immediate, and if the value can be accurately represented as a 782/// sign extension from a 16-bit value. If so, this returns true and the 783/// immediate. 784static bool isIntS16Immediate(SDNode *N, short &Imm) { 785 if (N->getOpcode() != ISD::Constant) 786 return false; 787 788 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 789 if (N->getValueType(0) == MVT::i32) 790 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 791 else 792 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 793} 794static bool isIntS16Immediate(SDValue Op, short &Imm) { 795 return isIntS16Immediate(Op.getNode(), Imm); 796} 797 798 799/// SelectAddressRegReg - Given the specified addressed, check to see if it 800/// can be represented as an indexed [r+r] operation. Returns false if it 801/// can be more efficiently represented with [r+imm]. 802bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, 803 SDValue &Index, 804 SelectionDAG &DAG) const { 805 short imm = 0; 806 if (N.getOpcode() == ISD::ADD) { 807 if (isIntS16Immediate(N.getOperand(1), imm)) 808 return false; // r+i 809 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 810 return false; // r+i 811 812 Base = N.getOperand(0); 813 Index = N.getOperand(1); 814 return true; 815 } else if (N.getOpcode() == ISD::OR) { 816 if (isIntS16Immediate(N.getOperand(1), imm)) 817 return false; // r+i can fold it if we can. 818 819 // If this is an or of disjoint bitfields, we can codegen this as an add 820 // (for better address arithmetic) if the LHS and RHS of the OR are provably 821 // disjoint. 822 APInt LHSKnownZero, LHSKnownOne; 823 APInt RHSKnownZero, RHSKnownOne; 824 DAG.ComputeMaskedBits(N.getOperand(0), 825 APInt::getAllOnesValue(N.getOperand(0) 826 .getValueSizeInBits()), 827 LHSKnownZero, LHSKnownOne); 828 829 if (LHSKnownZero.getBoolValue()) { 830 DAG.ComputeMaskedBits(N.getOperand(1), 831 APInt::getAllOnesValue(N.getOperand(1) 832 .getValueSizeInBits()), 833 RHSKnownZero, RHSKnownOne); 834 // If all of the bits are known zero on the LHS or RHS, the add won't 835 // carry. 836 if (~(LHSKnownZero | RHSKnownZero) == 0) { 837 Base = N.getOperand(0); 838 Index = N.getOperand(1); 839 return true; 840 } 841 } 842 } 843 844 return false; 845} 846 847/// Returns true if the address N can be represented by a base register plus 848/// a signed 16-bit displacement [r+imm], and if it is not better 849/// represented as reg+reg. 850bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, 851 SDValue &Base, 852 SelectionDAG &DAG) const { 853 // FIXME dl should come from parent load or store, not from address 854 DebugLoc dl = N.getDebugLoc(); 855 // If this can be more profitably realized as r+r, fail. 856 if (SelectAddressRegReg(N, Disp, Base, DAG)) 857 return false; 858 859 if (N.getOpcode() == ISD::ADD) { 860 short imm = 0; 861 if (isIntS16Immediate(N.getOperand(1), imm)) { 862 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 863 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 864 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 865 } else { 866 Base = N.getOperand(0); 867 } 868 return true; // [r+i] 869 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 870 // Match LOAD (ADD (X, Lo(G))). 871 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 872 && "Cannot handle constant offsets yet!"); 873 Disp = N.getOperand(1).getOperand(0); // The global address. 874 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 875 Disp.getOpcode() == ISD::TargetConstantPool || 876 Disp.getOpcode() == ISD::TargetJumpTable); 877 Base = N.getOperand(0); 878 return true; // [&g+r] 879 } 880 } else if (N.getOpcode() == ISD::OR) { 881 short imm = 0; 882 if (isIntS16Immediate(N.getOperand(1), imm)) { 883 // If this is an or of disjoint bitfields, we can codegen this as an add 884 // (for better address arithmetic) if the LHS and RHS of the OR are 885 // provably disjoint. 886 APInt LHSKnownZero, LHSKnownOne; 887 DAG.ComputeMaskedBits(N.getOperand(0), 888 APInt::getAllOnesValue(N.getOperand(0) 889 .getValueSizeInBits()), 890 LHSKnownZero, LHSKnownOne); 891 892 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 893 // If all of the bits are known zero on the LHS or RHS, the add won't 894 // carry. 895 Base = N.getOperand(0); 896 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 897 return true; 898 } 899 } 900 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 901 // Loading from a constant address. 902 903 // If this address fits entirely in a 16-bit sext immediate field, codegen 904 // this as "d, 0" 905 short Imm; 906 if (isIntS16Immediate(CN, Imm)) { 907 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 908 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 909 CN->getValueType(0)); 910 return true; 911 } 912 913 // Handle 32-bit sext immediates with LIS + addr mode. 914 if (CN->getValueType(0) == MVT::i32 || 915 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 916 int Addr = (int)CN->getZExtValue(); 917 918 // Otherwise, break this down into an LIS + disp. 919 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 920 921 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 922 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 923 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); 924 return true; 925 } 926 } 927 928 Disp = DAG.getTargetConstant(0, getPointerTy()); 929 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 930 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 931 else 932 Base = N; 933 return true; // [r+0] 934} 935 936/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 937/// represented as an indexed [r+r] operation. 938bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, 939 SDValue &Index, 940 SelectionDAG &DAG) const { 941 // Check to see if we can easily represent this as an [r+r] address. This 942 // will fail if it thinks that the address is more profitably represented as 943 // reg+imm, e.g. where imm = 0. 944 if (SelectAddressRegReg(N, Base, Index, DAG)) 945 return true; 946 947 // If the operand is an addition, always emit this as [r+r], since this is 948 // better (for code size, and execution, as the memop does the add for free) 949 // than emitting an explicit add. 950 if (N.getOpcode() == ISD::ADD) { 951 Base = N.getOperand(0); 952 Index = N.getOperand(1); 953 return true; 954 } 955 956 // Otherwise, do it the hard way, using R0 as the base register. 957 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 958 N.getValueType()); 959 Index = N; 960 return true; 961} 962 963/// SelectAddressRegImmShift - Returns true if the address N can be 964/// represented by a base register plus a signed 14-bit displacement 965/// [r+imm*4]. Suitable for use by STD and friends. 966bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, 967 SDValue &Base, 968 SelectionDAG &DAG) const { 969 // FIXME dl should come from the parent load or store, not the address 970 DebugLoc dl = N.getDebugLoc(); 971 // If this can be more profitably realized as r+r, fail. 972 if (SelectAddressRegReg(N, Disp, Base, DAG)) 973 return false; 974 975 if (N.getOpcode() == ISD::ADD) { 976 short imm = 0; 977 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 978 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 979 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 980 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 981 } else { 982 Base = N.getOperand(0); 983 } 984 return true; // [r+i] 985 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 986 // Match LOAD (ADD (X, Lo(G))). 987 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 988 && "Cannot handle constant offsets yet!"); 989 Disp = N.getOperand(1).getOperand(0); // The global address. 990 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 991 Disp.getOpcode() == ISD::TargetConstantPool || 992 Disp.getOpcode() == ISD::TargetJumpTable); 993 Base = N.getOperand(0); 994 return true; // [&g+r] 995 } 996 } else if (N.getOpcode() == ISD::OR) { 997 short imm = 0; 998 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 999 // If this is an or of disjoint bitfields, we can codegen this as an add 1000 // (for better address arithmetic) if the LHS and RHS of the OR are 1001 // provably disjoint. 1002 APInt LHSKnownZero, LHSKnownOne; 1003 DAG.ComputeMaskedBits(N.getOperand(0), 1004 APInt::getAllOnesValue(N.getOperand(0) 1005 .getValueSizeInBits()), 1006 LHSKnownZero, LHSKnownOne); 1007 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 1008 // If all of the bits are known zero on the LHS or RHS, the add won't 1009 // carry. 1010 Base = N.getOperand(0); 1011 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 1012 return true; 1013 } 1014 } 1015 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 1016 // Loading from a constant address. Verify low two bits are clear. 1017 if ((CN->getZExtValue() & 3) == 0) { 1018 // If this address fits entirely in a 14-bit sext immediate field, codegen 1019 // this as "d, 0" 1020 short Imm; 1021 if (isIntS16Immediate(CN, Imm)) { 1022 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 1023 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 1024 CN->getValueType(0)); 1025 return true; 1026 } 1027 1028 // Fold the low-part of 32-bit absolute addresses into addr mode. 1029 if (CN->getValueType(0) == MVT::i32 || 1030 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 1031 int Addr = (int)CN->getZExtValue(); 1032 1033 // Otherwise, break this down into an LIS + disp. 1034 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 1035 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 1036 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1037 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0); 1038 return true; 1039 } 1040 } 1041 } 1042 1043 Disp = DAG.getTargetConstant(0, getPointerTy()); 1044 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1045 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1046 else 1047 Base = N; 1048 return true; // [r+0] 1049} 1050 1051 1052/// getPreIndexedAddressParts - returns true by value, base pointer and 1053/// offset pointer and addressing mode by reference if the node's address 1054/// can be legally represented as pre-indexed load / store address. 1055bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1056 SDValue &Offset, 1057 ISD::MemIndexedMode &AM, 1058 SelectionDAG &DAG) const { 1059 // Disabled by default for now. 1060 if (!EnablePPCPreinc) return false; 1061 1062 SDValue Ptr; 1063 EVT VT; 1064 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1065 Ptr = LD->getBasePtr(); 1066 VT = LD->getMemoryVT(); 1067 1068 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1069 Ptr = ST->getBasePtr(); 1070 VT = ST->getMemoryVT(); 1071 } else 1072 return false; 1073 1074 // PowerPC doesn't have preinc load/store instructions for vectors. 1075 if (VT.isVector()) 1076 return false; 1077 1078 // TODO: Check reg+reg first. 1079 1080 // LDU/STU use reg+imm*4, others use reg+imm. 1081 if (VT != MVT::i64) { 1082 // reg + imm 1083 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 1084 return false; 1085 } else { 1086 // reg + imm * 4. 1087 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 1088 return false; 1089 } 1090 1091 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1092 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 1093 // sext i32 to i64 when addr mode is r+i. 1094 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 1095 LD->getExtensionType() == ISD::SEXTLOAD && 1096 isa<ConstantSDNode>(Offset)) 1097 return false; 1098 } 1099 1100 AM = ISD::PRE_INC; 1101 return true; 1102} 1103 1104//===----------------------------------------------------------------------===// 1105// LowerOperation implementation 1106//===----------------------------------------------------------------------===// 1107 1108/// GetLabelAccessInfo - Return true if we should reference labels using a 1109/// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags. 1110static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags, 1111 unsigned &LoOpFlags, const GlobalValue *GV = 0) { 1112 HiOpFlags = PPCII::MO_HA16; 1113 LoOpFlags = PPCII::MO_LO16; 1114 1115 // Don't use the pic base if not in PIC relocation model. Or if we are on a 1116 // non-darwin platform. We don't support PIC on other platforms yet. 1117 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ && 1118 TM.getSubtarget<PPCSubtarget>().isDarwin(); 1119 if (isPIC) { 1120 HiOpFlags |= PPCII::MO_PIC_FLAG; 1121 LoOpFlags |= PPCII::MO_PIC_FLAG; 1122 } 1123 1124 // If this is a reference to a global value that requires a non-lazy-ptr, make 1125 // sure that instruction lowering adds it. 1126 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) { 1127 HiOpFlags |= PPCII::MO_NLP_FLAG; 1128 LoOpFlags |= PPCII::MO_NLP_FLAG; 1129 1130 if (GV->hasHiddenVisibility()) { 1131 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; 1132 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; 1133 } 1134 } 1135 1136 return isPIC; 1137} 1138 1139static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, 1140 SelectionDAG &DAG) { 1141 EVT PtrVT = HiPart.getValueType(); 1142 SDValue Zero = DAG.getConstant(0, PtrVT); 1143 DebugLoc DL = HiPart.getDebugLoc(); 1144 1145 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero); 1146 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero); 1147 1148 // With PIC, the first instruction is actually "GR+hi(&G)". 1149 if (isPIC) 1150 Hi = DAG.getNode(ISD::ADD, DL, PtrVT, 1151 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi); 1152 1153 // Generate non-pic code that has direct accesses to the constant pool. 1154 // The address of the global is just (hi(&g)+lo(&g)). 1155 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1156} 1157 1158SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, 1159 SelectionDAG &DAG) const { 1160 EVT PtrVT = Op.getValueType(); 1161 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1162 const Constant *C = CP->getConstVal(); 1163 1164 unsigned MOHiFlag, MOLoFlag; 1165 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1166 SDValue CPIHi = 1167 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag); 1168 SDValue CPILo = 1169 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag); 1170 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG); 1171} 1172 1173SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 1174 EVT PtrVT = Op.getValueType(); 1175 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1176 1177 unsigned MOHiFlag, MOLoFlag; 1178 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1179 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag); 1180 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag); 1181 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG); 1182} 1183 1184SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, 1185 SelectionDAG &DAG) const { 1186 EVT PtrVT = Op.getValueType(); 1187 1188 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1189 1190 unsigned MOHiFlag, MOLoFlag; 1191 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1192 SDValue TgtBAHi = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOHiFlag); 1193 SDValue TgtBALo = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOLoFlag); 1194 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG); 1195} 1196 1197SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, 1198 SelectionDAG &DAG) const { 1199 EVT PtrVT = Op.getValueType(); 1200 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1201 DebugLoc DL = GSDN->getDebugLoc(); 1202 const GlobalValue *GV = GSDN->getGlobal(); 1203 1204 // 64-bit SVR4 ABI code is always position-independent. 1205 // The actual address of the GlobalValue is stored in the TOC. 1206 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1207 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset()); 1208 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA, 1209 DAG.getRegister(PPC::X2, MVT::i64)); 1210 } 1211 1212 unsigned MOHiFlag, MOLoFlag; 1213 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV); 1214 1215 SDValue GAHi = 1216 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag); 1217 SDValue GALo = 1218 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag); 1219 1220 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG); 1221 1222 // If the global reference is actually to a non-lazy-pointer, we have to do an 1223 // extra load to get the address of the global. 1224 if (MOHiFlag & PPCII::MO_NLP_FLAG) 1225 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(), 1226 false, false, false, 0); 1227 return Ptr; 1228} 1229 1230SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1231 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1232 DebugLoc dl = Op.getDebugLoc(); 1233 1234 // If we're comparing for equality to zero, expose the fact that this is 1235 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1236 // fold the new nodes. 1237 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1238 if (C->isNullValue() && CC == ISD::SETEQ) { 1239 EVT VT = Op.getOperand(0).getValueType(); 1240 SDValue Zext = Op.getOperand(0); 1241 if (VT.bitsLT(MVT::i32)) { 1242 VT = MVT::i32; 1243 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); 1244 } 1245 unsigned Log2b = Log2_32(VT.getSizeInBits()); 1246 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); 1247 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, 1248 DAG.getConstant(Log2b, MVT::i32)); 1249 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); 1250 } 1251 // Leave comparisons against 0 and -1 alone for now, since they're usually 1252 // optimized. FIXME: revisit this when we can custom lower all setcc 1253 // optimizations. 1254 if (C->isAllOnesValue() || C->isNullValue()) 1255 return SDValue(); 1256 } 1257 1258 // If we have an integer seteq/setne, turn it into a compare against zero 1259 // by xor'ing the rhs with the lhs, which is faster than setting a 1260 // condition register, reading it back out, and masking the correct bit. The 1261 // normal approach here uses sub to do this instead of xor. Using xor exposes 1262 // the result to other bit-twiddling opportunities. 1263 EVT LHSVT = Op.getOperand(0).getValueType(); 1264 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1265 EVT VT = Op.getValueType(); 1266 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), 1267 Op.getOperand(1)); 1268 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); 1269 } 1270 return SDValue(); 1271} 1272 1273SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, 1274 const PPCSubtarget &Subtarget) const { 1275 SDNode *Node = Op.getNode(); 1276 EVT VT = Node->getValueType(0); 1277 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1278 SDValue InChain = Node->getOperand(0); 1279 SDValue VAListPtr = Node->getOperand(1); 1280 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1281 DebugLoc dl = Node->getDebugLoc(); 1282 1283 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); 1284 1285 // gpr_index 1286 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, 1287 VAListPtr, MachinePointerInfo(SV), MVT::i8, 1288 false, false, 0); 1289 InChain = GprIndex.getValue(1); 1290 1291 if (VT == MVT::i64) { 1292 // Check if GprIndex is even 1293 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex, 1294 DAG.getConstant(1, MVT::i32)); 1295 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd, 1296 DAG.getConstant(0, MVT::i32), ISD::SETNE); 1297 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex, 1298 DAG.getConstant(1, MVT::i32)); 1299 // Align GprIndex to be even if it isn't 1300 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne, 1301 GprIndex); 1302 } 1303 1304 // fpr index is 1 byte after gpr 1305 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1306 DAG.getConstant(1, MVT::i32)); 1307 1308 // fpr 1309 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, 1310 FprPtr, MachinePointerInfo(SV), MVT::i8, 1311 false, false, 0); 1312 InChain = FprIndex.getValue(1); 1313 1314 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1315 DAG.getConstant(8, MVT::i32)); 1316 1317 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1318 DAG.getConstant(4, MVT::i32)); 1319 1320 // areas 1321 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, 1322 MachinePointerInfo(), false, false, 1323 false, 0); 1324 InChain = OverflowArea.getValue(1); 1325 1326 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, 1327 MachinePointerInfo(), false, false, 1328 false, 0); 1329 InChain = RegSaveArea.getValue(1); 1330 1331 // select overflow_area if index > 8 1332 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, 1333 DAG.getConstant(8, MVT::i32), ISD::SETLT); 1334 1335 // adjustment constant gpr_index * 4/8 1336 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32, 1337 VT.isInteger() ? GprIndex : FprIndex, 1338 DAG.getConstant(VT.isInteger() ? 4 : 8, 1339 MVT::i32)); 1340 1341 // OurReg = RegSaveArea + RegConstant 1342 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea, 1343 RegConstant); 1344 1345 // Floating types are 32 bytes into RegSaveArea 1346 if (VT.isFloatingPoint()) 1347 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg, 1348 DAG.getConstant(32, MVT::i32)); 1349 1350 // increase {f,g}pr_index by 1 (or 2 if VT is i64) 1351 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32, 1352 VT.isInteger() ? GprIndex : FprIndex, 1353 DAG.getConstant(VT == MVT::i64 ? 2 : 1, 1354 MVT::i32)); 1355 1356 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1, 1357 VT.isInteger() ? VAListPtr : FprPtr, 1358 MachinePointerInfo(SV), 1359 MVT::i8, false, false, 0); 1360 1361 // determine if we should load from reg_save_area or overflow_area 1362 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea); 1363 1364 // increase overflow_area by 4/8 if gpr/fpr > 8 1365 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea, 1366 DAG.getConstant(VT.isInteger() ? 4 : 8, 1367 MVT::i32)); 1368 1369 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea, 1370 OverflowAreaPlusN); 1371 1372 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, 1373 OverflowAreaPtr, 1374 MachinePointerInfo(), 1375 MVT::i32, false, false, 0); 1376 1377 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(), 1378 false, false, false, 0); 1379} 1380 1381SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 1382 SelectionDAG &DAG) const { 1383 return Op.getOperand(0); 1384} 1385 1386SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 1387 SelectionDAG &DAG) const { 1388 SDValue Chain = Op.getOperand(0); 1389 SDValue Trmp = Op.getOperand(1); // trampoline 1390 SDValue FPtr = Op.getOperand(2); // nested function 1391 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 1392 DebugLoc dl = Op.getDebugLoc(); 1393 1394 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1395 bool isPPC64 = (PtrVT == MVT::i64); 1396 Type *IntPtrTy = 1397 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType( 1398 *DAG.getContext()); 1399 1400 TargetLowering::ArgListTy Args; 1401 TargetLowering::ArgListEntry Entry; 1402 1403 Entry.Ty = IntPtrTy; 1404 Entry.Node = Trmp; Args.push_back(Entry); 1405 1406 // TrampSize == (isPPC64 ? 48 : 40); 1407 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, 1408 isPPC64 ? MVT::i64 : MVT::i32); 1409 Args.push_back(Entry); 1410 1411 Entry.Node = FPtr; Args.push_back(Entry); 1412 Entry.Node = Nest; Args.push_back(Entry); 1413 1414 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) 1415 std::pair<SDValue, SDValue> CallResult = 1416 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), 1417 false, false, false, false, 0, CallingConv::C, false, 1418 /*isReturnValueUsed=*/true, 1419 DAG.getExternalSymbol("__trampoline_setup", PtrVT), 1420 Args, DAG, dl); 1421 1422 return CallResult.second; 1423} 1424 1425SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, 1426 const PPCSubtarget &Subtarget) const { 1427 MachineFunction &MF = DAG.getMachineFunction(); 1428 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1429 1430 DebugLoc dl = Op.getDebugLoc(); 1431 1432 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) { 1433 // vastart just stores the address of the VarArgsFrameIndex slot into the 1434 // memory location argument. 1435 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1436 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1437 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1438 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 1439 MachinePointerInfo(SV), 1440 false, false, 0); 1441 } 1442 1443 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct. 1444 // We suppose the given va_list is already allocated. 1445 // 1446 // typedef struct { 1447 // char gpr; /* index into the array of 8 GPRs 1448 // * stored in the register save area 1449 // * gpr=0 corresponds to r3, 1450 // * gpr=1 to r4, etc. 1451 // */ 1452 // char fpr; /* index into the array of 8 FPRs 1453 // * stored in the register save area 1454 // * fpr=0 corresponds to f1, 1455 // * fpr=1 to f2, etc. 1456 // */ 1457 // char *overflow_arg_area; 1458 // /* location on stack that holds 1459 // * the next overflow argument 1460 // */ 1461 // char *reg_save_area; 1462 // /* where r3:r10 and f1:f8 (if saved) 1463 // * are stored 1464 // */ 1465 // } va_list[1]; 1466 1467 1468 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32); 1469 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32); 1470 1471 1472 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1473 1474 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(), 1475 PtrVT); 1476 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1477 PtrVT); 1478 1479 uint64_t FrameOffset = PtrVT.getSizeInBits()/8; 1480 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1481 1482 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; 1483 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1484 1485 uint64_t FPROffset = 1; 1486 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1487 1488 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1489 1490 // Store first byte : number of int regs 1491 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, 1492 Op.getOperand(1), 1493 MachinePointerInfo(SV), 1494 MVT::i8, false, false, 0); 1495 uint64_t nextOffset = FPROffset; 1496 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), 1497 ConstFPROffset); 1498 1499 // Store second byte : number of float regs 1500 SDValue secondStore = 1501 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, 1502 MachinePointerInfo(SV, nextOffset), MVT::i8, 1503 false, false, 0); 1504 nextOffset += StackOffset; 1505 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); 1506 1507 // Store second word : arguments given on stack 1508 SDValue thirdStore = 1509 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, 1510 MachinePointerInfo(SV, nextOffset), 1511 false, false, 0); 1512 nextOffset += FrameOffset; 1513 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset); 1514 1515 // Store third word : arguments given in registers 1516 return DAG.getStore(thirdStore, dl, FR, nextPtr, 1517 MachinePointerInfo(SV, nextOffset), 1518 false, false, 0); 1519 1520} 1521 1522#include "PPCGenCallingConv.inc" 1523 1524static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 1525 CCValAssign::LocInfo &LocInfo, 1526 ISD::ArgFlagsTy &ArgFlags, 1527 CCState &State) { 1528 return true; 1529} 1530 1531static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 1532 MVT &LocVT, 1533 CCValAssign::LocInfo &LocInfo, 1534 ISD::ArgFlagsTy &ArgFlags, 1535 CCState &State) { 1536 static const unsigned ArgRegs[] = { 1537 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1538 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1539 }; 1540 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1541 1542 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1543 1544 // Skip one register if the first unallocated register has an even register 1545 // number and there are still argument registers available which have not been 1546 // allocated yet. RegNum is actually an index into ArgRegs, which means we 1547 // need to skip a register if RegNum is odd. 1548 if (RegNum != NumArgRegs && RegNum % 2 == 1) { 1549 State.AllocateReg(ArgRegs[RegNum]); 1550 } 1551 1552 // Always return false here, as this function only makes sure that the first 1553 // unallocated register has an odd register number and does not actually 1554 // allocate a register for the current argument. 1555 return false; 1556} 1557 1558static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 1559 MVT &LocVT, 1560 CCValAssign::LocInfo &LocInfo, 1561 ISD::ArgFlagsTy &ArgFlags, 1562 CCState &State) { 1563 static const unsigned ArgRegs[] = { 1564 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1565 PPC::F8 1566 }; 1567 1568 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1569 1570 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1571 1572 // If there is only one Floating-point register left we need to put both f64 1573 // values of a split ppc_fp128 value on the stack. 1574 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { 1575 State.AllocateReg(ArgRegs[RegNum]); 1576 } 1577 1578 // Always return false here, as this function only makes sure that the two f64 1579 // values a ppc_fp128 value is split into are both passed in registers or both 1580 // passed on the stack and does not actually allocate a register for the 1581 // current argument. 1582 return false; 1583} 1584 1585/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1586/// on Darwin. 1587static const unsigned *GetFPR() { 1588 static const unsigned FPR[] = { 1589 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1590 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1591 }; 1592 1593 return FPR; 1594} 1595 1596/// CalculateStackSlotSize - Calculates the size reserved for this argument on 1597/// the stack. 1598static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, 1599 unsigned PtrByteSize) { 1600 unsigned ArgSize = ArgVT.getSizeInBits()/8; 1601 if (Flags.isByVal()) 1602 ArgSize = Flags.getByValSize(); 1603 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1604 1605 return ArgSize; 1606} 1607 1608SDValue 1609PPCTargetLowering::LowerFormalArguments(SDValue Chain, 1610 CallingConv::ID CallConv, bool isVarArg, 1611 const SmallVectorImpl<ISD::InputArg> 1612 &Ins, 1613 DebugLoc dl, SelectionDAG &DAG, 1614 SmallVectorImpl<SDValue> &InVals) 1615 const { 1616 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) { 1617 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins, 1618 dl, DAG, InVals); 1619 } else { 1620 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, 1621 dl, DAG, InVals); 1622 } 1623} 1624 1625SDValue 1626PPCTargetLowering::LowerFormalArguments_SVR4( 1627 SDValue Chain, 1628 CallingConv::ID CallConv, bool isVarArg, 1629 const SmallVectorImpl<ISD::InputArg> 1630 &Ins, 1631 DebugLoc dl, SelectionDAG &DAG, 1632 SmallVectorImpl<SDValue> &InVals) const { 1633 1634 // 32-bit SVR4 ABI Stack Frame Layout: 1635 // +-----------------------------------+ 1636 // +--> | Back chain | 1637 // | +-----------------------------------+ 1638 // | | Floating-point register save area | 1639 // | +-----------------------------------+ 1640 // | | General register save area | 1641 // | +-----------------------------------+ 1642 // | | CR save word | 1643 // | +-----------------------------------+ 1644 // | | VRSAVE save word | 1645 // | +-----------------------------------+ 1646 // | | Alignment padding | 1647 // | +-----------------------------------+ 1648 // | | Vector register save area | 1649 // | +-----------------------------------+ 1650 // | | Local variable space | 1651 // | +-----------------------------------+ 1652 // | | Parameter list area | 1653 // | +-----------------------------------+ 1654 // | | LR save word | 1655 // | +-----------------------------------+ 1656 // SP--> +--- | Back chain | 1657 // +-----------------------------------+ 1658 // 1659 // Specifications: 1660 // System V Application Binary Interface PowerPC Processor Supplement 1661 // AltiVec Technology Programming Interface Manual 1662 1663 MachineFunction &MF = DAG.getMachineFunction(); 1664 MachineFrameInfo *MFI = MF.getFrameInfo(); 1665 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1666 1667 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1668 // Potential tail calls could cause overwriting of argument stack slots. 1669 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast)); 1670 unsigned PtrByteSize = 4; 1671 1672 // Assign locations to all of the incoming arguments. 1673 SmallVector<CCValAssign, 16> ArgLocs; 1674 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1675 getTargetMachine(), ArgLocs, *DAG.getContext()); 1676 1677 // Reserve space for the linkage area on the stack. 1678 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); 1679 1680 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4); 1681 1682 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1683 CCValAssign &VA = ArgLocs[i]; 1684 1685 // Arguments stored in registers. 1686 if (VA.isRegLoc()) { 1687 TargetRegisterClass *RC; 1688 EVT ValVT = VA.getValVT(); 1689 1690 switch (ValVT.getSimpleVT().SimpleTy) { 1691 default: 1692 llvm_unreachable("ValVT not supported by formal arguments Lowering"); 1693 case MVT::i32: 1694 RC = PPC::GPRCRegisterClass; 1695 break; 1696 case MVT::f32: 1697 RC = PPC::F4RCRegisterClass; 1698 break; 1699 case MVT::f64: 1700 RC = PPC::F8RCRegisterClass; 1701 break; 1702 case MVT::v16i8: 1703 case MVT::v8i16: 1704 case MVT::v4i32: 1705 case MVT::v4f32: 1706 RC = PPC::VRRCRegisterClass; 1707 break; 1708 } 1709 1710 // Transform the arguments stored in physical registers into virtual ones. 1711 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1712 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT); 1713 1714 InVals.push_back(ArgValue); 1715 } else { 1716 // Argument stored in memory. 1717 assert(VA.isMemLoc()); 1718 1719 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; 1720 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), 1721 isImmutable); 1722 1723 // Create load nodes to retrieve arguments from the stack. 1724 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1725 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 1726 MachinePointerInfo(), 1727 false, false, false, 0)); 1728 } 1729 } 1730 1731 // Assign locations to all of the incoming aggregate by value arguments. 1732 // Aggregates passed by value are stored in the local variable space of the 1733 // caller's stack frame, right above the parameter list area. 1734 SmallVector<CCValAssign, 16> ByValArgLocs; 1735 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1736 getTargetMachine(), ByValArgLocs, *DAG.getContext()); 1737 1738 // Reserve stack space for the allocations in CCInfo. 1739 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 1740 1741 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal); 1742 1743 // Area that is at least reserved in the caller of this function. 1744 unsigned MinReservedArea = CCByValInfo.getNextStackOffset(); 1745 1746 // Set the size that is at least reserved in caller of this function. Tail 1747 // call optimized function's reserved stack space needs to be aligned so that 1748 // taking the difference between two stack areas will result in an aligned 1749 // stack. 1750 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1751 1752 MinReservedArea = 1753 std::max(MinReservedArea, 1754 PPCFrameLowering::getMinCallFrameSize(false, false)); 1755 1756 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> 1757 getStackAlignment(); 1758 unsigned AlignMask = TargetAlign-1; 1759 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 1760 1761 FI->setMinReservedArea(MinReservedArea); 1762 1763 SmallVector<SDValue, 8> MemOps; 1764 1765 // If the function takes variable number of arguments, make a frame index for 1766 // the start of the first vararg value... for expansion of llvm.va_start. 1767 if (isVarArg) { 1768 static const unsigned GPArgRegs[] = { 1769 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1770 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1771 }; 1772 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs); 1773 1774 static const unsigned FPArgRegs[] = { 1775 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1776 PPC::F8 1777 }; 1778 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs); 1779 1780 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs, 1781 NumGPArgRegs)); 1782 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs, 1783 NumFPArgRegs)); 1784 1785 // Make room for NumGPArgRegs and NumFPArgRegs. 1786 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 + 1787 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8; 1788 1789 FuncInfo->setVarArgsStackOffset( 1790 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 1791 CCInfo.getNextStackOffset(), true)); 1792 1793 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false)); 1794 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1795 1796 // The fixed integer arguments of a variadic function are stored to the 1797 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing 1798 // the result of va_next. 1799 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) { 1800 // Get an existing live-in vreg, or add a new one. 1801 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); 1802 if (!VReg) 1803 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); 1804 1805 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1806 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1807 MachinePointerInfo(), false, false, 0); 1808 MemOps.push_back(Store); 1809 // Increment the address by four for the next argument to store 1810 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 1811 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1812 } 1813 1814 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6 1815 // is set. 1816 // The double arguments are stored to the VarArgsFrameIndex 1817 // on the stack. 1818 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) { 1819 // Get an existing live-in vreg, or add a new one. 1820 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); 1821 if (!VReg) 1822 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); 1823 1824 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); 1825 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1826 MachinePointerInfo(), false, false, 0); 1827 MemOps.push_back(Store); 1828 // Increment the address by eight for the next argument to store 1829 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8, 1830 PtrVT); 1831 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1832 } 1833 } 1834 1835 if (!MemOps.empty()) 1836 Chain = DAG.getNode(ISD::TokenFactor, dl, 1837 MVT::Other, &MemOps[0], MemOps.size()); 1838 1839 return Chain; 1840} 1841 1842SDValue 1843PPCTargetLowering::LowerFormalArguments_Darwin( 1844 SDValue Chain, 1845 CallingConv::ID CallConv, bool isVarArg, 1846 const SmallVectorImpl<ISD::InputArg> 1847 &Ins, 1848 DebugLoc dl, SelectionDAG &DAG, 1849 SmallVectorImpl<SDValue> &InVals) const { 1850 // TODO: add description of PPC stack frame format, or at least some docs. 1851 // 1852 MachineFunction &MF = DAG.getMachineFunction(); 1853 MachineFrameInfo *MFI = MF.getFrameInfo(); 1854 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1855 1856 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1857 bool isPPC64 = PtrVT == MVT::i64; 1858 // Potential tail calls could cause overwriting of argument stack slots. 1859 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast)); 1860 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1861 1862 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); 1863 // Area that is at least reserved in caller of this function. 1864 unsigned MinReservedArea = ArgOffset; 1865 1866 static const unsigned GPR_32[] = { // 32-bit registers. 1867 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1868 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1869 }; 1870 static const unsigned GPR_64[] = { // 64-bit registers. 1871 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1872 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1873 }; 1874 1875 static const unsigned *FPR = GetFPR(); 1876 1877 static const unsigned VR[] = { 1878 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1879 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1880 }; 1881 1882 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 1883 const unsigned Num_FPR_Regs = 13; 1884 const unsigned Num_VR_Regs = array_lengthof( VR); 1885 1886 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1887 1888 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1889 1890 // In 32-bit non-varargs functions, the stack space for vectors is after the 1891 // stack space for non-vectors. We do not use this space unless we have 1892 // too many vectors to fit in registers, something that only occurs in 1893 // constructed examples:), but we have to walk the arglist to figure 1894 // that out...for the pathological case, compute VecArgOffset as the 1895 // start of the vector parameter area. Computing VecArgOffset is the 1896 // entire point of the following loop. 1897 unsigned VecArgOffset = ArgOffset; 1898 if (!isVarArg && !isPPC64) { 1899 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; 1900 ++ArgNo) { 1901 EVT ObjectVT = Ins[ArgNo].VT; 1902 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1903 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 1904 1905 if (Flags.isByVal()) { 1906 // ObjSize is the true size, ArgSize rounded up to multiple of regs. 1907 ObjSize = Flags.getByValSize(); 1908 unsigned ArgSize = 1909 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1910 VecArgOffset += ArgSize; 1911 continue; 1912 } 1913 1914 switch(ObjectVT.getSimpleVT().SimpleTy) { 1915 default: llvm_unreachable("Unhandled argument type!"); 1916 case MVT::i32: 1917 case MVT::f32: 1918 VecArgOffset += isPPC64 ? 8 : 4; 1919 break; 1920 case MVT::i64: // PPC64 1921 case MVT::f64: 1922 VecArgOffset += 8; 1923 break; 1924 case MVT::v4f32: 1925 case MVT::v4i32: 1926 case MVT::v8i16: 1927 case MVT::v16i8: 1928 // Nothing to do, we're only looking at Nonvector args here. 1929 break; 1930 } 1931 } 1932 } 1933 // We've found where the vector parameter area in memory is. Skip the 1934 // first 12 parameters; these don't use that memory. 1935 VecArgOffset = ((VecArgOffset+15)/16)*16; 1936 VecArgOffset += 12*16; 1937 1938 // Add DAG nodes to load the arguments or copy them out of registers. On 1939 // entry to a function on PPC, the arguments start after the linkage area, 1940 // although the first ones are often in registers. 1941 1942 SmallVector<SDValue, 8> MemOps; 1943 unsigned nAltivecParamsAtEnd = 0; 1944 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { 1945 SDValue ArgVal; 1946 bool needsLoad = false; 1947 EVT ObjectVT = Ins[ArgNo].VT; 1948 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1949 unsigned ArgSize = ObjSize; 1950 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 1951 1952 unsigned CurArgOffset = ArgOffset; 1953 1954 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 1955 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 1956 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 1957 if (isVarArg || isPPC64) { 1958 MinReservedArea = ((MinReservedArea+15)/16)*16; 1959 MinReservedArea += CalculateStackSlotSize(ObjectVT, 1960 Flags, 1961 PtrByteSize); 1962 } else nAltivecParamsAtEnd++; 1963 } else 1964 // Calculate min reserved area. 1965 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 1966 Flags, 1967 PtrByteSize); 1968 1969 // FIXME the codegen can be much improved in some cases. 1970 // We do not have to keep everything in memory. 1971 if (Flags.isByVal()) { 1972 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 1973 ObjSize = Flags.getByValSize(); 1974 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1975 // Objects of size 1 and 2 are right justified, everything else is 1976 // left justified. This means the memory address is adjusted forwards. 1977 if (ObjSize==1 || ObjSize==2) { 1978 CurArgOffset = CurArgOffset + (4 - ObjSize); 1979 } 1980 // The value of the object is its address. 1981 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true); 1982 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1983 InVals.push_back(FIN); 1984 if (ObjSize==1 || ObjSize==2) { 1985 if (GPR_idx != Num_GPR_Regs) { 1986 unsigned VReg; 1987 if (isPPC64) 1988 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 1989 else 1990 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1991 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1992 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 1993 MachinePointerInfo(), 1994 ObjSize==1 ? MVT::i8 : MVT::i16, 1995 false, false, 0); 1996 MemOps.push_back(Store); 1997 ++GPR_idx; 1998 } 1999 2000 ArgOffset += PtrByteSize; 2001 2002 continue; 2003 } 2004 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 2005 // Store whatever pieces of the object are in registers 2006 // to memory. ArgVal will be address of the beginning of 2007 // the object. 2008 if (GPR_idx != Num_GPR_Regs) { 2009 unsigned VReg; 2010 if (isPPC64) 2011 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2012 else 2013 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2014 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2015 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2016 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2017 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2018 MachinePointerInfo(), 2019 false, false, 0); 2020 MemOps.push_back(Store); 2021 ++GPR_idx; 2022 ArgOffset += PtrByteSize; 2023 } else { 2024 ArgOffset += ArgSize - (ArgOffset-CurArgOffset); 2025 break; 2026 } 2027 } 2028 continue; 2029 } 2030 2031 switch (ObjectVT.getSimpleVT().SimpleTy) { 2032 default: llvm_unreachable("Unhandled argument type!"); 2033 case MVT::i32: 2034 if (!isPPC64) { 2035 if (GPR_idx != Num_GPR_Regs) { 2036 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2037 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2038 ++GPR_idx; 2039 } else { 2040 needsLoad = true; 2041 ArgSize = PtrByteSize; 2042 } 2043 // All int arguments reserve stack space in the Darwin ABI. 2044 ArgOffset += PtrByteSize; 2045 break; 2046 } 2047 // FALLTHROUGH 2048 case MVT::i64: // PPC64 2049 if (GPR_idx != Num_GPR_Regs) { 2050 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2051 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2052 2053 if (ObjectVT == MVT::i32) { 2054 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 2055 // value to MVT::i64 and then truncate to the correct register size. 2056 if (Flags.isSExt()) 2057 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, 2058 DAG.getValueType(ObjectVT)); 2059 else if (Flags.isZExt()) 2060 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, 2061 DAG.getValueType(ObjectVT)); 2062 2063 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); 2064 } 2065 2066 ++GPR_idx; 2067 } else { 2068 needsLoad = true; 2069 ArgSize = PtrByteSize; 2070 } 2071 // All int arguments reserve stack space in the Darwin ABI. 2072 ArgOffset += 8; 2073 break; 2074 2075 case MVT::f32: 2076 case MVT::f64: 2077 // Every 4 bytes of argument space consumes one of the GPRs available for 2078 // argument passing. 2079 if (GPR_idx != Num_GPR_Regs) { 2080 ++GPR_idx; 2081 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 2082 ++GPR_idx; 2083 } 2084 if (FPR_idx != Num_FPR_Regs) { 2085 unsigned VReg; 2086 2087 if (ObjectVT == MVT::f32) 2088 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 2089 else 2090 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 2091 2092 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2093 ++FPR_idx; 2094 } else { 2095 needsLoad = true; 2096 } 2097 2098 // All FP arguments reserve stack space in the Darwin ABI. 2099 ArgOffset += isPPC64 ? 8 : ObjSize; 2100 break; 2101 case MVT::v4f32: 2102 case MVT::v4i32: 2103 case MVT::v8i16: 2104 case MVT::v16i8: 2105 // Note that vector arguments in registers don't reserve stack space, 2106 // except in varargs functions. 2107 if (VR_idx != Num_VR_Regs) { 2108 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 2109 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2110 if (isVarArg) { 2111 while ((ArgOffset % 16) != 0) { 2112 ArgOffset += PtrByteSize; 2113 if (GPR_idx != Num_GPR_Regs) 2114 GPR_idx++; 2115 } 2116 ArgOffset += 16; 2117 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 2118 } 2119 ++VR_idx; 2120 } else { 2121 if (!isVarArg && !isPPC64) { 2122 // Vectors go after all the nonvectors. 2123 CurArgOffset = VecArgOffset; 2124 VecArgOffset += 16; 2125 } else { 2126 // Vectors are aligned. 2127 ArgOffset = ((ArgOffset+15)/16)*16; 2128 CurArgOffset = ArgOffset; 2129 ArgOffset += 16; 2130 } 2131 needsLoad = true; 2132 } 2133 break; 2134 } 2135 2136 // We need to load the argument to a virtual register if we determined above 2137 // that we ran out of physical registers of the appropriate type. 2138 if (needsLoad) { 2139 int FI = MFI->CreateFixedObject(ObjSize, 2140 CurArgOffset + (ArgSize - ObjSize), 2141 isImmutable); 2142 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2143 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), 2144 false, false, false, 0); 2145 } 2146 2147 InVals.push_back(ArgVal); 2148 } 2149 2150 // Set the size that is at least reserved in caller of this function. Tail 2151 // call optimized function's reserved stack space needs to be aligned so that 2152 // taking the difference between two stack areas will result in an aligned 2153 // stack. 2154 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2155 // Add the Altivec parameters at the end, if needed. 2156 if (nAltivecParamsAtEnd) { 2157 MinReservedArea = ((MinReservedArea+15)/16)*16; 2158 MinReservedArea += 16*nAltivecParamsAtEnd; 2159 } 2160 MinReservedArea = 2161 std::max(MinReservedArea, 2162 PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); 2163 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> 2164 getStackAlignment(); 2165 unsigned AlignMask = TargetAlign-1; 2166 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 2167 FI->setMinReservedArea(MinReservedArea); 2168 2169 // If the function takes variable number of arguments, make a frame index for 2170 // the start of the first vararg value... for expansion of llvm.va_start. 2171 if (isVarArg) { 2172 int Depth = ArgOffset; 2173 2174 FuncInfo->setVarArgsFrameIndex( 2175 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2176 Depth, true)); 2177 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2178 2179 // If this function is vararg, store any remaining integer argument regs 2180 // to their spots on the stack so that they may be loaded by deferencing the 2181 // result of va_next. 2182 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2183 unsigned VReg; 2184 2185 if (isPPC64) 2186 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2187 else 2188 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2189 2190 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2191 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2192 MachinePointerInfo(), false, false, 0); 2193 MemOps.push_back(Store); 2194 // Increment the address by four for the next argument to store 2195 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2196 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2197 } 2198 } 2199 2200 if (!MemOps.empty()) 2201 Chain = DAG.getNode(ISD::TokenFactor, dl, 2202 MVT::Other, &MemOps[0], MemOps.size()); 2203 2204 return Chain; 2205} 2206 2207/// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus 2208/// linkage area for the Darwin ABI. 2209static unsigned 2210CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, 2211 bool isPPC64, 2212 bool isVarArg, 2213 unsigned CC, 2214 const SmallVectorImpl<ISD::OutputArg> 2215 &Outs, 2216 const SmallVectorImpl<SDValue> &OutVals, 2217 unsigned &nAltivecParamsAtEnd) { 2218 // Count how many bytes are to be pushed on the stack, including the linkage 2219 // area, and parameter passing area. We start with 24/48 bytes, which is 2220 // prereserved space for [SP][CR][LR][3 x unused]. 2221 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true); 2222 unsigned NumOps = Outs.size(); 2223 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2224 2225 // Add up all the space actually used. 2226 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually 2227 // they all go in registers, but we must reserve stack space for them for 2228 // possible use by the caller. In varargs or 64-bit calls, parameters are 2229 // assigned stack space in order, with padding so Altivec parameters are 2230 // 16-byte aligned. 2231 nAltivecParamsAtEnd = 0; 2232 for (unsigned i = 0; i != NumOps; ++i) { 2233 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2234 EVT ArgVT = Outs[i].VT; 2235 // Varargs Altivec parameters are padded to a 16 byte boundary. 2236 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 2237 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { 2238 if (!isVarArg && !isPPC64) { 2239 // Non-varargs Altivec parameters go after all the non-Altivec 2240 // parameters; handle those later so we know how much padding we need. 2241 nAltivecParamsAtEnd++; 2242 continue; 2243 } 2244 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. 2245 NumBytes = ((NumBytes+15)/16)*16; 2246 } 2247 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); 2248 } 2249 2250 // Allow for Altivec parameters at the end, if needed. 2251 if (nAltivecParamsAtEnd) { 2252 NumBytes = ((NumBytes+15)/16)*16; 2253 NumBytes += 16*nAltivecParamsAtEnd; 2254 } 2255 2256 // The prolog code of the callee may store up to 8 GPR argument registers to 2257 // the stack, allowing va_start to index over them in memory if its varargs. 2258 // Because we cannot tell if this is needed on the caller side, we have to 2259 // conservatively assume that it is needed. As such, make sure we have at 2260 // least enough stack space for the caller to store the 8 GPRs. 2261 NumBytes = std::max(NumBytes, 2262 PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); 2263 2264 // Tail call needs the stack to be aligned. 2265 if (CC==CallingConv::Fast && GuaranteedTailCallOpt) { 2266 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> 2267 getStackAlignment(); 2268 unsigned AlignMask = TargetAlign-1; 2269 NumBytes = (NumBytes + AlignMask) & ~AlignMask; 2270 } 2271 2272 return NumBytes; 2273} 2274 2275/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be 2276/// adjusted to accommodate the arguments for the tailcall. 2277static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, 2278 unsigned ParamSize) { 2279 2280 if (!isTailCall) return 0; 2281 2282 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>(); 2283 unsigned CallerMinReservedArea = FI->getMinReservedArea(); 2284 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize; 2285 // Remember only if the new adjustement is bigger. 2286 if (SPDiff < FI->getTailCallSPDelta()) 2287 FI->setTailCallSPDelta(SPDiff); 2288 2289 return SPDiff; 2290} 2291 2292/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2293/// for tail call optimization. Targets which want to do tail call 2294/// optimization should implement this function. 2295bool 2296PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2297 CallingConv::ID CalleeCC, 2298 bool isVarArg, 2299 const SmallVectorImpl<ISD::InputArg> &Ins, 2300 SelectionDAG& DAG) const { 2301 if (!GuaranteedTailCallOpt) 2302 return false; 2303 2304 // Variable argument functions are not supported. 2305 if (isVarArg) 2306 return false; 2307 2308 MachineFunction &MF = DAG.getMachineFunction(); 2309 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv(); 2310 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 2311 // Functions containing by val parameters are not supported. 2312 for (unsigned i = 0; i != Ins.size(); i++) { 2313 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2314 if (Flags.isByVal()) return false; 2315 } 2316 2317 // Non PIC/GOT tail calls are supported. 2318 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 2319 return true; 2320 2321 // At the moment we can only do local tail calls (in same module, hidden 2322 // or protected) if we are generating PIC. 2323 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2324 return G->getGlobal()->hasHiddenVisibility() 2325 || G->getGlobal()->hasProtectedVisibility(); 2326 } 2327 2328 return false; 2329} 2330 2331/// isCallCompatibleAddress - Return the immediate to use if the specified 2332/// 32-bit value is representable in the immediate field of a BxA instruction. 2333static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { 2334 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2335 if (!C) return 0; 2336 2337 int Addr = C->getZExtValue(); 2338 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 2339 (Addr << 6 >> 6) != Addr) 2340 return 0; // Top 6 bits have to be sext of immediate. 2341 2342 return DAG.getConstant((int)C->getZExtValue() >> 2, 2343 DAG.getTargetLoweringInfo().getPointerTy()).getNode(); 2344} 2345 2346namespace { 2347 2348struct TailCallArgumentInfo { 2349 SDValue Arg; 2350 SDValue FrameIdxOp; 2351 int FrameIdx; 2352 2353 TailCallArgumentInfo() : FrameIdx(0) {} 2354}; 2355 2356} 2357 2358/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. 2359static void 2360StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, 2361 SDValue Chain, 2362 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, 2363 SmallVector<SDValue, 8> &MemOpChains, 2364 DebugLoc dl) { 2365 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { 2366 SDValue Arg = TailCallArgs[i].Arg; 2367 SDValue FIN = TailCallArgs[i].FrameIdxOp; 2368 int FI = TailCallArgs[i].FrameIdx; 2369 // Store relative to framepointer. 2370 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN, 2371 MachinePointerInfo::getFixedStack(FI), 2372 false, false, 0)); 2373 } 2374} 2375 2376/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to 2377/// the appropriate stack slot for the tail call optimized function call. 2378static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, 2379 MachineFunction &MF, 2380 SDValue Chain, 2381 SDValue OldRetAddr, 2382 SDValue OldFP, 2383 int SPDiff, 2384 bool isPPC64, 2385 bool isDarwinABI, 2386 DebugLoc dl) { 2387 if (SPDiff) { 2388 // Calculate the new stack slot for the return address. 2389 int SlotSize = isPPC64 ? 8 : 4; 2390 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64, 2391 isDarwinABI); 2392 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, 2393 NewRetAddrLoc, true); 2394 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2395 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); 2396 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, 2397 MachinePointerInfo::getFixedStack(NewRetAddr), 2398 false, false, 0); 2399 2400 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack 2401 // slot as the FP is never overwritten. 2402 if (isDarwinABI) { 2403 int NewFPLoc = 2404 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 2405 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc, 2406 true); 2407 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); 2408 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, 2409 MachinePointerInfo::getFixedStack(NewFPIdx), 2410 false, false, 0); 2411 } 2412 } 2413 return Chain; 2414} 2415 2416/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate 2417/// the position of the argument. 2418static void 2419CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, 2420 SDValue Arg, int SPDiff, unsigned ArgOffset, 2421 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 2422 int Offset = ArgOffset + SPDiff; 2423 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; 2424 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2425 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2426 SDValue FIN = DAG.getFrameIndex(FI, VT); 2427 TailCallArgumentInfo Info; 2428 Info.Arg = Arg; 2429 Info.FrameIdxOp = FIN; 2430 Info.FrameIdx = FI; 2431 TailCallArguments.push_back(Info); 2432} 2433 2434/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address 2435/// stack slot. Returns the chain as result and the loaded frame pointers in 2436/// LROpOut/FPOpout. Used when tail calling. 2437SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 2438 int SPDiff, 2439 SDValue Chain, 2440 SDValue &LROpOut, 2441 SDValue &FPOpOut, 2442 bool isDarwinABI, 2443 DebugLoc dl) const { 2444 if (SPDiff) { 2445 // Load the LR and FP stack slot for later adjusting. 2446 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; 2447 LROpOut = getReturnAddrFrameIndex(DAG); 2448 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(), 2449 false, false, false, 0); 2450 Chain = SDValue(LROpOut.getNode(), 1); 2451 2452 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack 2453 // slot as the FP is never overwritten. 2454 if (isDarwinABI) { 2455 FPOpOut = getFramePointerFrameIndex(DAG); 2456 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(), 2457 false, false, false, 0); 2458 Chain = SDValue(FPOpOut.getNode(), 1); 2459 } 2460 } 2461 return Chain; 2462} 2463 2464/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 2465/// by "Src" to address "Dst" of size "Size". Alignment information is 2466/// specified by the specific parameter attribute. The copy will be passed as 2467/// a byval function parameter. 2468/// Sometimes what we are copying is the end of a larger object, the part that 2469/// does not fit in registers. 2470static SDValue 2471CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 2472 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 2473 DebugLoc dl) { 2474 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 2475 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 2476 false, false, MachinePointerInfo(0), 2477 MachinePointerInfo(0)); 2478} 2479 2480/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of 2481/// tail calls. 2482static void 2483LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, 2484 SDValue Arg, SDValue PtrOff, int SPDiff, 2485 unsigned ArgOffset, bool isPPC64, bool isTailCall, 2486 bool isVector, SmallVector<SDValue, 8> &MemOpChains, 2487 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments, 2488 DebugLoc dl) { 2489 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2490 if (!isTailCall) { 2491 if (isVector) { 2492 SDValue StackPtr; 2493 if (isPPC64) 2494 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2495 else 2496 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2497 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 2498 DAG.getConstant(ArgOffset, PtrVT)); 2499 } 2500 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2501 MachinePointerInfo(), false, false, 0)); 2502 // Calculate and remember argument location. 2503 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, 2504 TailCallArguments); 2505} 2506 2507static 2508void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, 2509 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, 2510 SDValue LROp, SDValue FPOp, bool isDarwinABI, 2511 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) { 2512 MachineFunction &MF = DAG.getMachineFunction(); 2513 2514 // Emit a sequence of copyto/copyfrom virtual registers for arguments that 2515 // might overwrite each other in case of tail call optimization. 2516 SmallVector<SDValue, 8> MemOpChains2; 2517 // Do not flag preceding copytoreg stuff together with the following stuff. 2518 InFlag = SDValue(); 2519 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, 2520 MemOpChains2, dl); 2521 if (!MemOpChains2.empty()) 2522 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2523 &MemOpChains2[0], MemOpChains2.size()); 2524 2525 // Store the return address to the appropriate stack slot. 2526 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, 2527 isPPC64, isDarwinABI, dl); 2528 2529 // Emit callseq_end just before tailcall node. 2530 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2531 DAG.getIntPtrConstant(0, true), InFlag); 2532 InFlag = Chain.getValue(1); 2533} 2534 2535static 2536unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, 2537 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall, 2538 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 2539 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys, 2540 const PPCSubtarget &PPCSubTarget) { 2541 2542 bool isPPC64 = PPCSubTarget.isPPC64(); 2543 bool isSVR4ABI = PPCSubTarget.isSVR4ABI(); 2544 2545 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2546 NodeTys.push_back(MVT::Other); // Returns a chain 2547 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use. 2548 2549 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin; 2550 2551 bool needIndirectCall = true; 2552 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) { 2553 // If this is an absolute destination address, use the munged value. 2554 Callee = SDValue(Dest, 0); 2555 needIndirectCall = false; 2556 } 2557 2558 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2559 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201 2560 // Use indirect calls for ALL functions calls in JIT mode, since the 2561 // far-call stubs may be outside relocation limits for a BL instruction. 2562 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) { 2563 unsigned OpFlags = 0; 2564 if (DAG.getTarget().getRelocationModel() != Reloc::Static && 2565 (PPCSubTarget.getTargetTriple().isMacOSX() && 2566 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) && 2567 (G->getGlobal()->isDeclaration() || 2568 G->getGlobal()->isWeakForLinker())) { 2569 // PC-relative references to external symbols should go through $stub, 2570 // unless we're building with the leopard linker or later, which 2571 // automatically synthesizes these stubs. 2572 OpFlags = PPCII::MO_DARWIN_STUB; 2573 } 2574 2575 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, 2576 // every direct call is) turn it into a TargetGlobalAddress / 2577 // TargetExternalSymbol node so that legalize doesn't hack it. 2578 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2579 Callee.getValueType(), 2580 0, OpFlags); 2581 needIndirectCall = false; 2582 } 2583 } 2584 2585 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2586 unsigned char OpFlags = 0; 2587 2588 if (DAG.getTarget().getRelocationModel() != Reloc::Static && 2589 (PPCSubTarget.getTargetTriple().isMacOSX() && 2590 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) { 2591 // PC-relative references to external symbols should go through $stub, 2592 // unless we're building with the leopard linker or later, which 2593 // automatically synthesizes these stubs. 2594 OpFlags = PPCII::MO_DARWIN_STUB; 2595 } 2596 2597 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(), 2598 OpFlags); 2599 needIndirectCall = false; 2600 } 2601 2602 if (needIndirectCall) { 2603 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 2604 // to do the call, we can't use PPCISD::CALL. 2605 SDValue MTCTROps[] = {Chain, Callee, InFlag}; 2606 2607 if (isSVR4ABI && isPPC64) { 2608 // Function pointers in the 64-bit SVR4 ABI do not point to the function 2609 // entry point, but to the function descriptor (the function entry point 2610 // address is part of the function descriptor though). 2611 // The function descriptor is a three doubleword structure with the 2612 // following fields: function entry point, TOC base address and 2613 // environment pointer. 2614 // Thus for a call through a function pointer, the following actions need 2615 // to be performed: 2616 // 1. Save the TOC of the caller in the TOC save area of its stack 2617 // frame (this is done in LowerCall_Darwin()). 2618 // 2. Load the address of the function entry point from the function 2619 // descriptor. 2620 // 3. Load the TOC of the callee from the function descriptor into r2. 2621 // 4. Load the environment pointer from the function descriptor into 2622 // r11. 2623 // 5. Branch to the function entry point address. 2624 // 6. On return of the callee, the TOC of the caller needs to be 2625 // restored (this is done in FinishCall()). 2626 // 2627 // All those operations are flagged together to ensure that no other 2628 // operations can be scheduled in between. E.g. without flagging the 2629 // operations together, a TOC access in the caller could be scheduled 2630 // between the load of the callee TOC and the branch to the callee, which 2631 // results in the TOC access going through the TOC of the callee instead 2632 // of going through the TOC of the caller, which leads to incorrect code. 2633 2634 // Load the address of the function entry point from the function 2635 // descriptor. 2636 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue); 2637 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps, 2638 InFlag.getNode() ? 3 : 2); 2639 Chain = LoadFuncPtr.getValue(1); 2640 InFlag = LoadFuncPtr.getValue(2); 2641 2642 // Load environment pointer into r11. 2643 // Offset of the environment pointer within the function descriptor. 2644 SDValue PtrOff = DAG.getIntPtrConstant(16); 2645 2646 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff); 2647 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr, 2648 InFlag); 2649 Chain = LoadEnvPtr.getValue(1); 2650 InFlag = LoadEnvPtr.getValue(2); 2651 2652 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr, 2653 InFlag); 2654 Chain = EnvVal.getValue(0); 2655 InFlag = EnvVal.getValue(1); 2656 2657 // Load TOC of the callee into r2. We are using a target-specific load 2658 // with r2 hard coded, because the result of a target-independent load 2659 // would never go directly into r2, since r2 is a reserved register (which 2660 // prevents the register allocator from allocating it), resulting in an 2661 // additional register being allocated and an unnecessary move instruction 2662 // being generated. 2663 VTs = DAG.getVTList(MVT::Other, MVT::Glue); 2664 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, 2665 Callee, InFlag); 2666 Chain = LoadTOCPtr.getValue(0); 2667 InFlag = LoadTOCPtr.getValue(1); 2668 2669 MTCTROps[0] = Chain; 2670 MTCTROps[1] = LoadFuncPtr; 2671 MTCTROps[2] = InFlag; 2672 } 2673 2674 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps, 2675 2 + (InFlag.getNode() != 0)); 2676 InFlag = Chain.getValue(1); 2677 2678 NodeTys.clear(); 2679 NodeTys.push_back(MVT::Other); 2680 NodeTys.push_back(MVT::Glue); 2681 Ops.push_back(Chain); 2682 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin; 2683 Callee.setNode(0); 2684 // Add CTR register as callee so a bctr can be emitted later. 2685 if (isTailCall) 2686 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT)); 2687 } 2688 2689 // If this is a direct call, pass the chain and the callee. 2690 if (Callee.getNode()) { 2691 Ops.push_back(Chain); 2692 Ops.push_back(Callee); 2693 } 2694 // If this is a tail call add stack pointer delta. 2695 if (isTailCall) 2696 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); 2697 2698 // Add argument registers to the end of the list so that they are known live 2699 // into the call. 2700 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2701 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2702 RegsToPass[i].second.getValueType())); 2703 2704 return CallOpc; 2705} 2706 2707SDValue 2708PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2709 CallingConv::ID CallConv, bool isVarArg, 2710 const SmallVectorImpl<ISD::InputArg> &Ins, 2711 DebugLoc dl, SelectionDAG &DAG, 2712 SmallVectorImpl<SDValue> &InVals) const { 2713 2714 SmallVector<CCValAssign, 16> RVLocs; 2715 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2716 getTargetMachine(), RVLocs, *DAG.getContext()); 2717 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC); 2718 2719 // Copy all of the result registers out of their specified physreg. 2720 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2721 CCValAssign &VA = RVLocs[i]; 2722 EVT VT = VA.getValVT(); 2723 assert(VA.isRegLoc() && "Can only return in registers!"); 2724 Chain = DAG.getCopyFromReg(Chain, dl, 2725 VA.getLocReg(), VT, InFlag).getValue(1); 2726 InVals.push_back(Chain.getValue(0)); 2727 InFlag = Chain.getValue(2); 2728 } 2729 2730 return Chain; 2731} 2732 2733SDValue 2734PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl, 2735 bool isTailCall, bool isVarArg, 2736 SelectionDAG &DAG, 2737 SmallVector<std::pair<unsigned, SDValue>, 8> 2738 &RegsToPass, 2739 SDValue InFlag, SDValue Chain, 2740 SDValue &Callee, 2741 int SPDiff, unsigned NumBytes, 2742 const SmallVectorImpl<ISD::InputArg> &Ins, 2743 SmallVectorImpl<SDValue> &InVals) const { 2744 std::vector<EVT> NodeTys; 2745 SmallVector<SDValue, 8> Ops; 2746 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff, 2747 isTailCall, RegsToPass, Ops, NodeTys, 2748 PPCSubTarget); 2749 2750 // When performing tail call optimization the callee pops its arguments off 2751 // the stack. Account for this here so these bytes can be pushed back on in 2752 // PPCRegisterInfo::eliminateCallFramePseudoInstr. 2753 int BytesCalleePops = 2754 (CallConv==CallingConv::Fast && GuaranteedTailCallOpt) ? NumBytes : 0; 2755 2756 if (InFlag.getNode()) 2757 Ops.push_back(InFlag); 2758 2759 // Emit tail call. 2760 if (isTailCall) { 2761 // If this is the first return lowered for this function, add the regs 2762 // to the liveout set for the function. 2763 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2764 SmallVector<CCValAssign, 16> RVLocs; 2765 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2766 getTargetMachine(), RVLocs, *DAG.getContext()); 2767 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC); 2768 for (unsigned i = 0; i != RVLocs.size(); ++i) 2769 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2770 } 2771 2772 assert(((Callee.getOpcode() == ISD::Register && 2773 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || 2774 Callee.getOpcode() == ISD::TargetExternalSymbol || 2775 Callee.getOpcode() == ISD::TargetGlobalAddress || 2776 isa<ConstantSDNode>(Callee)) && 2777 "Expecting an global address, external symbol, absolute value or register"); 2778 2779 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size()); 2780 } 2781 2782 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 2783 InFlag = Chain.getValue(1); 2784 2785 // Add a NOP immediately after the branch instruction when using the 64-bit 2786 // SVR4 ABI. At link time, if caller and callee are in a different module and 2787 // thus have a different TOC, the call will be replaced with a call to a stub 2788 // function which saves the current TOC, loads the TOC of the callee and 2789 // branches to the callee. The NOP will be replaced with a load instruction 2790 // which restores the TOC of the caller from the TOC save slot of the current 2791 // stack frame. If caller and callee belong to the same module (and have the 2792 // same TOC), the NOP will remain unchanged. 2793 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) { 2794 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); 2795 if (CallOpc == PPCISD::BCTRL_SVR4) { 2796 // This is a call through a function pointer. 2797 // Restore the caller TOC from the save area into R2. 2798 // See PrepareCall() for more information about calls through function 2799 // pointers in the 64-bit SVR4 ABI. 2800 // We are using a target-specific load with r2 hard coded, because the 2801 // result of a target-independent load would never go directly into r2, 2802 // since r2 is a reserved register (which prevents the register allocator 2803 // from allocating it), resulting in an additional register being 2804 // allocated and an unnecessary move instruction being generated. 2805 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag); 2806 InFlag = Chain.getValue(1); 2807 } else { 2808 // Otherwise insert NOP. 2809 InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Glue, InFlag); 2810 } 2811 } 2812 2813 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2814 DAG.getIntPtrConstant(BytesCalleePops, true), 2815 InFlag); 2816 if (!Ins.empty()) 2817 InFlag = Chain.getValue(1); 2818 2819 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2820 Ins, dl, DAG, InVals); 2821} 2822 2823SDValue 2824PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2825 CallingConv::ID CallConv, bool isVarArg, 2826 bool &isTailCall, 2827 const SmallVectorImpl<ISD::OutputArg> &Outs, 2828 const SmallVectorImpl<SDValue> &OutVals, 2829 const SmallVectorImpl<ISD::InputArg> &Ins, 2830 DebugLoc dl, SelectionDAG &DAG, 2831 SmallVectorImpl<SDValue> &InVals) const { 2832 if (isTailCall) 2833 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, 2834 Ins, DAG); 2835 2836 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) 2837 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg, 2838 isTailCall, Outs, OutVals, Ins, 2839 dl, DAG, InVals); 2840 2841 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg, 2842 isTailCall, Outs, OutVals, Ins, 2843 dl, DAG, InVals); 2844} 2845 2846SDValue 2847PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee, 2848 CallingConv::ID CallConv, bool isVarArg, 2849 bool isTailCall, 2850 const SmallVectorImpl<ISD::OutputArg> &Outs, 2851 const SmallVectorImpl<SDValue> &OutVals, 2852 const SmallVectorImpl<ISD::InputArg> &Ins, 2853 DebugLoc dl, SelectionDAG &DAG, 2854 SmallVectorImpl<SDValue> &InVals) const { 2855 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description 2856 // of the 32-bit SVR4 ABI stack frame layout. 2857 2858 assert((CallConv == CallingConv::C || 2859 CallConv == CallingConv::Fast) && "Unknown calling convention!"); 2860 2861 unsigned PtrByteSize = 4; 2862 2863 MachineFunction &MF = DAG.getMachineFunction(); 2864 2865 // Mark this function as potentially containing a function that contains a 2866 // tail call. As a consequence the frame pointer will be used for dynamicalloc 2867 // and restoring the callers stack pointer in this functions epilog. This is 2868 // done because by tail calling the called function might overwrite the value 2869 // in this function's (MF) stack pointer stack slot 0(SP). 2870 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast) 2871 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 2872 2873 // Count how many bytes are to be pushed on the stack, including the linkage 2874 // area, parameter list area and the part of the local variable space which 2875 // contains copies of aggregates which are passed by value. 2876 2877 // Assign locations to all of the outgoing arguments. 2878 SmallVector<CCValAssign, 16> ArgLocs; 2879 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2880 getTargetMachine(), ArgLocs, *DAG.getContext()); 2881 2882 // Reserve space for the linkage area on the stack. 2883 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); 2884 2885 if (isVarArg) { 2886 // Handle fixed and variable vector arguments differently. 2887 // Fixed vector arguments go into registers as long as registers are 2888 // available. Variable vector arguments always go into memory. 2889 unsigned NumArgs = Outs.size(); 2890 2891 for (unsigned i = 0; i != NumArgs; ++i) { 2892 MVT ArgVT = Outs[i].VT; 2893 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 2894 bool Result; 2895 2896 if (Outs[i].IsFixed) { 2897 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, 2898 CCInfo); 2899 } else { 2900 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, 2901 ArgFlags, CCInfo); 2902 } 2903 2904 if (Result) { 2905#ifndef NDEBUG 2906 errs() << "Call operand #" << i << " has unhandled type " 2907 << EVT(ArgVT).getEVTString() << "\n"; 2908#endif 2909 llvm_unreachable(0); 2910 } 2911 } 2912 } else { 2913 // All arguments are treated the same. 2914 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4); 2915 } 2916 2917 // Assign locations to all of the outgoing aggregate by value arguments. 2918 SmallVector<CCValAssign, 16> ByValArgLocs; 2919 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2920 getTargetMachine(), ByValArgLocs, *DAG.getContext()); 2921 2922 // Reserve stack space for the allocations in CCInfo. 2923 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 2924 2925 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal); 2926 2927 // Size of the linkage area, parameter list area and the part of the local 2928 // space variable where copies of aggregates which are passed by value are 2929 // stored. 2930 unsigned NumBytes = CCByValInfo.getNextStackOffset(); 2931 2932 // Calculate by how many bytes the stack has to be adjusted in case of tail 2933 // call optimization. 2934 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 2935 2936 // Adjust the stack pointer for the new arguments... 2937 // These operations are automatically eliminated by the prolog/epilog pass 2938 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2939 SDValue CallSeqStart = Chain; 2940 2941 // Load the return address and frame pointer so it can be moved somewhere else 2942 // later. 2943 SDValue LROp, FPOp; 2944 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false, 2945 dl); 2946 2947 // Set up a copy of the stack pointer for use loading and storing any 2948 // arguments that may not fit in the registers available for argument 2949 // passing. 2950 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2951 2952 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2953 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 2954 SmallVector<SDValue, 8> MemOpChains; 2955 2956 bool seenFloatArg = false; 2957 // Walk the register/memloc assignments, inserting copies/loads. 2958 for (unsigned i = 0, j = 0, e = ArgLocs.size(); 2959 i != e; 2960 ++i) { 2961 CCValAssign &VA = ArgLocs[i]; 2962 SDValue Arg = OutVals[i]; 2963 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2964 2965 if (Flags.isByVal()) { 2966 // Argument is an aggregate which is passed by value, thus we need to 2967 // create a copy of it in the local variable space of the current stack 2968 // frame (which is the stack frame of the caller) and pass the address of 2969 // this copy to the callee. 2970 assert((j < ByValArgLocs.size()) && "Index out of bounds!"); 2971 CCValAssign &ByValVA = ByValArgLocs[j++]; 2972 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"); 2973 2974 // Memory reserved in the local variable space of the callers stack frame. 2975 unsigned LocMemOffset = ByValVA.getLocMemOffset(); 2976 2977 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2978 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2979 2980 // Create a copy of the argument in the local area of the current 2981 // stack frame. 2982 SDValue MemcpyCall = 2983 CreateCopyOfByValArgument(Arg, PtrOff, 2984 CallSeqStart.getNode()->getOperand(0), 2985 Flags, DAG, dl); 2986 2987 // This must go outside the CALLSEQ_START..END. 2988 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 2989 CallSeqStart.getNode()->getOperand(1)); 2990 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 2991 NewCallSeqStart.getNode()); 2992 Chain = CallSeqStart = NewCallSeqStart; 2993 2994 // Pass the address of the aggregate copy on the stack either in a 2995 // physical register or in the parameter list area of the current stack 2996 // frame to the callee. 2997 Arg = PtrOff; 2998 } 2999 3000 if (VA.isRegLoc()) { 3001 seenFloatArg |= VA.getLocVT().isFloatingPoint(); 3002 // Put argument in a physical register. 3003 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3004 } else { 3005 // Put argument in the parameter list area of the current stack frame. 3006 assert(VA.isMemLoc()); 3007 unsigned LocMemOffset = VA.getLocMemOffset(); 3008 3009 if (!isTailCall) { 3010 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 3011 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 3012 3013 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 3014 MachinePointerInfo(), 3015 false, false, 0)); 3016 } else { 3017 // Calculate and remember argument location. 3018 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset, 3019 TailCallArguments); 3020 } 3021 } 3022 } 3023 3024 if (!MemOpChains.empty()) 3025 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3026 &MemOpChains[0], MemOpChains.size()); 3027 3028 // Set CR6 to true if this is a vararg call with floating args passed in 3029 // registers. 3030 if (isVarArg) { 3031 SDValue SetCR(DAG.getMachineNode(seenFloatArg ? PPC::CRSET : PPC::CRUNSET, 3032 dl, MVT::i32), 0); 3033 RegsToPass.push_back(std::make_pair(unsigned(PPC::CR1EQ), SetCR)); 3034 } 3035 3036 // Build a sequence of copy-to-reg nodes chained together with token chain 3037 // and flag operands which copy the outgoing args into the appropriate regs. 3038 SDValue InFlag; 3039 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3040 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3041 RegsToPass[i].second, InFlag); 3042 InFlag = Chain.getValue(1); 3043 } 3044 3045 if (isTailCall) 3046 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp, 3047 false, TailCallArguments); 3048 3049 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 3050 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 3051 Ins, InVals); 3052} 3053 3054SDValue 3055PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, 3056 CallingConv::ID CallConv, bool isVarArg, 3057 bool isTailCall, 3058 const SmallVectorImpl<ISD::OutputArg> &Outs, 3059 const SmallVectorImpl<SDValue> &OutVals, 3060 const SmallVectorImpl<ISD::InputArg> &Ins, 3061 DebugLoc dl, SelectionDAG &DAG, 3062 SmallVectorImpl<SDValue> &InVals) const { 3063 3064 unsigned NumOps = Outs.size(); 3065 3066 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3067 bool isPPC64 = PtrVT == MVT::i64; 3068 unsigned PtrByteSize = isPPC64 ? 8 : 4; 3069 3070 MachineFunction &MF = DAG.getMachineFunction(); 3071 3072 // Mark this function as potentially containing a function that contains a 3073 // tail call. As a consequence the frame pointer will be used for dynamicalloc 3074 // and restoring the callers stack pointer in this functions epilog. This is 3075 // done because by tail calling the called function might overwrite the value 3076 // in this function's (MF) stack pointer stack slot 0(SP). 3077 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast) 3078 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 3079 3080 unsigned nAltivecParamsAtEnd = 0; 3081 3082 // Count how many bytes are to be pushed on the stack, including the linkage 3083 // area, and parameter passing area. We start with 24/48 bytes, which is 3084 // prereserved space for [SP][CR][LR][3 x unused]. 3085 unsigned NumBytes = 3086 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv, 3087 Outs, OutVals, 3088 nAltivecParamsAtEnd); 3089 3090 // Calculate by how many bytes the stack has to be adjusted in case of tail 3091 // call optimization. 3092 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 3093 3094 // To protect arguments on the stack from being clobbered in a tail call, 3095 // force all the loads to happen before doing any other lowering. 3096 if (isTailCall) 3097 Chain = DAG.getStackArgumentTokenFactor(Chain); 3098 3099 // Adjust the stack pointer for the new arguments... 3100 // These operations are automatically eliminated by the prolog/epilog pass 3101 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 3102 SDValue CallSeqStart = Chain; 3103 3104 // Load the return address and frame pointer so it can be move somewhere else 3105 // later. 3106 SDValue LROp, FPOp; 3107 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 3108 dl); 3109 3110 // Set up a copy of the stack pointer for use loading and storing any 3111 // arguments that may not fit in the registers available for argument 3112 // passing. 3113 SDValue StackPtr; 3114 if (isPPC64) 3115 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 3116 else 3117 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 3118 3119 // Figure out which arguments are going to go in registers, and which in 3120 // memory. Also, if this is a vararg function, floating point operations 3121 // must be stored to our stack, and loaded into integer regs as well, if 3122 // any integer regs are available for argument passing. 3123 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); 3124 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 3125 3126 static const unsigned GPR_32[] = { // 32-bit registers. 3127 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 3128 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 3129 }; 3130 static const unsigned GPR_64[] = { // 64-bit registers. 3131 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 3132 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 3133 }; 3134 static const unsigned *FPR = GetFPR(); 3135 3136 static const unsigned VR[] = { 3137 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 3138 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 3139 }; 3140 const unsigned NumGPRs = array_lengthof(GPR_32); 3141 const unsigned NumFPRs = 13; 3142 const unsigned NumVRs = array_lengthof(VR); 3143 3144 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 3145 3146 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3147 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3148 3149 SmallVector<SDValue, 8> MemOpChains; 3150 for (unsigned i = 0; i != NumOps; ++i) { 3151 SDValue Arg = OutVals[i]; 3152 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3153 3154 // PtrOff will be used to store the current argument to the stack if a 3155 // register cannot be found for it. 3156 SDValue PtrOff; 3157 3158 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 3159 3160 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3161 3162 // On PPC64, promote integers to 64-bit values. 3163 if (isPPC64 && Arg.getValueType() == MVT::i32) { 3164 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 3165 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3166 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 3167 } 3168 3169 // FIXME memcpy is used way more than necessary. Correctness first. 3170 if (Flags.isByVal()) { 3171 unsigned Size = Flags.getByValSize(); 3172 if (Size==1 || Size==2) { 3173 // Very small objects are passed right-justified. 3174 // Everything else is passed left-justified. 3175 EVT VT = (Size==1) ? MVT::i8 : MVT::i16; 3176 if (GPR_idx != NumGPRs) { 3177 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, 3178 MachinePointerInfo(), VT, 3179 false, false, 0); 3180 MemOpChains.push_back(Load.getValue(1)); 3181 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3182 3183 ArgOffset += PtrByteSize; 3184 } else { 3185 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType()); 3186 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3187 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, 3188 CallSeqStart.getNode()->getOperand(0), 3189 Flags, DAG, dl); 3190 // This must go outside the CALLSEQ_START..END. 3191 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3192 CallSeqStart.getNode()->getOperand(1)); 3193 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3194 NewCallSeqStart.getNode()); 3195 Chain = CallSeqStart = NewCallSeqStart; 3196 ArgOffset += PtrByteSize; 3197 } 3198 continue; 3199 } 3200 // Copy entire object into memory. There are cases where gcc-generated 3201 // code assumes it is there, even if it could be put entirely into 3202 // registers. (This is not what the doc says.) 3203 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, 3204 CallSeqStart.getNode()->getOperand(0), 3205 Flags, DAG, dl); 3206 // This must go outside the CALLSEQ_START..END. 3207 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3208 CallSeqStart.getNode()->getOperand(1)); 3209 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode()); 3210 Chain = CallSeqStart = NewCallSeqStart; 3211 // And copy the pieces of it that fit into registers. 3212 for (unsigned j=0; j<Size; j+=PtrByteSize) { 3213 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 3214 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 3215 if (GPR_idx != NumGPRs) { 3216 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 3217 MachinePointerInfo(), 3218 false, false, false, 0); 3219 MemOpChains.push_back(Load.getValue(1)); 3220 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3221 ArgOffset += PtrByteSize; 3222 } else { 3223 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 3224 break; 3225 } 3226 } 3227 continue; 3228 } 3229 3230 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 3231 default: llvm_unreachable("Unexpected ValueType for argument!"); 3232 case MVT::i32: 3233 case MVT::i64: 3234 if (GPR_idx != NumGPRs) { 3235 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 3236 } else { 3237 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3238 isPPC64, isTailCall, false, MemOpChains, 3239 TailCallArguments, dl); 3240 } 3241 ArgOffset += PtrByteSize; 3242 break; 3243 case MVT::f32: 3244 case MVT::f64: 3245 if (FPR_idx != NumFPRs) { 3246 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 3247 3248 if (isVarArg) { 3249 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 3250 MachinePointerInfo(), false, false, 0); 3251 MemOpChains.push_back(Store); 3252 3253 // Float varargs are always shadowed in available integer registers 3254 if (GPR_idx != NumGPRs) { 3255 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 3256 MachinePointerInfo(), false, false, 3257 false, 0); 3258 MemOpChains.push_back(Load.getValue(1)); 3259 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3260 } 3261 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 3262 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3263 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 3264 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 3265 MachinePointerInfo(), 3266 false, false, false, 0); 3267 MemOpChains.push_back(Load.getValue(1)); 3268 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3269 } 3270 } else { 3271 // If we have any FPRs remaining, we may also have GPRs remaining. 3272 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 3273 // GPRs. 3274 if (GPR_idx != NumGPRs) 3275 ++GPR_idx; 3276 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 3277 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 3278 ++GPR_idx; 3279 } 3280 } else { 3281 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3282 isPPC64, isTailCall, false, MemOpChains, 3283 TailCallArguments, dl); 3284 } 3285 if (isPPC64) 3286 ArgOffset += 8; 3287 else 3288 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 3289 break; 3290 case MVT::v4f32: 3291 case MVT::v4i32: 3292 case MVT::v8i16: 3293 case MVT::v16i8: 3294 if (isVarArg) { 3295 // These go aligned on the stack, or in the corresponding R registers 3296 // when within range. The Darwin PPC ABI doc claims they also go in 3297 // V registers; in fact gcc does this only for arguments that are 3298 // prototyped, not for those that match the ... We do it for all 3299 // arguments, seems to work. 3300 while (ArgOffset % 16 !=0) { 3301 ArgOffset += PtrByteSize; 3302 if (GPR_idx != NumGPRs) 3303 GPR_idx++; 3304 } 3305 // We could elide this store in the case where the object fits 3306 // entirely in R registers. Maybe later. 3307 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 3308 DAG.getConstant(ArgOffset, PtrVT)); 3309 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 3310 MachinePointerInfo(), false, false, 0); 3311 MemOpChains.push_back(Store); 3312 if (VR_idx != NumVRs) { 3313 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, 3314 MachinePointerInfo(), 3315 false, false, false, 0); 3316 MemOpChains.push_back(Load.getValue(1)); 3317 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 3318 } 3319 ArgOffset += 16; 3320 for (unsigned i=0; i<16; i+=PtrByteSize) { 3321 if (GPR_idx == NumGPRs) 3322 break; 3323 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 3324 DAG.getConstant(i, PtrVT)); 3325 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(), 3326 false, false, false, 0); 3327 MemOpChains.push_back(Load.getValue(1)); 3328 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3329 } 3330 break; 3331 } 3332 3333 // Non-varargs Altivec params generally go in registers, but have 3334 // stack space allocated at the end. 3335 if (VR_idx != NumVRs) { 3336 // Doesn't have GPR space allocated. 3337 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 3338 } else if (nAltivecParamsAtEnd==0) { 3339 // We are emitting Altivec params in order. 3340 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3341 isPPC64, isTailCall, true, MemOpChains, 3342 TailCallArguments, dl); 3343 ArgOffset += 16; 3344 } 3345 break; 3346 } 3347 } 3348 // If all Altivec parameters fit in registers, as they usually do, 3349 // they get stack space following the non-Altivec parameters. We 3350 // don't track this here because nobody below needs it. 3351 // If there are more Altivec parameters than fit in registers emit 3352 // the stores here. 3353 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) { 3354 unsigned j = 0; 3355 // Offset is aligned; skip 1st 12 params which go in V registers. 3356 ArgOffset = ((ArgOffset+15)/16)*16; 3357 ArgOffset += 12*16; 3358 for (unsigned i = 0; i != NumOps; ++i) { 3359 SDValue Arg = OutVals[i]; 3360 EVT ArgType = Outs[i].VT; 3361 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || 3362 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { 3363 if (++j > NumVRs) { 3364 SDValue PtrOff; 3365 // We are emitting Altivec params in order. 3366 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3367 isPPC64, isTailCall, true, MemOpChains, 3368 TailCallArguments, dl); 3369 ArgOffset += 16; 3370 } 3371 } 3372 } 3373 } 3374 3375 if (!MemOpChains.empty()) 3376 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3377 &MemOpChains[0], MemOpChains.size()); 3378 3379 // Check if this is an indirect call (MTCTR/BCTRL). 3380 // See PrepareCall() for more information about calls through function 3381 // pointers in the 64-bit SVR4 ABI. 3382 if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() && 3383 !dyn_cast<GlobalAddressSDNode>(Callee) && 3384 !dyn_cast<ExternalSymbolSDNode>(Callee) && 3385 !isBLACompatibleAddress(Callee, DAG)) { 3386 // Load r2 into a virtual register and store it to the TOC save area. 3387 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); 3388 // TOC save area offset. 3389 SDValue PtrOff = DAG.getIntPtrConstant(40); 3390 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3391 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(), 3392 false, false, 0); 3393 } 3394 3395 // On Darwin, R12 must contain the address of an indirect callee. This does 3396 // not mean the MTCTR instruction must use R12; it's easier to model this as 3397 // an extra parameter, so do that. 3398 if (!isTailCall && 3399 !dyn_cast<GlobalAddressSDNode>(Callee) && 3400 !dyn_cast<ExternalSymbolSDNode>(Callee) && 3401 !isBLACompatibleAddress(Callee, DAG)) 3402 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 : 3403 PPC::R12), Callee)); 3404 3405 // Build a sequence of copy-to-reg nodes chained together with token chain 3406 // and flag operands which copy the outgoing args into the appropriate regs. 3407 SDValue InFlag; 3408 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3409 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3410 RegsToPass[i].second, InFlag); 3411 InFlag = Chain.getValue(1); 3412 } 3413 3414 if (isTailCall) 3415 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp, 3416 FPOp, true, TailCallArguments); 3417 3418 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 3419 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 3420 Ins, InVals); 3421} 3422 3423bool 3424PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3425 MachineFunction &MF, bool isVarArg, 3426 const SmallVectorImpl<ISD::OutputArg> &Outs, 3427 LLVMContext &Context) const { 3428 SmallVector<CCValAssign, 16> RVLocs; 3429 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 3430 RVLocs, Context); 3431 return CCInfo.CheckReturn(Outs, RetCC_PPC); 3432} 3433 3434SDValue 3435PPCTargetLowering::LowerReturn(SDValue Chain, 3436 CallingConv::ID CallConv, bool isVarArg, 3437 const SmallVectorImpl<ISD::OutputArg> &Outs, 3438 const SmallVectorImpl<SDValue> &OutVals, 3439 DebugLoc dl, SelectionDAG &DAG) const { 3440 3441 SmallVector<CCValAssign, 16> RVLocs; 3442 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3443 getTargetMachine(), RVLocs, *DAG.getContext()); 3444 CCInfo.AnalyzeReturn(Outs, RetCC_PPC); 3445 3446 // If this is the first return lowered for this function, add the regs to the 3447 // liveout set for the function. 3448 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 3449 for (unsigned i = 0; i != RVLocs.size(); ++i) 3450 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 3451 } 3452 3453 SDValue Flag; 3454 3455 // Copy the result values into the output registers. 3456 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3457 CCValAssign &VA = RVLocs[i]; 3458 assert(VA.isRegLoc() && "Can only return in registers!"); 3459 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 3460 OutVals[i], Flag); 3461 Flag = Chain.getValue(1); 3462 } 3463 3464 if (Flag.getNode()) 3465 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 3466 else 3467 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain); 3468} 3469 3470SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 3471 const PPCSubtarget &Subtarget) const { 3472 // When we pop the dynamic allocation we need to restore the SP link. 3473 DebugLoc dl = Op.getDebugLoc(); 3474 3475 // Get the corect type for pointers. 3476 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3477 3478 // Construct the stack pointer operand. 3479 bool isPPC64 = Subtarget.isPPC64(); 3480 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; 3481 SDValue StackPtr = DAG.getRegister(SP, PtrVT); 3482 3483 // Get the operands for the STACKRESTORE. 3484 SDValue Chain = Op.getOperand(0); 3485 SDValue SaveSP = Op.getOperand(1); 3486 3487 // Load the old link SP. 3488 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, 3489 MachinePointerInfo(), 3490 false, false, false, 0); 3491 3492 // Restore the stack pointer. 3493 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); 3494 3495 // Store the old link SP. 3496 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(), 3497 false, false, 0); 3498} 3499 3500 3501 3502SDValue 3503PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { 3504 MachineFunction &MF = DAG.getMachineFunction(); 3505 bool isPPC64 = PPCSubTarget.isPPC64(); 3506 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 3507 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3508 3509 // Get current frame pointer save index. The users of this index will be 3510 // primarily DYNALLOC instructions. 3511 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3512 int RASI = FI->getReturnAddrSaveIndex(); 3513 3514 // If the frame pointer save index hasn't been defined yet. 3515 if (!RASI) { 3516 // Find out what the fix offset of the frame pointer save area. 3517 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 3518 // Allocate the frame index for frame pointer save area. 3519 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true); 3520 // Save the result. 3521 FI->setReturnAddrSaveIndex(RASI); 3522 } 3523 return DAG.getFrameIndex(RASI, PtrVT); 3524} 3525 3526SDValue 3527PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { 3528 MachineFunction &MF = DAG.getMachineFunction(); 3529 bool isPPC64 = PPCSubTarget.isPPC64(); 3530 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 3531 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3532 3533 // Get current frame pointer save index. The users of this index will be 3534 // primarily DYNALLOC instructions. 3535 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3536 int FPSI = FI->getFramePointerSaveIndex(); 3537 3538 // If the frame pointer save index hasn't been defined yet. 3539 if (!FPSI) { 3540 // Find out what the fix offset of the frame pointer save area. 3541 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, 3542 isDarwinABI); 3543 3544 // Allocate the frame index for frame pointer save area. 3545 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 3546 // Save the result. 3547 FI->setFramePointerSaveIndex(FPSI); 3548 } 3549 return DAG.getFrameIndex(FPSI, PtrVT); 3550} 3551 3552SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 3553 SelectionDAG &DAG, 3554 const PPCSubtarget &Subtarget) const { 3555 // Get the inputs. 3556 SDValue Chain = Op.getOperand(0); 3557 SDValue Size = Op.getOperand(1); 3558 DebugLoc dl = Op.getDebugLoc(); 3559 3560 // Get the corect type for pointers. 3561 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3562 // Negate the size. 3563 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, 3564 DAG.getConstant(0, PtrVT), Size); 3565 // Construct a node for the frame pointer save index. 3566 SDValue FPSIdx = getFramePointerFrameIndex(DAG); 3567 // Build a DYNALLOC node. 3568 SDValue Ops[3] = { Chain, NegSize, FPSIdx }; 3569 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 3570 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3); 3571} 3572 3573/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 3574/// possible. 3575SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 3576 // Not FP? Not a fsel. 3577 if (!Op.getOperand(0).getValueType().isFloatingPoint() || 3578 !Op.getOperand(2).getValueType().isFloatingPoint()) 3579 return Op; 3580 3581 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 3582 3583 // Cannot handle SETEQ/SETNE. 3584 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op; 3585 3586 EVT ResVT = Op.getValueType(); 3587 EVT CmpVT = Op.getOperand(0).getValueType(); 3588 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3589 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); 3590 DebugLoc dl = Op.getDebugLoc(); 3591 3592 // If the RHS of the comparison is a 0.0, we don't need to do the 3593 // subtraction at all. 3594 if (isFloatingPointZero(RHS)) 3595 switch (CC) { 3596 default: break; // SETUO etc aren't handled by fsel. 3597 case ISD::SETULT: 3598 case ISD::SETLT: 3599 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 3600 case ISD::SETOGE: 3601 case ISD::SETGE: 3602 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 3603 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 3604 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); 3605 case ISD::SETUGT: 3606 case ISD::SETGT: 3607 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 3608 case ISD::SETOLE: 3609 case ISD::SETLE: 3610 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 3611 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 3612 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 3613 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); 3614 } 3615 3616 SDValue Cmp; 3617 switch (CC) { 3618 default: break; // SETUO etc aren't handled by fsel. 3619 case ISD::SETULT: 3620 case ISD::SETLT: 3621 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 3622 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3623 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3624 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 3625 case ISD::SETOGE: 3626 case ISD::SETGE: 3627 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 3628 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3629 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3630 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 3631 case ISD::SETUGT: 3632 case ISD::SETGT: 3633 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 3634 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3635 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3636 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 3637 case ISD::SETOLE: 3638 case ISD::SETLE: 3639 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 3640 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3641 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3642 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 3643 } 3644 return Op; 3645} 3646 3647// FIXME: Split this code up when LegalizeDAGTypes lands. 3648SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 3649 DebugLoc dl) const { 3650 assert(Op.getOperand(0).getValueType().isFloatingPoint()); 3651 SDValue Src = Op.getOperand(0); 3652 if (Src.getValueType() == MVT::f32) 3653 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); 3654 3655 SDValue Tmp; 3656 switch (Op.getValueType().getSimpleVT().SimpleTy) { 3657 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); 3658 case MVT::i32: 3659 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : 3660 PPCISD::FCTIDZ, 3661 dl, MVT::f64, Src); 3662 break; 3663 case MVT::i64: 3664 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src); 3665 break; 3666 } 3667 3668 // Convert the FP value to an int value through memory. 3669 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); 3670 3671 // Emit a store to the stack slot. 3672 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, 3673 MachinePointerInfo(), false, false, 0); 3674 3675 // Result is a load from the stack slot. If loading 4 bytes, make sure to 3676 // add in a bias. 3677 if (Op.getValueType() == MVT::i32) 3678 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, 3679 DAG.getConstant(4, FIPtr.getValueType())); 3680 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(), 3681 false, false, false, 0); 3682} 3683 3684SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, 3685 SelectionDAG &DAG) const { 3686 DebugLoc dl = Op.getDebugLoc(); 3687 // Don't handle ppc_fp128 here; let it be lowered to a libcall. 3688 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) 3689 return SDValue(); 3690 3691 if (Op.getOperand(0).getValueType() == MVT::i64) { 3692 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0)); 3693 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); 3694 if (Op.getValueType() == MVT::f32) 3695 FP = DAG.getNode(ISD::FP_ROUND, dl, 3696 MVT::f32, FP, DAG.getIntPtrConstant(0)); 3697 return FP; 3698 } 3699 3700 assert(Op.getOperand(0).getValueType() == MVT::i32 && 3701 "Unhandled SINT_TO_FP type in custom expander!"); 3702 // Since we only generate this in 64-bit mode, we can take advantage of 3703 // 64-bit registers. In particular, sign extend the input value into the 3704 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 3705 // then lfd it and fcfid it. 3706 MachineFunction &MF = DAG.getMachineFunction(); 3707 MachineFrameInfo *FrameInfo = MF.getFrameInfo(); 3708 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false); 3709 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3710 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 3711 3712 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32, 3713 Op.getOperand(0)); 3714 3715 // STD the extended value into the stack slot. 3716 MachineMemOperand *MMO = 3717 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 3718 MachineMemOperand::MOStore, 8, 8); 3719 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx }; 3720 SDValue Store = 3721 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other), 3722 Ops, 4, MVT::i64, MMO); 3723 // Load the value as a double. 3724 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(), 3725 false, false, false, 0); 3726 3727 // FCFID it and return it. 3728 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); 3729 if (Op.getValueType() == MVT::f32) 3730 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); 3731 return FP; 3732} 3733 3734SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 3735 SelectionDAG &DAG) const { 3736 DebugLoc dl = Op.getDebugLoc(); 3737 /* 3738 The rounding mode is in bits 30:31 of FPSR, and has the following 3739 settings: 3740 00 Round to nearest 3741 01 Round to 0 3742 10 Round to +inf 3743 11 Round to -inf 3744 3745 FLT_ROUNDS, on the other hand, expects the following: 3746 -1 Undefined 3747 0 Round to 0 3748 1 Round to nearest 3749 2 Round to +inf 3750 3 Round to -inf 3751 3752 To perform the conversion, we do: 3753 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 3754 */ 3755 3756 MachineFunction &MF = DAG.getMachineFunction(); 3757 EVT VT = Op.getValueType(); 3758 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3759 std::vector<EVT> NodeTys; 3760 SDValue MFFSreg, InFlag; 3761 3762 // Save FP Control Word to register 3763 NodeTys.push_back(MVT::f64); // return register 3764 NodeTys.push_back(MVT::Glue); // unused in this context 3765 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 3766 3767 // Save FP register to stack slot 3768 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 3769 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 3770 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, 3771 StackSlot, MachinePointerInfo(), false, false,0); 3772 3773 // Load FP Control Word from low 32 bits of stack slot. 3774 SDValue Four = DAG.getConstant(4, PtrVT); 3775 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); 3776 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(), 3777 false, false, false, 0); 3778 3779 // Transform as necessary 3780 SDValue CWD1 = 3781 DAG.getNode(ISD::AND, dl, MVT::i32, 3782 CWD, DAG.getConstant(3, MVT::i32)); 3783 SDValue CWD2 = 3784 DAG.getNode(ISD::SRL, dl, MVT::i32, 3785 DAG.getNode(ISD::AND, dl, MVT::i32, 3786 DAG.getNode(ISD::XOR, dl, MVT::i32, 3787 CWD, DAG.getConstant(3, MVT::i32)), 3788 DAG.getConstant(3, MVT::i32)), 3789 DAG.getConstant(1, MVT::i32)); 3790 3791 SDValue RetVal = 3792 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); 3793 3794 return DAG.getNode((VT.getSizeInBits() < 16 ? 3795 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 3796} 3797 3798SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const { 3799 EVT VT = Op.getValueType(); 3800 unsigned BitWidth = VT.getSizeInBits(); 3801 DebugLoc dl = Op.getDebugLoc(); 3802 assert(Op.getNumOperands() == 3 && 3803 VT == Op.getOperand(1).getValueType() && 3804 "Unexpected SHL!"); 3805 3806 // Expand into a bunch of logical ops. Note that these ops 3807 // depend on the PPC behavior for oversized shift amounts. 3808 SDValue Lo = Op.getOperand(0); 3809 SDValue Hi = Op.getOperand(1); 3810 SDValue Amt = Op.getOperand(2); 3811 EVT AmtVT = Amt.getValueType(); 3812 3813 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3814 DAG.getConstant(BitWidth, AmtVT), Amt); 3815 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); 3816 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); 3817 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); 3818 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3819 DAG.getConstant(-BitWidth, AmtVT)); 3820 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); 3821 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 3822 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); 3823 SDValue OutOps[] = { OutLo, OutHi }; 3824 return DAG.getMergeValues(OutOps, 2, dl); 3825} 3826 3827SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const { 3828 EVT VT = Op.getValueType(); 3829 DebugLoc dl = Op.getDebugLoc(); 3830 unsigned BitWidth = VT.getSizeInBits(); 3831 assert(Op.getNumOperands() == 3 && 3832 VT == Op.getOperand(1).getValueType() && 3833 "Unexpected SRL!"); 3834 3835 // Expand into a bunch of logical ops. Note that these ops 3836 // depend on the PPC behavior for oversized shift amounts. 3837 SDValue Lo = Op.getOperand(0); 3838 SDValue Hi = Op.getOperand(1); 3839 SDValue Amt = Op.getOperand(2); 3840 EVT AmtVT = Amt.getValueType(); 3841 3842 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3843 DAG.getConstant(BitWidth, AmtVT), Amt); 3844 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3845 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 3846 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 3847 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3848 DAG.getConstant(-BitWidth, AmtVT)); 3849 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); 3850 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 3851 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); 3852 SDValue OutOps[] = { OutLo, OutHi }; 3853 return DAG.getMergeValues(OutOps, 2, dl); 3854} 3855 3856SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const { 3857 DebugLoc dl = Op.getDebugLoc(); 3858 EVT VT = Op.getValueType(); 3859 unsigned BitWidth = VT.getSizeInBits(); 3860 assert(Op.getNumOperands() == 3 && 3861 VT == Op.getOperand(1).getValueType() && 3862 "Unexpected SRA!"); 3863 3864 // Expand into a bunch of logical ops, followed by a select_cc. 3865 SDValue Lo = Op.getOperand(0); 3866 SDValue Hi = Op.getOperand(1); 3867 SDValue Amt = Op.getOperand(2); 3868 EVT AmtVT = Amt.getValueType(); 3869 3870 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3871 DAG.getConstant(BitWidth, AmtVT), Amt); 3872 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3873 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 3874 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 3875 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3876 DAG.getConstant(-BitWidth, AmtVT)); 3877 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); 3878 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); 3879 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), 3880 Tmp4, Tmp6, ISD::SETLE); 3881 SDValue OutOps[] = { OutLo, OutHi }; 3882 return DAG.getMergeValues(OutOps, 2, dl); 3883} 3884 3885//===----------------------------------------------------------------------===// 3886// Vector related lowering. 3887// 3888 3889/// BuildSplatI - Build a canonical splati of Val with an element size of 3890/// SplatSize. Cast the result to VT. 3891static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT, 3892 SelectionDAG &DAG, DebugLoc dl) { 3893 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 3894 3895 static const EVT VTys[] = { // canonical VT to use for each size. 3896 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 3897 }; 3898 3899 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 3900 3901 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 3902 if (Val == -1) 3903 SplatSize = 1; 3904 3905 EVT CanonicalVT = VTys[SplatSize-1]; 3906 3907 // Build a canonical splat for this value. 3908 SDValue Elt = DAG.getConstant(Val, MVT::i32); 3909 SmallVector<SDValue, 8> Ops; 3910 Ops.assign(CanonicalVT.getVectorNumElements(), Elt); 3911 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, 3912 &Ops[0], Ops.size()); 3913 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res); 3914} 3915 3916/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 3917/// specified intrinsic ID. 3918static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, 3919 SelectionDAG &DAG, DebugLoc dl, 3920 EVT DestVT = MVT::Other) { 3921 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 3922 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 3923 DAG.getConstant(IID, MVT::i32), LHS, RHS); 3924} 3925 3926/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 3927/// specified intrinsic ID. 3928static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, 3929 SDValue Op2, SelectionDAG &DAG, 3930 DebugLoc dl, EVT DestVT = MVT::Other) { 3931 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 3932 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 3933 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 3934} 3935 3936 3937/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 3938/// amount. The result has the specified value type. 3939static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, 3940 EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3941 // Force LHS/RHS to be the right type. 3942 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS); 3943 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS); 3944 3945 int Ops[16]; 3946 for (unsigned i = 0; i != 16; ++i) 3947 Ops[i] = i + Amt; 3948 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); 3949 return DAG.getNode(ISD::BITCAST, dl, VT, T); 3950} 3951 3952// If this is a case we can't handle, return null and let the default 3953// expansion code take care of it. If we CAN select this case, and if it 3954// selects to a single instruction, return Op. Otherwise, if we can codegen 3955// this case more efficiently than a constant pool load, lower it to the 3956// sequence of ops that should be used. 3957SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, 3958 SelectionDAG &DAG) const { 3959 DebugLoc dl = Op.getDebugLoc(); 3960 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 3961 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR"); 3962 3963 // Check if this is a splat of a constant value. 3964 APInt APSplatBits, APSplatUndef; 3965 unsigned SplatBitSize; 3966 bool HasAnyUndefs; 3967 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize, 3968 HasAnyUndefs, 0, true) || SplatBitSize > 32) 3969 return SDValue(); 3970 3971 unsigned SplatBits = APSplatBits.getZExtValue(); 3972 unsigned SplatUndef = APSplatUndef.getZExtValue(); 3973 unsigned SplatSize = SplatBitSize / 8; 3974 3975 // First, handle single instruction cases. 3976 3977 // All zeros? 3978 if (SplatBits == 0) { 3979 // Canonicalize all zero vectors to be v4i32. 3980 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 3981 SDValue Z = DAG.getConstant(0, MVT::i32); 3982 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); 3983 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z); 3984 } 3985 return Op; 3986 } 3987 3988 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 3989 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >> 3990 (32-SplatBitSize)); 3991 if (SextVal >= -16 && SextVal <= 15) 3992 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl); 3993 3994 3995 // Two instruction sequences. 3996 3997 // If this value is in the range [-32,30] and is even, use: 3998 // tmp = VSPLTI[bhw], result = add tmp, tmp 3999 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 4000 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl); 4001 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res); 4002 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 4003 } 4004 4005 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 4006 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 4007 // for fneg/fabs. 4008 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 4009 // Make -1 and vspltisw -1: 4010 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); 4011 4012 // Make the VSLW intrinsic, computing 0x8000_0000. 4013 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 4014 OnesV, DAG, dl); 4015 4016 // xor by OnesV to invert it. 4017 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); 4018 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 4019 } 4020 4021 // Check to see if this is a wide variety of vsplti*, binop self cases. 4022 static const signed char SplatCsts[] = { 4023 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 4024 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 4025 }; 4026 4027 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 4028 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 4029 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 4030 int i = SplatCsts[idx]; 4031 4032 // Figure out what shift amount will be used by altivec if shifted by i in 4033 // this splat size. 4034 unsigned TypeShiftAmt = i & (SplatBitSize-1); 4035 4036 // vsplti + shl self. 4037 if (SextVal == (i << (int)TypeShiftAmt)) { 4038 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 4039 static const unsigned IIDs[] = { // Intrinsic to use for each size. 4040 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 4041 Intrinsic::ppc_altivec_vslw 4042 }; 4043 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 4044 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 4045 } 4046 4047 // vsplti + srl self. 4048 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 4049 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 4050 static const unsigned IIDs[] = { // Intrinsic to use for each size. 4051 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 4052 Intrinsic::ppc_altivec_vsrw 4053 }; 4054 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 4055 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 4056 } 4057 4058 // vsplti + sra self. 4059 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 4060 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 4061 static const unsigned IIDs[] = { // Intrinsic to use for each size. 4062 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 4063 Intrinsic::ppc_altivec_vsraw 4064 }; 4065 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 4066 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 4067 } 4068 4069 // vsplti + rol self. 4070 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 4071 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 4072 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 4073 static const unsigned IIDs[] = { // Intrinsic to use for each size. 4074 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 4075 Intrinsic::ppc_altivec_vrlw 4076 }; 4077 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 4078 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 4079 } 4080 4081 // t = vsplti c, result = vsldoi t, t, 1 4082 if (SextVal == ((i << 8) | (i < 0 ? 0xFF : 0))) { 4083 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 4084 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); 4085 } 4086 // t = vsplti c, result = vsldoi t, t, 2 4087 if (SextVal == ((i << 16) | (i < 0 ? 0xFFFF : 0))) { 4088 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 4089 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); 4090 } 4091 // t = vsplti c, result = vsldoi t, t, 3 4092 if (SextVal == ((i << 24) | (i < 0 ? 0xFFFFFF : 0))) { 4093 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 4094 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); 4095 } 4096 } 4097 4098 // Three instruction sequences. 4099 4100 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 4101 if (SextVal >= 0 && SextVal <= 31) { 4102 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl); 4103 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 4104 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS); 4105 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS); 4106 } 4107 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 4108 if (SextVal >= -31 && SextVal <= 0) { 4109 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl); 4110 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 4111 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS); 4112 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS); 4113 } 4114 4115 return SDValue(); 4116} 4117 4118/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 4119/// the specified operations to build the shuffle. 4120static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 4121 SDValue RHS, SelectionDAG &DAG, 4122 DebugLoc dl) { 4123 unsigned OpNum = (PFEntry >> 26) & 0x0F; 4124 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 4125 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 4126 4127 enum { 4128 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 4129 OP_VMRGHW, 4130 OP_VMRGLW, 4131 OP_VSPLTISW0, 4132 OP_VSPLTISW1, 4133 OP_VSPLTISW2, 4134 OP_VSPLTISW3, 4135 OP_VSLDOI4, 4136 OP_VSLDOI8, 4137 OP_VSLDOI12 4138 }; 4139 4140 if (OpNum == OP_COPY) { 4141 if (LHSID == (1*9+2)*9+3) return LHS; 4142 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 4143 return RHS; 4144 } 4145 4146 SDValue OpLHS, OpRHS; 4147 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 4148 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 4149 4150 int ShufIdxs[16]; 4151 switch (OpNum) { 4152 default: llvm_unreachable("Unknown i32 permute!"); 4153 case OP_VMRGHW: 4154 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 4155 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 4156 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 4157 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 4158 break; 4159 case OP_VMRGLW: 4160 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 4161 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 4162 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 4163 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 4164 break; 4165 case OP_VSPLTISW0: 4166 for (unsigned i = 0; i != 16; ++i) 4167 ShufIdxs[i] = (i&3)+0; 4168 break; 4169 case OP_VSPLTISW1: 4170 for (unsigned i = 0; i != 16; ++i) 4171 ShufIdxs[i] = (i&3)+4; 4172 break; 4173 case OP_VSPLTISW2: 4174 for (unsigned i = 0; i != 16; ++i) 4175 ShufIdxs[i] = (i&3)+8; 4176 break; 4177 case OP_VSPLTISW3: 4178 for (unsigned i = 0; i != 16; ++i) 4179 ShufIdxs[i] = (i&3)+12; 4180 break; 4181 case OP_VSLDOI4: 4182 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl); 4183 case OP_VSLDOI8: 4184 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl); 4185 case OP_VSLDOI12: 4186 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl); 4187 } 4188 EVT VT = OpLHS.getValueType(); 4189 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS); 4190 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS); 4191 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); 4192 return DAG.getNode(ISD::BITCAST, dl, VT, T); 4193} 4194 4195/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 4196/// is a shuffle we can handle in a single instruction, return it. Otherwise, 4197/// return the code it can be lowered into. Worst case, it can always be 4198/// lowered into a vperm. 4199SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 4200 SelectionDAG &DAG) const { 4201 DebugLoc dl = Op.getDebugLoc(); 4202 SDValue V1 = Op.getOperand(0); 4203 SDValue V2 = Op.getOperand(1); 4204 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4205 EVT VT = Op.getValueType(); 4206 4207 // Cases that are handled by instructions that take permute immediates 4208 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 4209 // selected by the instruction selector. 4210 if (V2.getOpcode() == ISD::UNDEF) { 4211 if (PPC::isSplatShuffleMask(SVOp, 1) || 4212 PPC::isSplatShuffleMask(SVOp, 2) || 4213 PPC::isSplatShuffleMask(SVOp, 4) || 4214 PPC::isVPKUWUMShuffleMask(SVOp, true) || 4215 PPC::isVPKUHUMShuffleMask(SVOp, true) || 4216 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 || 4217 PPC::isVMRGLShuffleMask(SVOp, 1, true) || 4218 PPC::isVMRGLShuffleMask(SVOp, 2, true) || 4219 PPC::isVMRGLShuffleMask(SVOp, 4, true) || 4220 PPC::isVMRGHShuffleMask(SVOp, 1, true) || 4221 PPC::isVMRGHShuffleMask(SVOp, 2, true) || 4222 PPC::isVMRGHShuffleMask(SVOp, 4, true)) { 4223 return Op; 4224 } 4225 } 4226 4227 // Altivec has a variety of "shuffle immediates" that take two vector inputs 4228 // and produce a fixed permutation. If any of these match, do not lower to 4229 // VPERM. 4230 if (PPC::isVPKUWUMShuffleMask(SVOp, false) || 4231 PPC::isVPKUHUMShuffleMask(SVOp, false) || 4232 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 || 4233 PPC::isVMRGLShuffleMask(SVOp, 1, false) || 4234 PPC::isVMRGLShuffleMask(SVOp, 2, false) || 4235 PPC::isVMRGLShuffleMask(SVOp, 4, false) || 4236 PPC::isVMRGHShuffleMask(SVOp, 1, false) || 4237 PPC::isVMRGHShuffleMask(SVOp, 2, false) || 4238 PPC::isVMRGHShuffleMask(SVOp, 4, false)) 4239 return Op; 4240 4241 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 4242 // perfect shuffle table to emit an optimal matching sequence. 4243 SmallVector<int, 16> PermMask; 4244 SVOp->getMask(PermMask); 4245 4246 unsigned PFIndexes[4]; 4247 bool isFourElementShuffle = true; 4248 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 4249 unsigned EltNo = 8; // Start out undef. 4250 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 4251 if (PermMask[i*4+j] < 0) 4252 continue; // Undef, ignore it. 4253 4254 unsigned ByteSource = PermMask[i*4+j]; 4255 if ((ByteSource & 3) != j) { 4256 isFourElementShuffle = false; 4257 break; 4258 } 4259 4260 if (EltNo == 8) { 4261 EltNo = ByteSource/4; 4262 } else if (EltNo != ByteSource/4) { 4263 isFourElementShuffle = false; 4264 break; 4265 } 4266 } 4267 PFIndexes[i] = EltNo; 4268 } 4269 4270 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 4271 // perfect shuffle vector to determine if it is cost effective to do this as 4272 // discrete instructions, or whether we should use a vperm. 4273 if (isFourElementShuffle) { 4274 // Compute the index in the perfect shuffle table. 4275 unsigned PFTableIndex = 4276 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4277 4278 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4279 unsigned Cost = (PFEntry >> 30); 4280 4281 // Determining when to avoid vperm is tricky. Many things affect the cost 4282 // of vperm, particularly how many times the perm mask needs to be computed. 4283 // For example, if the perm mask can be hoisted out of a loop or is already 4284 // used (perhaps because there are multiple permutes with the same shuffle 4285 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 4286 // the loop requires an extra register. 4287 // 4288 // As a compromise, we only emit discrete instructions if the shuffle can be 4289 // generated in 3 or fewer operations. When we have loop information 4290 // available, if this block is within a loop, we should avoid using vperm 4291 // for 3-operation perms and use a constant pool load instead. 4292 if (Cost < 3) 4293 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 4294 } 4295 4296 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 4297 // vector that will get spilled to the constant pool. 4298 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 4299 4300 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 4301 // that it is in input element units, not in bytes. Convert now. 4302 EVT EltVT = V1.getValueType().getVectorElementType(); 4303 unsigned BytesPerElement = EltVT.getSizeInBits()/8; 4304 4305 SmallVector<SDValue, 16> ResultMask; 4306 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { 4307 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i]; 4308 4309 for (unsigned j = 0; j != BytesPerElement; ++j) 4310 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 4311 MVT::i32)); 4312 } 4313 4314 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, 4315 &ResultMask[0], ResultMask.size()); 4316 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); 4317} 4318 4319/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 4320/// altivec comparison. If it is, return true and fill in Opc/isDot with 4321/// information about the intrinsic. 4322static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, 4323 bool &isDot) { 4324 unsigned IntrinsicID = 4325 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue(); 4326 CompareOpc = -1; 4327 isDot = false; 4328 switch (IntrinsicID) { 4329 default: return false; 4330 // Comparison predicates. 4331 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 4332 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 4333 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 4334 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 4335 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 4336 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 4337 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 4338 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 4339 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 4340 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 4341 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 4342 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 4343 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 4344 4345 // Normal Comparisons. 4346 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 4347 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 4348 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 4349 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 4350 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 4351 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 4352 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 4353 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 4354 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 4355 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 4356 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 4357 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 4358 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 4359 } 4360 return true; 4361} 4362 4363/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 4364/// lower, do it, otherwise return null. 4365SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 4366 SelectionDAG &DAG) const { 4367 // If this is a lowered altivec predicate compare, CompareOpc is set to the 4368 // opcode number of the comparison. 4369 DebugLoc dl = Op.getDebugLoc(); 4370 int CompareOpc; 4371 bool isDot; 4372 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 4373 return SDValue(); // Don't custom lower most intrinsics. 4374 4375 // If this is a non-dot comparison, make the VCMP node and we are done. 4376 if (!isDot) { 4377 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), 4378 Op.getOperand(1), Op.getOperand(2), 4379 DAG.getConstant(CompareOpc, MVT::i32)); 4380 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp); 4381 } 4382 4383 // Create the PPCISD altivec 'dot' comparison node. 4384 SDValue Ops[] = { 4385 Op.getOperand(2), // LHS 4386 Op.getOperand(3), // RHS 4387 DAG.getConstant(CompareOpc, MVT::i32) 4388 }; 4389 std::vector<EVT> VTs; 4390 VTs.push_back(Op.getOperand(2).getValueType()); 4391 VTs.push_back(MVT::Glue); 4392 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 4393 4394 // Now that we have the comparison, emit a copy from the CR to a GPR. 4395 // This is flagged to the above dot comparison. 4396 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32, 4397 DAG.getRegister(PPC::CR6, MVT::i32), 4398 CompNode.getValue(1)); 4399 4400 // Unpack the result based on how the target uses it. 4401 unsigned BitNo; // Bit # of CR6. 4402 bool InvertBit; // Invert result? 4403 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) { 4404 default: // Can't happen, don't crash on invalid number though. 4405 case 0: // Return the value of the EQ bit of CR6. 4406 BitNo = 0; InvertBit = false; 4407 break; 4408 case 1: // Return the inverted value of the EQ bit of CR6. 4409 BitNo = 0; InvertBit = true; 4410 break; 4411 case 2: // Return the value of the LT bit of CR6. 4412 BitNo = 2; InvertBit = false; 4413 break; 4414 case 3: // Return the inverted value of the LT bit of CR6. 4415 BitNo = 2; InvertBit = true; 4416 break; 4417 } 4418 4419 // Shift the bit into the low position. 4420 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, 4421 DAG.getConstant(8-(3-BitNo), MVT::i32)); 4422 // Isolate the bit. 4423 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, 4424 DAG.getConstant(1, MVT::i32)); 4425 4426 // If we are supposed to, toggle the bit. 4427 if (InvertBit) 4428 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, 4429 DAG.getConstant(1, MVT::i32)); 4430 return Flags; 4431} 4432 4433SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, 4434 SelectionDAG &DAG) const { 4435 DebugLoc dl = Op.getDebugLoc(); 4436 // Create a stack slot that is 16-byte aligned. 4437 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 4438 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false); 4439 EVT PtrVT = getPointerTy(); 4440 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 4441 4442 // Store the input value into Value#0 of the stack slot. 4443 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 4444 Op.getOperand(0), FIdx, MachinePointerInfo(), 4445 false, false, 0); 4446 // Load it out. 4447 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(), 4448 false, false, false, 0); 4449} 4450 4451SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 4452 DebugLoc dl = Op.getDebugLoc(); 4453 if (Op.getValueType() == MVT::v4i32) { 4454 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4455 4456 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); 4457 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. 4458 4459 SDValue RHSSwap = // = vrlw RHS, 16 4460 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); 4461 4462 // Shrinkify inputs to v8i16. 4463 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS); 4464 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS); 4465 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap); 4466 4467 // Low parts multiplied together, generating 32-bit results (we ignore the 4468 // top parts). 4469 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 4470 LHS, RHS, DAG, dl, MVT::v4i32); 4471 4472 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 4473 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); 4474 // Shift the high parts up 16 bits. 4475 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, 4476 Neg16, DAG, dl); 4477 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); 4478 } else if (Op.getValueType() == MVT::v8i16) { 4479 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4480 4481 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); 4482 4483 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 4484 LHS, RHS, Zero, DAG, dl); 4485 } else if (Op.getValueType() == MVT::v16i8) { 4486 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4487 4488 // Multiply the even 8-bit parts, producing 16-bit sums. 4489 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 4490 LHS, RHS, DAG, dl, MVT::v8i16); 4491 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts); 4492 4493 // Multiply the odd 8-bit parts, producing 16-bit sums. 4494 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 4495 LHS, RHS, DAG, dl, MVT::v8i16); 4496 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts); 4497 4498 // Merge the results together. 4499 int Ops[16]; 4500 for (unsigned i = 0; i != 8; ++i) { 4501 Ops[i*2 ] = 2*i+1; 4502 Ops[i*2+1] = 2*i+1+16; 4503 } 4504 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); 4505 } else { 4506 llvm_unreachable("Unknown mul to lower!"); 4507 } 4508} 4509 4510/// LowerOperation - Provide custom lowering hooks for some operations. 4511/// 4512SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 4513 switch (Op.getOpcode()) { 4514 default: llvm_unreachable("Wasn't expecting to be able to lower this!"); 4515 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 4516 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 4517 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 4518 case ISD::GlobalTLSAddress: llvm_unreachable("TLS not implemented for PPC"); 4519 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 4520 case ISD::SETCC: return LowerSETCC(Op, DAG); 4521 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 4522 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 4523 case ISD::VASTART: 4524 return LowerVASTART(Op, DAG, PPCSubTarget); 4525 4526 case ISD::VAARG: 4527 return LowerVAARG(Op, DAG, PPCSubTarget); 4528 4529 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 4530 case ISD::DYNAMIC_STACKALLOC: 4531 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 4532 4533 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 4534 case ISD::FP_TO_UINT: 4535 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, 4536 Op.getDebugLoc()); 4537 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 4538 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 4539 4540 // Lower 64-bit shifts. 4541 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 4542 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 4543 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 4544 4545 // Vector-related lowering. 4546 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 4547 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 4548 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 4549 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 4550 case ISD::MUL: return LowerMUL(Op, DAG); 4551 4552 // Frame & Return address. 4553 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 4554 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 4555 } 4556 return SDValue(); 4557} 4558 4559void PPCTargetLowering::ReplaceNodeResults(SDNode *N, 4560 SmallVectorImpl<SDValue>&Results, 4561 SelectionDAG &DAG) const { 4562 const TargetMachine &TM = getTargetMachine(); 4563 DebugLoc dl = N->getDebugLoc(); 4564 switch (N->getOpcode()) { 4565 default: 4566 assert(false && "Do not know how to custom type legalize this operation!"); 4567 return; 4568 case ISD::VAARG: { 4569 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI() 4570 || TM.getSubtarget<PPCSubtarget>().isPPC64()) 4571 return; 4572 4573 EVT VT = N->getValueType(0); 4574 4575 if (VT == MVT::i64) { 4576 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget); 4577 4578 Results.push_back(NewNode); 4579 Results.push_back(NewNode.getValue(1)); 4580 } 4581 return; 4582 } 4583 case ISD::FP_ROUND_INREG: { 4584 assert(N->getValueType(0) == MVT::ppcf128); 4585 assert(N->getOperand(0).getValueType() == MVT::ppcf128); 4586 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 4587 MVT::f64, N->getOperand(0), 4588 DAG.getIntPtrConstant(0)); 4589 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 4590 MVT::f64, N->getOperand(0), 4591 DAG.getIntPtrConstant(1)); 4592 4593 // This sequence changes FPSCR to do round-to-zero, adds the two halves 4594 // of the long double, and puts FPSCR back the way it was. We do not 4595 // actually model FPSCR. 4596 std::vector<EVT> NodeTys; 4597 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg; 4598 4599 NodeTys.push_back(MVT::f64); // Return register 4600 NodeTys.push_back(MVT::Glue); // Returns a flag for later insns 4601 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 4602 MFFSreg = Result.getValue(0); 4603 InFlag = Result.getValue(1); 4604 4605 NodeTys.clear(); 4606 NodeTys.push_back(MVT::Glue); // Returns a flag 4607 Ops[0] = DAG.getConstant(31, MVT::i32); 4608 Ops[1] = InFlag; 4609 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2); 4610 InFlag = Result.getValue(0); 4611 4612 NodeTys.clear(); 4613 NodeTys.push_back(MVT::Glue); // Returns a flag 4614 Ops[0] = DAG.getConstant(30, MVT::i32); 4615 Ops[1] = InFlag; 4616 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2); 4617 InFlag = Result.getValue(0); 4618 4619 NodeTys.clear(); 4620 NodeTys.push_back(MVT::f64); // result of add 4621 NodeTys.push_back(MVT::Glue); // Returns a flag 4622 Ops[0] = Lo; 4623 Ops[1] = Hi; 4624 Ops[2] = InFlag; 4625 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3); 4626 FPreg = Result.getValue(0); 4627 InFlag = Result.getValue(1); 4628 4629 NodeTys.clear(); 4630 NodeTys.push_back(MVT::f64); 4631 Ops[0] = DAG.getConstant(1, MVT::i32); 4632 Ops[1] = MFFSreg; 4633 Ops[2] = FPreg; 4634 Ops[3] = InFlag; 4635 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4); 4636 FPreg = Result.getValue(0); 4637 4638 // We know the low half is about to be thrown away, so just use something 4639 // convenient. 4640 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, 4641 FPreg, FPreg)); 4642 return; 4643 } 4644 case ISD::FP_TO_SINT: 4645 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl)); 4646 return; 4647 } 4648} 4649 4650 4651//===----------------------------------------------------------------------===// 4652// Other Lowering Code 4653//===----------------------------------------------------------------------===// 4654 4655MachineBasicBlock * 4656PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 4657 bool is64bit, unsigned BinOpcode) const { 4658 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4659 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4660 4661 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4662 MachineFunction *F = BB->getParent(); 4663 MachineFunction::iterator It = BB; 4664 ++It; 4665 4666 unsigned dest = MI->getOperand(0).getReg(); 4667 unsigned ptrA = MI->getOperand(1).getReg(); 4668 unsigned ptrB = MI->getOperand(2).getReg(); 4669 unsigned incr = MI->getOperand(3).getReg(); 4670 DebugLoc dl = MI->getDebugLoc(); 4671 4672 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4673 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4674 F->insert(It, loopMBB); 4675 F->insert(It, exitMBB); 4676 exitMBB->splice(exitMBB->begin(), BB, 4677 llvm::next(MachineBasicBlock::iterator(MI)), 4678 BB->end()); 4679 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4680 4681 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4682 unsigned TmpReg = (!BinOpcode) ? incr : 4683 RegInfo.createVirtualRegister( 4684 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4685 (const TargetRegisterClass *) &PPC::GPRCRegClass); 4686 4687 // thisMBB: 4688 // ... 4689 // fallthrough --> loopMBB 4690 BB->addSuccessor(loopMBB); 4691 4692 // loopMBB: 4693 // l[wd]arx dest, ptr 4694 // add r0, dest, incr 4695 // st[wd]cx. r0, ptr 4696 // bne- loopMBB 4697 // fallthrough --> exitMBB 4698 BB = loopMBB; 4699 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4700 .addReg(ptrA).addReg(ptrB); 4701 if (BinOpcode) 4702 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); 4703 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4704 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); 4705 BuildMI(BB, dl, TII->get(PPC::BCC)) 4706 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4707 BB->addSuccessor(loopMBB); 4708 BB->addSuccessor(exitMBB); 4709 4710 // exitMBB: 4711 // ... 4712 BB = exitMBB; 4713 return BB; 4714} 4715 4716MachineBasicBlock * 4717PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, 4718 MachineBasicBlock *BB, 4719 bool is8bit, // operation 4720 unsigned BinOpcode) const { 4721 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4722 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4723 // In 64 bit mode we have to use 64 bits for addresses, even though the 4724 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address 4725 // registers without caring whether they're 32 or 64, but here we're 4726 // doing actual arithmetic on the addresses. 4727 bool is64bit = PPCSubTarget.isPPC64(); 4728 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; 4729 4730 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4731 MachineFunction *F = BB->getParent(); 4732 MachineFunction::iterator It = BB; 4733 ++It; 4734 4735 unsigned dest = MI->getOperand(0).getReg(); 4736 unsigned ptrA = MI->getOperand(1).getReg(); 4737 unsigned ptrB = MI->getOperand(2).getReg(); 4738 unsigned incr = MI->getOperand(3).getReg(); 4739 DebugLoc dl = MI->getDebugLoc(); 4740 4741 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4742 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4743 F->insert(It, loopMBB); 4744 F->insert(It, exitMBB); 4745 exitMBB->splice(exitMBB->begin(), BB, 4746 llvm::next(MachineBasicBlock::iterator(MI)), 4747 BB->end()); 4748 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4749 4750 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4751 const TargetRegisterClass *RC = 4752 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4753 (const TargetRegisterClass *) &PPC::GPRCRegClass; 4754 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 4755 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 4756 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 4757 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC); 4758 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 4759 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4760 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4761 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4762 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC); 4763 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4764 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4765 unsigned Ptr1Reg; 4766 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); 4767 4768 // thisMBB: 4769 // ... 4770 // fallthrough --> loopMBB 4771 BB->addSuccessor(loopMBB); 4772 4773 // The 4-byte load must be aligned, while a char or short may be 4774 // anywhere in the word. Hence all this nasty bookkeeping code. 4775 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4776 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4777 // xori shift, shift1, 24 [16] 4778 // rlwinm ptr, ptr1, 0, 0, 29 4779 // slw incr2, incr, shift 4780 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 4781 // slw mask, mask2, shift 4782 // loopMBB: 4783 // lwarx tmpDest, ptr 4784 // add tmp, tmpDest, incr2 4785 // andc tmp2, tmpDest, mask 4786 // and tmp3, tmp, mask 4787 // or tmp4, tmp3, tmp2 4788 // stwcx. tmp4, ptr 4789 // bne- loopMBB 4790 // fallthrough --> exitMBB 4791 // srw dest, tmpDest, shift 4792 if (ptrA != ZeroReg) { 4793 Ptr1Reg = RegInfo.createVirtualRegister(RC); 4794 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 4795 .addReg(ptrA).addReg(ptrB); 4796 } else { 4797 Ptr1Reg = ptrB; 4798 } 4799 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 4800 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 4801 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 4802 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 4803 if (is64bit) 4804 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 4805 .addReg(Ptr1Reg).addImm(0).addImm(61); 4806 else 4807 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 4808 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 4809 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg) 4810 .addReg(incr).addReg(ShiftReg); 4811 if (is8bit) 4812 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 4813 else { 4814 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 4815 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535); 4816 } 4817 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 4818 .addReg(Mask2Reg).addReg(ShiftReg); 4819 4820 BB = loopMBB; 4821 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 4822 .addReg(ZeroReg).addReg(PtrReg); 4823 if (BinOpcode) 4824 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) 4825 .addReg(Incr2Reg).addReg(TmpDestReg); 4826 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) 4827 .addReg(TmpDestReg).addReg(MaskReg); 4828 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) 4829 .addReg(TmpReg).addReg(MaskReg); 4830 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) 4831 .addReg(Tmp3Reg).addReg(Tmp2Reg); 4832 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4833 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg); 4834 BuildMI(BB, dl, TII->get(PPC::BCC)) 4835 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4836 BB->addSuccessor(loopMBB); 4837 BB->addSuccessor(exitMBB); 4838 4839 // exitMBB: 4840 // ... 4841 BB = exitMBB; 4842 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg) 4843 .addReg(ShiftReg); 4844 return BB; 4845} 4846 4847MachineBasicBlock * 4848PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 4849 MachineBasicBlock *BB) const { 4850 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4851 4852 // To "insert" these instructions we actually have to insert their 4853 // control-flow patterns. 4854 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4855 MachineFunction::iterator It = BB; 4856 ++It; 4857 4858 MachineFunction *F = BB->getParent(); 4859 4860 if (MI->getOpcode() == PPC::SELECT_CC_I4 || 4861 MI->getOpcode() == PPC::SELECT_CC_I8 || 4862 MI->getOpcode() == PPC::SELECT_CC_F4 || 4863 MI->getOpcode() == PPC::SELECT_CC_F8 || 4864 MI->getOpcode() == PPC::SELECT_CC_VRRC) { 4865 4866 // The incoming instruction knows the destination vreg to set, the 4867 // condition code register to branch on, the true/false values to 4868 // select between, and a branch opcode to use. 4869 4870 // thisMBB: 4871 // ... 4872 // TrueVal = ... 4873 // cmpTY ccX, r1, r2 4874 // bCC copy1MBB 4875 // fallthrough --> copy0MBB 4876 MachineBasicBlock *thisMBB = BB; 4877 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4878 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4879 unsigned SelectPred = MI->getOperand(4).getImm(); 4880 DebugLoc dl = MI->getDebugLoc(); 4881 F->insert(It, copy0MBB); 4882 F->insert(It, sinkMBB); 4883 4884 // Transfer the remainder of BB and its successor edges to sinkMBB. 4885 sinkMBB->splice(sinkMBB->begin(), BB, 4886 llvm::next(MachineBasicBlock::iterator(MI)), 4887 BB->end()); 4888 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4889 4890 // Next, add the true and fallthrough blocks as its successors. 4891 BB->addSuccessor(copy0MBB); 4892 BB->addSuccessor(sinkMBB); 4893 4894 BuildMI(BB, dl, TII->get(PPC::BCC)) 4895 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 4896 4897 // copy0MBB: 4898 // %FalseValue = ... 4899 // # fallthrough to sinkMBB 4900 BB = copy0MBB; 4901 4902 // Update machine-CFG edges 4903 BB->addSuccessor(sinkMBB); 4904 4905 // sinkMBB: 4906 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 4907 // ... 4908 BB = sinkMBB; 4909 BuildMI(*BB, BB->begin(), dl, 4910 TII->get(PPC::PHI), MI->getOperand(0).getReg()) 4911 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 4912 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 4913 } 4914 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) 4915 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); 4916 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) 4917 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); 4918 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) 4919 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4); 4920 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) 4921 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8); 4922 4923 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8) 4924 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); 4925 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16) 4926 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); 4927 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32) 4928 BB = EmitAtomicBinary(MI, BB, false, PPC::AND); 4929 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64) 4930 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8); 4931 4932 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8) 4933 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); 4934 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16) 4935 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); 4936 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32) 4937 BB = EmitAtomicBinary(MI, BB, false, PPC::OR); 4938 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64) 4939 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8); 4940 4941 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) 4942 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); 4943 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) 4944 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); 4945 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) 4946 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR); 4947 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) 4948 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8); 4949 4950 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) 4951 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC); 4952 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) 4953 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC); 4954 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) 4955 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC); 4956 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) 4957 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8); 4958 4959 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) 4960 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); 4961 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) 4962 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); 4963 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) 4964 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF); 4965 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) 4966 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8); 4967 4968 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8) 4969 BB = EmitPartwordAtomicBinary(MI, BB, true, 0); 4970 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16) 4971 BB = EmitPartwordAtomicBinary(MI, BB, false, 0); 4972 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32) 4973 BB = EmitAtomicBinary(MI, BB, false, 0); 4974 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64) 4975 BB = EmitAtomicBinary(MI, BB, true, 0); 4976 4977 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || 4978 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) { 4979 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; 4980 4981 unsigned dest = MI->getOperand(0).getReg(); 4982 unsigned ptrA = MI->getOperand(1).getReg(); 4983 unsigned ptrB = MI->getOperand(2).getReg(); 4984 unsigned oldval = MI->getOperand(3).getReg(); 4985 unsigned newval = MI->getOperand(4).getReg(); 4986 DebugLoc dl = MI->getDebugLoc(); 4987 4988 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 4989 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 4990 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 4991 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4992 F->insert(It, loop1MBB); 4993 F->insert(It, loop2MBB); 4994 F->insert(It, midMBB); 4995 F->insert(It, exitMBB); 4996 exitMBB->splice(exitMBB->begin(), BB, 4997 llvm::next(MachineBasicBlock::iterator(MI)), 4998 BB->end()); 4999 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5000 5001 // thisMBB: 5002 // ... 5003 // fallthrough --> loopMBB 5004 BB->addSuccessor(loop1MBB); 5005 5006 // loop1MBB: 5007 // l[wd]arx dest, ptr 5008 // cmp[wd] dest, oldval 5009 // bne- midMBB 5010 // loop2MBB: 5011 // st[wd]cx. newval, ptr 5012 // bne- loopMBB 5013 // b exitBB 5014 // midMBB: 5015 // st[wd]cx. dest, ptr 5016 // exitBB: 5017 BB = loop1MBB; 5018 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 5019 .addReg(ptrA).addReg(ptrB); 5020 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) 5021 .addReg(oldval).addReg(dest); 5022 BuildMI(BB, dl, TII->get(PPC::BCC)) 5023 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 5024 BB->addSuccessor(loop2MBB); 5025 BB->addSuccessor(midMBB); 5026 5027 BB = loop2MBB; 5028 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 5029 .addReg(newval).addReg(ptrA).addReg(ptrB); 5030 BuildMI(BB, dl, TII->get(PPC::BCC)) 5031 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 5032 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 5033 BB->addSuccessor(loop1MBB); 5034 BB->addSuccessor(exitMBB); 5035 5036 BB = midMBB; 5037 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 5038 .addReg(dest).addReg(ptrA).addReg(ptrB); 5039 BB->addSuccessor(exitMBB); 5040 5041 // exitMBB: 5042 // ... 5043 BB = exitMBB; 5044 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || 5045 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { 5046 // We must use 64-bit registers for addresses when targeting 64-bit, 5047 // since we're actually doing arithmetic on them. Other registers 5048 // can be 32-bit. 5049 bool is64bit = PPCSubTarget.isPPC64(); 5050 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; 5051 5052 unsigned dest = MI->getOperand(0).getReg(); 5053 unsigned ptrA = MI->getOperand(1).getReg(); 5054 unsigned ptrB = MI->getOperand(2).getReg(); 5055 unsigned oldval = MI->getOperand(3).getReg(); 5056 unsigned newval = MI->getOperand(4).getReg(); 5057 DebugLoc dl = MI->getDebugLoc(); 5058 5059 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 5060 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 5061 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 5062 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 5063 F->insert(It, loop1MBB); 5064 F->insert(It, loop2MBB); 5065 F->insert(It, midMBB); 5066 F->insert(It, exitMBB); 5067 exitMBB->splice(exitMBB->begin(), BB, 5068 llvm::next(MachineBasicBlock::iterator(MI)), 5069 BB->end()); 5070 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5071 5072 MachineRegisterInfo &RegInfo = F->getRegInfo(); 5073 const TargetRegisterClass *RC = 5074 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 5075 (const TargetRegisterClass *) &PPC::GPRCRegClass; 5076 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 5077 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 5078 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 5079 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC); 5080 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC); 5081 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC); 5082 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC); 5083 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 5084 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 5085 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 5086 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 5087 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 5088 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 5089 unsigned Ptr1Reg; 5090 unsigned TmpReg = RegInfo.createVirtualRegister(RC); 5091 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; 5092 // thisMBB: 5093 // ... 5094 // fallthrough --> loopMBB 5095 BB->addSuccessor(loop1MBB); 5096 5097 // The 4-byte load must be aligned, while a char or short may be 5098 // anywhere in the word. Hence all this nasty bookkeeping code. 5099 // add ptr1, ptrA, ptrB [copy if ptrA==0] 5100 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 5101 // xori shift, shift1, 24 [16] 5102 // rlwinm ptr, ptr1, 0, 0, 29 5103 // slw newval2, newval, shift 5104 // slw oldval2, oldval,shift 5105 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 5106 // slw mask, mask2, shift 5107 // and newval3, newval2, mask 5108 // and oldval3, oldval2, mask 5109 // loop1MBB: 5110 // lwarx tmpDest, ptr 5111 // and tmp, tmpDest, mask 5112 // cmpw tmp, oldval3 5113 // bne- midMBB 5114 // loop2MBB: 5115 // andc tmp2, tmpDest, mask 5116 // or tmp4, tmp2, newval3 5117 // stwcx. tmp4, ptr 5118 // bne- loop1MBB 5119 // b exitBB 5120 // midMBB: 5121 // stwcx. tmpDest, ptr 5122 // exitBB: 5123 // srw dest, tmpDest, shift 5124 if (ptrA != ZeroReg) { 5125 Ptr1Reg = RegInfo.createVirtualRegister(RC); 5126 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 5127 .addReg(ptrA).addReg(ptrB); 5128 } else { 5129 Ptr1Reg = ptrB; 5130 } 5131 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 5132 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 5133 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 5134 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 5135 if (is64bit) 5136 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 5137 .addReg(Ptr1Reg).addImm(0).addImm(61); 5138 else 5139 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 5140 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 5141 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) 5142 .addReg(newval).addReg(ShiftReg); 5143 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) 5144 .addReg(oldval).addReg(ShiftReg); 5145 if (is8bit) 5146 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 5147 else { 5148 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 5149 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) 5150 .addReg(Mask3Reg).addImm(65535); 5151 } 5152 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 5153 .addReg(Mask2Reg).addReg(ShiftReg); 5154 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg) 5155 .addReg(NewVal2Reg).addReg(MaskReg); 5156 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg) 5157 .addReg(OldVal2Reg).addReg(MaskReg); 5158 5159 BB = loop1MBB; 5160 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 5161 .addReg(ZeroReg).addReg(PtrReg); 5162 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) 5163 .addReg(TmpDestReg).addReg(MaskReg); 5164 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0) 5165 .addReg(TmpReg).addReg(OldVal3Reg); 5166 BuildMI(BB, dl, TII->get(PPC::BCC)) 5167 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 5168 BB->addSuccessor(loop2MBB); 5169 BB->addSuccessor(midMBB); 5170 5171 BB = loop2MBB; 5172 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg) 5173 .addReg(TmpDestReg).addReg(MaskReg); 5174 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg) 5175 .addReg(Tmp2Reg).addReg(NewVal3Reg); 5176 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg) 5177 .addReg(ZeroReg).addReg(PtrReg); 5178 BuildMI(BB, dl, TII->get(PPC::BCC)) 5179 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 5180 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 5181 BB->addSuccessor(loop1MBB); 5182 BB->addSuccessor(exitMBB); 5183 5184 BB = midMBB; 5185 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg) 5186 .addReg(ZeroReg).addReg(PtrReg); 5187 BB->addSuccessor(exitMBB); 5188 5189 // exitMBB: 5190 // ... 5191 BB = exitMBB; 5192 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg) 5193 .addReg(ShiftReg); 5194 } else { 5195 llvm_unreachable("Unexpected instr type to insert"); 5196 } 5197 5198 MI->eraseFromParent(); // The pseudo instruction is gone now. 5199 return BB; 5200} 5201 5202//===----------------------------------------------------------------------===// 5203// Target Optimization Hooks 5204//===----------------------------------------------------------------------===// 5205 5206SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, 5207 DAGCombinerInfo &DCI) const { 5208 const TargetMachine &TM = getTargetMachine(); 5209 SelectionDAG &DAG = DCI.DAG; 5210 DebugLoc dl = N->getDebugLoc(); 5211 switch (N->getOpcode()) { 5212 default: break; 5213 case PPCISD::SHL: 5214 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5215 if (C->isNullValue()) // 0 << V -> 0. 5216 return N->getOperand(0); 5217 } 5218 break; 5219 case PPCISD::SRL: 5220 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5221 if (C->isNullValue()) // 0 >>u V -> 0. 5222 return N->getOperand(0); 5223 } 5224 break; 5225 case PPCISD::SRA: 5226 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5227 if (C->isNullValue() || // 0 >>s V -> 0. 5228 C->isAllOnesValue()) // -1 >>s V -> -1. 5229 return N->getOperand(0); 5230 } 5231 break; 5232 5233 case ISD::SINT_TO_FP: 5234 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 5235 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 5236 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 5237 // We allow the src/dst to be either f32/f64, but the intermediate 5238 // type must be i64. 5239 if (N->getOperand(0).getValueType() == MVT::i64 && 5240 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 5241 SDValue Val = N->getOperand(0).getOperand(0); 5242 if (Val.getValueType() == MVT::f32) { 5243 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 5244 DCI.AddToWorklist(Val.getNode()); 5245 } 5246 5247 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val); 5248 DCI.AddToWorklist(Val.getNode()); 5249 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val); 5250 DCI.AddToWorklist(Val.getNode()); 5251 if (N->getValueType(0) == MVT::f32) { 5252 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val, 5253 DAG.getIntPtrConstant(0)); 5254 DCI.AddToWorklist(Val.getNode()); 5255 } 5256 return Val; 5257 } else if (N->getOperand(0).getValueType() == MVT::i32) { 5258 // If the intermediate type is i32, we can avoid the load/store here 5259 // too. 5260 } 5261 } 5262 } 5263 break; 5264 case ISD::STORE: 5265 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 5266 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 5267 !cast<StoreSDNode>(N)->isTruncatingStore() && 5268 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 5269 N->getOperand(1).getValueType() == MVT::i32 && 5270 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 5271 SDValue Val = N->getOperand(1).getOperand(0); 5272 if (Val.getValueType() == MVT::f32) { 5273 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 5274 DCI.AddToWorklist(Val.getNode()); 5275 } 5276 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); 5277 DCI.AddToWorklist(Val.getNode()); 5278 5279 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val, 5280 N->getOperand(2), N->getOperand(3)); 5281 DCI.AddToWorklist(Val.getNode()); 5282 return Val; 5283 } 5284 5285 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 5286 if (cast<StoreSDNode>(N)->isUnindexed() && 5287 N->getOperand(1).getOpcode() == ISD::BSWAP && 5288 N->getOperand(1).getNode()->hasOneUse() && 5289 (N->getOperand(1).getValueType() == MVT::i32 || 5290 N->getOperand(1).getValueType() == MVT::i16)) { 5291 SDValue BSwapOp = N->getOperand(1).getOperand(0); 5292 // Do an any-extend to 32-bits if this is a half-word input. 5293 if (BSwapOp.getValueType() == MVT::i16) 5294 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); 5295 5296 SDValue Ops[] = { 5297 N->getOperand(0), BSwapOp, N->getOperand(2), 5298 DAG.getValueType(N->getOperand(1).getValueType()) 5299 }; 5300 return 5301 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), 5302 Ops, array_lengthof(Ops), 5303 cast<StoreSDNode>(N)->getMemoryVT(), 5304 cast<StoreSDNode>(N)->getMemOperand()); 5305 } 5306 break; 5307 case ISD::BSWAP: 5308 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 5309 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) && 5310 N->getOperand(0).hasOneUse() && 5311 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 5312 SDValue Load = N->getOperand(0); 5313 LoadSDNode *LD = cast<LoadSDNode>(Load); 5314 // Create the byte-swapping load. 5315 SDValue Ops[] = { 5316 LD->getChain(), // Chain 5317 LD->getBasePtr(), // Ptr 5318 DAG.getValueType(N->getValueType(0)) // VT 5319 }; 5320 SDValue BSLoad = 5321 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl, 5322 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3, 5323 LD->getMemoryVT(), LD->getMemOperand()); 5324 5325 // If this is an i16 load, insert the truncate. 5326 SDValue ResVal = BSLoad; 5327 if (N->getValueType(0) == MVT::i16) 5328 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); 5329 5330 // First, combine the bswap away. This makes the value produced by the 5331 // load dead. 5332 DCI.CombineTo(N, ResVal); 5333 5334 // Next, combine the load away, we give it a bogus result value but a real 5335 // chain result. The result value is dead because the bswap is dead. 5336 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1)); 5337 5338 // Return N so it doesn't get rechecked! 5339 return SDValue(N, 0); 5340 } 5341 5342 break; 5343 case PPCISD::VCMP: { 5344 // If a VCMPo node already exists with exactly the same operands as this 5345 // node, use its result instead of this node (VCMPo computes both a CR6 and 5346 // a normal output). 5347 // 5348 if (!N->getOperand(0).hasOneUse() && 5349 !N->getOperand(1).hasOneUse() && 5350 !N->getOperand(2).hasOneUse()) { 5351 5352 // Scan all of the users of the LHS, looking for VCMPo's that match. 5353 SDNode *VCMPoNode = 0; 5354 5355 SDNode *LHSN = N->getOperand(0).getNode(); 5356 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 5357 UI != E; ++UI) 5358 if (UI->getOpcode() == PPCISD::VCMPo && 5359 UI->getOperand(1) == N->getOperand(1) && 5360 UI->getOperand(2) == N->getOperand(2) && 5361 UI->getOperand(0) == N->getOperand(0)) { 5362 VCMPoNode = *UI; 5363 break; 5364 } 5365 5366 // If there is no VCMPo node, or if the flag value has a single use, don't 5367 // transform this. 5368 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 5369 break; 5370 5371 // Look at the (necessarily single) use of the flag value. If it has a 5372 // chain, this transformation is more complex. Note that multiple things 5373 // could use the value result, which we should ignore. 5374 SDNode *FlagUser = 0; 5375 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 5376 FlagUser == 0; ++UI) { 5377 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 5378 SDNode *User = *UI; 5379 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 5380 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) { 5381 FlagUser = User; 5382 break; 5383 } 5384 } 5385 } 5386 5387 // If the user is a MFCR instruction, we know this is safe. Otherwise we 5388 // give up for right now. 5389 if (FlagUser->getOpcode() == PPCISD::MFCR) 5390 return SDValue(VCMPoNode, 0); 5391 } 5392 break; 5393 } 5394 case ISD::BR_CC: { 5395 // If this is a branch on an altivec predicate comparison, lower this so 5396 // that we don't have to do a MFCR: instead, branch directly on CR6. This 5397 // lowering is done pre-legalize, because the legalizer lowers the predicate 5398 // compare down to code that is difficult to reassemble. 5399 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 5400 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 5401 int CompareOpc; 5402 bool isDot; 5403 5404 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 5405 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 5406 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 5407 assert(isDot && "Can't compare against a vector result!"); 5408 5409 // If this is a comparison against something other than 0/1, then we know 5410 // that the condition is never/always true. 5411 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue(); 5412 if (Val != 0 && Val != 1) { 5413 if (CC == ISD::SETEQ) // Cond never true, remove branch. 5414 return N->getOperand(0); 5415 // Always !=, turn it into an unconditional branch. 5416 return DAG.getNode(ISD::BR, dl, MVT::Other, 5417 N->getOperand(0), N->getOperand(4)); 5418 } 5419 5420 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 5421 5422 // Create the PPCISD altivec 'dot' comparison node. 5423 std::vector<EVT> VTs; 5424 SDValue Ops[] = { 5425 LHS.getOperand(2), // LHS of compare 5426 LHS.getOperand(3), // RHS of compare 5427 DAG.getConstant(CompareOpc, MVT::i32) 5428 }; 5429 VTs.push_back(LHS.getOperand(2).getValueType()); 5430 VTs.push_back(MVT::Glue); 5431 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 5432 5433 // Unpack the result based on how the target uses it. 5434 PPC::Predicate CompOpc; 5435 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) { 5436 default: // Can't happen, don't crash on invalid number though. 5437 case 0: // Branch on the value of the EQ bit of CR6. 5438 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 5439 break; 5440 case 1: // Branch on the inverted value of the EQ bit of CR6. 5441 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 5442 break; 5443 case 2: // Branch on the value of the LT bit of CR6. 5444 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 5445 break; 5446 case 3: // Branch on the inverted value of the LT bit of CR6. 5447 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 5448 break; 5449 } 5450 5451 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), 5452 DAG.getConstant(CompOpc, MVT::i32), 5453 DAG.getRegister(PPC::CR6, MVT::i32), 5454 N->getOperand(4), CompNode.getValue(1)); 5455 } 5456 break; 5457 } 5458 } 5459 5460 return SDValue(); 5461} 5462 5463//===----------------------------------------------------------------------===// 5464// Inline Assembly Support 5465//===----------------------------------------------------------------------===// 5466 5467void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 5468 const APInt &Mask, 5469 APInt &KnownZero, 5470 APInt &KnownOne, 5471 const SelectionDAG &DAG, 5472 unsigned Depth) const { 5473 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 5474 switch (Op.getOpcode()) { 5475 default: break; 5476 case PPCISD::LBRX: { 5477 // lhbrx is known to have the top bits cleared out. 5478 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) 5479 KnownZero = 0xFFFF0000; 5480 break; 5481 } 5482 case ISD::INTRINSIC_WO_CHAIN: { 5483 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) { 5484 default: break; 5485 case Intrinsic::ppc_altivec_vcmpbfp_p: 5486 case Intrinsic::ppc_altivec_vcmpeqfp_p: 5487 case Intrinsic::ppc_altivec_vcmpequb_p: 5488 case Intrinsic::ppc_altivec_vcmpequh_p: 5489 case Intrinsic::ppc_altivec_vcmpequw_p: 5490 case Intrinsic::ppc_altivec_vcmpgefp_p: 5491 case Intrinsic::ppc_altivec_vcmpgtfp_p: 5492 case Intrinsic::ppc_altivec_vcmpgtsb_p: 5493 case Intrinsic::ppc_altivec_vcmpgtsh_p: 5494 case Intrinsic::ppc_altivec_vcmpgtsw_p: 5495 case Intrinsic::ppc_altivec_vcmpgtub_p: 5496 case Intrinsic::ppc_altivec_vcmpgtuh_p: 5497 case Intrinsic::ppc_altivec_vcmpgtuw_p: 5498 KnownZero = ~1U; // All bits but the low one are known to be zero. 5499 break; 5500 } 5501 } 5502 } 5503} 5504 5505 5506/// getConstraintType - Given a constraint, return the type of 5507/// constraint it is for this target. 5508PPCTargetLowering::ConstraintType 5509PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 5510 if (Constraint.size() == 1) { 5511 switch (Constraint[0]) { 5512 default: break; 5513 case 'b': 5514 case 'r': 5515 case 'f': 5516 case 'v': 5517 case 'y': 5518 return C_RegisterClass; 5519 } 5520 } 5521 return TargetLowering::getConstraintType(Constraint); 5522} 5523 5524/// Examine constraint type and operand type and determine a weight value. 5525/// This object must already have been set up with the operand type 5526/// and the current alternative constraint selected. 5527TargetLowering::ConstraintWeight 5528PPCTargetLowering::getSingleConstraintMatchWeight( 5529 AsmOperandInfo &info, const char *constraint) const { 5530 ConstraintWeight weight = CW_Invalid; 5531 Value *CallOperandVal = info.CallOperandVal; 5532 // If we don't have a value, we can't do a match, 5533 // but allow it at the lowest weight. 5534 if (CallOperandVal == NULL) 5535 return CW_Default; 5536 Type *type = CallOperandVal->getType(); 5537 // Look at the constraint type. 5538 switch (*constraint) { 5539 default: 5540 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 5541 break; 5542 case 'b': 5543 if (type->isIntegerTy()) 5544 weight = CW_Register; 5545 break; 5546 case 'f': 5547 if (type->isFloatTy()) 5548 weight = CW_Register; 5549 break; 5550 case 'd': 5551 if (type->isDoubleTy()) 5552 weight = CW_Register; 5553 break; 5554 case 'v': 5555 if (type->isVectorTy()) 5556 weight = CW_Register; 5557 break; 5558 case 'y': 5559 weight = CW_Register; 5560 break; 5561 } 5562 return weight; 5563} 5564 5565std::pair<unsigned, const TargetRegisterClass*> 5566PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 5567 EVT VT) const { 5568 if (Constraint.size() == 1) { 5569 // GCC RS6000 Constraint Letters 5570 switch (Constraint[0]) { 5571 case 'b': // R1-R31 5572 case 'r': // R0-R31 5573 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 5574 return std::make_pair(0U, PPC::G8RCRegisterClass); 5575 return std::make_pair(0U, PPC::GPRCRegisterClass); 5576 case 'f': 5577 if (VT == MVT::f32) 5578 return std::make_pair(0U, PPC::F4RCRegisterClass); 5579 else if (VT == MVT::f64) 5580 return std::make_pair(0U, PPC::F8RCRegisterClass); 5581 break; 5582 case 'v': 5583 return std::make_pair(0U, PPC::VRRCRegisterClass); 5584 case 'y': // crrc 5585 return std::make_pair(0U, PPC::CRRCRegisterClass); 5586 } 5587 } 5588 5589 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 5590} 5591 5592 5593/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 5594/// vector. If it is invalid, don't add anything to Ops. 5595void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 5596 std::string &Constraint, 5597 std::vector<SDValue>&Ops, 5598 SelectionDAG &DAG) const { 5599 SDValue Result(0,0); 5600 5601 // Only support length 1 constraints. 5602 if (Constraint.length() > 1) return; 5603 5604 char Letter = Constraint[0]; 5605 switch (Letter) { 5606 default: break; 5607 case 'I': 5608 case 'J': 5609 case 'K': 5610 case 'L': 5611 case 'M': 5612 case 'N': 5613 case 'O': 5614 case 'P': { 5615 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 5616 if (!CST) return; // Must be an immediate to match. 5617 unsigned Value = CST->getZExtValue(); 5618 switch (Letter) { 5619 default: llvm_unreachable("Unknown constraint letter!"); 5620 case 'I': // "I" is a signed 16-bit constant. 5621 if ((short)Value == (int)Value) 5622 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5623 break; 5624 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 5625 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 5626 if ((short)Value == 0) 5627 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5628 break; 5629 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 5630 if ((Value >> 16) == 0) 5631 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5632 break; 5633 case 'M': // "M" is a constant that is greater than 31. 5634 if (Value > 31) 5635 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5636 break; 5637 case 'N': // "N" is a positive constant that is an exact power of two. 5638 if ((int)Value > 0 && isPowerOf2_32(Value)) 5639 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5640 break; 5641 case 'O': // "O" is the constant zero. 5642 if (Value == 0) 5643 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5644 break; 5645 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 5646 if ((short)-Value == (int)-Value) 5647 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5648 break; 5649 } 5650 break; 5651 } 5652 } 5653 5654 if (Result.getNode()) { 5655 Ops.push_back(Result); 5656 return; 5657 } 5658 5659 // Handle standard constraint letters. 5660 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 5661} 5662 5663// isLegalAddressingMode - Return true if the addressing mode represented 5664// by AM is legal for this target, for a load/store of the specified type. 5665bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 5666 Type *Ty) const { 5667 // FIXME: PPC does not allow r+i addressing modes for vectors! 5668 5669 // PPC allows a sign-extended 16-bit immediate field. 5670 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 5671 return false; 5672 5673 // No global is ever allowed as a base. 5674 if (AM.BaseGV) 5675 return false; 5676 5677 // PPC only support r+r, 5678 switch (AM.Scale) { 5679 case 0: // "r+i" or just "i", depending on HasBaseReg. 5680 break; 5681 case 1: 5682 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 5683 return false; 5684 // Otherwise we have r+r or r+i. 5685 break; 5686 case 2: 5687 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 5688 return false; 5689 // Allow 2*r as r+r. 5690 break; 5691 default: 5692 // No other scales are supported. 5693 return false; 5694 } 5695 5696 return true; 5697} 5698 5699/// isLegalAddressImmediate - Return true if the integer value can be used 5700/// as the offset of the target addressing mode for load / store of the 5701/// given type. 5702bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{ 5703 // PPC allows a sign-extended 16-bit immediate field. 5704 return (V > -(1 << 16) && V < (1 << 16)-1); 5705} 5706 5707bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 5708 return false; 5709} 5710 5711SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, 5712 SelectionDAG &DAG) const { 5713 MachineFunction &MF = DAG.getMachineFunction(); 5714 MachineFrameInfo *MFI = MF.getFrameInfo(); 5715 MFI->setReturnAddressIsTaken(true); 5716 5717 DebugLoc dl = Op.getDebugLoc(); 5718 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 5719 5720 // Make sure the function does not optimize away the store of the RA to 5721 // the stack. 5722 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 5723 FuncInfo->setLRStoreRequired(); 5724 bool isPPC64 = PPCSubTarget.isPPC64(); 5725 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 5726 5727 if (Depth > 0) { 5728 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 5729 SDValue Offset = 5730 5731 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI), 5732 isPPC64? MVT::i64 : MVT::i32); 5733 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 5734 DAG.getNode(ISD::ADD, dl, getPointerTy(), 5735 FrameAddr, Offset), 5736 MachinePointerInfo(), false, false, false, 0); 5737 } 5738 5739 // Just load the return address off the stack. 5740 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); 5741 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 5742 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 5743} 5744 5745SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, 5746 SelectionDAG &DAG) const { 5747 DebugLoc dl = Op.getDebugLoc(); 5748 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 5749 5750 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 5751 bool isPPC64 = PtrVT == MVT::i64; 5752 5753 MachineFunction &MF = DAG.getMachineFunction(); 5754 MachineFrameInfo *MFI = MF.getFrameInfo(); 5755 MFI->setFrameAddressIsTaken(true); 5756 bool is31 = (DisableFramePointerElim(MF) || MFI->hasVarSizedObjects()) && 5757 MFI->getStackSize() && 5758 !MF.getFunction()->hasFnAttr(Attribute::Naked); 5759 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) : 5760 (is31 ? PPC::R31 : PPC::R1); 5761 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, 5762 PtrVT); 5763 while (Depth--) 5764 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(), 5765 FrameAddr, MachinePointerInfo(), false, false, 5766 false, 0); 5767 return FrameAddr; 5768} 5769 5770bool 5771PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 5772 // The PowerPC target isn't yet aware of offsets. 5773 return false; 5774} 5775 5776/// getOptimalMemOpType - Returns the target specific optimal type for load 5777/// and store operations as a result of memset, memcpy, and memmove 5778/// lowering. If DstAlign is zero that means it's safe to destination 5779/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 5780/// means there isn't a need to check it against alignment requirement, 5781/// probably because the source does not need to be loaded. If 5782/// 'IsZeroVal' is true, that means it's safe to return a 5783/// non-scalar-integer type, e.g. empty string source, constant, or loaded 5784/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 5785/// constant so it does not need to be loaded. 5786/// It returns EVT::Other if the type should be determined using generic 5787/// target-independent logic. 5788EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, 5789 unsigned DstAlign, unsigned SrcAlign, 5790 bool IsZeroVal, 5791 bool MemcpyStrSrc, 5792 MachineFunction &MF) const { 5793 if (this->PPCSubTarget.isPPC64()) { 5794 return MVT::i64; 5795 } else { 5796 return MVT::i32; 5797 } 5798} 5799