PPCISelLowering.cpp revision d75686a471ee6ed5260e29d22d54f15152bbc9b4
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPredicates.h" 17#include "PPCTargetMachine.h" 18#include "PPCPerfectShuffle.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/ADT/VectorExtras.h" 21#include "llvm/Analysis/ScalarEvolutionExpressions.h" 22#include "llvm/CodeGen/CallingConvLower.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineFunction.h" 25#include "llvm/CodeGen/MachineInstrBuilder.h" 26#include "llvm/CodeGen/MachineRegisterInfo.h" 27#include "llvm/CodeGen/PseudoSourceValue.h" 28#include "llvm/CodeGen/SelectionDAG.h" 29#include "llvm/Constants.h" 30#include "llvm/Function.h" 31#include "llvm/Intrinsics.h" 32#include "llvm/Support/MathExtras.h" 33#include "llvm/Target/TargetOptions.h" 34#include "llvm/Support/CommandLine.h" 35using namespace llvm; 36 37static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", 38cl::desc("enable preincrement load/store generation on PPC (experimental)"), 39 cl::Hidden); 40 41PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 42 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { 43 44 setPow2DivIsCheap(); 45 46 // Use _setjmp/_longjmp instead of setjmp/longjmp. 47 setUseUnderscoreSetJmp(true); 48 setUseUnderscoreLongJmp(true); 49 50 // Set up the register classes. 51 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 52 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 53 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 54 55 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 56 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 57 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); 58 59 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 60 61 // PowerPC has pre-inc load and store's. 62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 65 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 67 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 70 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 72 73 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg) 74 setConvertAction(MVT::ppcf128, MVT::f64, Expand); 75 setConvertAction(MVT::ppcf128, MVT::f32, Expand); 76 // This is used in the ppcf128->int sequence. Note it has different semantics 77 // from FP_ROUND: that rounds to nearest, this rounds to zero. 78 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 79 80 // PowerPC has no intrinsics for these particular operations 81 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 82 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 83 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 84 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 85 86 // PowerPC has no SREM/UREM instructions 87 setOperationAction(ISD::SREM, MVT::i32, Expand); 88 setOperationAction(ISD::UREM, MVT::i32, Expand); 89 setOperationAction(ISD::SREM, MVT::i64, Expand); 90 setOperationAction(ISD::UREM, MVT::i64, Expand); 91 92 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 93 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 94 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 95 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 96 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 97 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 98 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 99 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 100 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 101 102 // We don't support sin/cos/sqrt/fmod/pow 103 setOperationAction(ISD::FSIN , MVT::f64, Expand); 104 setOperationAction(ISD::FCOS , MVT::f64, Expand); 105 setOperationAction(ISD::FREM , MVT::f64, Expand); 106 setOperationAction(ISD::FPOW , MVT::f64, Expand); 107 setOperationAction(ISD::FSIN , MVT::f32, Expand); 108 setOperationAction(ISD::FCOS , MVT::f32, Expand); 109 setOperationAction(ISD::FREM , MVT::f32, Expand); 110 setOperationAction(ISD::FPOW , MVT::f32, Expand); 111 112 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 113 114 // If we're enabling GP optimizations, use hardware square root 115 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 116 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 117 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 118 } 119 120 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 121 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 122 123 // PowerPC does not have BSWAP, CTPOP or CTTZ 124 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 125 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 126 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 127 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 128 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 129 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 130 131 // PowerPC does not have ROTR 132 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 133 134 // PowerPC does not have Select 135 setOperationAction(ISD::SELECT, MVT::i32, Expand); 136 setOperationAction(ISD::SELECT, MVT::i64, Expand); 137 setOperationAction(ISD::SELECT, MVT::f32, Expand); 138 setOperationAction(ISD::SELECT, MVT::f64, Expand); 139 140 // PowerPC wants to turn select_cc of FP into fsel when possible. 141 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 142 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 143 144 // PowerPC wants to optimize integer setcc a bit 145 setOperationAction(ISD::SETCC, MVT::i32, Custom); 146 147 // PowerPC does not have BRCOND which requires SetCC 148 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 149 150 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 151 152 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 153 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 154 155 // PowerPC does not have [U|S]INT_TO_FP 156 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 157 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 158 159 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 160 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 161 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 162 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 163 164 // We cannot sextinreg(i1). Expand to shifts. 165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 166 167 // Support label based line numbers. 168 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 169 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 170 171 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 172 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 173 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 174 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 175 176 177 // We want to legalize GlobalAddress and ConstantPool nodes into the 178 // appropriate instructions to materialize the address. 179 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 180 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 181 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 182 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 183 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 184 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 185 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 186 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 187 188 // RET must be custom lowered, to meet ABI requirements 189 setOperationAction(ISD::RET , MVT::Other, Custom); 190 191 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 192 setOperationAction(ISD::VASTART , MVT::Other, Custom); 193 194 // VAARG is custom lowered with ELF 32 ABI 195 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI()) 196 setOperationAction(ISD::VAARG, MVT::Other, Custom); 197 else 198 setOperationAction(ISD::VAARG, MVT::Other, Expand); 199 200 // Use the default implementation. 201 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 202 setOperationAction(ISD::VAEND , MVT::Other, Expand); 203 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 204 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 205 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 207 208 // We want to custom lower some of our intrinsics. 209 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 210 211 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 212 // They also have instructions for converting between i64 and fp. 213 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 214 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 215 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 216 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 217 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 218 219 // FIXME: disable this lowered code. This generates 64-bit register values, 220 // and we don't model the fact that the top part is clobbered by calls. We 221 // need to flag these together so that the value isn't live across a call. 222 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 223 224 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 225 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 226 } else { 227 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 228 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 229 } 230 231 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 232 // 64-bit PowerPC implementations can support i64 types directly 233 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 234 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 235 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 236 // 64-bit PowerPC wants to expand i128 shifts itself. 237 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 238 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 239 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 240 } else { 241 // 32-bit PowerPC wants to expand i64 shifts itself. 242 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 243 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 244 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 245 } 246 247 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 248 // First set operation action for all vector types to expand. Then we 249 // will selectively turn on ones that can be effectively codegen'd. 250 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 251 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 252 // add/sub are legal for all supported vector VT's. 253 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); 254 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); 255 256 // We promote all shuffles to v16i8. 257 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); 258 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); 259 260 // We promote all non-typed operations to v4i32. 261 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote); 262 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32); 263 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote); 264 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32); 265 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote); 266 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32); 267 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote); 268 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32); 269 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); 270 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32); 271 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote); 272 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32); 273 274 // No other operations are legal. 275 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); 276 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); 277 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); 278 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); 279 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); 280 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); 281 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand); 282 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 283 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 284 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); 285 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand); 286 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand); 287 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand); 288 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand); 289 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); 290 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand); 291 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand); 292 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand); 293 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand); 294 } 295 296 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 297 // with merges, splats, etc. 298 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 299 300 setOperationAction(ISD::AND , MVT::v4i32, Legal); 301 setOperationAction(ISD::OR , MVT::v4i32, Legal); 302 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 303 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 304 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 305 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 306 307 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 308 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 309 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 310 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 311 312 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 313 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 314 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 315 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 316 317 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 318 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 319 320 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 321 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 322 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 323 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 324 } 325 326 setShiftAmountType(MVT::i32); 327 setSetCCResultContents(ZeroOrOneSetCCResult); 328 329 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 330 setStackPointerRegisterToSaveRestore(PPC::X1); 331 setExceptionPointerRegister(PPC::X3); 332 setExceptionSelectorRegister(PPC::X4); 333 } else { 334 setStackPointerRegisterToSaveRestore(PPC::R1); 335 setExceptionPointerRegister(PPC::R3); 336 setExceptionSelectorRegister(PPC::R4); 337 } 338 339 // We have target-specific dag combine patterns for the following nodes: 340 setTargetDAGCombine(ISD::SINT_TO_FP); 341 setTargetDAGCombine(ISD::STORE); 342 setTargetDAGCombine(ISD::BR_CC); 343 setTargetDAGCombine(ISD::BSWAP); 344 345 // Darwin long double math library functions have $LDBL128 appended. 346 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) { 347 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 348 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 349 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 350 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 351 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 352 } 353 354 computeRegisterProperties(); 355} 356 357/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 358/// function arguments in the caller parameter area. 359unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const { 360 TargetMachine &TM = getTargetMachine(); 361 // Darwin passes everything on 4 byte boundary. 362 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) 363 return 4; 364 // FIXME Elf TBD 365 return 4; 366} 367 368const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 369 switch (Opcode) { 370 default: return 0; 371 case PPCISD::FSEL: return "PPCISD::FSEL"; 372 case PPCISD::FCFID: return "PPCISD::FCFID"; 373 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 374 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 375 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 376 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 377 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 378 case PPCISD::VPERM: return "PPCISD::VPERM"; 379 case PPCISD::Hi: return "PPCISD::Hi"; 380 case PPCISD::Lo: return "PPCISD::Lo"; 381 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 382 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 383 case PPCISD::SRL: return "PPCISD::SRL"; 384 case PPCISD::SRA: return "PPCISD::SRA"; 385 case PPCISD::SHL: return "PPCISD::SHL"; 386 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 387 case PPCISD::STD_32: return "PPCISD::STD_32"; 388 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF"; 389 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho"; 390 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 391 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho"; 392 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF"; 393 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 394 case PPCISD::MFCR: return "PPCISD::MFCR"; 395 case PPCISD::VCMP: return "PPCISD::VCMP"; 396 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 397 case PPCISD::LBRX: return "PPCISD::LBRX"; 398 case PPCISD::STBRX: return "PPCISD::STBRX"; 399 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 400 case PPCISD::MFFS: return "PPCISD::MFFS"; 401 case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; 402 case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; 403 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 404 case PPCISD::MTFSF: return "PPCISD::MTFSF"; 405 } 406} 407 408 409MVT::ValueType 410PPCTargetLowering::getSetCCResultType(const SDOperand &) const { 411 return MVT::i32; 412} 413 414 415//===----------------------------------------------------------------------===// 416// Node matching predicates, for use by the tblgen matching code. 417//===----------------------------------------------------------------------===// 418 419/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 420static bool isFloatingPointZero(SDOperand Op) { 421 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 422 return CFP->getValueAPF().isZero(); 423 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { 424 // Maybe this has already been legalized into the constant pool? 425 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 426 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 427 return CFP->getValueAPF().isZero(); 428 } 429 return false; 430} 431 432/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 433/// true if Op is undef or if it matches the specified value. 434static bool isConstantOrUndef(SDOperand Op, unsigned Val) { 435 return Op.getOpcode() == ISD::UNDEF || 436 cast<ConstantSDNode>(Op)->getValue() == Val; 437} 438 439/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 440/// VPKUHUM instruction. 441bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { 442 if (!isUnary) { 443 for (unsigned i = 0; i != 16; ++i) 444 if (!isConstantOrUndef(N->getOperand(i), i*2+1)) 445 return false; 446 } else { 447 for (unsigned i = 0; i != 8; ++i) 448 if (!isConstantOrUndef(N->getOperand(i), i*2+1) || 449 !isConstantOrUndef(N->getOperand(i+8), i*2+1)) 450 return false; 451 } 452 return true; 453} 454 455/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 456/// VPKUWUM instruction. 457bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { 458 if (!isUnary) { 459 for (unsigned i = 0; i != 16; i += 2) 460 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 461 !isConstantOrUndef(N->getOperand(i+1), i*2+3)) 462 return false; 463 } else { 464 for (unsigned i = 0; i != 8; i += 2) 465 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 466 !isConstantOrUndef(N->getOperand(i+1), i*2+3) || 467 !isConstantOrUndef(N->getOperand(i+8), i*2+2) || 468 !isConstantOrUndef(N->getOperand(i+9), i*2+3)) 469 return false; 470 } 471 return true; 472} 473 474/// isVMerge - Common function, used to match vmrg* shuffles. 475/// 476static bool isVMerge(SDNode *N, unsigned UnitSize, 477 unsigned LHSStart, unsigned RHSStart) { 478 assert(N->getOpcode() == ISD::BUILD_VECTOR && 479 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 480 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 481 "Unsupported merge size!"); 482 483 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 484 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 485 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), 486 LHSStart+j+i*UnitSize) || 487 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), 488 RHSStart+j+i*UnitSize)) 489 return false; 490 } 491 return true; 492} 493 494/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 495/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 496bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 497 if (!isUnary) 498 return isVMerge(N, UnitSize, 8, 24); 499 return isVMerge(N, UnitSize, 8, 8); 500} 501 502/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 503/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 504bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 505 if (!isUnary) 506 return isVMerge(N, UnitSize, 0, 16); 507 return isVMerge(N, UnitSize, 0, 0); 508} 509 510 511/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 512/// amount, otherwise return -1. 513int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 514 assert(N->getOpcode() == ISD::BUILD_VECTOR && 515 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 516 // Find the first non-undef value in the shuffle mask. 517 unsigned i; 518 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) 519 /*search*/; 520 521 if (i == 16) return -1; // all undef. 522 523 // Otherwise, check to see if the rest of the elements are consequtively 524 // numbered from this value. 525 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue(); 526 if (ShiftAmt < i) return -1; 527 ShiftAmt -= i; 528 529 if (!isUnary) { 530 // Check the rest of the elements to see if they are consequtive. 531 for (++i; i != 16; ++i) 532 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) 533 return -1; 534 } else { 535 // Check the rest of the elements to see if they are consequtive. 536 for (++i; i != 16; ++i) 537 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) 538 return -1; 539 } 540 541 return ShiftAmt; 542} 543 544/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 545/// specifies a splat of a single element that is suitable for input to 546/// VSPLTB/VSPLTH/VSPLTW. 547bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { 548 assert(N->getOpcode() == ISD::BUILD_VECTOR && 549 N->getNumOperands() == 16 && 550 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 551 552 // This is a splat operation if each element of the permute is the same, and 553 // if the value doesn't reference the second vector. 554 unsigned ElementBase = 0; 555 SDOperand Elt = N->getOperand(0); 556 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) 557 ElementBase = EltV->getValue(); 558 else 559 return false; // FIXME: Handle UNDEF elements too! 560 561 if (cast<ConstantSDNode>(Elt)->getValue() >= 16) 562 return false; 563 564 // Check that they are consequtive. 565 for (unsigned i = 1; i != EltSize; ++i) { 566 if (!isa<ConstantSDNode>(N->getOperand(i)) || 567 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase) 568 return false; 569 } 570 571 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); 572 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 573 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 574 assert(isa<ConstantSDNode>(N->getOperand(i)) && 575 "Invalid VECTOR_SHUFFLE mask!"); 576 for (unsigned j = 0; j != EltSize; ++j) 577 if (N->getOperand(i+j) != N->getOperand(j)) 578 return false; 579 } 580 581 return true; 582} 583 584/// isAllNegativeZeroVector - Returns true if all elements of build_vector 585/// are -0.0. 586bool PPC::isAllNegativeZeroVector(SDNode *N) { 587 assert(N->getOpcode() == ISD::BUILD_VECTOR); 588 if (PPC::isSplatShuffleMask(N, N->getNumOperands())) 589 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N)) 590 return CFP->getValueAPF().isNegZero(); 591 return false; 592} 593 594/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 595/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 596unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 597 assert(isSplatShuffleMask(N, EltSize)); 598 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize; 599} 600 601/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 602/// by using a vspltis[bhw] instruction of the specified element size, return 603/// the constant being splatted. The ByteSize field indicates the number of 604/// bytes of each element [124] -> [bhw]. 605SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 606 SDOperand OpVal(0, 0); 607 608 // If ByteSize of the splat is bigger than the element size of the 609 // build_vector, then we have a case where we are checking for a splat where 610 // multiple elements of the buildvector are folded together into a single 611 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 612 unsigned EltSize = 16/N->getNumOperands(); 613 if (EltSize < ByteSize) { 614 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 615 SDOperand UniquedVals[4]; 616 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 617 618 // See if all of the elements in the buildvector agree across. 619 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 620 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 621 // If the element isn't a constant, bail fully out. 622 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand(); 623 624 625 if (UniquedVals[i&(Multiple-1)].Val == 0) 626 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 627 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 628 return SDOperand(); // no match. 629 } 630 631 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 632 // either constant or undef values that are identical for each chunk. See 633 // if these chunks can form into a larger vspltis*. 634 635 // Check to see if all of the leading entries are either 0 or -1. If 636 // neither, then this won't fit into the immediate field. 637 bool LeadingZero = true; 638 bool LeadingOnes = true; 639 for (unsigned i = 0; i != Multiple-1; ++i) { 640 if (UniquedVals[i].Val == 0) continue; // Must have been undefs. 641 642 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 643 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 644 } 645 // Finally, check the least significant entry. 646 if (LeadingZero) { 647 if (UniquedVals[Multiple-1].Val == 0) 648 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 649 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue(); 650 if (Val < 16) 651 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 652 } 653 if (LeadingOnes) { 654 if (UniquedVals[Multiple-1].Val == 0) 655 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 656 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended(); 657 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 658 return DAG.getTargetConstant(Val, MVT::i32); 659 } 660 661 return SDOperand(); 662 } 663 664 // Check to see if this buildvec has a single non-undef value in its elements. 665 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 666 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 667 if (OpVal.Val == 0) 668 OpVal = N->getOperand(i); 669 else if (OpVal != N->getOperand(i)) 670 return SDOperand(); 671 } 672 673 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def. 674 675 unsigned ValSizeInBytes = 0; 676 uint64_t Value = 0; 677 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 678 Value = CN->getValue(); 679 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8; 680 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 681 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 682 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 683 ValSizeInBytes = 4; 684 } 685 686 // If the splat value is larger than the element value, then we can never do 687 // this splat. The only case that we could fit the replicated bits into our 688 // immediate field for would be zero, and we prefer to use vxor for it. 689 if (ValSizeInBytes < ByteSize) return SDOperand(); 690 691 // If the element value is larger than the splat value, cut it in half and 692 // check to see if the two halves are equal. Continue doing this until we 693 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 694 while (ValSizeInBytes > ByteSize) { 695 ValSizeInBytes >>= 1; 696 697 // If the top half equals the bottom half, we're still ok. 698 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 699 (Value & ((1 << (8*ValSizeInBytes))-1))) 700 return SDOperand(); 701 } 702 703 // Properly sign extend the value. 704 int ShAmt = (4-ByteSize)*8; 705 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 706 707 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 708 if (MaskVal == 0) return SDOperand(); 709 710 // Finally, if this value fits in a 5 bit sext field, return it 711 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 712 return DAG.getTargetConstant(MaskVal, MVT::i32); 713 return SDOperand(); 714} 715 716//===----------------------------------------------------------------------===// 717// Addressing Mode Selection 718//===----------------------------------------------------------------------===// 719 720/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 721/// or 64-bit immediate, and if the value can be accurately represented as a 722/// sign extension from a 16-bit value. If so, this returns true and the 723/// immediate. 724static bool isIntS16Immediate(SDNode *N, short &Imm) { 725 if (N->getOpcode() != ISD::Constant) 726 return false; 727 728 Imm = (short)cast<ConstantSDNode>(N)->getValue(); 729 if (N->getValueType(0) == MVT::i32) 730 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue(); 731 else 732 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue(); 733} 734static bool isIntS16Immediate(SDOperand Op, short &Imm) { 735 return isIntS16Immediate(Op.Val, Imm); 736} 737 738 739/// SelectAddressRegReg - Given the specified addressed, check to see if it 740/// can be represented as an indexed [r+r] operation. Returns false if it 741/// can be more efficiently represented with [r+imm]. 742bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base, 743 SDOperand &Index, 744 SelectionDAG &DAG) { 745 short imm = 0; 746 if (N.getOpcode() == ISD::ADD) { 747 if (isIntS16Immediate(N.getOperand(1), imm)) 748 return false; // r+i 749 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 750 return false; // r+i 751 752 Base = N.getOperand(0); 753 Index = N.getOperand(1); 754 return true; 755 } else if (N.getOpcode() == ISD::OR) { 756 if (isIntS16Immediate(N.getOperand(1), imm)) 757 return false; // r+i can fold it if we can. 758 759 // If this is an or of disjoint bitfields, we can codegen this as an add 760 // (for better address arithmetic) if the LHS and RHS of the OR are provably 761 // disjoint. 762 APInt LHSKnownZero, LHSKnownOne; 763 APInt RHSKnownZero, RHSKnownOne; 764 DAG.ComputeMaskedBits(N.getOperand(0), 765 APInt::getAllOnesValue(N.getOperand(0) 766 .getValueSizeInBits()), 767 LHSKnownZero, LHSKnownOne); 768 769 if (LHSKnownZero.getBoolValue()) { 770 DAG.ComputeMaskedBits(N.getOperand(1), 771 APInt::getAllOnesValue(N.getOperand(1) 772 .getValueSizeInBits()), 773 RHSKnownZero, RHSKnownOne); 774 // If all of the bits are known zero on the LHS or RHS, the add won't 775 // carry. 776 if (~(LHSKnownZero | RHSKnownZero) == 0) { 777 Base = N.getOperand(0); 778 Index = N.getOperand(1); 779 return true; 780 } 781 } 782 } 783 784 return false; 785} 786 787/// Returns true if the address N can be represented by a base register plus 788/// a signed 16-bit displacement [r+imm], and if it is not better 789/// represented as reg+reg. 790bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp, 791 SDOperand &Base, SelectionDAG &DAG){ 792 // If this can be more profitably realized as r+r, fail. 793 if (SelectAddressRegReg(N, Disp, Base, DAG)) 794 return false; 795 796 if (N.getOpcode() == ISD::ADD) { 797 short imm = 0; 798 if (isIntS16Immediate(N.getOperand(1), imm)) { 799 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 800 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 801 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 802 } else { 803 Base = N.getOperand(0); 804 } 805 return true; // [r+i] 806 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 807 // Match LOAD (ADD (X, Lo(G))). 808 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 809 && "Cannot handle constant offsets yet!"); 810 Disp = N.getOperand(1).getOperand(0); // The global address. 811 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 812 Disp.getOpcode() == ISD::TargetConstantPool || 813 Disp.getOpcode() == ISD::TargetJumpTable); 814 Base = N.getOperand(0); 815 return true; // [&g+r] 816 } 817 } else if (N.getOpcode() == ISD::OR) { 818 short imm = 0; 819 if (isIntS16Immediate(N.getOperand(1), imm)) { 820 // If this is an or of disjoint bitfields, we can codegen this as an add 821 // (for better address arithmetic) if the LHS and RHS of the OR are 822 // provably disjoint. 823 APInt LHSKnownZero, LHSKnownOne; 824 DAG.ComputeMaskedBits(N.getOperand(0), 825 APInt::getAllOnesValue(32), 826 LHSKnownZero, LHSKnownOne); 827 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 828 // If all of the bits are known zero on the LHS or RHS, the add won't 829 // carry. 830 Base = N.getOperand(0); 831 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 832 return true; 833 } 834 } 835 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 836 // Loading from a constant address. 837 838 // If this address fits entirely in a 16-bit sext immediate field, codegen 839 // this as "d, 0" 840 short Imm; 841 if (isIntS16Immediate(CN, Imm)) { 842 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 843 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 844 return true; 845 } 846 847 // Handle 32-bit sext immediates with LIS + addr mode. 848 if (CN->getValueType(0) == MVT::i32 || 849 (int64_t)CN->getValue() == (int)CN->getValue()) { 850 int Addr = (int)CN->getValue(); 851 852 // Otherwise, break this down into an LIS + disp. 853 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 854 855 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 856 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 857 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 858 return true; 859 } 860 } 861 862 Disp = DAG.getTargetConstant(0, getPointerTy()); 863 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 864 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 865 else 866 Base = N; 867 return true; // [r+0] 868} 869 870/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 871/// represented as an indexed [r+r] operation. 872bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, 873 SDOperand &Index, 874 SelectionDAG &DAG) { 875 // Check to see if we can easily represent this as an [r+r] address. This 876 // will fail if it thinks that the address is more profitably represented as 877 // reg+imm, e.g. where imm = 0. 878 if (SelectAddressRegReg(N, Base, Index, DAG)) 879 return true; 880 881 // If the operand is an addition, always emit this as [r+r], since this is 882 // better (for code size, and execution, as the memop does the add for free) 883 // than emitting an explicit add. 884 if (N.getOpcode() == ISD::ADD) { 885 Base = N.getOperand(0); 886 Index = N.getOperand(1); 887 return true; 888 } 889 890 // Otherwise, do it the hard way, using R0 as the base register. 891 Base = DAG.getRegister(PPC::R0, N.getValueType()); 892 Index = N; 893 return true; 894} 895 896/// SelectAddressRegImmShift - Returns true if the address N can be 897/// represented by a base register plus a signed 14-bit displacement 898/// [r+imm*4]. Suitable for use by STD and friends. 899bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, 900 SDOperand &Base, 901 SelectionDAG &DAG) { 902 // If this can be more profitably realized as r+r, fail. 903 if (SelectAddressRegReg(N, Disp, Base, DAG)) 904 return false; 905 906 if (N.getOpcode() == ISD::ADD) { 907 short imm = 0; 908 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 909 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 910 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 911 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 912 } else { 913 Base = N.getOperand(0); 914 } 915 return true; // [r+i] 916 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 917 // Match LOAD (ADD (X, Lo(G))). 918 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 919 && "Cannot handle constant offsets yet!"); 920 Disp = N.getOperand(1).getOperand(0); // The global address. 921 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 922 Disp.getOpcode() == ISD::TargetConstantPool || 923 Disp.getOpcode() == ISD::TargetJumpTable); 924 Base = N.getOperand(0); 925 return true; // [&g+r] 926 } 927 } else if (N.getOpcode() == ISD::OR) { 928 short imm = 0; 929 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 930 // If this is an or of disjoint bitfields, we can codegen this as an add 931 // (for better address arithmetic) if the LHS and RHS of the OR are 932 // provably disjoint. 933 APInt LHSKnownZero, LHSKnownOne; 934 DAG.ComputeMaskedBits(N.getOperand(0), 935 APInt::getAllOnesValue(32), 936 LHSKnownZero, LHSKnownOne); 937 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 938 // If all of the bits are known zero on the LHS or RHS, the add won't 939 // carry. 940 Base = N.getOperand(0); 941 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 942 return true; 943 } 944 } 945 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 946 // Loading from a constant address. Verify low two bits are clear. 947 if ((CN->getValue() & 3) == 0) { 948 // If this address fits entirely in a 14-bit sext immediate field, codegen 949 // this as "d, 0" 950 short Imm; 951 if (isIntS16Immediate(CN, Imm)) { 952 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 953 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 954 return true; 955 } 956 957 // Fold the low-part of 32-bit absolute addresses into addr mode. 958 if (CN->getValueType(0) == MVT::i32 || 959 (int64_t)CN->getValue() == (int)CN->getValue()) { 960 int Addr = (int)CN->getValue(); 961 962 // Otherwise, break this down into an LIS + disp. 963 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 964 965 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 966 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 967 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 968 return true; 969 } 970 } 971 } 972 973 Disp = DAG.getTargetConstant(0, getPointerTy()); 974 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 975 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 976 else 977 Base = N; 978 return true; // [r+0] 979} 980 981 982/// getPreIndexedAddressParts - returns true by value, base pointer and 983/// offset pointer and addressing mode by reference if the node's address 984/// can be legally represented as pre-indexed load / store address. 985bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 986 SDOperand &Offset, 987 ISD::MemIndexedMode &AM, 988 SelectionDAG &DAG) { 989 // Disabled by default for now. 990 if (!EnablePPCPreinc) return false; 991 992 SDOperand Ptr; 993 MVT::ValueType VT; 994 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 995 Ptr = LD->getBasePtr(); 996 VT = LD->getMemoryVT(); 997 998 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 999 ST = ST; 1000 Ptr = ST->getBasePtr(); 1001 VT = ST->getMemoryVT(); 1002 } else 1003 return false; 1004 1005 // PowerPC doesn't have preinc load/store instructions for vectors. 1006 if (MVT::isVector(VT)) 1007 return false; 1008 1009 // TODO: Check reg+reg first. 1010 1011 // LDU/STU use reg+imm*4, others use reg+imm. 1012 if (VT != MVT::i64) { 1013 // reg + imm 1014 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 1015 return false; 1016 } else { 1017 // reg + imm * 4. 1018 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 1019 return false; 1020 } 1021 1022 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1023 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 1024 // sext i32 to i64 when addr mode is r+i. 1025 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 1026 LD->getExtensionType() == ISD::SEXTLOAD && 1027 isa<ConstantSDNode>(Offset)) 1028 return false; 1029 } 1030 1031 AM = ISD::PRE_INC; 1032 return true; 1033} 1034 1035//===----------------------------------------------------------------------===// 1036// LowerOperation implementation 1037//===----------------------------------------------------------------------===// 1038 1039SDOperand PPCTargetLowering::LowerConstantPool(SDOperand Op, 1040 SelectionDAG &DAG) { 1041 MVT::ValueType PtrVT = Op.getValueType(); 1042 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1043 Constant *C = CP->getConstVal(); 1044 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 1045 SDOperand Zero = DAG.getConstant(0, PtrVT); 1046 1047 const TargetMachine &TM = DAG.getTarget(); 1048 1049 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); 1050 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); 1051 1052 // If this is a non-darwin platform, we don't support non-static relo models 1053 // yet. 1054 if (TM.getRelocationModel() == Reloc::Static || 1055 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1056 // Generate non-pic code that has direct accesses to the constant pool. 1057 // The address of the global is just (hi(&g)+lo(&g)). 1058 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1059 } 1060 1061 if (TM.getRelocationModel() == Reloc::PIC_) { 1062 // With PIC, the first instruction is actually "GR+hi(&G)". 1063 Hi = DAG.getNode(ISD::ADD, PtrVT, 1064 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1065 } 1066 1067 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1068 return Lo; 1069} 1070 1071SDOperand PPCTargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { 1072 MVT::ValueType PtrVT = Op.getValueType(); 1073 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1074 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1075 SDOperand Zero = DAG.getConstant(0, PtrVT); 1076 1077 const TargetMachine &TM = DAG.getTarget(); 1078 1079 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); 1080 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); 1081 1082 // If this is a non-darwin platform, we don't support non-static relo models 1083 // yet. 1084 if (TM.getRelocationModel() == Reloc::Static || 1085 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1086 // Generate non-pic code that has direct accesses to the constant pool. 1087 // The address of the global is just (hi(&g)+lo(&g)). 1088 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1089 } 1090 1091 if (TM.getRelocationModel() == Reloc::PIC_) { 1092 // With PIC, the first instruction is actually "GR+hi(&G)". 1093 Hi = DAG.getNode(ISD::ADD, PtrVT, 1094 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1095 } 1096 1097 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1098 return Lo; 1099} 1100 1101SDOperand PPCTargetLowering::LowerGlobalTLSAddress(SDOperand Op, 1102 SelectionDAG &DAG) { 1103 assert(0 && "TLS not implemented for PPC."); 1104} 1105 1106SDOperand PPCTargetLowering::LowerGlobalAddress(SDOperand Op, 1107 SelectionDAG &DAG) { 1108 MVT::ValueType PtrVT = Op.getValueType(); 1109 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1110 GlobalValue *GV = GSDN->getGlobal(); 1111 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); 1112 // If it's a debug information descriptor, don't mess with it. 1113 if (DAG.isVerifiedDebugInfoDesc(Op)) 1114 return GA; 1115 SDOperand Zero = DAG.getConstant(0, PtrVT); 1116 1117 const TargetMachine &TM = DAG.getTarget(); 1118 1119 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); 1120 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); 1121 1122 // If this is a non-darwin platform, we don't support non-static relo models 1123 // yet. 1124 if (TM.getRelocationModel() == Reloc::Static || 1125 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1126 // Generate non-pic code that has direct accesses to globals. 1127 // The address of the global is just (hi(&g)+lo(&g)). 1128 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1129 } 1130 1131 if (TM.getRelocationModel() == Reloc::PIC_) { 1132 // With PIC, the first instruction is actually "GR+hi(&G)". 1133 Hi = DAG.getNode(ISD::ADD, PtrVT, 1134 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1135 } 1136 1137 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1138 1139 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV)) 1140 return Lo; 1141 1142 // If the global is weak or external, we have to go through the lazy 1143 // resolution stub. 1144 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); 1145} 1146 1147SDOperand PPCTargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) { 1148 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1149 1150 // If we're comparing for equality to zero, expose the fact that this is 1151 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1152 // fold the new nodes. 1153 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1154 if (C->isNullValue() && CC == ISD::SETEQ) { 1155 MVT::ValueType VT = Op.getOperand(0).getValueType(); 1156 SDOperand Zext = Op.getOperand(0); 1157 if (VT < MVT::i32) { 1158 VT = MVT::i32; 1159 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); 1160 } 1161 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); 1162 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); 1163 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, 1164 DAG.getConstant(Log2b, MVT::i32)); 1165 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); 1166 } 1167 // Leave comparisons against 0 and -1 alone for now, since they're usually 1168 // optimized. FIXME: revisit this when we can custom lower all setcc 1169 // optimizations. 1170 if (C->isAllOnesValue() || C->isNullValue()) 1171 return SDOperand(); 1172 } 1173 1174 // If we have an integer seteq/setne, turn it into a compare against zero 1175 // by xor'ing the rhs with the lhs, which is faster than setting a 1176 // condition register, reading it back out, and masking the correct bit. The 1177 // normal approach here uses sub to do this instead of xor. Using xor exposes 1178 // the result to other bit-twiddling opportunities. 1179 MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); 1180 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1181 MVT::ValueType VT = Op.getValueType(); 1182 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), 1183 Op.getOperand(1)); 1184 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); 1185 } 1186 return SDOperand(); 1187} 1188 1189SDOperand PPCTargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG, 1190 int VarArgsFrameIndex, 1191 int VarArgsStackOffset, 1192 unsigned VarArgsNumGPR, 1193 unsigned VarArgsNumFPR, 1194 const PPCSubtarget &Subtarget) { 1195 1196 assert(0 && "VAARG in ELF32 ABI not implemented yet!"); 1197} 1198 1199SDOperand PPCTargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG, 1200 int VarArgsFrameIndex, 1201 int VarArgsStackOffset, 1202 unsigned VarArgsNumGPR, 1203 unsigned VarArgsNumFPR, 1204 const PPCSubtarget &Subtarget) { 1205 1206 if (Subtarget.isMachoABI()) { 1207 // vastart just stores the address of the VarArgsFrameIndex slot into the 1208 // memory location argument. 1209 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1210 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1211 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1212 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); 1213 } 1214 1215 // For ELF 32 ABI we follow the layout of the va_list struct. 1216 // We suppose the given va_list is already allocated. 1217 // 1218 // typedef struct { 1219 // char gpr; /* index into the array of 8 GPRs 1220 // * stored in the register save area 1221 // * gpr=0 corresponds to r3, 1222 // * gpr=1 to r4, etc. 1223 // */ 1224 // char fpr; /* index into the array of 8 FPRs 1225 // * stored in the register save area 1226 // * fpr=0 corresponds to f1, 1227 // * fpr=1 to f2, etc. 1228 // */ 1229 // char *overflow_arg_area; 1230 // /* location on stack that holds 1231 // * the next overflow argument 1232 // */ 1233 // char *reg_save_area; 1234 // /* where r3:r10 and f1:f8 (if saved) 1235 // * are stored 1236 // */ 1237 // } va_list[1]; 1238 1239 1240 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8); 1241 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8); 1242 1243 1244 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1245 1246 SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); 1247 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1248 1249 uint64_t FrameOffset = MVT::getSizeInBits(PtrVT)/8; 1250 SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1251 1252 uint64_t StackOffset = MVT::getSizeInBits(PtrVT)/8 - 1; 1253 SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1254 1255 uint64_t FPROffset = 1; 1256 SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1257 1258 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1259 1260 // Store first byte : number of int regs 1261 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, 1262 Op.getOperand(1), SV, 0); 1263 uint64_t nextOffset = FPROffset; 1264 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), 1265 ConstFPROffset); 1266 1267 // Store second byte : number of float regs 1268 SDOperand secondStore = 1269 DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset); 1270 nextOffset += StackOffset; 1271 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset); 1272 1273 // Store second word : arguments given on stack 1274 SDOperand thirdStore = 1275 DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset); 1276 nextOffset += FrameOffset; 1277 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset); 1278 1279 // Store third word : arguments given in registers 1280 return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset); 1281 1282} 1283 1284#include "PPCGenCallingConv.inc" 1285 1286/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1287/// depending on which subtarget is selected. 1288static const unsigned *GetFPR(const PPCSubtarget &Subtarget) { 1289 if (Subtarget.isMachoABI()) { 1290 static const unsigned FPR[] = { 1291 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1292 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1293 }; 1294 return FPR; 1295 } 1296 1297 1298 static const unsigned FPR[] = { 1299 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1300 PPC::F8 1301 }; 1302 return FPR; 1303} 1304 1305SDOperand 1306PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, 1307 SelectionDAG &DAG, 1308 int &VarArgsFrameIndex, 1309 int &VarArgsStackOffset, 1310 unsigned &VarArgsNumGPR, 1311 unsigned &VarArgsNumFPR, 1312 const PPCSubtarget &Subtarget) { 1313 // TODO: add description of PPC stack frame format, or at least some docs. 1314 // 1315 MachineFunction &MF = DAG.getMachineFunction(); 1316 MachineFrameInfo *MFI = MF.getFrameInfo(); 1317 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 1318 SmallVector<SDOperand, 8> ArgValues; 1319 SDOperand Root = Op.getOperand(0); 1320 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1321 1322 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1323 bool isPPC64 = PtrVT == MVT::i64; 1324 bool isMachoABI = Subtarget.isMachoABI(); 1325 bool isELF32_ABI = Subtarget.isELF32_ABI(); 1326 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1327 1328 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1329 1330 static const unsigned GPR_32[] = { // 32-bit registers. 1331 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1332 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1333 }; 1334 static const unsigned GPR_64[] = { // 64-bit registers. 1335 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1336 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1337 }; 1338 1339 static const unsigned *FPR = GetFPR(Subtarget); 1340 1341 static const unsigned VR[] = { 1342 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1343 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1344 }; 1345 1346 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 1347 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8; 1348 const unsigned Num_VR_Regs = array_lengthof( VR); 1349 1350 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1351 1352 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1353 1354 // Add DAG nodes to load the arguments or copy them out of registers. On 1355 // entry to a function on PPC, the arguments start after the linkage area, 1356 // although the first ones are often in registers. 1357 // 1358 // In the ELF 32 ABI, GPRs and stack are double word align: an argument 1359 // represented with two words (long long or double) must be copied to an 1360 // even GPR_idx value or to an even ArgOffset value. 1361 1362 SmallVector<SDOperand, 8> MemOps; 1363 1364 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { 1365 SDOperand ArgVal; 1366 bool needsLoad = false; 1367 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); 1368 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; 1369 unsigned ArgSize = ObjSize; 1370 ISD::ParamFlags::ParamFlagsTy Flags = 1371 cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue(); 1372 unsigned AlignFlag = ISD::ParamFlags::One 1373 << ISD::ParamFlags::OrigAlignmentOffs; 1374 unsigned isByVal = Flags & ISD::ParamFlags::ByVal; 1375 // See if next argument requires stack alignment in ELF 1376 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) && 1377 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) && 1378 (!(Flags & AlignFlag))); 1379 1380 unsigned CurArgOffset = ArgOffset; 1381 1382 // FIXME alignment for ELF may not be right 1383 // FIXME the codegen can be much improved in some cases. 1384 // We do not have to keep everything in memory. 1385 if (isByVal) { 1386 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 1387 ObjSize = (Flags & ISD::ParamFlags::ByValSize) >> 1388 ISD::ParamFlags::ByValSizeOffs; 1389 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1390 // Double word align in ELF 1391 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2); 1392 // Objects of size 1 and 2 are right justified, everything else is 1393 // left justified. This means the memory address is adjusted forwards. 1394 if (ObjSize==1 || ObjSize==2) { 1395 CurArgOffset = CurArgOffset + (4 - ObjSize); 1396 } 1397 // The value of the object is its address. 1398 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset); 1399 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); 1400 ArgValues.push_back(FIN); 1401 if (ObjSize==1 || ObjSize==2) { 1402 if (GPR_idx != Num_GPR_Regs) { 1403 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1404 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1405 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 1406 SDOperand Store = DAG.getTruncStore(Val.getValue(1), Val, FIN, 1407 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 ); 1408 MemOps.push_back(Store); 1409 ++GPR_idx; 1410 if (isMachoABI) ArgOffset += PtrByteSize; 1411 } else { 1412 ArgOffset += PtrByteSize; 1413 } 1414 continue; 1415 } 1416 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 1417 // Store whatever pieces of the object are in registers 1418 // to memory. ArgVal will be address of the beginning of 1419 // the object. 1420 if (GPR_idx != Num_GPR_Regs) { 1421 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1422 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1423 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset); 1424 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); 1425 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 1426 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1427 MemOps.push_back(Store); 1428 ++GPR_idx; 1429 if (isMachoABI) ArgOffset += PtrByteSize; 1430 } else { 1431 ArgOffset += ArgSize - (ArgOffset-CurArgOffset); 1432 break; 1433 } 1434 } 1435 continue; 1436 } 1437 1438 switch (ObjectVT) { 1439 default: assert(0 && "Unhandled argument type!"); 1440 case MVT::i32: 1441 if (!isPPC64) { 1442 // Double word align in ELF 1443 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2); 1444 1445 if (GPR_idx != Num_GPR_Regs) { 1446 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1447 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1448 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1449 ++GPR_idx; 1450 } else { 1451 needsLoad = true; 1452 ArgSize = PtrByteSize; 1453 } 1454 // Stack align in ELF 1455 if (needsLoad && Expand && isELF32_ABI) 1456 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1457 // All int arguments reserve stack space in Macho ABI. 1458 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize; 1459 break; 1460 } 1461 // FALLTHROUGH 1462 case MVT::i64: // PPC64 1463 if (GPR_idx != Num_GPR_Regs) { 1464 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); 1465 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1466 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); 1467 1468 if (ObjectVT == MVT::i32) { 1469 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 1470 // value to MVT::i64 and then truncate to the correct register size. 1471 if (Flags & ISD::ParamFlags::SExt) 1472 ArgVal = DAG.getNode(ISD::AssertSext, MVT::i64, ArgVal, 1473 DAG.getValueType(ObjectVT)); 1474 else if (Flags & ISD::ParamFlags::ZExt) 1475 ArgVal = DAG.getNode(ISD::AssertZext, MVT::i64, ArgVal, 1476 DAG.getValueType(ObjectVT)); 1477 1478 ArgVal = DAG.getNode(ISD::TRUNCATE, MVT::i32, ArgVal); 1479 } 1480 1481 ++GPR_idx; 1482 } else { 1483 needsLoad = true; 1484 } 1485 // All int arguments reserve stack space in Macho ABI. 1486 if (isMachoABI || needsLoad) ArgOffset += 8; 1487 break; 1488 1489 case MVT::f32: 1490 case MVT::f64: 1491 // Every 4 bytes of argument space consumes one of the GPRs available for 1492 // argument passing. 1493 if (GPR_idx != Num_GPR_Regs && isMachoABI) { 1494 ++GPR_idx; 1495 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 1496 ++GPR_idx; 1497 } 1498 if (FPR_idx != Num_FPR_Regs) { 1499 unsigned VReg; 1500 if (ObjectVT == MVT::f32) 1501 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass); 1502 else 1503 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); 1504 RegInfo.addLiveIn(FPR[FPR_idx], VReg); 1505 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1506 ++FPR_idx; 1507 } else { 1508 needsLoad = true; 1509 } 1510 1511 // Stack align in ELF 1512 if (needsLoad && Expand && isELF32_ABI) 1513 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1514 // All FP arguments reserve stack space in Macho ABI. 1515 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize; 1516 break; 1517 case MVT::v4f32: 1518 case MVT::v4i32: 1519 case MVT::v8i16: 1520 case MVT::v16i8: 1521 // Note that vector arguments in registers don't reserve stack space, 1522 // except in varargs functions. 1523 if (VR_idx != Num_VR_Regs) { 1524 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass); 1525 RegInfo.addLiveIn(VR[VR_idx], VReg); 1526 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1527 if (isVarArg) { 1528 while ((ArgOffset % 16) != 0) { 1529 ArgOffset += PtrByteSize; 1530 if (GPR_idx != Num_GPR_Regs) 1531 GPR_idx++; 1532 } 1533 ArgOffset += 16; 1534 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); 1535 } 1536 ++VR_idx; 1537 } else { 1538 // Stack offset is aligned. 1539 while (ArgOffset % 16 !=0) { 1540 ArgOffset += PtrByteSize; 1541 } 1542 ArgOffset += 16; 1543 needsLoad = true; 1544 } 1545 break; 1546 } 1547 1548 // We need to load the argument to a virtual register if we determined above 1549 // that we ran out of physical registers of the appropriate type. 1550 if (needsLoad) { 1551 int FI = MFI->CreateFixedObject(ObjSize, 1552 CurArgOffset + (ArgSize - ObjSize)); 1553 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); 1554 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 1555 } 1556 1557 ArgValues.push_back(ArgVal); 1558 } 1559 1560 // If the function takes variable number of arguments, make a frame index for 1561 // the start of the first vararg value... for expansion of llvm.va_start. 1562 if (isVarArg) { 1563 1564 int depth; 1565 if (isELF32_ABI) { 1566 VarArgsNumGPR = GPR_idx; 1567 VarArgsNumFPR = FPR_idx; 1568 1569 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame 1570 // pointer. 1571 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 + 1572 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 + 1573 MVT::getSizeInBits(PtrVT)/8); 1574 1575 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, 1576 ArgOffset); 1577 1578 } 1579 else 1580 depth = ArgOffset; 1581 1582 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, 1583 depth); 1584 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1585 1586 // In ELF 32 ABI, the fixed integer arguments of a variadic function are 1587 // stored to the VarArgsFrameIndex on the stack. 1588 if (isELF32_ABI) { 1589 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) { 1590 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT); 1591 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); 1592 MemOps.push_back(Store); 1593 // Increment the address by four for the next argument to store 1594 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); 1595 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1596 } 1597 } 1598 1599 // If this function is vararg, store any remaining integer argument regs 1600 // to their spots on the stack so that they may be loaded by deferencing the 1601 // result of va_next. 1602 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 1603 unsigned VReg; 1604 if (isPPC64) 1605 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); 1606 else 1607 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1608 1609 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1610 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 1611 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1612 MemOps.push_back(Store); 1613 // Increment the address by four for the next argument to store 1614 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); 1615 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1616 } 1617 1618 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex 1619 // on the stack. 1620 if (isELF32_ABI) { 1621 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) { 1622 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64); 1623 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); 1624 MemOps.push_back(Store); 1625 // Increment the address by eight for the next argument to store 1626 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, 1627 PtrVT); 1628 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1629 } 1630 1631 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) { 1632 unsigned VReg; 1633 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); 1634 1635 RegInfo.addLiveIn(FPR[FPR_idx], VReg); 1636 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64); 1637 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1638 MemOps.push_back(Store); 1639 // Increment the address by eight for the next argument to store 1640 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, 1641 PtrVT); 1642 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1643 } 1644 } 1645 } 1646 1647 if (!MemOps.empty()) 1648 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); 1649 1650 ArgValues.push_back(Root); 1651 1652 // Return the new list of results. 1653 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 1654 Op.Val->value_end()); 1655 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); 1656} 1657 1658/// isCallCompatibleAddress - Return the immediate to use if the specified 1659/// 32-bit value is representable in the immediate field of a BxA instruction. 1660static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) { 1661 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1662 if (!C) return 0; 1663 1664 int Addr = C->getValue(); 1665 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 1666 (Addr << 6 >> 6) != Addr) 1667 return 0; // Top 6 bits have to be sext of immediate. 1668 1669 return DAG.getConstant((int)C->getValue() >> 2, 1670 DAG.getTargetLoweringInfo().getPointerTy()).Val; 1671} 1672 1673/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1674/// by "Src" to address "Dst" of size "Size". Alignment information is 1675/// specified by the specific parameter attribute. The copy will be passed as 1676/// a byval function parameter. 1677/// Sometimes what we are copying is the end of a larger object, the part that 1678/// does not fit in registers. 1679static SDOperand 1680CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain, 1681 ISD::ParamFlags::ParamFlagsTy Flags, 1682 SelectionDAG &DAG, unsigned Size) { 1683 unsigned Align = ISD::ParamFlags::One << 1684 ((Flags & ISD::ParamFlags::ByValAlign) >> ISD::ParamFlags::ByValAlignOffs); 1685 SDOperand AlignNode = DAG.getConstant(Align, MVT::i32); 1686 SDOperand SizeNode = DAG.getConstant(Size, MVT::i32); 1687 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i32); 1688 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, AlignNode, AlwaysInline); 1689} 1690 1691SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, 1692 const PPCSubtarget &Subtarget) { 1693 SDOperand Chain = Op.getOperand(0); 1694 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1695 SDOperand Callee = Op.getOperand(4); 1696 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 1697 1698 bool isMachoABI = Subtarget.isMachoABI(); 1699 bool isELF32_ABI = Subtarget.isELF32_ABI(); 1700 1701 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1702 bool isPPC64 = PtrVT == MVT::i64; 1703 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1704 1705 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in 1706 // SelectExpr to use to put the arguments in the appropriate registers. 1707 std::vector<SDOperand> args_to_use; 1708 1709 // Count how many bytes are to be pushed on the stack, including the linkage 1710 // area, and parameter passing area. We start with 24/48 bytes, which is 1711 // prereserved space for [SP][CR][LR][3 x unused]. 1712 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1713 1714 // Add up all the space actually used. 1715 for (unsigned i = 0; i != NumOps; ++i) { 1716 SDOperand Arg = Op.getOperand(5+2*i); 1717 MVT::ValueType ArgVT = Arg.getValueType(); 1718 // Non-varargs Altivec parameters do not have corresponding stack space. 1719 if (!isVarArg && 1720 (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 1721 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8)) 1722 continue; 1723 ISD::ParamFlags::ParamFlagsTy Flags = 1724 cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue(); 1725 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8; 1726 if (Flags & ISD::ParamFlags::ByVal) 1727 ArgSize = (Flags & ISD::ParamFlags::ByValSize) >> 1728 ISD::ParamFlags::ByValSizeOffs; 1729 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1730 // Varargs Altivec parameters are padded to a 16 byte boundary. 1731 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 1732 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) 1733 NumBytes = ((NumBytes+15)/16)*16; 1734 NumBytes += ArgSize; 1735 } 1736 1737 // The prolog code of the callee may store up to 8 GPR argument registers to 1738 // the stack, allowing va_start to index over them in memory if its varargs. 1739 // Because we cannot tell if this is needed on the caller side, we have to 1740 // conservatively assume that it is needed. As such, make sure we have at 1741 // least enough stack space for the caller to store the 8 GPRs. 1742 NumBytes = std::max(NumBytes, 1743 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI)); 1744 1745 // Adjust the stack pointer for the new arguments... 1746 // These operations are automatically eliminated by the prolog/epilog pass 1747 Chain = DAG.getCALLSEQ_START(Chain, 1748 DAG.getConstant(NumBytes, PtrVT)); 1749 SDOperand CallSeqStart = Chain; 1750 1751 // Set up a copy of the stack pointer for use loading and storing any 1752 // arguments that may not fit in the registers available for argument 1753 // passing. 1754 SDOperand StackPtr; 1755 if (isPPC64) 1756 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 1757 else 1758 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 1759 1760 // Figure out which arguments are going to go in registers, and which in 1761 // memory. Also, if this is a vararg function, floating point operations 1762 // must be stored to our stack, and loaded into integer regs as well, if 1763 // any integer regs are available for argument passing. 1764 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1765 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1766 1767 static const unsigned GPR_32[] = { // 32-bit registers. 1768 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1769 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1770 }; 1771 static const unsigned GPR_64[] = { // 64-bit registers. 1772 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1773 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1774 }; 1775 static const unsigned *FPR = GetFPR(Subtarget); 1776 1777 static const unsigned VR[] = { 1778 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1779 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1780 }; 1781 const unsigned NumGPRs = array_lengthof(GPR_32); 1782 const unsigned NumFPRs = isMachoABI ? 13 : 8; 1783 const unsigned NumVRs = array_lengthof( VR); 1784 1785 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1786 1787 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 1788 SmallVector<SDOperand, 8> MemOpChains; 1789 for (unsigned i = 0; i != NumOps; ++i) { 1790 bool inMem = false; 1791 SDOperand Arg = Op.getOperand(5+2*i); 1792 ISD::ParamFlags::ParamFlagsTy Flags = 1793 cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue(); 1794 unsigned AlignFlag = ISD::ParamFlags::One << 1795 ISD::ParamFlags::OrigAlignmentOffs; 1796 // See if next argument requires stack alignment in ELF 1797 unsigned next = 5+2*(i+1)+1; 1798 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) && 1799 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) && 1800 (!(Flags & AlignFlag))); 1801 1802 // PtrOff will be used to store the current argument to the stack if a 1803 // register cannot be found for it. 1804 SDOperand PtrOff; 1805 1806 // Stack align in ELF 32 1807 if (isELF32_ABI && Expand) 1808 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize, 1809 StackPtr.getValueType()); 1810 else 1811 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 1812 1813 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); 1814 1815 // On PPC64, promote integers to 64-bit values. 1816 if (isPPC64 && Arg.getValueType() == MVT::i32) { 1817 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 1818 Arg = DAG.getNode(ExtOp, MVT::i64, Arg); 1819 } 1820 1821 // FIXME Elf untested, what are alignment rules? 1822 // FIXME memcpy is used way more than necessary. Correctness first. 1823 if (Flags & ISD::ParamFlags::ByVal) { 1824 unsigned Size = (Flags & ISD::ParamFlags::ByValSize) >> 1825 ISD::ParamFlags::ByValSizeOffs; 1826 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2); 1827 if (Size==1 || Size==2) { 1828 // Very small objects are passed right-justified. 1829 // Everything else is passed left-justified. 1830 MVT::ValueType VT = (Size==1) ? MVT::i8 : MVT::i16; 1831 if (GPR_idx != NumGPRs) { 1832 SDOperand Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg, 1833 NULL, 0, VT); 1834 MemOpChains.push_back(Load.getValue(1)); 1835 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 1836 if (isMachoABI) 1837 ArgOffset += PtrByteSize; 1838 } else { 1839 SDOperand Const = DAG.getConstant(4 - Size, PtrOff.getValueType()); 1840 SDOperand AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const); 1841 SDOperand MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, 1842 CallSeqStart.Val->getOperand(0), 1843 Flags, DAG, Size); 1844 // This must go outside the CALLSEQ_START..END. 1845 SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 1846 CallSeqStart.Val->getOperand(1)); 1847 DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val); 1848 Chain = CallSeqStart = NewCallSeqStart; 1849 ArgOffset += PtrByteSize; 1850 } 1851 continue; 1852 } 1853 for (unsigned j=0; j<Size; j+=PtrByteSize) { 1854 SDOperand Const = DAG.getConstant(j, PtrOff.getValueType()); 1855 SDOperand AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const); 1856 if (GPR_idx != NumGPRs) { 1857 SDOperand Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0); 1858 MemOpChains.push_back(Load.getValue(1)); 1859 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 1860 if (isMachoABI) 1861 ArgOffset += PtrByteSize; 1862 } else { 1863 SDOperand AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const); 1864 SDOperand MemcpyCall = CreateCopyOfByValArgument(AddArg, AddPtr, 1865 CallSeqStart.Val->getOperand(0), 1866 Flags, DAG, Size - j); 1867 // This must go outside the CALLSEQ_START..END. 1868 SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 1869 CallSeqStart.Val->getOperand(1)); 1870 DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val); 1871 Chain = CallSeqStart = NewCallSeqStart; 1872 ArgOffset += ((Size - j + 3)/4)*4; 1873 break; 1874 } 1875 } 1876 continue; 1877 } 1878 1879 switch (Arg.getValueType()) { 1880 default: assert(0 && "Unexpected ValueType for argument!"); 1881 case MVT::i32: 1882 case MVT::i64: 1883 // Double word align in ELF 1884 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2); 1885 if (GPR_idx != NumGPRs) { 1886 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 1887 } else { 1888 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1889 inMem = true; 1890 } 1891 if (inMem || isMachoABI) { 1892 // Stack align in ELF 1893 if (isELF32_ABI && Expand) 1894 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1895 1896 ArgOffset += PtrByteSize; 1897 } 1898 break; 1899 case MVT::f32: 1900 case MVT::f64: 1901 if (FPR_idx != NumFPRs) { 1902 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 1903 1904 if (isVarArg) { 1905 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); 1906 MemOpChains.push_back(Store); 1907 1908 // Float varargs are always shadowed in available integer registers 1909 if (GPR_idx != NumGPRs) { 1910 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1911 MemOpChains.push_back(Load.getValue(1)); 1912 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 1913 Load)); 1914 } 1915 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 1916 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 1917 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); 1918 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1919 MemOpChains.push_back(Load.getValue(1)); 1920 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 1921 Load)); 1922 } 1923 } else { 1924 // If we have any FPRs remaining, we may also have GPRs remaining. 1925 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 1926 // GPRs. 1927 if (isMachoABI) { 1928 if (GPR_idx != NumGPRs) 1929 ++GPR_idx; 1930 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 1931 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 1932 ++GPR_idx; 1933 } 1934 } 1935 } else { 1936 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1937 inMem = true; 1938 } 1939 if (inMem || isMachoABI) { 1940 // Stack align in ELF 1941 if (isELF32_ABI && Expand) 1942 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1943 if (isPPC64) 1944 ArgOffset += 8; 1945 else 1946 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 1947 } 1948 break; 1949 case MVT::v4f32: 1950 case MVT::v4i32: 1951 case MVT::v8i16: 1952 case MVT::v16i8: 1953 if (isVarArg) { 1954 // These go aligned on the stack, or in the corresponding R registers 1955 // when within range. The Darwin PPC ABI doc claims they also go in 1956 // V registers; in fact gcc does this only for arguments that are 1957 // prototyped, not for those that match the ... We do it for all 1958 // arguments, seems to work. 1959 while (ArgOffset % 16 !=0) { 1960 ArgOffset += PtrByteSize; 1961 if (GPR_idx != NumGPRs) 1962 GPR_idx++; 1963 } 1964 // We could elide this store in the case where the object fits 1965 // entirely in R registers. Maybe later. 1966 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, 1967 DAG.getConstant(ArgOffset, PtrVT)); 1968 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); 1969 MemOpChains.push_back(Store); 1970 if (VR_idx != NumVRs) { 1971 SDOperand Load = DAG.getLoad(MVT::v4f32, Store, PtrOff, NULL, 0); 1972 MemOpChains.push_back(Load.getValue(1)); 1973 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 1974 } 1975 ArgOffset += 16; 1976 for (unsigned i=0; i<16; i+=PtrByteSize) { 1977 if (GPR_idx == NumGPRs) 1978 break; 1979 SDOperand Ix = DAG.getNode(ISD::ADD, PtrVT, PtrOff, 1980 DAG.getConstant(i, PtrVT)); 1981 SDOperand Load = DAG.getLoad(PtrVT, Store, Ix, NULL, 0); 1982 MemOpChains.push_back(Load.getValue(1)); 1983 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 1984 } 1985 break; 1986 } 1987 if (VR_idx == NumVRs) { 1988 // Out of V registers; these go aligned on the stack. 1989 while (ArgOffset % 16 !=0) { 1990 ArgOffset += PtrByteSize; 1991 } 1992 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, 1993 DAG.getConstant(ArgOffset, PtrVT)); 1994 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); 1995 MemOpChains.push_back(Store); 1996 ArgOffset += 16; 1997 } else { 1998 // Doesn't have memory or GPR space allocated 1999 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 2000 } 2001 break; 2002 } 2003 } 2004 if (!MemOpChains.empty()) 2005 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 2006 &MemOpChains[0], MemOpChains.size()); 2007 2008 // Build a sequence of copy-to-reg nodes chained together with token chain 2009 // and flag operands which copy the outgoing args into the appropriate regs. 2010 SDOperand InFlag; 2011 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2012 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 2013 InFlag); 2014 InFlag = Chain.getValue(1); 2015 } 2016 2017 // With the ELF 32 ABI, set CR6 to true if this is a vararg call. 2018 if (isVarArg && isELF32_ABI) { 2019 SDOperand SetCR(DAG.getTargetNode(PPC::CRSET, MVT::i32), 0); 2020 Chain = DAG.getCopyToReg(Chain, PPC::CR1EQ, SetCR, InFlag); 2021 InFlag = Chain.getValue(1); 2022 } 2023 2024 std::vector<MVT::ValueType> NodeTys; 2025 NodeTys.push_back(MVT::Other); // Returns a chain 2026 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 2027 2028 SmallVector<SDOperand, 8> Ops; 2029 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF; 2030 2031 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2032 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2033 // node so that legalize doesn't hack it. 2034 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2035 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); 2036 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 2037 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); 2038 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) 2039 // If this is an absolute destination address, use the munged value. 2040 Callee = SDOperand(Dest, 0); 2041 else { 2042 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 2043 // to do the call, we can't use PPCISD::CALL. 2044 SDOperand MTCTROps[] = {Chain, Callee, InFlag}; 2045 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0)); 2046 InFlag = Chain.getValue(1); 2047 2048 // Copy the callee address into R12/X12 on darwin. 2049 if (isMachoABI) { 2050 unsigned Reg = Callee.getValueType() == MVT::i32 ? PPC::R12 : PPC::X12; 2051 Chain = DAG.getCopyToReg(Chain, Reg, Callee, InFlag); 2052 InFlag = Chain.getValue(1); 2053 } 2054 2055 NodeTys.clear(); 2056 NodeTys.push_back(MVT::Other); 2057 NodeTys.push_back(MVT::Flag); 2058 Ops.push_back(Chain); 2059 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF; 2060 Callee.Val = 0; 2061 } 2062 2063 // If this is a direct call, pass the chain and the callee. 2064 if (Callee.Val) { 2065 Ops.push_back(Chain); 2066 Ops.push_back(Callee); 2067 } 2068 2069 // Add argument registers to the end of the list so that they are known live 2070 // into the call. 2071 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2072 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2073 RegsToPass[i].second.getValueType())); 2074 2075 if (InFlag.Val) 2076 Ops.push_back(InFlag); 2077 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 2078 InFlag = Chain.getValue(1); 2079 2080 Chain = DAG.getCALLSEQ_END(Chain, 2081 DAG.getConstant(NumBytes, PtrVT), 2082 DAG.getConstant(0, PtrVT), 2083 InFlag); 2084 if (Op.Val->getValueType(0) != MVT::Other) 2085 InFlag = Chain.getValue(1); 2086 2087 SDOperand ResultVals[3]; 2088 unsigned NumResults = 0; 2089 NodeTys.clear(); 2090 2091 // If the call has results, copy the values out of the ret val registers. 2092 switch (Op.Val->getValueType(0)) { 2093 default: assert(0 && "Unexpected ret value!"); 2094 case MVT::Other: break; 2095 case MVT::i32: 2096 if (Op.Val->getValueType(1) == MVT::i32) { 2097 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); 2098 ResultVals[0] = Chain.getValue(0); 2099 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, 2100 Chain.getValue(2)).getValue(1); 2101 ResultVals[1] = Chain.getValue(0); 2102 NumResults = 2; 2103 NodeTys.push_back(MVT::i32); 2104 } else { 2105 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); 2106 ResultVals[0] = Chain.getValue(0); 2107 NumResults = 1; 2108 } 2109 NodeTys.push_back(MVT::i32); 2110 break; 2111 case MVT::i64: 2112 if (Op.Val->getValueType(1) == MVT::i64) { 2113 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1); 2114 ResultVals[0] = Chain.getValue(0); 2115 Chain = DAG.getCopyFromReg(Chain, PPC::X4, MVT::i64, 2116 Chain.getValue(2)).getValue(1); 2117 ResultVals[1] = Chain.getValue(0); 2118 NumResults = 2; 2119 NodeTys.push_back(MVT::i64); 2120 } else { 2121 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1); 2122 ResultVals[0] = Chain.getValue(0); 2123 NumResults = 1; 2124 } 2125 NodeTys.push_back(MVT::i64); 2126 break; 2127 case MVT::f64: 2128 if (Op.Val->getValueType(1) == MVT::f64) { 2129 Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1); 2130 ResultVals[0] = Chain.getValue(0); 2131 Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64, 2132 Chain.getValue(2)).getValue(1); 2133 ResultVals[1] = Chain.getValue(0); 2134 NumResults = 2; 2135 NodeTys.push_back(MVT::f64); 2136 NodeTys.push_back(MVT::f64); 2137 break; 2138 } 2139 // else fall through 2140 case MVT::f32: 2141 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0), 2142 InFlag).getValue(1); 2143 ResultVals[0] = Chain.getValue(0); 2144 NumResults = 1; 2145 NodeTys.push_back(Op.Val->getValueType(0)); 2146 break; 2147 case MVT::v4f32: 2148 case MVT::v4i32: 2149 case MVT::v8i16: 2150 case MVT::v16i8: 2151 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0), 2152 InFlag).getValue(1); 2153 ResultVals[0] = Chain.getValue(0); 2154 NumResults = 1; 2155 NodeTys.push_back(Op.Val->getValueType(0)); 2156 break; 2157 } 2158 2159 NodeTys.push_back(MVT::Other); 2160 2161 // If the function returns void, just return the chain. 2162 if (NumResults == 0) 2163 return Chain; 2164 2165 // Otherwise, merge everything together with a MERGE_VALUES node. 2166 ResultVals[NumResults++] = Chain; 2167 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, 2168 ResultVals, NumResults); 2169 return Res.getValue(Op.ResNo); 2170} 2171 2172SDOperand PPCTargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG, 2173 TargetMachine &TM) { 2174 SmallVector<CCValAssign, 16> RVLocs; 2175 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 2176 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 2177 CCState CCInfo(CC, isVarArg, TM, RVLocs); 2178 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC); 2179 2180 // If this is the first return lowered for this function, add the regs to the 2181 // liveout set for the function. 2182 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2183 for (unsigned i = 0; i != RVLocs.size(); ++i) 2184 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2185 } 2186 2187 SDOperand Chain = Op.getOperand(0); 2188 SDOperand Flag; 2189 2190 // Copy the result values into the output registers. 2191 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2192 CCValAssign &VA = RVLocs[i]; 2193 assert(VA.isRegLoc() && "Can only return in registers!"); 2194 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); 2195 Flag = Chain.getValue(1); 2196 } 2197 2198 if (Flag.Val) 2199 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag); 2200 else 2201 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain); 2202} 2203 2204SDOperand PPCTargetLowering::LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, 2205 const PPCSubtarget &Subtarget) { 2206 // When we pop the dynamic allocation we need to restore the SP link. 2207 2208 // Get the corect type for pointers. 2209 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2210 2211 // Construct the stack pointer operand. 2212 bool IsPPC64 = Subtarget.isPPC64(); 2213 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1; 2214 SDOperand StackPtr = DAG.getRegister(SP, PtrVT); 2215 2216 // Get the operands for the STACKRESTORE. 2217 SDOperand Chain = Op.getOperand(0); 2218 SDOperand SaveSP = Op.getOperand(1); 2219 2220 // Load the old link SP. 2221 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0); 2222 2223 // Restore the stack pointer. 2224 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP); 2225 2226 // Store the old link SP. 2227 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0); 2228} 2229 2230SDOperand PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op, 2231 SelectionDAG &DAG, 2232 const PPCSubtarget &Subtarget) { 2233 MachineFunction &MF = DAG.getMachineFunction(); 2234 bool IsPPC64 = Subtarget.isPPC64(); 2235 bool isMachoABI = Subtarget.isMachoABI(); 2236 2237 // Get current frame pointer save index. The users of this index will be 2238 // primarily DYNALLOC instructions. 2239 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2240 int FPSI = FI->getFramePointerSaveIndex(); 2241 2242 // If the frame pointer save index hasn't been defined yet. 2243 if (!FPSI) { 2244 // Find out what the fix offset of the frame pointer save area. 2245 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI); 2246 2247 // Allocate the frame index for frame pointer save area. 2248 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 2249 // Save the result. 2250 FI->setFramePointerSaveIndex(FPSI); 2251 } 2252 2253 // Get the inputs. 2254 SDOperand Chain = Op.getOperand(0); 2255 SDOperand Size = Op.getOperand(1); 2256 2257 // Get the corect type for pointers. 2258 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2259 // Negate the size. 2260 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT, 2261 DAG.getConstant(0, PtrVT), Size); 2262 // Construct a node for the frame pointer save index. 2263 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT); 2264 // Build a DYNALLOC node. 2265 SDOperand Ops[3] = { Chain, NegSize, FPSIdx }; 2266 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 2267 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3); 2268} 2269 2270 2271/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 2272/// possible. 2273SDOperand PPCTargetLowering::LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { 2274 // Not FP? Not a fsel. 2275 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 2276 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 2277 return SDOperand(); 2278 2279 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2280 2281 // Cannot handle SETEQ/SETNE. 2282 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand(); 2283 2284 MVT::ValueType ResVT = Op.getValueType(); 2285 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 2286 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2287 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 2288 2289 // If the RHS of the comparison is a 0.0, we don't need to do the 2290 // subtraction at all. 2291 if (isFloatingPointZero(RHS)) 2292 switch (CC) { 2293 default: break; // SETUO etc aren't handled by fsel. 2294 case ISD::SETULT: 2295 case ISD::SETOLT: 2296 case ISD::SETLT: 2297 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 2298 case ISD::SETUGE: 2299 case ISD::SETOGE: 2300 case ISD::SETGE: 2301 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 2302 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 2303 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 2304 case ISD::SETUGT: 2305 case ISD::SETOGT: 2306 case ISD::SETGT: 2307 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 2308 case ISD::SETULE: 2309 case ISD::SETOLE: 2310 case ISD::SETLE: 2311 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 2312 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 2313 return DAG.getNode(PPCISD::FSEL, ResVT, 2314 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 2315 } 2316 2317 SDOperand Cmp; 2318 switch (CC) { 2319 default: break; // SETUO etc aren't handled by fsel. 2320 case ISD::SETULT: 2321 case ISD::SETOLT: 2322 case ISD::SETLT: 2323 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2324 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2325 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2326 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2327 case ISD::SETUGE: 2328 case ISD::SETOGE: 2329 case ISD::SETGE: 2330 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2331 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2332 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2333 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2334 case ISD::SETUGT: 2335 case ISD::SETOGT: 2336 case ISD::SETGT: 2337 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2338 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2339 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2340 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2341 case ISD::SETULE: 2342 case ISD::SETOLE: 2343 case ISD::SETLE: 2344 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2345 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2346 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2347 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2348 } 2349 return SDOperand(); 2350} 2351 2352// FIXME: Split this code up when LegalizeDAGTypes lands. 2353SDOperand PPCTargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 2354 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 2355 SDOperand Src = Op.getOperand(0); 2356 if (Src.getValueType() == MVT::f32) 2357 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 2358 2359 SDOperand Tmp; 2360 switch (Op.getValueType()) { 2361 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 2362 case MVT::i32: 2363 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 2364 break; 2365 case MVT::i64: 2366 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 2367 break; 2368 } 2369 2370 // Convert the FP value to an int value through memory. 2371 SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64); 2372 2373 // Emit a store to the stack slot. 2374 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0); 2375 2376 // Result is a load from the stack slot. If loading 4 bytes, make sure to 2377 // add in a bias. 2378 if (Op.getValueType() == MVT::i32) 2379 FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, 2380 DAG.getConstant(4, FIPtr.getValueType())); 2381 return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0); 2382} 2383 2384SDOperand PPCTargetLowering::LowerFP_ROUND_INREG(SDOperand Op, 2385 SelectionDAG &DAG) { 2386 assert(Op.getValueType() == MVT::ppcf128); 2387 SDNode *Node = Op.Val; 2388 assert(Node->getOperand(0).getValueType() == MVT::ppcf128); 2389 assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR); 2390 SDOperand Lo = Node->getOperand(0).Val->getOperand(0); 2391 SDOperand Hi = Node->getOperand(0).Val->getOperand(1); 2392 2393 // This sequence changes FPSCR to do round-to-zero, adds the two halves 2394 // of the long double, and puts FPSCR back the way it was. We do not 2395 // actually model FPSCR. 2396 std::vector<MVT::ValueType> NodeTys; 2397 SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg; 2398 2399 NodeTys.push_back(MVT::f64); // Return register 2400 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns 2401 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); 2402 MFFSreg = Result.getValue(0); 2403 InFlag = Result.getValue(1); 2404 2405 NodeTys.clear(); 2406 NodeTys.push_back(MVT::Flag); // Returns a flag 2407 Ops[0] = DAG.getConstant(31, MVT::i32); 2408 Ops[1] = InFlag; 2409 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2); 2410 InFlag = Result.getValue(0); 2411 2412 NodeTys.clear(); 2413 NodeTys.push_back(MVT::Flag); // Returns a flag 2414 Ops[0] = DAG.getConstant(30, MVT::i32); 2415 Ops[1] = InFlag; 2416 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2); 2417 InFlag = Result.getValue(0); 2418 2419 NodeTys.clear(); 2420 NodeTys.push_back(MVT::f64); // result of add 2421 NodeTys.push_back(MVT::Flag); // Returns a flag 2422 Ops[0] = Lo; 2423 Ops[1] = Hi; 2424 Ops[2] = InFlag; 2425 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3); 2426 FPreg = Result.getValue(0); 2427 InFlag = Result.getValue(1); 2428 2429 NodeTys.clear(); 2430 NodeTys.push_back(MVT::f64); 2431 Ops[0] = DAG.getConstant(1, MVT::i32); 2432 Ops[1] = MFFSreg; 2433 Ops[2] = FPreg; 2434 Ops[3] = InFlag; 2435 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4); 2436 FPreg = Result.getValue(0); 2437 2438 // We know the low half is about to be thrown away, so just use something 2439 // convenient. 2440 return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg); 2441} 2442 2443SDOperand PPCTargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 2444 // Don't handle ppc_fp128 here; let it be lowered to a libcall. 2445 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) 2446 return SDOperand(); 2447 2448 if (Op.getOperand(0).getValueType() == MVT::i64) { 2449 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 2450 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 2451 if (Op.getValueType() == MVT::f32) 2452 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); 2453 return FP; 2454 } 2455 2456 assert(Op.getOperand(0).getValueType() == MVT::i32 && 2457 "Unhandled SINT_TO_FP type in custom expander!"); 2458 // Since we only generate this in 64-bit mode, we can take advantage of 2459 // 64-bit registers. In particular, sign extend the input value into the 2460 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 2461 // then lfd it and fcfid it. 2462 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2463 int FrameIdx = FrameInfo->CreateStackObject(8, 8); 2464 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2465 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2466 2467 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, 2468 Op.getOperand(0)); 2469 2470 // STD the extended value into the stack slot. 2471 MemOperand MO(PseudoSourceValue::getFixedStack(), 2472 MemOperand::MOStore, FrameIdx, 8, 8); 2473 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, 2474 DAG.getEntryNode(), Ext64, FIdx, 2475 DAG.getMemOperand(MO)); 2476 // Load the value as a double. 2477 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); 2478 2479 // FCFID it and return it. 2480 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); 2481 if (Op.getValueType() == MVT::f32) 2482 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); 2483 return FP; 2484} 2485 2486SDOperand PPCTargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) { 2487 /* 2488 The rounding mode is in bits 30:31 of FPSR, and has the following 2489 settings: 2490 00 Round to nearest 2491 01 Round to 0 2492 10 Round to +inf 2493 11 Round to -inf 2494 2495 FLT_ROUNDS, on the other hand, expects the following: 2496 -1 Undefined 2497 0 Round to 0 2498 1 Round to nearest 2499 2 Round to +inf 2500 3 Round to -inf 2501 2502 To perform the conversion, we do: 2503 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 2504 */ 2505 2506 MachineFunction &MF = DAG.getMachineFunction(); 2507 MVT::ValueType VT = Op.getValueType(); 2508 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2509 std::vector<MVT::ValueType> NodeTys; 2510 SDOperand MFFSreg, InFlag; 2511 2512 // Save FP Control Word to register 2513 NodeTys.push_back(MVT::f64); // return register 2514 NodeTys.push_back(MVT::Flag); // unused in this context 2515 SDOperand Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); 2516 2517 // Save FP register to stack slot 2518 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 2519 SDOperand StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 2520 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Chain, 2521 StackSlot, NULL, 0); 2522 2523 // Load FP Control Word from low 32 bits of stack slot. 2524 SDOperand Four = DAG.getConstant(4, PtrVT); 2525 SDOperand Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four); 2526 SDOperand CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0); 2527 2528 // Transform as necessary 2529 SDOperand CWD1 = 2530 DAG.getNode(ISD::AND, MVT::i32, 2531 CWD, DAG.getConstant(3, MVT::i32)); 2532 SDOperand CWD2 = 2533 DAG.getNode(ISD::SRL, MVT::i32, 2534 DAG.getNode(ISD::AND, MVT::i32, 2535 DAG.getNode(ISD::XOR, MVT::i32, 2536 CWD, DAG.getConstant(3, MVT::i32)), 2537 DAG.getConstant(3, MVT::i32)), 2538 DAG.getConstant(1, MVT::i8)); 2539 2540 SDOperand RetVal = 2541 DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2); 2542 2543 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ? 2544 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); 2545} 2546 2547SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { 2548 MVT::ValueType VT = Op.getValueType(); 2549 unsigned BitWidth = MVT::getSizeInBits(VT); 2550 assert(Op.getNumOperands() == 3 && 2551 VT == Op.getOperand(1).getValueType() && 2552 "Unexpected SHL!"); 2553 2554 // Expand into a bunch of logical ops. Note that these ops 2555 // depend on the PPC behavior for oversized shift amounts. 2556 SDOperand Lo = Op.getOperand(0); 2557 SDOperand Hi = Op.getOperand(1); 2558 SDOperand Amt = Op.getOperand(2); 2559 MVT::ValueType AmtVT = Amt.getValueType(); 2560 2561 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT, 2562 DAG.getConstant(BitWidth, AmtVT), Amt); 2563 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt); 2564 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1); 2565 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); 2566 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, 2567 DAG.getConstant(-BitWidth, AmtVT)); 2568 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5); 2569 SDOperand OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); 2570 SDOperand OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt); 2571 SDOperand OutOps[] = { OutLo, OutHi }; 2572 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT), 2573 OutOps, 2); 2574} 2575 2576SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { 2577 MVT::ValueType VT = Op.getValueType(); 2578 unsigned BitWidth = MVT::getSizeInBits(VT); 2579 assert(Op.getNumOperands() == 3 && 2580 VT == Op.getOperand(1).getValueType() && 2581 "Unexpected SRL!"); 2582 2583 // Expand into a bunch of logical ops. Note that these ops 2584 // depend on the PPC behavior for oversized shift amounts. 2585 SDOperand Lo = Op.getOperand(0); 2586 SDOperand Hi = Op.getOperand(1); 2587 SDOperand Amt = Op.getOperand(2); 2588 MVT::ValueType AmtVT = Amt.getValueType(); 2589 2590 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT, 2591 DAG.getConstant(BitWidth, AmtVT), Amt); 2592 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt); 2593 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1); 2594 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); 2595 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, 2596 DAG.getConstant(-BitWidth, AmtVT)); 2597 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5); 2598 SDOperand OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); 2599 SDOperand OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt); 2600 SDOperand OutOps[] = { OutLo, OutHi }; 2601 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT), 2602 OutOps, 2); 2603} 2604 2605SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { 2606 MVT::ValueType VT = Op.getValueType(); 2607 unsigned BitWidth = MVT::getSizeInBits(VT); 2608 assert(Op.getNumOperands() == 3 && 2609 VT == Op.getOperand(1).getValueType() && 2610 "Unexpected SRA!"); 2611 2612 // Expand into a bunch of logical ops, followed by a select_cc. 2613 SDOperand Lo = Op.getOperand(0); 2614 SDOperand Hi = Op.getOperand(1); 2615 SDOperand Amt = Op.getOperand(2); 2616 MVT::ValueType AmtVT = Amt.getValueType(); 2617 2618 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT, 2619 DAG.getConstant(BitWidth, AmtVT), Amt); 2620 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt); 2621 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1); 2622 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); 2623 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, 2624 DAG.getConstant(-BitWidth, AmtVT)); 2625 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5); 2626 SDOperand OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt); 2627 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT), 2628 Tmp4, Tmp6, ISD::SETLE); 2629 SDOperand OutOps[] = { OutLo, OutHi }; 2630 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT), 2631 OutOps, 2); 2632} 2633 2634//===----------------------------------------------------------------------===// 2635// Vector related lowering. 2636// 2637 2638// If this is a vector of constants or undefs, get the bits. A bit in 2639// UndefBits is set if the corresponding element of the vector is an 2640// ISD::UNDEF value. For undefs, the corresponding VectorBits values are 2641// zero. Return true if this is not an array of constants, false if it is. 2642// 2643static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], 2644 uint64_t UndefBits[2]) { 2645 // Start with zero'd results. 2646 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; 2647 2648 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType()); 2649 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 2650 SDOperand OpVal = BV->getOperand(i); 2651 2652 unsigned PartNo = i >= e/2; // In the upper 128 bits? 2653 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. 2654 2655 uint64_t EltBits = 0; 2656 if (OpVal.getOpcode() == ISD::UNDEF) { 2657 uint64_t EltUndefBits = ~0U >> (32-EltBitSize); 2658 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); 2659 continue; 2660 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 2661 EltBits = CN->getValue() & (~0U >> (32-EltBitSize)); 2662 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 2663 assert(CN->getValueType(0) == MVT::f32 && 2664 "Only one legal FP vector type!"); 2665 EltBits = FloatToBits(CN->getValueAPF().convertToFloat()); 2666 } else { 2667 // Nonconstant element. 2668 return true; 2669 } 2670 2671 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); 2672 } 2673 2674 //printf("%llx %llx %llx %llx\n", 2675 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); 2676 return false; 2677} 2678 2679// If this is a splat (repetition) of a value across the whole vector, return 2680// the smallest size that splats it. For example, "0x01010101010101..." is a 2681// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 2682// SplatSize = 1 byte. 2683static bool isConstantSplat(const uint64_t Bits128[2], 2684 const uint64_t Undef128[2], 2685 unsigned &SplatBits, unsigned &SplatUndef, 2686 unsigned &SplatSize) { 2687 2688 // Don't let undefs prevent splats from matching. See if the top 64-bits are 2689 // the same as the lower 64-bits, ignoring undefs. 2690 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0])) 2691 return false; // Can't be a splat if two pieces don't match. 2692 2693 uint64_t Bits64 = Bits128[0] | Bits128[1]; 2694 uint64_t Undef64 = Undef128[0] & Undef128[1]; 2695 2696 // Check that the top 32-bits are the same as the lower 32-bits, ignoring 2697 // undefs. 2698 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64)) 2699 return false; // Can't be a splat if two pieces don't match. 2700 2701 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32); 2702 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32); 2703 2704 // If the top 16-bits are different than the lower 16-bits, ignoring 2705 // undefs, we have an i32 splat. 2706 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) { 2707 SplatBits = Bits32; 2708 SplatUndef = Undef32; 2709 SplatSize = 4; 2710 return true; 2711 } 2712 2713 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16); 2714 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16); 2715 2716 // If the top 8-bits are different than the lower 8-bits, ignoring 2717 // undefs, we have an i16 splat. 2718 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) { 2719 SplatBits = Bits16; 2720 SplatUndef = Undef16; 2721 SplatSize = 2; 2722 return true; 2723 } 2724 2725 // Otherwise, we have an 8-bit splat. 2726 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); 2727 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); 2728 SplatSize = 1; 2729 return true; 2730} 2731 2732/// BuildSplatI - Build a canonical splati of Val with an element size of 2733/// SplatSize. Cast the result to VT. 2734static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT, 2735 SelectionDAG &DAG) { 2736 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 2737 2738 static const MVT::ValueType VTys[] = { // canonical VT to use for each size. 2739 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 2740 }; 2741 2742 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 2743 2744 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 2745 if (Val == -1) 2746 SplatSize = 1; 2747 2748 MVT::ValueType CanonicalVT = VTys[SplatSize-1]; 2749 2750 // Build a canonical splat for this value. 2751 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT)); 2752 SmallVector<SDOperand, 8> Ops; 2753 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt); 2754 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, 2755 &Ops[0], Ops.size()); 2756 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res); 2757} 2758 2759/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 2760/// specified intrinsic ID. 2761static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS, 2762 SelectionDAG &DAG, 2763 MVT::ValueType DestVT = MVT::Other) { 2764 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 2765 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 2766 DAG.getConstant(IID, MVT::i32), LHS, RHS); 2767} 2768 2769/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 2770/// specified intrinsic ID. 2771static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1, 2772 SDOperand Op2, SelectionDAG &DAG, 2773 MVT::ValueType DestVT = MVT::Other) { 2774 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 2775 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 2776 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 2777} 2778 2779 2780/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 2781/// amount. The result has the specified value type. 2782static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt, 2783 MVT::ValueType VT, SelectionDAG &DAG) { 2784 // Force LHS/RHS to be the right type. 2785 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); 2786 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); 2787 2788 SDOperand Ops[16]; 2789 for (unsigned i = 0; i != 16; ++i) 2790 Ops[i] = DAG.getConstant(i+Amt, MVT::i32); 2791 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, 2792 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16)); 2793 return DAG.getNode(ISD::BIT_CONVERT, VT, T); 2794} 2795 2796// If this is a case we can't handle, return null and let the default 2797// expansion code take care of it. If we CAN select this case, and if it 2798// selects to a single instruction, return Op. Otherwise, if we can codegen 2799// this case more efficiently than a constant pool load, lower it to the 2800// sequence of ops that should be used. 2801SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op, 2802 SelectionDAG &DAG) { 2803 // If this is a vector of constants or undefs, get the bits. A bit in 2804 // UndefBits is set if the corresponding element of the vector is an 2805 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are 2806 // zero. 2807 uint64_t VectorBits[2]; 2808 uint64_t UndefBits[2]; 2809 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) 2810 return SDOperand(); // Not a constant vector. 2811 2812 // If this is a splat (repetition) of a value across the whole vector, return 2813 // the smallest size that splats it. For example, "0x01010101010101..." is a 2814 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 2815 // SplatSize = 1 byte. 2816 unsigned SplatBits, SplatUndef, SplatSize; 2817 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){ 2818 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0; 2819 2820 // First, handle single instruction cases. 2821 2822 // All zeros? 2823 if (SplatBits == 0) { 2824 // Canonicalize all zero vectors to be v4i32. 2825 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 2826 SDOperand Z = DAG.getConstant(0, MVT::i32); 2827 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); 2828 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); 2829 } 2830 return Op; 2831 } 2832 2833 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 2834 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); 2835 if (SextVal >= -16 && SextVal <= 15) 2836 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG); 2837 2838 2839 // Two instruction sequences. 2840 2841 // If this value is in the range [-32,30] and is even, use: 2842 // tmp = VSPLTI[bhw], result = add tmp, tmp 2843 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 2844 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG); 2845 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op); 2846 } 2847 2848 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 2849 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 2850 // for fneg/fabs. 2851 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 2852 // Make -1 and vspltisw -1: 2853 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); 2854 2855 // Make the VSLW intrinsic, computing 0x8000_0000. 2856 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 2857 OnesV, DAG); 2858 2859 // xor by OnesV to invert it. 2860 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); 2861 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2862 } 2863 2864 // Check to see if this is a wide variety of vsplti*, binop self cases. 2865 unsigned SplatBitSize = SplatSize*8; 2866 static const signed char SplatCsts[] = { 2867 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 2868 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 2869 }; 2870 2871 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 2872 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 2873 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 2874 int i = SplatCsts[idx]; 2875 2876 // Figure out what shift amount will be used by altivec if shifted by i in 2877 // this splat size. 2878 unsigned TypeShiftAmt = i & (SplatBitSize-1); 2879 2880 // vsplti + shl self. 2881 if (SextVal == (i << (int)TypeShiftAmt)) { 2882 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2883 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2884 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 2885 Intrinsic::ppc_altivec_vslw 2886 }; 2887 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2888 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2889 } 2890 2891 // vsplti + srl self. 2892 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2893 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2894 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2895 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 2896 Intrinsic::ppc_altivec_vsrw 2897 }; 2898 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2899 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2900 } 2901 2902 // vsplti + sra self. 2903 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2904 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2905 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2906 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 2907 Intrinsic::ppc_altivec_vsraw 2908 }; 2909 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2910 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2911 } 2912 2913 // vsplti + rol self. 2914 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 2915 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 2916 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2917 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2918 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 2919 Intrinsic::ppc_altivec_vrlw 2920 }; 2921 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2922 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2923 } 2924 2925 // t = vsplti c, result = vsldoi t, t, 1 2926 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { 2927 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2928 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG); 2929 } 2930 // t = vsplti c, result = vsldoi t, t, 2 2931 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { 2932 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2933 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG); 2934 } 2935 // t = vsplti c, result = vsldoi t, t, 3 2936 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { 2937 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2938 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG); 2939 } 2940 } 2941 2942 // Three instruction sequences. 2943 2944 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 2945 if (SextVal >= 0 && SextVal <= 31) { 2946 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG); 2947 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 2948 LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS); 2949 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 2950 } 2951 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 2952 if (SextVal >= -31 && SextVal <= 0) { 2953 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG); 2954 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 2955 LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS); 2956 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 2957 } 2958 } 2959 2960 return SDOperand(); 2961} 2962 2963/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 2964/// the specified operations to build the shuffle. 2965static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, 2966 SDOperand RHS, SelectionDAG &DAG) { 2967 unsigned OpNum = (PFEntry >> 26) & 0x0F; 2968 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 2969 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 2970 2971 enum { 2972 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 2973 OP_VMRGHW, 2974 OP_VMRGLW, 2975 OP_VSPLTISW0, 2976 OP_VSPLTISW1, 2977 OP_VSPLTISW2, 2978 OP_VSPLTISW3, 2979 OP_VSLDOI4, 2980 OP_VSLDOI8, 2981 OP_VSLDOI12 2982 }; 2983 2984 if (OpNum == OP_COPY) { 2985 if (LHSID == (1*9+2)*9+3) return LHS; 2986 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 2987 return RHS; 2988 } 2989 2990 SDOperand OpLHS, OpRHS; 2991 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG); 2992 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG); 2993 2994 unsigned ShufIdxs[16]; 2995 switch (OpNum) { 2996 default: assert(0 && "Unknown i32 permute!"); 2997 case OP_VMRGHW: 2998 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 2999 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 3000 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 3001 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 3002 break; 3003 case OP_VMRGLW: 3004 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 3005 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 3006 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 3007 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 3008 break; 3009 case OP_VSPLTISW0: 3010 for (unsigned i = 0; i != 16; ++i) 3011 ShufIdxs[i] = (i&3)+0; 3012 break; 3013 case OP_VSPLTISW1: 3014 for (unsigned i = 0; i != 16; ++i) 3015 ShufIdxs[i] = (i&3)+4; 3016 break; 3017 case OP_VSPLTISW2: 3018 for (unsigned i = 0; i != 16; ++i) 3019 ShufIdxs[i] = (i&3)+8; 3020 break; 3021 case OP_VSPLTISW3: 3022 for (unsigned i = 0; i != 16; ++i) 3023 ShufIdxs[i] = (i&3)+12; 3024 break; 3025 case OP_VSLDOI4: 3026 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG); 3027 case OP_VSLDOI8: 3028 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG); 3029 case OP_VSLDOI12: 3030 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); 3031 } 3032 SDOperand Ops[16]; 3033 for (unsigned i = 0; i != 16; ++i) 3034 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32); 3035 3036 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS, 3037 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 3038} 3039 3040/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 3041/// is a shuffle we can handle in a single instruction, return it. Otherwise, 3042/// return the code it can be lowered into. Worst case, it can always be 3043/// lowered into a vperm. 3044SDOperand PPCTargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, 3045 SelectionDAG &DAG) { 3046 SDOperand V1 = Op.getOperand(0); 3047 SDOperand V2 = Op.getOperand(1); 3048 SDOperand PermMask = Op.getOperand(2); 3049 3050 // Cases that are handled by instructions that take permute immediates 3051 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 3052 // selected by the instruction selector. 3053 if (V2.getOpcode() == ISD::UNDEF) { 3054 if (PPC::isSplatShuffleMask(PermMask.Val, 1) || 3055 PPC::isSplatShuffleMask(PermMask.Val, 2) || 3056 PPC::isSplatShuffleMask(PermMask.Val, 4) || 3057 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || 3058 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || 3059 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || 3060 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || 3061 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || 3062 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || 3063 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || 3064 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || 3065 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { 3066 return Op; 3067 } 3068 } 3069 3070 // Altivec has a variety of "shuffle immediates" that take two vector inputs 3071 // and produce a fixed permutation. If any of these match, do not lower to 3072 // VPERM. 3073 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || 3074 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || 3075 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || 3076 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || 3077 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || 3078 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || 3079 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || 3080 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || 3081 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) 3082 return Op; 3083 3084 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 3085 // perfect shuffle table to emit an optimal matching sequence. 3086 unsigned PFIndexes[4]; 3087 bool isFourElementShuffle = true; 3088 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 3089 unsigned EltNo = 8; // Start out undef. 3090 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 3091 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF) 3092 continue; // Undef, ignore it. 3093 3094 unsigned ByteSource = 3095 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue(); 3096 if ((ByteSource & 3) != j) { 3097 isFourElementShuffle = false; 3098 break; 3099 } 3100 3101 if (EltNo == 8) { 3102 EltNo = ByteSource/4; 3103 } else if (EltNo != ByteSource/4) { 3104 isFourElementShuffle = false; 3105 break; 3106 } 3107 } 3108 PFIndexes[i] = EltNo; 3109 } 3110 3111 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 3112 // perfect shuffle vector to determine if it is cost effective to do this as 3113 // discrete instructions, or whether we should use a vperm. 3114 if (isFourElementShuffle) { 3115 // Compute the index in the perfect shuffle table. 3116 unsigned PFTableIndex = 3117 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 3118 3119 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 3120 unsigned Cost = (PFEntry >> 30); 3121 3122 // Determining when to avoid vperm is tricky. Many things affect the cost 3123 // of vperm, particularly how many times the perm mask needs to be computed. 3124 // For example, if the perm mask can be hoisted out of a loop or is already 3125 // used (perhaps because there are multiple permutes with the same shuffle 3126 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 3127 // the loop requires an extra register. 3128 // 3129 // As a compromise, we only emit discrete instructions if the shuffle can be 3130 // generated in 3 or fewer operations. When we have loop information 3131 // available, if this block is within a loop, we should avoid using vperm 3132 // for 3-operation perms and use a constant pool load instead. 3133 if (Cost < 3) 3134 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG); 3135 } 3136 3137 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 3138 // vector that will get spilled to the constant pool. 3139 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 3140 3141 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 3142 // that it is in input element units, not in bytes. Convert now. 3143 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType()); 3144 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; 3145 3146 SmallVector<SDOperand, 16> ResultMask; 3147 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { 3148 unsigned SrcElt; 3149 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) 3150 SrcElt = 0; 3151 else 3152 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue(); 3153 3154 for (unsigned j = 0; j != BytesPerElement; ++j) 3155 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 3156 MVT::i8)); 3157 } 3158 3159 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, 3160 &ResultMask[0], ResultMask.size()); 3161 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); 3162} 3163 3164/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 3165/// altivec comparison. If it is, return true and fill in Opc/isDot with 3166/// information about the intrinsic. 3167static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc, 3168 bool &isDot) { 3169 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue(); 3170 CompareOpc = -1; 3171 isDot = false; 3172 switch (IntrinsicID) { 3173 default: return false; 3174 // Comparison predicates. 3175 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 3176 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 3177 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 3178 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 3179 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 3180 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 3181 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 3182 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 3183 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 3184 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 3185 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 3186 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 3187 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 3188 3189 // Normal Comparisons. 3190 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 3191 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 3192 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 3193 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 3194 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 3195 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 3196 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 3197 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 3198 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 3199 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 3200 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 3201 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 3202 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 3203 } 3204 return true; 3205} 3206 3207/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 3208/// lower, do it, otherwise return null. 3209SDOperand PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, 3210 SelectionDAG &DAG) { 3211 // If this is a lowered altivec predicate compare, CompareOpc is set to the 3212 // opcode number of the comparison. 3213 int CompareOpc; 3214 bool isDot; 3215 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 3216 return SDOperand(); // Don't custom lower most intrinsics. 3217 3218 // If this is a non-dot comparison, make the VCMP node and we are done. 3219 if (!isDot) { 3220 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), 3221 Op.getOperand(1), Op.getOperand(2), 3222 DAG.getConstant(CompareOpc, MVT::i32)); 3223 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); 3224 } 3225 3226 // Create the PPCISD altivec 'dot' comparison node. 3227 SDOperand Ops[] = { 3228 Op.getOperand(2), // LHS 3229 Op.getOperand(3), // RHS 3230 DAG.getConstant(CompareOpc, MVT::i32) 3231 }; 3232 std::vector<MVT::ValueType> VTs; 3233 VTs.push_back(Op.getOperand(2).getValueType()); 3234 VTs.push_back(MVT::Flag); 3235 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 3236 3237 // Now that we have the comparison, emit a copy from the CR to a GPR. 3238 // This is flagged to the above dot comparison. 3239 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, 3240 DAG.getRegister(PPC::CR6, MVT::i32), 3241 CompNode.getValue(1)); 3242 3243 // Unpack the result based on how the target uses it. 3244 unsigned BitNo; // Bit # of CR6. 3245 bool InvertBit; // Invert result? 3246 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { 3247 default: // Can't happen, don't crash on invalid number though. 3248 case 0: // Return the value of the EQ bit of CR6. 3249 BitNo = 0; InvertBit = false; 3250 break; 3251 case 1: // Return the inverted value of the EQ bit of CR6. 3252 BitNo = 0; InvertBit = true; 3253 break; 3254 case 2: // Return the value of the LT bit of CR6. 3255 BitNo = 2; InvertBit = false; 3256 break; 3257 case 3: // Return the inverted value of the LT bit of CR6. 3258 BitNo = 2; InvertBit = true; 3259 break; 3260 } 3261 3262 // Shift the bit into the low position. 3263 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, 3264 DAG.getConstant(8-(3-BitNo), MVT::i32)); 3265 // Isolate the bit. 3266 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, 3267 DAG.getConstant(1, MVT::i32)); 3268 3269 // If we are supposed to, toggle the bit. 3270 if (InvertBit) 3271 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, 3272 DAG.getConstant(1, MVT::i32)); 3273 return Flags; 3274} 3275 3276SDOperand PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, 3277 SelectionDAG &DAG) { 3278 // Create a stack slot that is 16-byte aligned. 3279 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 3280 int FrameIdx = FrameInfo->CreateStackObject(16, 16); 3281 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3282 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 3283 3284 // Store the input value into Value#0 of the stack slot. 3285 SDOperand Store = DAG.getStore(DAG.getEntryNode(), 3286 Op.getOperand(0), FIdx, NULL, 0); 3287 // Load it out. 3288 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); 3289} 3290 3291SDOperand PPCTargetLowering::LowerMUL(SDOperand Op, SelectionDAG &DAG) { 3292 if (Op.getValueType() == MVT::v4i32) { 3293 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3294 3295 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); 3296 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. 3297 3298 SDOperand RHSSwap = // = vrlw RHS, 16 3299 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG); 3300 3301 // Shrinkify inputs to v8i16. 3302 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS); 3303 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS); 3304 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap); 3305 3306 // Low parts multiplied together, generating 32-bit results (we ignore the 3307 // top parts). 3308 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 3309 LHS, RHS, DAG, MVT::v4i32); 3310 3311 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 3312 LHS, RHSSwap, Zero, DAG, MVT::v4i32); 3313 // Shift the high parts up 16 bits. 3314 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG); 3315 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd); 3316 } else if (Op.getValueType() == MVT::v8i16) { 3317 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3318 3319 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); 3320 3321 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 3322 LHS, RHS, Zero, DAG); 3323 } else if (Op.getValueType() == MVT::v16i8) { 3324 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3325 3326 // Multiply the even 8-bit parts, producing 16-bit sums. 3327 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 3328 LHS, RHS, DAG, MVT::v8i16); 3329 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts); 3330 3331 // Multiply the odd 8-bit parts, producing 16-bit sums. 3332 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 3333 LHS, RHS, DAG, MVT::v8i16); 3334 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); 3335 3336 // Merge the results together. 3337 SDOperand Ops[16]; 3338 for (unsigned i = 0; i != 8; ++i) { 3339 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); 3340 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); 3341 } 3342 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts, 3343 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 3344 } else { 3345 assert(0 && "Unknown mul to lower!"); 3346 abort(); 3347 } 3348} 3349 3350/// LowerOperation - Provide custom lowering hooks for some operations. 3351/// 3352SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 3353 switch (Op.getOpcode()) { 3354 default: assert(0 && "Wasn't expecting to be able to lower this!"); 3355 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 3356 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 3357 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 3358 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 3359 case ISD::SETCC: return LowerSETCC(Op, DAG); 3360 case ISD::VASTART: 3361 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 3362 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 3363 3364 case ISD::VAARG: 3365 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 3366 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 3367 3368 case ISD::FORMAL_ARGUMENTS: 3369 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex, 3370 VarArgsStackOffset, VarArgsNumGPR, 3371 VarArgsNumFPR, PPCSubTarget); 3372 3373 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget); 3374 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine()); 3375 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 3376 case ISD::DYNAMIC_STACKALLOC: 3377 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 3378 3379 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 3380 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 3381 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 3382 case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG); 3383 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 3384 3385 // Lower 64-bit shifts. 3386 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 3387 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 3388 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 3389 3390 // Vector-related lowering. 3391 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 3392 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 3393 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 3394 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 3395 case ISD::MUL: return LowerMUL(Op, DAG); 3396 3397 // Frame & Return address. 3398 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 3399 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 3400 } 3401 return SDOperand(); 3402} 3403 3404SDNode *PPCTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) { 3405 switch (N->getOpcode()) { 3406 default: assert(0 && "Wasn't expecting to be able to lower this!"); 3407 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(SDOperand(N, 0), DAG).Val; 3408 } 3409} 3410 3411 3412//===----------------------------------------------------------------------===// 3413// Other Lowering Code 3414//===----------------------------------------------------------------------===// 3415 3416MachineBasicBlock * 3417PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 3418 MachineBasicBlock *BB) { 3419 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 3420 assert((MI->getOpcode() == PPC::SELECT_CC_I4 || 3421 MI->getOpcode() == PPC::SELECT_CC_I8 || 3422 MI->getOpcode() == PPC::SELECT_CC_F4 || 3423 MI->getOpcode() == PPC::SELECT_CC_F8 || 3424 MI->getOpcode() == PPC::SELECT_CC_VRRC) && 3425 "Unexpected instr type to insert"); 3426 3427 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 3428 // control-flow pattern. The incoming instruction knows the destination vreg 3429 // to set, the condition code register to branch on, the true/false values to 3430 // select between, and a branch opcode to use. 3431 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3432 ilist<MachineBasicBlock>::iterator It = BB; 3433 ++It; 3434 3435 // thisMBB: 3436 // ... 3437 // TrueVal = ... 3438 // cmpTY ccX, r1, r2 3439 // bCC copy1MBB 3440 // fallthrough --> copy0MBB 3441 MachineBasicBlock *thisMBB = BB; 3442 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 3443 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 3444 unsigned SelectPred = MI->getOperand(4).getImm(); 3445 BuildMI(BB, TII->get(PPC::BCC)) 3446 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 3447 MachineFunction *F = BB->getParent(); 3448 F->getBasicBlockList().insert(It, copy0MBB); 3449 F->getBasicBlockList().insert(It, sinkMBB); 3450 // Update machine-CFG edges by first adding all successors of the current 3451 // block to the new block which will contain the Phi node for the select. 3452 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 3453 e = BB->succ_end(); i != e; ++i) 3454 sinkMBB->addSuccessor(*i); 3455 // Next, remove all successors of the current block, and add the true 3456 // and fallthrough blocks as its successors. 3457 while(!BB->succ_empty()) 3458 BB->removeSuccessor(BB->succ_begin()); 3459 BB->addSuccessor(copy0MBB); 3460 BB->addSuccessor(sinkMBB); 3461 3462 // copy0MBB: 3463 // %FalseValue = ... 3464 // # fallthrough to sinkMBB 3465 BB = copy0MBB; 3466 3467 // Update machine-CFG edges 3468 BB->addSuccessor(sinkMBB); 3469 3470 // sinkMBB: 3471 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 3472 // ... 3473 BB = sinkMBB; 3474 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg()) 3475 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 3476 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 3477 3478 delete MI; // The pseudo instruction is gone now. 3479 return BB; 3480} 3481 3482//===----------------------------------------------------------------------===// 3483// Target Optimization Hooks 3484//===----------------------------------------------------------------------===// 3485 3486SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, 3487 DAGCombinerInfo &DCI) const { 3488 TargetMachine &TM = getTargetMachine(); 3489 SelectionDAG &DAG = DCI.DAG; 3490 switch (N->getOpcode()) { 3491 default: break; 3492 case PPCISD::SHL: 3493 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3494 if (C->getValue() == 0) // 0 << V -> 0. 3495 return N->getOperand(0); 3496 } 3497 break; 3498 case PPCISD::SRL: 3499 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3500 if (C->getValue() == 0) // 0 >>u V -> 0. 3501 return N->getOperand(0); 3502 } 3503 break; 3504 case PPCISD::SRA: 3505 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3506 if (C->getValue() == 0 || // 0 >>s V -> 0. 3507 C->isAllOnesValue()) // -1 >>s V -> -1. 3508 return N->getOperand(0); 3509 } 3510 break; 3511 3512 case ISD::SINT_TO_FP: 3513 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 3514 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 3515 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 3516 // We allow the src/dst to be either f32/f64, but the intermediate 3517 // type must be i64. 3518 if (N->getOperand(0).getValueType() == MVT::i64 && 3519 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 3520 SDOperand Val = N->getOperand(0).getOperand(0); 3521 if (Val.getValueType() == MVT::f32) { 3522 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 3523 DCI.AddToWorklist(Val.Val); 3524 } 3525 3526 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); 3527 DCI.AddToWorklist(Val.Val); 3528 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); 3529 DCI.AddToWorklist(Val.Val); 3530 if (N->getValueType(0) == MVT::f32) { 3531 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val, 3532 DAG.getIntPtrConstant(0)); 3533 DCI.AddToWorklist(Val.Val); 3534 } 3535 return Val; 3536 } else if (N->getOperand(0).getValueType() == MVT::i32) { 3537 // If the intermediate type is i32, we can avoid the load/store here 3538 // too. 3539 } 3540 } 3541 } 3542 break; 3543 case ISD::STORE: 3544 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 3545 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 3546 !cast<StoreSDNode>(N)->isTruncatingStore() && 3547 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 3548 N->getOperand(1).getValueType() == MVT::i32 && 3549 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 3550 SDOperand Val = N->getOperand(1).getOperand(0); 3551 if (Val.getValueType() == MVT::f32) { 3552 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 3553 DCI.AddToWorklist(Val.Val); 3554 } 3555 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); 3556 DCI.AddToWorklist(Val.Val); 3557 3558 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, 3559 N->getOperand(2), N->getOperand(3)); 3560 DCI.AddToWorklist(Val.Val); 3561 return Val; 3562 } 3563 3564 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 3565 if (N->getOperand(1).getOpcode() == ISD::BSWAP && 3566 N->getOperand(1).Val->hasOneUse() && 3567 (N->getOperand(1).getValueType() == MVT::i32 || 3568 N->getOperand(1).getValueType() == MVT::i16)) { 3569 SDOperand BSwapOp = N->getOperand(1).getOperand(0); 3570 // Do an any-extend to 32-bits if this is a half-word input. 3571 if (BSwapOp.getValueType() == MVT::i16) 3572 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp); 3573 3574 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp, 3575 N->getOperand(2), N->getOperand(3), 3576 DAG.getValueType(N->getOperand(1).getValueType())); 3577 } 3578 break; 3579 case ISD::BSWAP: 3580 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 3581 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) && 3582 N->getOperand(0).hasOneUse() && 3583 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 3584 SDOperand Load = N->getOperand(0); 3585 LoadSDNode *LD = cast<LoadSDNode>(Load); 3586 // Create the byte-swapping load. 3587 std::vector<MVT::ValueType> VTs; 3588 VTs.push_back(MVT::i32); 3589 VTs.push_back(MVT::Other); 3590 SDOperand MO = DAG.getMemOperand(LD->getMemOperand()); 3591 SDOperand Ops[] = { 3592 LD->getChain(), // Chain 3593 LD->getBasePtr(), // Ptr 3594 MO, // MemOperand 3595 DAG.getValueType(N->getValueType(0)) // VT 3596 }; 3597 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); 3598 3599 // If this is an i16 load, insert the truncate. 3600 SDOperand ResVal = BSLoad; 3601 if (N->getValueType(0) == MVT::i16) 3602 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad); 3603 3604 // First, combine the bswap away. This makes the value produced by the 3605 // load dead. 3606 DCI.CombineTo(N, ResVal); 3607 3608 // Next, combine the load away, we give it a bogus result value but a real 3609 // chain result. The result value is dead because the bswap is dead. 3610 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1)); 3611 3612 // Return N so it doesn't get rechecked! 3613 return SDOperand(N, 0); 3614 } 3615 3616 break; 3617 case PPCISD::VCMP: { 3618 // If a VCMPo node already exists with exactly the same operands as this 3619 // node, use its result instead of this node (VCMPo computes both a CR6 and 3620 // a normal output). 3621 // 3622 if (!N->getOperand(0).hasOneUse() && 3623 !N->getOperand(1).hasOneUse() && 3624 !N->getOperand(2).hasOneUse()) { 3625 3626 // Scan all of the users of the LHS, looking for VCMPo's that match. 3627 SDNode *VCMPoNode = 0; 3628 3629 SDNode *LHSN = N->getOperand(0).Val; 3630 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 3631 UI != E; ++UI) 3632 if ((*UI)->getOpcode() == PPCISD::VCMPo && 3633 (*UI)->getOperand(1) == N->getOperand(1) && 3634 (*UI)->getOperand(2) == N->getOperand(2) && 3635 (*UI)->getOperand(0) == N->getOperand(0)) { 3636 VCMPoNode = *UI; 3637 break; 3638 } 3639 3640 // If there is no VCMPo node, or if the flag value has a single use, don't 3641 // transform this. 3642 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 3643 break; 3644 3645 // Look at the (necessarily single) use of the flag value. If it has a 3646 // chain, this transformation is more complex. Note that multiple things 3647 // could use the value result, which we should ignore. 3648 SDNode *FlagUser = 0; 3649 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 3650 FlagUser == 0; ++UI) { 3651 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 3652 SDNode *User = *UI; 3653 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 3654 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) { 3655 FlagUser = User; 3656 break; 3657 } 3658 } 3659 } 3660 3661 // If the user is a MFCR instruction, we know this is safe. Otherwise we 3662 // give up for right now. 3663 if (FlagUser->getOpcode() == PPCISD::MFCR) 3664 return SDOperand(VCMPoNode, 0); 3665 } 3666 break; 3667 } 3668 case ISD::BR_CC: { 3669 // If this is a branch on an altivec predicate comparison, lower this so 3670 // that we don't have to do a MFCR: instead, branch directly on CR6. This 3671 // lowering is done pre-legalize, because the legalizer lowers the predicate 3672 // compare down to code that is difficult to reassemble. 3673 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 3674 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3); 3675 int CompareOpc; 3676 bool isDot; 3677 3678 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 3679 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 3680 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 3681 assert(isDot && "Can't compare against a vector result!"); 3682 3683 // If this is a comparison against something other than 0/1, then we know 3684 // that the condition is never/always true. 3685 unsigned Val = cast<ConstantSDNode>(RHS)->getValue(); 3686 if (Val != 0 && Val != 1) { 3687 if (CC == ISD::SETEQ) // Cond never true, remove branch. 3688 return N->getOperand(0); 3689 // Always !=, turn it into an unconditional branch. 3690 return DAG.getNode(ISD::BR, MVT::Other, 3691 N->getOperand(0), N->getOperand(4)); 3692 } 3693 3694 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 3695 3696 // Create the PPCISD altivec 'dot' comparison node. 3697 std::vector<MVT::ValueType> VTs; 3698 SDOperand Ops[] = { 3699 LHS.getOperand(2), // LHS of compare 3700 LHS.getOperand(3), // RHS of compare 3701 DAG.getConstant(CompareOpc, MVT::i32) 3702 }; 3703 VTs.push_back(LHS.getOperand(2).getValueType()); 3704 VTs.push_back(MVT::Flag); 3705 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 3706 3707 // Unpack the result based on how the target uses it. 3708 PPC::Predicate CompOpc; 3709 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) { 3710 default: // Can't happen, don't crash on invalid number though. 3711 case 0: // Branch on the value of the EQ bit of CR6. 3712 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 3713 break; 3714 case 1: // Branch on the inverted value of the EQ bit of CR6. 3715 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 3716 break; 3717 case 2: // Branch on the value of the LT bit of CR6. 3718 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 3719 break; 3720 case 3: // Branch on the inverted value of the LT bit of CR6. 3721 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 3722 break; 3723 } 3724 3725 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), 3726 DAG.getConstant(CompOpc, MVT::i32), 3727 DAG.getRegister(PPC::CR6, MVT::i32), 3728 N->getOperand(4), CompNode.getValue(1)); 3729 } 3730 break; 3731 } 3732 } 3733 3734 return SDOperand(); 3735} 3736 3737//===----------------------------------------------------------------------===// 3738// Inline Assembly Support 3739//===----------------------------------------------------------------------===// 3740 3741void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 3742 const APInt &Mask, 3743 APInt &KnownZero, 3744 APInt &KnownOne, 3745 const SelectionDAG &DAG, 3746 unsigned Depth) const { 3747 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 3748 switch (Op.getOpcode()) { 3749 default: break; 3750 case PPCISD::LBRX: { 3751 // lhbrx is known to have the top bits cleared out. 3752 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16) 3753 KnownZero = 0xFFFF0000; 3754 break; 3755 } 3756 case ISD::INTRINSIC_WO_CHAIN: { 3757 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) { 3758 default: break; 3759 case Intrinsic::ppc_altivec_vcmpbfp_p: 3760 case Intrinsic::ppc_altivec_vcmpeqfp_p: 3761 case Intrinsic::ppc_altivec_vcmpequb_p: 3762 case Intrinsic::ppc_altivec_vcmpequh_p: 3763 case Intrinsic::ppc_altivec_vcmpequw_p: 3764 case Intrinsic::ppc_altivec_vcmpgefp_p: 3765 case Intrinsic::ppc_altivec_vcmpgtfp_p: 3766 case Intrinsic::ppc_altivec_vcmpgtsb_p: 3767 case Intrinsic::ppc_altivec_vcmpgtsh_p: 3768 case Intrinsic::ppc_altivec_vcmpgtsw_p: 3769 case Intrinsic::ppc_altivec_vcmpgtub_p: 3770 case Intrinsic::ppc_altivec_vcmpgtuh_p: 3771 case Intrinsic::ppc_altivec_vcmpgtuw_p: 3772 KnownZero = ~1U; // All bits but the low one are known to be zero. 3773 break; 3774 } 3775 } 3776 } 3777} 3778 3779 3780/// getConstraintType - Given a constraint, return the type of 3781/// constraint it is for this target. 3782PPCTargetLowering::ConstraintType 3783PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 3784 if (Constraint.size() == 1) { 3785 switch (Constraint[0]) { 3786 default: break; 3787 case 'b': 3788 case 'r': 3789 case 'f': 3790 case 'v': 3791 case 'y': 3792 return C_RegisterClass; 3793 } 3794 } 3795 return TargetLowering::getConstraintType(Constraint); 3796} 3797 3798std::pair<unsigned, const TargetRegisterClass*> 3799PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 3800 MVT::ValueType VT) const { 3801 if (Constraint.size() == 1) { 3802 // GCC RS6000 Constraint Letters 3803 switch (Constraint[0]) { 3804 case 'b': // R1-R31 3805 case 'r': // R0-R31 3806 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 3807 return std::make_pair(0U, PPC::G8RCRegisterClass); 3808 return std::make_pair(0U, PPC::GPRCRegisterClass); 3809 case 'f': 3810 if (VT == MVT::f32) 3811 return std::make_pair(0U, PPC::F4RCRegisterClass); 3812 else if (VT == MVT::f64) 3813 return std::make_pair(0U, PPC::F8RCRegisterClass); 3814 break; 3815 case 'v': 3816 return std::make_pair(0U, PPC::VRRCRegisterClass); 3817 case 'y': // crrc 3818 return std::make_pair(0U, PPC::CRRCRegisterClass); 3819 } 3820 } 3821 3822 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3823} 3824 3825 3826/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3827/// vector. If it is invalid, don't add anything to Ops. 3828void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter, 3829 std::vector<SDOperand>&Ops, 3830 SelectionDAG &DAG) { 3831 SDOperand Result(0,0); 3832 switch (Letter) { 3833 default: break; 3834 case 'I': 3835 case 'J': 3836 case 'K': 3837 case 'L': 3838 case 'M': 3839 case 'N': 3840 case 'O': 3841 case 'P': { 3842 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 3843 if (!CST) return; // Must be an immediate to match. 3844 unsigned Value = CST->getValue(); 3845 switch (Letter) { 3846 default: assert(0 && "Unknown constraint letter!"); 3847 case 'I': // "I" is a signed 16-bit constant. 3848 if ((short)Value == (int)Value) 3849 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3850 break; 3851 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 3852 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 3853 if ((short)Value == 0) 3854 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3855 break; 3856 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 3857 if ((Value >> 16) == 0) 3858 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3859 break; 3860 case 'M': // "M" is a constant that is greater than 31. 3861 if (Value > 31) 3862 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3863 break; 3864 case 'N': // "N" is a positive constant that is an exact power of two. 3865 if ((int)Value > 0 && isPowerOf2_32(Value)) 3866 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3867 break; 3868 case 'O': // "O" is the constant zero. 3869 if (Value == 0) 3870 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3871 break; 3872 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 3873 if ((short)-Value == (int)-Value) 3874 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3875 break; 3876 } 3877 break; 3878 } 3879 } 3880 3881 if (Result.Val) { 3882 Ops.push_back(Result); 3883 return; 3884 } 3885 3886 // Handle standard constraint letters. 3887 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG); 3888} 3889 3890// isLegalAddressingMode - Return true if the addressing mode represented 3891// by AM is legal for this target, for a load/store of the specified type. 3892bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 3893 const Type *Ty) const { 3894 // FIXME: PPC does not allow r+i addressing modes for vectors! 3895 3896 // PPC allows a sign-extended 16-bit immediate field. 3897 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3898 return false; 3899 3900 // No global is ever allowed as a base. 3901 if (AM.BaseGV) 3902 return false; 3903 3904 // PPC only support r+r, 3905 switch (AM.Scale) { 3906 case 0: // "r+i" or just "i", depending on HasBaseReg. 3907 break; 3908 case 1: 3909 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3910 return false; 3911 // Otherwise we have r+r or r+i. 3912 break; 3913 case 2: 3914 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3915 return false; 3916 // Allow 2*r as r+r. 3917 break; 3918 default: 3919 // No other scales are supported. 3920 return false; 3921 } 3922 3923 return true; 3924} 3925 3926/// isLegalAddressImmediate - Return true if the integer value can be used 3927/// as the offset of the target addressing mode for load / store of the 3928/// given type. 3929bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{ 3930 // PPC allows a sign-extended 16-bit immediate field. 3931 return (V > -(1 << 16) && V < (1 << 16)-1); 3932} 3933 3934bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 3935 return false; 3936} 3937 3938SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) { 3939 // Depths > 0 not supported yet! 3940 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 3941 return SDOperand(); 3942 3943 MachineFunction &MF = DAG.getMachineFunction(); 3944 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 3945 int RAIdx = FuncInfo->getReturnAddrSaveIndex(); 3946 if (RAIdx == 0) { 3947 bool isPPC64 = PPCSubTarget.isPPC64(); 3948 int Offset = 3949 PPCFrameInfo::getReturnSaveOffset(isPPC64, PPCSubTarget.isMachoABI()); 3950 3951 // Set up a frame object for the return address. 3952 RAIdx = MF.getFrameInfo()->CreateFixedObject(isPPC64 ? 8 : 4, Offset); 3953 3954 // Remember it for next time. 3955 FuncInfo->setReturnAddrSaveIndex(RAIdx); 3956 3957 // Make sure the function really does not optimize away the store of the RA 3958 // to the stack. 3959 FuncInfo->setLRStoreRequired(); 3960 } 3961 3962 // Just load the return address off the stack. 3963 SDOperand RetAddrFI = DAG.getFrameIndex(RAIdx, getPointerTy()); 3964 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); 3965} 3966 3967SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) { 3968 // Depths > 0 not supported yet! 3969 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 3970 return SDOperand(); 3971 3972 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3973 bool isPPC64 = PtrVT == MVT::i64; 3974 3975 MachineFunction &MF = DAG.getMachineFunction(); 3976 MachineFrameInfo *MFI = MF.getFrameInfo(); 3977 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects()) 3978 && MFI->getStackSize(); 3979 3980 if (isPPC64) 3981 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1, 3982 MVT::i64); 3983 else 3984 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1, 3985 MVT::i32); 3986} 3987