PPCISelLowering.cpp revision dfebc4cc4c267f797e823b781d73586cc6fc49c5
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "MCTargetDesc/PPCPredicates.h" 16#include "PPCMachineFunctionInfo.h" 17#include "PPCPerfectShuffle.h" 18#include "PPCTargetMachine.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/CallingConv.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/SelectionDAG.h" 27#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 28#include "llvm/Constants.h" 29#include "llvm/DerivedTypes.h" 30#include "llvm/Function.h" 31#include "llvm/Intrinsics.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/Target/TargetOptions.h" 37using namespace llvm; 38 39static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 40 CCValAssign::LocInfo &LocInfo, 41 ISD::ArgFlagsTy &ArgFlags, 42 CCState &State); 43static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 44 MVT &LocVT, 45 CCValAssign::LocInfo &LocInfo, 46 ISD::ArgFlagsTy &ArgFlags, 47 CCState &State); 48static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 49 MVT &LocVT, 50 CCValAssign::LocInfo &LocInfo, 51 ISD::ArgFlagsTy &ArgFlags, 52 CCState &State); 53 54static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc", 55cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden); 56 57static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref", 58cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden); 59 60static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) { 61 if (TM.getSubtargetImpl()->isDarwin()) 62 return new TargetLoweringObjectFileMachO(); 63 64 return new TargetLoweringObjectFileELF(); 65} 66 67PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) { 69 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>(); 70 71 setPow2DivIsCheap(); 72 73 // Use _setjmp/_longjmp instead of setjmp/longjmp. 74 setUseUnderscoreSetJmp(true); 75 setUseUnderscoreLongJmp(true); 76 77 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all 78 // arguments are at least 4/8 bytes aligned. 79 bool isPPC64 = Subtarget->isPPC64(); 80 setMinStackArgumentAlignment(isPPC64 ? 8:4); 81 82 // Set up the register classes. 83 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); 84 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); 85 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); 86 87 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 88 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 90 91 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 92 93 // PowerPC has pre-inc load and store's. 94 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 95 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 96 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 97 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 98 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 99 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 100 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 101 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 102 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 103 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 104 105 // This is used in the ppcf128->int sequence. Note it has different semantics 106 // from FP_ROUND: that rounds to nearest, this rounds to zero. 107 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 108 109 // We do not currently implement these libm ops for PowerPC. 110 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand); 111 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); 112 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand); 113 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand); 114 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand); 115 116 // PowerPC has no SREM/UREM instructions 117 setOperationAction(ISD::SREM, MVT::i32, Expand); 118 setOperationAction(ISD::UREM, MVT::i32, Expand); 119 setOperationAction(ISD::SREM, MVT::i64, Expand); 120 setOperationAction(ISD::UREM, MVT::i64, Expand); 121 122 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 123 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 124 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 125 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 126 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 127 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 128 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 129 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 130 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 131 132 // We don't support sin/cos/sqrt/fmod/pow 133 setOperationAction(ISD::FSIN , MVT::f64, Expand); 134 setOperationAction(ISD::FCOS , MVT::f64, Expand); 135 setOperationAction(ISD::FREM , MVT::f64, Expand); 136 setOperationAction(ISD::FPOW , MVT::f64, Expand); 137 setOperationAction(ISD::FMA , MVT::f64, Legal); 138 setOperationAction(ISD::FSIN , MVT::f32, Expand); 139 setOperationAction(ISD::FCOS , MVT::f32, Expand); 140 setOperationAction(ISD::FREM , MVT::f32, Expand); 141 setOperationAction(ISD::FPOW , MVT::f32, Expand); 142 setOperationAction(ISD::FMA , MVT::f32, Legal); 143 144 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 145 146 // If we're enabling GP optimizations, use hardware square root 147 if (!Subtarget->hasFSQRT()) { 148 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 149 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 150 } 151 152 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 153 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 154 155 // PowerPC does not have BSWAP, CTPOP or CTTZ 156 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 157 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 158 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 159 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 160 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 161 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 162 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 163 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 164 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 165 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 166 167 // PowerPC does not have ROTR 168 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 169 setOperationAction(ISD::ROTR, MVT::i64 , Expand); 170 171 // PowerPC does not have Select 172 setOperationAction(ISD::SELECT, MVT::i32, Expand); 173 setOperationAction(ISD::SELECT, MVT::i64, Expand); 174 setOperationAction(ISD::SELECT, MVT::f32, Expand); 175 setOperationAction(ISD::SELECT, MVT::f64, Expand); 176 177 // PowerPC wants to turn select_cc of FP into fsel when possible. 178 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 179 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 180 181 // PowerPC wants to optimize integer setcc a bit 182 setOperationAction(ISD::SETCC, MVT::i32, Custom); 183 184 // PowerPC does not have BRCOND which requires SetCC 185 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 186 187 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 188 189 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 190 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 191 192 // PowerPC does not have [U|S]INT_TO_FP 193 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 194 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 195 196 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 197 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 198 setOperationAction(ISD::BITCAST, MVT::i64, Expand); 199 setOperationAction(ISD::BITCAST, MVT::f64, Expand); 200 201 // We cannot sextinreg(i1). Expand to shifts. 202 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 203 204 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 205 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 206 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 207 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 208 209 210 // We want to legalize GlobalAddress and ConstantPool nodes into the 211 // appropriate instructions to materialize the address. 212 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 213 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 214 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 215 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 216 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 217 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 218 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 219 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 220 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 221 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 222 223 // TRAP is legal. 224 setOperationAction(ISD::TRAP, MVT::Other, Legal); 225 226 // TRAMPOLINE is custom lowered. 227 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 228 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 229 230 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 231 setOperationAction(ISD::VASTART , MVT::Other, Custom); 232 233 if (Subtarget->isSVR4ABI()) { 234 if (isPPC64) { 235 // VAARG always uses double-word chunks, so promote anything smaller. 236 setOperationAction(ISD::VAARG, MVT::i1, Promote); 237 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64); 238 setOperationAction(ISD::VAARG, MVT::i8, Promote); 239 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64); 240 setOperationAction(ISD::VAARG, MVT::i16, Promote); 241 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64); 242 setOperationAction(ISD::VAARG, MVT::i32, Promote); 243 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64); 244 setOperationAction(ISD::VAARG, MVT::Other, Expand); 245 } else { 246 // VAARG is custom lowered with the 32-bit SVR4 ABI. 247 setOperationAction(ISD::VAARG, MVT::Other, Custom); 248 setOperationAction(ISD::VAARG, MVT::i64, Custom); 249 } 250 } else 251 setOperationAction(ISD::VAARG, MVT::Other, Expand); 252 253 // Use the default implementation. 254 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 255 setOperationAction(ISD::VAEND , MVT::Other, Expand); 256 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 257 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 258 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 259 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 260 261 // We want to custom lower some of our intrinsics. 262 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 263 264 // Comparisons that require checking two conditions. 265 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 266 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); 267 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); 268 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); 269 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); 270 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); 271 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 272 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 273 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 274 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 275 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); 276 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); 277 278 if (Subtarget->has64BitSupport()) { 279 // They also have instructions for converting between i64 and fp. 280 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 281 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 282 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 283 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 284 // This is just the low 32 bits of a (signed) fp->i64 conversion. 285 // We cannot do this with Promote because i64 is not a legal type. 286 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 287 288 // FIXME: disable this lowered code. This generates 64-bit register values, 289 // and we don't model the fact that the top part is clobbered by calls. We 290 // need to flag these together so that the value isn't live across a call. 291 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 292 } else { 293 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 294 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 295 } 296 297 if (Subtarget->use64BitRegs()) { 298 // 64-bit PowerPC implementations can support i64 types directly 299 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); 300 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 301 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 302 // 64-bit PowerPC wants to expand i128 shifts itself. 303 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 304 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 305 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 306 } else { 307 // 32-bit PowerPC wants to expand i64 shifts itself. 308 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 309 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 310 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 311 } 312 313 if (Subtarget->hasAltivec()) { 314 // First set operation action for all vector types to expand. Then we 315 // will selectively turn on ones that can be effectively codegen'd. 316 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 317 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 318 MVT::SimpleValueType VT = (MVT::SimpleValueType)i; 319 320 // add/sub are legal for all supported vector VT's. 321 setOperationAction(ISD::ADD , VT, Legal); 322 setOperationAction(ISD::SUB , VT, Legal); 323 324 // We promote all shuffles to v16i8. 325 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 326 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 327 328 // We promote all non-typed operations to v4i32. 329 setOperationAction(ISD::AND , VT, Promote); 330 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 331 setOperationAction(ISD::OR , VT, Promote); 332 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 333 setOperationAction(ISD::XOR , VT, Promote); 334 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 335 setOperationAction(ISD::LOAD , VT, Promote); 336 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 337 setOperationAction(ISD::SELECT, VT, Promote); 338 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 339 setOperationAction(ISD::STORE, VT, Promote); 340 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 341 342 // No other operations are legal. 343 setOperationAction(ISD::MUL , VT, Expand); 344 setOperationAction(ISD::SDIV, VT, Expand); 345 setOperationAction(ISD::SREM, VT, Expand); 346 setOperationAction(ISD::UDIV, VT, Expand); 347 setOperationAction(ISD::UREM, VT, Expand); 348 setOperationAction(ISD::FDIV, VT, Expand); 349 setOperationAction(ISD::FNEG, VT, Expand); 350 setOperationAction(ISD::FSQRT, VT, Expand); 351 setOperationAction(ISD::FLOG, VT, Expand); 352 setOperationAction(ISD::FLOG10, VT, Expand); 353 setOperationAction(ISD::FLOG2, VT, Expand); 354 setOperationAction(ISD::FEXP, VT, Expand); 355 setOperationAction(ISD::FEXP2, VT, Expand); 356 setOperationAction(ISD::FSIN, VT, Expand); 357 setOperationAction(ISD::FCOS, VT, Expand); 358 setOperationAction(ISD::FABS, VT, Expand); 359 setOperationAction(ISD::FPOWI, VT, Expand); 360 setOperationAction(ISD::FFLOOR, VT, Expand); 361 setOperationAction(ISD::FCEIL, VT, Expand); 362 setOperationAction(ISD::FTRUNC, VT, Expand); 363 setOperationAction(ISD::FRINT, VT, Expand); 364 setOperationAction(ISD::FNEARBYINT, VT, Expand); 365 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); 366 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 367 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); 368 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 369 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 370 setOperationAction(ISD::UDIVREM, VT, Expand); 371 setOperationAction(ISD::SDIVREM, VT, Expand); 372 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); 373 setOperationAction(ISD::FPOW, VT, Expand); 374 setOperationAction(ISD::CTPOP, VT, Expand); 375 setOperationAction(ISD::CTLZ, VT, Expand); 376 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); 377 setOperationAction(ISD::CTTZ, VT, Expand); 378 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); 379 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); 380 381 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 382 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) { 383 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j; 384 setTruncStoreAction(VT, InnerVT, Expand); 385 } 386 setLoadExtAction(ISD::SEXTLOAD, VT, Expand); 387 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand); 388 setLoadExtAction(ISD::EXTLOAD, VT, Expand); 389 } 390 391 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 392 // with merges, splats, etc. 393 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 394 395 setOperationAction(ISD::AND , MVT::v4i32, Legal); 396 setOperationAction(ISD::OR , MVT::v4i32, Legal); 397 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 398 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 399 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 400 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 401 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 402 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal); 403 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 404 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); 405 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); 406 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); 407 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); 408 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); 409 410 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); 411 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); 412 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); 413 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass); 414 415 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 416 setOperationAction(ISD::FMA, MVT::v4f32, Legal); 417 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 418 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 419 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 420 421 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 422 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 423 424 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 425 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 426 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 427 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 428 429 // Altivec does not contain unordered floating-point compare instructions 430 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand); 431 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand); 432 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand); 433 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand); 434 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand); 435 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand); 436 } 437 438 if (Subtarget->has64BitSupport()) { 439 setOperationAction(ISD::PREFETCH, MVT::Other, Legal); 440 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal); 441 } 442 443 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 444 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 445 446 setBooleanContents(ZeroOrOneBooleanContent); 447 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 448 449 if (isPPC64) { 450 setStackPointerRegisterToSaveRestore(PPC::X1); 451 setExceptionPointerRegister(PPC::X3); 452 setExceptionSelectorRegister(PPC::X4); 453 } else { 454 setStackPointerRegisterToSaveRestore(PPC::R1); 455 setExceptionPointerRegister(PPC::R3); 456 setExceptionSelectorRegister(PPC::R4); 457 } 458 459 // We have target-specific dag combine patterns for the following nodes: 460 setTargetDAGCombine(ISD::SINT_TO_FP); 461 setTargetDAGCombine(ISD::STORE); 462 setTargetDAGCombine(ISD::BR_CC); 463 setTargetDAGCombine(ISD::BSWAP); 464 465 // Darwin long double math library functions have $LDBL128 appended. 466 if (Subtarget->isDarwin()) { 467 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 468 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 469 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 470 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 471 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 472 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128"); 473 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128"); 474 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128"); 475 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128"); 476 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128"); 477 } 478 479 setMinFunctionAlignment(2); 480 if (PPCSubTarget.isDarwin()) 481 setPrefFunctionAlignment(4); 482 483 if (isPPC64 && Subtarget->isJITCodeModel()) 484 // Temporary workaround for the inability of PPC64 JIT to handle jump 485 // tables. 486 setSupportJumpTables(false); 487 488 setInsertFencesForAtomic(true); 489 490 setSchedulingPreference(Sched::Hybrid); 491 492 computeRegisterProperties(); 493 494 // The Freescale cores does better with aggressive inlining of memcpy and 495 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores). 496 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc || 497 Subtarget->getDarwinDirective() == PPC::DIR_E5500) { 498 maxStoresPerMemset = 32; 499 maxStoresPerMemsetOptSize = 16; 500 maxStoresPerMemcpy = 32; 501 maxStoresPerMemcpyOptSize = 8; 502 maxStoresPerMemmove = 32; 503 maxStoresPerMemmoveOptSize = 8; 504 505 setPrefFunctionAlignment(4); 506 benefitFromCodePlacementOpt = true; 507 } 508} 509 510/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 511/// function arguments in the caller parameter area. 512unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const { 513 const TargetMachine &TM = getTargetMachine(); 514 // Darwin passes everything on 4 byte boundary. 515 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) 516 return 4; 517 518 // 16byte and wider vectors are passed on 16byte boundary. 519 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) 520 if (VTy->getBitWidth() >= 128) 521 return 16; 522 523 // The rest is 8 on PPC64 and 4 on PPC32 boundary. 524 if (PPCSubTarget.isPPC64()) 525 return 8; 526 527 return 4; 528} 529 530const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 531 switch (Opcode) { 532 default: return 0; 533 case PPCISD::FSEL: return "PPCISD::FSEL"; 534 case PPCISD::FCFID: return "PPCISD::FCFID"; 535 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 536 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 537 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 538 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 539 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 540 case PPCISD::VPERM: return "PPCISD::VPERM"; 541 case PPCISD::Hi: return "PPCISD::Hi"; 542 case PPCISD::Lo: return "PPCISD::Lo"; 543 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY"; 544 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE"; 545 case PPCISD::LOAD: return "PPCISD::LOAD"; 546 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC"; 547 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 548 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 549 case PPCISD::SRL: return "PPCISD::SRL"; 550 case PPCISD::SRA: return "PPCISD::SRA"; 551 case PPCISD::SHL: return "PPCISD::SHL"; 552 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 553 case PPCISD::STD_32: return "PPCISD::STD_32"; 554 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4"; 555 case PPCISD::CALL_NOP_SVR4: return "PPCISD::CALL_NOP_SVR4"; 556 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin"; 557 case PPCISD::NOP: return "PPCISD::NOP"; 558 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 559 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin"; 560 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4"; 561 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 562 case PPCISD::MFCR: return "PPCISD::MFCR"; 563 case PPCISD::VCMP: return "PPCISD::VCMP"; 564 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 565 case PPCISD::LBRX: return "PPCISD::LBRX"; 566 case PPCISD::STBRX: return "PPCISD::STBRX"; 567 case PPCISD::LARX: return "PPCISD::LARX"; 568 case PPCISD::STCX: return "PPCISD::STCX"; 569 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 570 case PPCISD::MFFS: return "PPCISD::MFFS"; 571 case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; 572 case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; 573 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 574 case PPCISD::MTFSF: return "PPCISD::MTFSF"; 575 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; 576 case PPCISD::CR6SET: return "PPCISD::CR6SET"; 577 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET"; 578 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA"; 579 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L"; 580 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L"; 581 case PPCISD::LD_GOT_TPREL: return "PPCISD::LD_GOT_TPREL"; 582 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS"; 583 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA"; 584 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L"; 585 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR"; 586 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA"; 587 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L"; 588 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR"; 589 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA"; 590 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L"; 591 } 592} 593 594EVT PPCTargetLowering::getSetCCResultType(EVT VT) const { 595 if (!VT.isVector()) 596 return MVT::i32; 597 return VT.changeVectorElementTypeToInteger(); 598} 599 600//===----------------------------------------------------------------------===// 601// Node matching predicates, for use by the tblgen matching code. 602//===----------------------------------------------------------------------===// 603 604/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 605static bool isFloatingPointZero(SDValue Op) { 606 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 607 return CFP->getValueAPF().isZero(); 608 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 609 // Maybe this has already been legalized into the constant pool? 610 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 611 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 612 return CFP->getValueAPF().isZero(); 613 } 614 return false; 615} 616 617/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 618/// true if Op is undef or if it matches the specified value. 619static bool isConstantOrUndef(int Op, int Val) { 620 return Op < 0 || Op == Val; 621} 622 623/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 624/// VPKUHUM instruction. 625bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 626 if (!isUnary) { 627 for (unsigned i = 0; i != 16; ++i) 628 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1)) 629 return false; 630 } else { 631 for (unsigned i = 0; i != 8; ++i) 632 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) || 633 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1)) 634 return false; 635 } 636 return true; 637} 638 639/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 640/// VPKUWUM instruction. 641bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 642 if (!isUnary) { 643 for (unsigned i = 0; i != 16; i += 2) 644 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 645 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3)) 646 return false; 647 } else { 648 for (unsigned i = 0; i != 8; i += 2) 649 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 650 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) || 651 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) || 652 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3)) 653 return false; 654 } 655 return true; 656} 657 658/// isVMerge - Common function, used to match vmrg* shuffles. 659/// 660static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, 661 unsigned LHSStart, unsigned RHSStart) { 662 assert(N->getValueType(0) == MVT::v16i8 && 663 "PPC only supports shuffles by bytes!"); 664 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 665 "Unsupported merge size!"); 666 667 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 668 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 669 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j), 670 LHSStart+j+i*UnitSize) || 671 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j), 672 RHSStart+j+i*UnitSize)) 673 return false; 674 } 675 return true; 676} 677 678/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 679/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 680bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 681 bool isUnary) { 682 if (!isUnary) 683 return isVMerge(N, UnitSize, 8, 24); 684 return isVMerge(N, UnitSize, 8, 8); 685} 686 687/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 688/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 689bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 690 bool isUnary) { 691 if (!isUnary) 692 return isVMerge(N, UnitSize, 0, 16); 693 return isVMerge(N, UnitSize, 0, 0); 694} 695 696 697/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 698/// amount, otherwise return -1. 699int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 700 assert(N->getValueType(0) == MVT::v16i8 && 701 "PPC only supports shuffles by bytes!"); 702 703 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 704 705 // Find the first non-undef value in the shuffle mask. 706 unsigned i; 707 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i) 708 /*search*/; 709 710 if (i == 16) return -1; // all undef. 711 712 // Otherwise, check to see if the rest of the elements are consecutively 713 // numbered from this value. 714 unsigned ShiftAmt = SVOp->getMaskElt(i); 715 if (ShiftAmt < i) return -1; 716 ShiftAmt -= i; 717 718 if (!isUnary) { 719 // Check the rest of the elements to see if they are consecutive. 720 for (++i; i != 16; ++i) 721 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) 722 return -1; 723 } else { 724 // Check the rest of the elements to see if they are consecutive. 725 for (++i; i != 16; ++i) 726 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) 727 return -1; 728 } 729 return ShiftAmt; 730} 731 732/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 733/// specifies a splat of a single element that is suitable for input to 734/// VSPLTB/VSPLTH/VSPLTW. 735bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { 736 assert(N->getValueType(0) == MVT::v16i8 && 737 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 738 739 // This is a splat operation if each element of the permute is the same, and 740 // if the value doesn't reference the second vector. 741 unsigned ElementBase = N->getMaskElt(0); 742 743 // FIXME: Handle UNDEF elements too! 744 if (ElementBase >= 16) 745 return false; 746 747 // Check that the indices are consecutive, in the case of a multi-byte element 748 // splatted with a v16i8 mask. 749 for (unsigned i = 1; i != EltSize; ++i) 750 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase)) 751 return false; 752 753 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 754 if (N->getMaskElt(i) < 0) continue; 755 for (unsigned j = 0; j != EltSize; ++j) 756 if (N->getMaskElt(i+j) != N->getMaskElt(j)) 757 return false; 758 } 759 return true; 760} 761 762/// isAllNegativeZeroVector - Returns true if all elements of build_vector 763/// are -0.0. 764bool PPC::isAllNegativeZeroVector(SDNode *N) { 765 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N); 766 767 APInt APVal, APUndef; 768 unsigned BitSize; 769 bool HasAnyUndefs; 770 771 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true)) 772 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 773 return CFP->getValueAPF().isNegZero(); 774 775 return false; 776} 777 778/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 779/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 780unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 781 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 782 assert(isSplatShuffleMask(SVOp, EltSize)); 783 return SVOp->getMaskElt(0) / EltSize; 784} 785 786/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 787/// by using a vspltis[bhw] instruction of the specified element size, return 788/// the constant being splatted. The ByteSize field indicates the number of 789/// bytes of each element [124] -> [bhw]. 790SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 791 SDValue OpVal(0, 0); 792 793 // If ByteSize of the splat is bigger than the element size of the 794 // build_vector, then we have a case where we are checking for a splat where 795 // multiple elements of the buildvector are folded together into a single 796 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 797 unsigned EltSize = 16/N->getNumOperands(); 798 if (EltSize < ByteSize) { 799 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 800 SDValue UniquedVals[4]; 801 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 802 803 // See if all of the elements in the buildvector agree across. 804 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 805 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 806 // If the element isn't a constant, bail fully out. 807 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue(); 808 809 810 if (UniquedVals[i&(Multiple-1)].getNode() == 0) 811 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 812 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 813 return SDValue(); // no match. 814 } 815 816 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 817 // either constant or undef values that are identical for each chunk. See 818 // if these chunks can form into a larger vspltis*. 819 820 // Check to see if all of the leading entries are either 0 or -1. If 821 // neither, then this won't fit into the immediate field. 822 bool LeadingZero = true; 823 bool LeadingOnes = true; 824 for (unsigned i = 0; i != Multiple-1; ++i) { 825 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs. 826 827 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 828 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 829 } 830 // Finally, check the least significant entry. 831 if (LeadingZero) { 832 if (UniquedVals[Multiple-1].getNode() == 0) 833 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 834 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue(); 835 if (Val < 16) 836 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 837 } 838 if (LeadingOnes) { 839 if (UniquedVals[Multiple-1].getNode() == 0) 840 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 841 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue(); 842 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 843 return DAG.getTargetConstant(Val, MVT::i32); 844 } 845 846 return SDValue(); 847 } 848 849 // Check to see if this buildvec has a single non-undef value in its elements. 850 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 851 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 852 if (OpVal.getNode() == 0) 853 OpVal = N->getOperand(i); 854 else if (OpVal != N->getOperand(i)) 855 return SDValue(); 856 } 857 858 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def. 859 860 unsigned ValSizeInBytes = EltSize; 861 uint64_t Value = 0; 862 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 863 Value = CN->getZExtValue(); 864 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 865 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 866 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 867 } 868 869 // If the splat value is larger than the element value, then we can never do 870 // this splat. The only case that we could fit the replicated bits into our 871 // immediate field for would be zero, and we prefer to use vxor for it. 872 if (ValSizeInBytes < ByteSize) return SDValue(); 873 874 // If the element value is larger than the splat value, cut it in half and 875 // check to see if the two halves are equal. Continue doing this until we 876 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 877 while (ValSizeInBytes > ByteSize) { 878 ValSizeInBytes >>= 1; 879 880 // If the top half equals the bottom half, we're still ok. 881 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 882 (Value & ((1 << (8*ValSizeInBytes))-1))) 883 return SDValue(); 884 } 885 886 // Properly sign extend the value. 887 int MaskVal = SignExtend32(Value, ByteSize * 8); 888 889 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 890 if (MaskVal == 0) return SDValue(); 891 892 // Finally, if this value fits in a 5 bit sext field, return it 893 if (SignExtend32<5>(MaskVal) == MaskVal) 894 return DAG.getTargetConstant(MaskVal, MVT::i32); 895 return SDValue(); 896} 897 898//===----------------------------------------------------------------------===// 899// Addressing Mode Selection 900//===----------------------------------------------------------------------===// 901 902/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 903/// or 64-bit immediate, and if the value can be accurately represented as a 904/// sign extension from a 16-bit value. If so, this returns true and the 905/// immediate. 906static bool isIntS16Immediate(SDNode *N, short &Imm) { 907 if (N->getOpcode() != ISD::Constant) 908 return false; 909 910 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 911 if (N->getValueType(0) == MVT::i32) 912 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 913 else 914 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 915} 916static bool isIntS16Immediate(SDValue Op, short &Imm) { 917 return isIntS16Immediate(Op.getNode(), Imm); 918} 919 920 921/// SelectAddressRegReg - Given the specified addressed, check to see if it 922/// can be represented as an indexed [r+r] operation. Returns false if it 923/// can be more efficiently represented with [r+imm]. 924bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, 925 SDValue &Index, 926 SelectionDAG &DAG) const { 927 short imm = 0; 928 if (N.getOpcode() == ISD::ADD) { 929 if (isIntS16Immediate(N.getOperand(1), imm)) 930 return false; // r+i 931 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 932 return false; // r+i 933 934 Base = N.getOperand(0); 935 Index = N.getOperand(1); 936 return true; 937 } else if (N.getOpcode() == ISD::OR) { 938 if (isIntS16Immediate(N.getOperand(1), imm)) 939 return false; // r+i can fold it if we can. 940 941 // If this is an or of disjoint bitfields, we can codegen this as an add 942 // (for better address arithmetic) if the LHS and RHS of the OR are provably 943 // disjoint. 944 APInt LHSKnownZero, LHSKnownOne; 945 APInt RHSKnownZero, RHSKnownOne; 946 DAG.ComputeMaskedBits(N.getOperand(0), 947 LHSKnownZero, LHSKnownOne); 948 949 if (LHSKnownZero.getBoolValue()) { 950 DAG.ComputeMaskedBits(N.getOperand(1), 951 RHSKnownZero, RHSKnownOne); 952 // If all of the bits are known zero on the LHS or RHS, the add won't 953 // carry. 954 if (~(LHSKnownZero | RHSKnownZero) == 0) { 955 Base = N.getOperand(0); 956 Index = N.getOperand(1); 957 return true; 958 } 959 } 960 } 961 962 return false; 963} 964 965/// Returns true if the address N can be represented by a base register plus 966/// a signed 16-bit displacement [r+imm], and if it is not better 967/// represented as reg+reg. 968bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, 969 SDValue &Base, 970 SelectionDAG &DAG) const { 971 // FIXME dl should come from parent load or store, not from address 972 DebugLoc dl = N.getDebugLoc(); 973 // If this can be more profitably realized as r+r, fail. 974 if (SelectAddressRegReg(N, Disp, Base, DAG)) 975 return false; 976 977 if (N.getOpcode() == ISD::ADD) { 978 short imm = 0; 979 if (isIntS16Immediate(N.getOperand(1), imm)) { 980 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 981 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 982 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 983 } else { 984 Base = N.getOperand(0); 985 } 986 return true; // [r+i] 987 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 988 // Match LOAD (ADD (X, Lo(G))). 989 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 990 && "Cannot handle constant offsets yet!"); 991 Disp = N.getOperand(1).getOperand(0); // The global address. 992 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 993 Disp.getOpcode() == ISD::TargetGlobalTLSAddress || 994 Disp.getOpcode() == ISD::TargetConstantPool || 995 Disp.getOpcode() == ISD::TargetJumpTable); 996 Base = N.getOperand(0); 997 return true; // [&g+r] 998 } 999 } else if (N.getOpcode() == ISD::OR) { 1000 short imm = 0; 1001 if (isIntS16Immediate(N.getOperand(1), imm)) { 1002 // If this is an or of disjoint bitfields, we can codegen this as an add 1003 // (for better address arithmetic) if the LHS and RHS of the OR are 1004 // provably disjoint. 1005 APInt LHSKnownZero, LHSKnownOne; 1006 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne); 1007 1008 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 1009 // If all of the bits are known zero on the LHS or RHS, the add won't 1010 // carry. 1011 Base = N.getOperand(0); 1012 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 1013 return true; 1014 } 1015 } 1016 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 1017 // Loading from a constant address. 1018 1019 // If this address fits entirely in a 16-bit sext immediate field, codegen 1020 // this as "d, 0" 1021 short Imm; 1022 if (isIntS16Immediate(CN, Imm)) { 1023 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 1024 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 1025 CN->getValueType(0)); 1026 return true; 1027 } 1028 1029 // Handle 32-bit sext immediates with LIS + addr mode. 1030 if (CN->getValueType(0) == MVT::i32 || 1031 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 1032 int Addr = (int)CN->getZExtValue(); 1033 1034 // Otherwise, break this down into an LIS + disp. 1035 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 1036 1037 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 1038 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1039 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); 1040 return true; 1041 } 1042 } 1043 1044 Disp = DAG.getTargetConstant(0, getPointerTy()); 1045 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1046 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1047 else 1048 Base = N; 1049 return true; // [r+0] 1050} 1051 1052/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 1053/// represented as an indexed [r+r] operation. 1054bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, 1055 SDValue &Index, 1056 SelectionDAG &DAG) const { 1057 // Check to see if we can easily represent this as an [r+r] address. This 1058 // will fail if it thinks that the address is more profitably represented as 1059 // reg+imm, e.g. where imm = 0. 1060 if (SelectAddressRegReg(N, Base, Index, DAG)) 1061 return true; 1062 1063 // If the operand is an addition, always emit this as [r+r], since this is 1064 // better (for code size, and execution, as the memop does the add for free) 1065 // than emitting an explicit add. 1066 if (N.getOpcode() == ISD::ADD) { 1067 Base = N.getOperand(0); 1068 Index = N.getOperand(1); 1069 return true; 1070 } 1071 1072 // Otherwise, do it the hard way, using R0 as the base register. 1073 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 1074 N.getValueType()); 1075 Index = N; 1076 return true; 1077} 1078 1079/// SelectAddressRegImmShift - Returns true if the address N can be 1080/// represented by a base register plus a signed 14-bit displacement 1081/// [r+imm*4]. Suitable for use by STD and friends. 1082bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, 1083 SDValue &Base, 1084 SelectionDAG &DAG) const { 1085 // FIXME dl should come from the parent load or store, not the address 1086 DebugLoc dl = N.getDebugLoc(); 1087 // If this can be more profitably realized as r+r, fail. 1088 if (SelectAddressRegReg(N, Disp, Base, DAG)) 1089 return false; 1090 1091 if (N.getOpcode() == ISD::ADD) { 1092 short imm = 0; 1093 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 1094 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 1095 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 1096 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1097 } else { 1098 Base = N.getOperand(0); 1099 } 1100 return true; // [r+i] 1101 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 1102 // Match LOAD (ADD (X, Lo(G))). 1103 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 1104 && "Cannot handle constant offsets yet!"); 1105 Disp = N.getOperand(1).getOperand(0); // The global address. 1106 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 1107 Disp.getOpcode() == ISD::TargetConstantPool || 1108 Disp.getOpcode() == ISD::TargetJumpTable); 1109 Base = N.getOperand(0); 1110 return true; // [&g+r] 1111 } 1112 } else if (N.getOpcode() == ISD::OR) { 1113 short imm = 0; 1114 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 1115 // If this is an or of disjoint bitfields, we can codegen this as an add 1116 // (for better address arithmetic) if the LHS and RHS of the OR are 1117 // provably disjoint. 1118 APInt LHSKnownZero, LHSKnownOne; 1119 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne); 1120 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 1121 // If all of the bits are known zero on the LHS or RHS, the add won't 1122 // carry. 1123 Base = N.getOperand(0); 1124 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 1125 return true; 1126 } 1127 } 1128 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 1129 // Loading from a constant address. Verify low two bits are clear. 1130 if ((CN->getZExtValue() & 3) == 0) { 1131 // If this address fits entirely in a 14-bit sext immediate field, codegen 1132 // this as "d, 0" 1133 short Imm; 1134 if (isIntS16Immediate(CN, Imm)) { 1135 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 1136 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 1137 CN->getValueType(0)); 1138 return true; 1139 } 1140 1141 // Fold the low-part of 32-bit absolute addresses into addr mode. 1142 if (CN->getValueType(0) == MVT::i32 || 1143 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 1144 int Addr = (int)CN->getZExtValue(); 1145 1146 // Otherwise, break this down into an LIS + disp. 1147 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 1148 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 1149 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1150 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0); 1151 return true; 1152 } 1153 } 1154 } 1155 1156 Disp = DAG.getTargetConstant(0, getPointerTy()); 1157 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1158 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1159 else 1160 Base = N; 1161 return true; // [r+0] 1162} 1163 1164 1165/// getPreIndexedAddressParts - returns true by value, base pointer and 1166/// offset pointer and addressing mode by reference if the node's address 1167/// can be legally represented as pre-indexed load / store address. 1168bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1169 SDValue &Offset, 1170 ISD::MemIndexedMode &AM, 1171 SelectionDAG &DAG) const { 1172 if (DisablePPCPreinc) return false; 1173 1174 SDValue Ptr; 1175 EVT VT; 1176 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1177 Ptr = LD->getBasePtr(); 1178 VT = LD->getMemoryVT(); 1179 1180 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1181 Ptr = ST->getBasePtr(); 1182 VT = ST->getMemoryVT(); 1183 } else 1184 return false; 1185 1186 // PowerPC doesn't have preinc load/store instructions for vectors. 1187 if (VT.isVector()) 1188 return false; 1189 1190 if (SelectAddressRegReg(Ptr, Offset, Base, DAG)) { 1191 AM = ISD::PRE_INC; 1192 return true; 1193 } 1194 1195 // LDU/STU use reg+imm*4, others use reg+imm. 1196 if (VT != MVT::i64) { 1197 // reg + imm 1198 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 1199 return false; 1200 } else { 1201 // reg + imm * 4. 1202 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 1203 return false; 1204 } 1205 1206 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1207 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 1208 // sext i32 to i64 when addr mode is r+i. 1209 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 1210 LD->getExtensionType() == ISD::SEXTLOAD && 1211 isa<ConstantSDNode>(Offset)) 1212 return false; 1213 } 1214 1215 AM = ISD::PRE_INC; 1216 return true; 1217} 1218 1219//===----------------------------------------------------------------------===// 1220// LowerOperation implementation 1221//===----------------------------------------------------------------------===// 1222 1223/// GetLabelAccessInfo - Return true if we should reference labels using a 1224/// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags. 1225static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags, 1226 unsigned &LoOpFlags, const GlobalValue *GV = 0) { 1227 HiOpFlags = PPCII::MO_HA16; 1228 LoOpFlags = PPCII::MO_LO16; 1229 1230 // Don't use the pic base if not in PIC relocation model. Or if we are on a 1231 // non-darwin platform. We don't support PIC on other platforms yet. 1232 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ && 1233 TM.getSubtarget<PPCSubtarget>().isDarwin(); 1234 if (isPIC) { 1235 HiOpFlags |= PPCII::MO_PIC_FLAG; 1236 LoOpFlags |= PPCII::MO_PIC_FLAG; 1237 } 1238 1239 // If this is a reference to a global value that requires a non-lazy-ptr, make 1240 // sure that instruction lowering adds it. 1241 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) { 1242 HiOpFlags |= PPCII::MO_NLP_FLAG; 1243 LoOpFlags |= PPCII::MO_NLP_FLAG; 1244 1245 if (GV->hasHiddenVisibility()) { 1246 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; 1247 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; 1248 } 1249 } 1250 1251 return isPIC; 1252} 1253 1254static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, 1255 SelectionDAG &DAG) { 1256 EVT PtrVT = HiPart.getValueType(); 1257 SDValue Zero = DAG.getConstant(0, PtrVT); 1258 DebugLoc DL = HiPart.getDebugLoc(); 1259 1260 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero); 1261 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero); 1262 1263 // With PIC, the first instruction is actually "GR+hi(&G)". 1264 if (isPIC) 1265 Hi = DAG.getNode(ISD::ADD, DL, PtrVT, 1266 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi); 1267 1268 // Generate non-pic code that has direct accesses to the constant pool. 1269 // The address of the global is just (hi(&g)+lo(&g)). 1270 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1271} 1272 1273SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, 1274 SelectionDAG &DAG) const { 1275 EVT PtrVT = Op.getValueType(); 1276 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1277 const Constant *C = CP->getConstVal(); 1278 1279 // 64-bit SVR4 ABI code is always position-independent. 1280 // The actual address of the GlobalValue is stored in the TOC. 1281 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1282 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0); 1283 return DAG.getNode(PPCISD::TOC_ENTRY, CP->getDebugLoc(), MVT::i64, GA, 1284 DAG.getRegister(PPC::X2, MVT::i64)); 1285 } 1286 1287 unsigned MOHiFlag, MOLoFlag; 1288 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1289 SDValue CPIHi = 1290 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag); 1291 SDValue CPILo = 1292 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag); 1293 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG); 1294} 1295 1296SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 1297 EVT PtrVT = Op.getValueType(); 1298 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1299 1300 // 64-bit SVR4 ABI code is always position-independent. 1301 // The actual address of the GlobalValue is stored in the TOC. 1302 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1303 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1304 return DAG.getNode(PPCISD::TOC_ENTRY, JT->getDebugLoc(), MVT::i64, GA, 1305 DAG.getRegister(PPC::X2, MVT::i64)); 1306 } 1307 1308 unsigned MOHiFlag, MOLoFlag; 1309 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1310 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag); 1311 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag); 1312 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG); 1313} 1314 1315SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, 1316 SelectionDAG &DAG) const { 1317 EVT PtrVT = Op.getValueType(); 1318 1319 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1320 1321 unsigned MOHiFlag, MOLoFlag; 1322 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1323 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag); 1324 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag); 1325 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG); 1326} 1327 1328SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, 1329 SelectionDAG &DAG) const { 1330 1331 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1332 DebugLoc dl = GA->getDebugLoc(); 1333 const GlobalValue *GV = GA->getGlobal(); 1334 EVT PtrVT = getPointerTy(); 1335 bool is64bit = PPCSubTarget.isPPC64(); 1336 1337 TLSModel::Model Model = getTargetMachine().getTLSModel(GV); 1338 1339 if (Model == TLSModel::LocalExec) { 1340 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1341 PPCII::MO_TPREL16_HA); 1342 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1343 PPCII::MO_TPREL16_LO); 1344 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2, 1345 is64bit ? MVT::i64 : MVT::i32); 1346 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg); 1347 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi); 1348 } 1349 1350 if (!is64bit) 1351 llvm_unreachable("only local-exec is currently supported for ppc32"); 1352 1353 if (Model == TLSModel::InitialExec) { 1354 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0); 1355 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); 1356 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL, dl, 1357 PtrVT, TGA, GOTReg); 1358 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGA); 1359 } 1360 1361 if (Model == TLSModel::GeneralDynamic) { 1362 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0); 1363 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); 1364 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT, 1365 GOTReg, TGA); 1366 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT, 1367 GOTEntryHi, TGA); 1368 1369 // We need a chain node, and don't have one handy. The underlying 1370 // call has no side effects, so using the function entry node 1371 // suffices. 1372 SDValue Chain = DAG.getEntryNode(); 1373 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry); 1374 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64); 1375 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl, 1376 PtrVT, ParmReg, TGA); 1377 // The return value from GET_TLS_ADDR really is in X3 already, but 1378 // some hacks are needed here to tie everything together. The extra 1379 // copies dissolve during subsequent transforms. 1380 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr); 1381 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT); 1382 } 1383 1384 if (Model == TLSModel::LocalDynamic) { 1385 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0); 1386 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); 1387 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT, 1388 GOTReg, TGA); 1389 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT, 1390 GOTEntryHi, TGA); 1391 1392 // We need a chain node, and don't have one handy. The underlying 1393 // call has no side effects, so using the function entry node 1394 // suffices. 1395 SDValue Chain = DAG.getEntryNode(); 1396 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry); 1397 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64); 1398 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl, 1399 PtrVT, ParmReg, TGA); 1400 // The return value from GET_TLSLD_ADDR really is in X3 already, but 1401 // some hacks are needed here to tie everything together. The extra 1402 // copies dissolve during subsequent transforms. 1403 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr); 1404 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT, 1405 ParmReg, TGA, Chain); 1406 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA); 1407 } 1408 1409 llvm_unreachable("Unknown TLS model!"); 1410} 1411 1412SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, 1413 SelectionDAG &DAG) const { 1414 EVT PtrVT = Op.getValueType(); 1415 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1416 DebugLoc DL = GSDN->getDebugLoc(); 1417 const GlobalValue *GV = GSDN->getGlobal(); 1418 1419 // 64-bit SVR4 ABI code is always position-independent. 1420 // The actual address of the GlobalValue is stored in the TOC. 1421 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1422 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset()); 1423 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA, 1424 DAG.getRegister(PPC::X2, MVT::i64)); 1425 } 1426 1427 unsigned MOHiFlag, MOLoFlag; 1428 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV); 1429 1430 SDValue GAHi = 1431 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag); 1432 SDValue GALo = 1433 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag); 1434 1435 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG); 1436 1437 // If the global reference is actually to a non-lazy-pointer, we have to do an 1438 // extra load to get the address of the global. 1439 if (MOHiFlag & PPCII::MO_NLP_FLAG) 1440 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(), 1441 false, false, false, 0); 1442 return Ptr; 1443} 1444 1445SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1446 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1447 DebugLoc dl = Op.getDebugLoc(); 1448 1449 // If we're comparing for equality to zero, expose the fact that this is 1450 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1451 // fold the new nodes. 1452 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1453 if (C->isNullValue() && CC == ISD::SETEQ) { 1454 EVT VT = Op.getOperand(0).getValueType(); 1455 SDValue Zext = Op.getOperand(0); 1456 if (VT.bitsLT(MVT::i32)) { 1457 VT = MVT::i32; 1458 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); 1459 } 1460 unsigned Log2b = Log2_32(VT.getSizeInBits()); 1461 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); 1462 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, 1463 DAG.getConstant(Log2b, MVT::i32)); 1464 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); 1465 } 1466 // Leave comparisons against 0 and -1 alone for now, since they're usually 1467 // optimized. FIXME: revisit this when we can custom lower all setcc 1468 // optimizations. 1469 if (C->isAllOnesValue() || C->isNullValue()) 1470 return SDValue(); 1471 } 1472 1473 // If we have an integer seteq/setne, turn it into a compare against zero 1474 // by xor'ing the rhs with the lhs, which is faster than setting a 1475 // condition register, reading it back out, and masking the correct bit. The 1476 // normal approach here uses sub to do this instead of xor. Using xor exposes 1477 // the result to other bit-twiddling opportunities. 1478 EVT LHSVT = Op.getOperand(0).getValueType(); 1479 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1480 EVT VT = Op.getValueType(); 1481 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), 1482 Op.getOperand(1)); 1483 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); 1484 } 1485 return SDValue(); 1486} 1487 1488SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, 1489 const PPCSubtarget &Subtarget) const { 1490 SDNode *Node = Op.getNode(); 1491 EVT VT = Node->getValueType(0); 1492 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1493 SDValue InChain = Node->getOperand(0); 1494 SDValue VAListPtr = Node->getOperand(1); 1495 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1496 DebugLoc dl = Node->getDebugLoc(); 1497 1498 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); 1499 1500 // gpr_index 1501 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, 1502 VAListPtr, MachinePointerInfo(SV), MVT::i8, 1503 false, false, 0); 1504 InChain = GprIndex.getValue(1); 1505 1506 if (VT == MVT::i64) { 1507 // Check if GprIndex is even 1508 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex, 1509 DAG.getConstant(1, MVT::i32)); 1510 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd, 1511 DAG.getConstant(0, MVT::i32), ISD::SETNE); 1512 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex, 1513 DAG.getConstant(1, MVT::i32)); 1514 // Align GprIndex to be even if it isn't 1515 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne, 1516 GprIndex); 1517 } 1518 1519 // fpr index is 1 byte after gpr 1520 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1521 DAG.getConstant(1, MVT::i32)); 1522 1523 // fpr 1524 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, 1525 FprPtr, MachinePointerInfo(SV), MVT::i8, 1526 false, false, 0); 1527 InChain = FprIndex.getValue(1); 1528 1529 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1530 DAG.getConstant(8, MVT::i32)); 1531 1532 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1533 DAG.getConstant(4, MVT::i32)); 1534 1535 // areas 1536 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, 1537 MachinePointerInfo(), false, false, 1538 false, 0); 1539 InChain = OverflowArea.getValue(1); 1540 1541 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, 1542 MachinePointerInfo(), false, false, 1543 false, 0); 1544 InChain = RegSaveArea.getValue(1); 1545 1546 // select overflow_area if index > 8 1547 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, 1548 DAG.getConstant(8, MVT::i32), ISD::SETLT); 1549 1550 // adjustment constant gpr_index * 4/8 1551 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32, 1552 VT.isInteger() ? GprIndex : FprIndex, 1553 DAG.getConstant(VT.isInteger() ? 4 : 8, 1554 MVT::i32)); 1555 1556 // OurReg = RegSaveArea + RegConstant 1557 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea, 1558 RegConstant); 1559 1560 // Floating types are 32 bytes into RegSaveArea 1561 if (VT.isFloatingPoint()) 1562 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg, 1563 DAG.getConstant(32, MVT::i32)); 1564 1565 // increase {f,g}pr_index by 1 (or 2 if VT is i64) 1566 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32, 1567 VT.isInteger() ? GprIndex : FprIndex, 1568 DAG.getConstant(VT == MVT::i64 ? 2 : 1, 1569 MVT::i32)); 1570 1571 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1, 1572 VT.isInteger() ? VAListPtr : FprPtr, 1573 MachinePointerInfo(SV), 1574 MVT::i8, false, false, 0); 1575 1576 // determine if we should load from reg_save_area or overflow_area 1577 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea); 1578 1579 // increase overflow_area by 4/8 if gpr/fpr > 8 1580 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea, 1581 DAG.getConstant(VT.isInteger() ? 4 : 8, 1582 MVT::i32)); 1583 1584 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea, 1585 OverflowAreaPlusN); 1586 1587 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, 1588 OverflowAreaPtr, 1589 MachinePointerInfo(), 1590 MVT::i32, false, false, 0); 1591 1592 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(), 1593 false, false, false, 0); 1594} 1595 1596SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 1597 SelectionDAG &DAG) const { 1598 return Op.getOperand(0); 1599} 1600 1601SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 1602 SelectionDAG &DAG) const { 1603 SDValue Chain = Op.getOperand(0); 1604 SDValue Trmp = Op.getOperand(1); // trampoline 1605 SDValue FPtr = Op.getOperand(2); // nested function 1606 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 1607 DebugLoc dl = Op.getDebugLoc(); 1608 1609 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1610 bool isPPC64 = (PtrVT == MVT::i64); 1611 Type *IntPtrTy = 1612 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType( 1613 *DAG.getContext()); 1614 1615 TargetLowering::ArgListTy Args; 1616 TargetLowering::ArgListEntry Entry; 1617 1618 Entry.Ty = IntPtrTy; 1619 Entry.Node = Trmp; Args.push_back(Entry); 1620 1621 // TrampSize == (isPPC64 ? 48 : 40); 1622 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, 1623 isPPC64 ? MVT::i64 : MVT::i32); 1624 Args.push_back(Entry); 1625 1626 Entry.Node = FPtr; Args.push_back(Entry); 1627 Entry.Node = Nest; Args.push_back(Entry); 1628 1629 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) 1630 TargetLowering::CallLoweringInfo CLI(Chain, 1631 Type::getVoidTy(*DAG.getContext()), 1632 false, false, false, false, 0, 1633 CallingConv::C, 1634 /*isTailCall=*/false, 1635 /*doesNotRet=*/false, 1636 /*isReturnValueUsed=*/true, 1637 DAG.getExternalSymbol("__trampoline_setup", PtrVT), 1638 Args, DAG, dl); 1639 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1640 1641 return CallResult.second; 1642} 1643 1644SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, 1645 const PPCSubtarget &Subtarget) const { 1646 MachineFunction &MF = DAG.getMachineFunction(); 1647 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1648 1649 DebugLoc dl = Op.getDebugLoc(); 1650 1651 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) { 1652 // vastart just stores the address of the VarArgsFrameIndex slot into the 1653 // memory location argument. 1654 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1655 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1656 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1657 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 1658 MachinePointerInfo(SV), 1659 false, false, 0); 1660 } 1661 1662 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct. 1663 // We suppose the given va_list is already allocated. 1664 // 1665 // typedef struct { 1666 // char gpr; /* index into the array of 8 GPRs 1667 // * stored in the register save area 1668 // * gpr=0 corresponds to r3, 1669 // * gpr=1 to r4, etc. 1670 // */ 1671 // char fpr; /* index into the array of 8 FPRs 1672 // * stored in the register save area 1673 // * fpr=0 corresponds to f1, 1674 // * fpr=1 to f2, etc. 1675 // */ 1676 // char *overflow_arg_area; 1677 // /* location on stack that holds 1678 // * the next overflow argument 1679 // */ 1680 // char *reg_save_area; 1681 // /* where r3:r10 and f1:f8 (if saved) 1682 // * are stored 1683 // */ 1684 // } va_list[1]; 1685 1686 1687 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32); 1688 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32); 1689 1690 1691 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1692 1693 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(), 1694 PtrVT); 1695 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1696 PtrVT); 1697 1698 uint64_t FrameOffset = PtrVT.getSizeInBits()/8; 1699 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1700 1701 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; 1702 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1703 1704 uint64_t FPROffset = 1; 1705 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1706 1707 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1708 1709 // Store first byte : number of int regs 1710 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, 1711 Op.getOperand(1), 1712 MachinePointerInfo(SV), 1713 MVT::i8, false, false, 0); 1714 uint64_t nextOffset = FPROffset; 1715 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), 1716 ConstFPROffset); 1717 1718 // Store second byte : number of float regs 1719 SDValue secondStore = 1720 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, 1721 MachinePointerInfo(SV, nextOffset), MVT::i8, 1722 false, false, 0); 1723 nextOffset += StackOffset; 1724 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); 1725 1726 // Store second word : arguments given on stack 1727 SDValue thirdStore = 1728 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, 1729 MachinePointerInfo(SV, nextOffset), 1730 false, false, 0); 1731 nextOffset += FrameOffset; 1732 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset); 1733 1734 // Store third word : arguments given in registers 1735 return DAG.getStore(thirdStore, dl, FR, nextPtr, 1736 MachinePointerInfo(SV, nextOffset), 1737 false, false, 0); 1738 1739} 1740 1741#include "PPCGenCallingConv.inc" 1742 1743static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 1744 CCValAssign::LocInfo &LocInfo, 1745 ISD::ArgFlagsTy &ArgFlags, 1746 CCState &State) { 1747 return true; 1748} 1749 1750static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 1751 MVT &LocVT, 1752 CCValAssign::LocInfo &LocInfo, 1753 ISD::ArgFlagsTy &ArgFlags, 1754 CCState &State) { 1755 static const uint16_t ArgRegs[] = { 1756 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1757 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1758 }; 1759 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1760 1761 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1762 1763 // Skip one register if the first unallocated register has an even register 1764 // number and there are still argument registers available which have not been 1765 // allocated yet. RegNum is actually an index into ArgRegs, which means we 1766 // need to skip a register if RegNum is odd. 1767 if (RegNum != NumArgRegs && RegNum % 2 == 1) { 1768 State.AllocateReg(ArgRegs[RegNum]); 1769 } 1770 1771 // Always return false here, as this function only makes sure that the first 1772 // unallocated register has an odd register number and does not actually 1773 // allocate a register for the current argument. 1774 return false; 1775} 1776 1777static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 1778 MVT &LocVT, 1779 CCValAssign::LocInfo &LocInfo, 1780 ISD::ArgFlagsTy &ArgFlags, 1781 CCState &State) { 1782 static const uint16_t ArgRegs[] = { 1783 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1784 PPC::F8 1785 }; 1786 1787 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1788 1789 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1790 1791 // If there is only one Floating-point register left we need to put both f64 1792 // values of a split ppc_fp128 value on the stack. 1793 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { 1794 State.AllocateReg(ArgRegs[RegNum]); 1795 } 1796 1797 // Always return false here, as this function only makes sure that the two f64 1798 // values a ppc_fp128 value is split into are both passed in registers or both 1799 // passed on the stack and does not actually allocate a register for the 1800 // current argument. 1801 return false; 1802} 1803 1804/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1805/// on Darwin. 1806static const uint16_t *GetFPR() { 1807 static const uint16_t FPR[] = { 1808 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1809 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1810 }; 1811 1812 return FPR; 1813} 1814 1815/// CalculateStackSlotSize - Calculates the size reserved for this argument on 1816/// the stack. 1817static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, 1818 unsigned PtrByteSize) { 1819 unsigned ArgSize = ArgVT.getSizeInBits()/8; 1820 if (Flags.isByVal()) 1821 ArgSize = Flags.getByValSize(); 1822 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1823 1824 return ArgSize; 1825} 1826 1827SDValue 1828PPCTargetLowering::LowerFormalArguments(SDValue Chain, 1829 CallingConv::ID CallConv, bool isVarArg, 1830 const SmallVectorImpl<ISD::InputArg> 1831 &Ins, 1832 DebugLoc dl, SelectionDAG &DAG, 1833 SmallVectorImpl<SDValue> &InVals) 1834 const { 1835 if (PPCSubTarget.isSVR4ABI()) { 1836 if (PPCSubTarget.isPPC64()) 1837 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins, 1838 dl, DAG, InVals); 1839 else 1840 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins, 1841 dl, DAG, InVals); 1842 } else { 1843 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, 1844 dl, DAG, InVals); 1845 } 1846} 1847 1848SDValue 1849PPCTargetLowering::LowerFormalArguments_32SVR4( 1850 SDValue Chain, 1851 CallingConv::ID CallConv, bool isVarArg, 1852 const SmallVectorImpl<ISD::InputArg> 1853 &Ins, 1854 DebugLoc dl, SelectionDAG &DAG, 1855 SmallVectorImpl<SDValue> &InVals) const { 1856 1857 // 32-bit SVR4 ABI Stack Frame Layout: 1858 // +-----------------------------------+ 1859 // +--> | Back chain | 1860 // | +-----------------------------------+ 1861 // | | Floating-point register save area | 1862 // | +-----------------------------------+ 1863 // | | General register save area | 1864 // | +-----------------------------------+ 1865 // | | CR save word | 1866 // | +-----------------------------------+ 1867 // | | VRSAVE save word | 1868 // | +-----------------------------------+ 1869 // | | Alignment padding | 1870 // | +-----------------------------------+ 1871 // | | Vector register save area | 1872 // | +-----------------------------------+ 1873 // | | Local variable space | 1874 // | +-----------------------------------+ 1875 // | | Parameter list area | 1876 // | +-----------------------------------+ 1877 // | | LR save word | 1878 // | +-----------------------------------+ 1879 // SP--> +--- | Back chain | 1880 // +-----------------------------------+ 1881 // 1882 // Specifications: 1883 // System V Application Binary Interface PowerPC Processor Supplement 1884 // AltiVec Technology Programming Interface Manual 1885 1886 MachineFunction &MF = DAG.getMachineFunction(); 1887 MachineFrameInfo *MFI = MF.getFrameInfo(); 1888 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1889 1890 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1891 // Potential tail calls could cause overwriting of argument stack slots. 1892 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt && 1893 (CallConv == CallingConv::Fast)); 1894 unsigned PtrByteSize = 4; 1895 1896 // Assign locations to all of the incoming arguments. 1897 SmallVector<CCValAssign, 16> ArgLocs; 1898 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1899 getTargetMachine(), ArgLocs, *DAG.getContext()); 1900 1901 // Reserve space for the linkage area on the stack. 1902 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); 1903 1904 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4); 1905 1906 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1907 CCValAssign &VA = ArgLocs[i]; 1908 1909 // Arguments stored in registers. 1910 if (VA.isRegLoc()) { 1911 const TargetRegisterClass *RC; 1912 EVT ValVT = VA.getValVT(); 1913 1914 switch (ValVT.getSimpleVT().SimpleTy) { 1915 default: 1916 llvm_unreachable("ValVT not supported by formal arguments Lowering"); 1917 case MVT::i32: 1918 RC = &PPC::GPRCRegClass; 1919 break; 1920 case MVT::f32: 1921 RC = &PPC::F4RCRegClass; 1922 break; 1923 case MVT::f64: 1924 RC = &PPC::F8RCRegClass; 1925 break; 1926 case MVT::v16i8: 1927 case MVT::v8i16: 1928 case MVT::v4i32: 1929 case MVT::v4f32: 1930 RC = &PPC::VRRCRegClass; 1931 break; 1932 } 1933 1934 // Transform the arguments stored in physical registers into virtual ones. 1935 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1936 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT); 1937 1938 InVals.push_back(ArgValue); 1939 } else { 1940 // Argument stored in memory. 1941 assert(VA.isMemLoc()); 1942 1943 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; 1944 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), 1945 isImmutable); 1946 1947 // Create load nodes to retrieve arguments from the stack. 1948 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1949 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 1950 MachinePointerInfo(), 1951 false, false, false, 0)); 1952 } 1953 } 1954 1955 // Assign locations to all of the incoming aggregate by value arguments. 1956 // Aggregates passed by value are stored in the local variable space of the 1957 // caller's stack frame, right above the parameter list area. 1958 SmallVector<CCValAssign, 16> ByValArgLocs; 1959 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1960 getTargetMachine(), ByValArgLocs, *DAG.getContext()); 1961 1962 // Reserve stack space for the allocations in CCInfo. 1963 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 1964 1965 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal); 1966 1967 // Area that is at least reserved in the caller of this function. 1968 unsigned MinReservedArea = CCByValInfo.getNextStackOffset(); 1969 1970 // Set the size that is at least reserved in caller of this function. Tail 1971 // call optimized function's reserved stack space needs to be aligned so that 1972 // taking the difference between two stack areas will result in an aligned 1973 // stack. 1974 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1975 1976 MinReservedArea = 1977 std::max(MinReservedArea, 1978 PPCFrameLowering::getMinCallFrameSize(false, false)); 1979 1980 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> 1981 getStackAlignment(); 1982 unsigned AlignMask = TargetAlign-1; 1983 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 1984 1985 FI->setMinReservedArea(MinReservedArea); 1986 1987 SmallVector<SDValue, 8> MemOps; 1988 1989 // If the function takes variable number of arguments, make a frame index for 1990 // the start of the first vararg value... for expansion of llvm.va_start. 1991 if (isVarArg) { 1992 static const uint16_t GPArgRegs[] = { 1993 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1994 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1995 }; 1996 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs); 1997 1998 static const uint16_t FPArgRegs[] = { 1999 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 2000 PPC::F8 2001 }; 2002 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs); 2003 2004 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs, 2005 NumGPArgRegs)); 2006 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs, 2007 NumFPArgRegs)); 2008 2009 // Make room for NumGPArgRegs and NumFPArgRegs. 2010 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 + 2011 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8; 2012 2013 FuncInfo->setVarArgsStackOffset( 2014 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2015 CCInfo.getNextStackOffset(), true)); 2016 2017 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false)); 2018 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2019 2020 // The fixed integer arguments of a variadic function are stored to the 2021 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing 2022 // the result of va_next. 2023 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) { 2024 // Get an existing live-in vreg, or add a new one. 2025 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); 2026 if (!VReg) 2027 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); 2028 2029 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2030 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2031 MachinePointerInfo(), false, false, 0); 2032 MemOps.push_back(Store); 2033 // Increment the address by four for the next argument to store 2034 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2035 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2036 } 2037 2038 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6 2039 // is set. 2040 // The double arguments are stored to the VarArgsFrameIndex 2041 // on the stack. 2042 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) { 2043 // Get an existing live-in vreg, or add a new one. 2044 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); 2045 if (!VReg) 2046 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); 2047 2048 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); 2049 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2050 MachinePointerInfo(), false, false, 0); 2051 MemOps.push_back(Store); 2052 // Increment the address by eight for the next argument to store 2053 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8, 2054 PtrVT); 2055 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2056 } 2057 } 2058 2059 if (!MemOps.empty()) 2060 Chain = DAG.getNode(ISD::TokenFactor, dl, 2061 MVT::Other, &MemOps[0], MemOps.size()); 2062 2063 return Chain; 2064} 2065 2066// PPC64 passes i8, i16, and i32 values in i64 registers. Promote 2067// value to MVT::i64 and then truncate to the correct register size. 2068SDValue 2069PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, 2070 SelectionDAG &DAG, SDValue ArgVal, 2071 DebugLoc dl) const { 2072 if (Flags.isSExt()) 2073 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, 2074 DAG.getValueType(ObjectVT)); 2075 else if (Flags.isZExt()) 2076 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, 2077 DAG.getValueType(ObjectVT)); 2078 2079 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); 2080} 2081 2082// Set the size that is at least reserved in caller of this function. Tail 2083// call optimized functions' reserved stack space needs to be aligned so that 2084// taking the difference between two stack areas will result in an aligned 2085// stack. 2086void 2087PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG, 2088 unsigned nAltivecParamsAtEnd, 2089 unsigned MinReservedArea, 2090 bool isPPC64) const { 2091 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2092 // Add the Altivec parameters at the end, if needed. 2093 if (nAltivecParamsAtEnd) { 2094 MinReservedArea = ((MinReservedArea+15)/16)*16; 2095 MinReservedArea += 16*nAltivecParamsAtEnd; 2096 } 2097 MinReservedArea = 2098 std::max(MinReservedArea, 2099 PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); 2100 unsigned TargetAlign 2101 = DAG.getMachineFunction().getTarget().getFrameLowering()-> 2102 getStackAlignment(); 2103 unsigned AlignMask = TargetAlign-1; 2104 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 2105 FI->setMinReservedArea(MinReservedArea); 2106} 2107 2108SDValue 2109PPCTargetLowering::LowerFormalArguments_64SVR4( 2110 SDValue Chain, 2111 CallingConv::ID CallConv, bool isVarArg, 2112 const SmallVectorImpl<ISD::InputArg> 2113 &Ins, 2114 DebugLoc dl, SelectionDAG &DAG, 2115 SmallVectorImpl<SDValue> &InVals) const { 2116 // TODO: add description of PPC stack frame format, or at least some docs. 2117 // 2118 MachineFunction &MF = DAG.getMachineFunction(); 2119 MachineFrameInfo *MFI = MF.getFrameInfo(); 2120 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 2121 2122 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2123 // Potential tail calls could cause overwriting of argument stack slots. 2124 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt && 2125 (CallConv == CallingConv::Fast)); 2126 unsigned PtrByteSize = 8; 2127 2128 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true); 2129 // Area that is at least reserved in caller of this function. 2130 unsigned MinReservedArea = ArgOffset; 2131 2132 static const uint16_t GPR[] = { 2133 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 2134 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 2135 }; 2136 2137 static const uint16_t *FPR = GetFPR(); 2138 2139 static const uint16_t VR[] = { 2140 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 2141 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 2142 }; 2143 2144 const unsigned Num_GPR_Regs = array_lengthof(GPR); 2145 const unsigned Num_FPR_Regs = 13; 2146 const unsigned Num_VR_Regs = array_lengthof(VR); 2147 2148 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 2149 2150 // Add DAG nodes to load the arguments or copy them out of registers. On 2151 // entry to a function on PPC, the arguments start after the linkage area, 2152 // although the first ones are often in registers. 2153 2154 SmallVector<SDValue, 8> MemOps; 2155 unsigned nAltivecParamsAtEnd = 0; 2156 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin(); 2157 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo, ++FuncArg) { 2158 SDValue ArgVal; 2159 bool needsLoad = false; 2160 EVT ObjectVT = Ins[ArgNo].VT; 2161 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 2162 unsigned ArgSize = ObjSize; 2163 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 2164 2165 unsigned CurArgOffset = ArgOffset; 2166 2167 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 2168 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 2169 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 2170 if (isVarArg) { 2171 MinReservedArea = ((MinReservedArea+15)/16)*16; 2172 MinReservedArea += CalculateStackSlotSize(ObjectVT, 2173 Flags, 2174 PtrByteSize); 2175 } else 2176 nAltivecParamsAtEnd++; 2177 } else 2178 // Calculate min reserved area. 2179 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 2180 Flags, 2181 PtrByteSize); 2182 2183 // FIXME the codegen can be much improved in some cases. 2184 // We do not have to keep everything in memory. 2185 if (Flags.isByVal()) { 2186 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 2187 ObjSize = Flags.getByValSize(); 2188 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 2189 // Empty aggregate parameters do not take up registers. Examples: 2190 // struct { } a; 2191 // union { } b; 2192 // int c[0]; 2193 // etc. However, we have to provide a place-holder in InVals, so 2194 // pretend we have an 8-byte item at the current address for that 2195 // purpose. 2196 if (!ObjSize) { 2197 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2198 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2199 InVals.push_back(FIN); 2200 continue; 2201 } 2202 // All aggregates smaller than 8 bytes must be passed right-justified. 2203 if (ObjSize < PtrByteSize) 2204 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize); 2205 // The value of the object is its address. 2206 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true); 2207 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2208 InVals.push_back(FIN); 2209 2210 if (ObjSize < 8) { 2211 if (GPR_idx != Num_GPR_Regs) { 2212 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2213 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2214 SDValue Store; 2215 2216 if (ObjSize==1 || ObjSize==2 || ObjSize==4) { 2217 EVT ObjType = (ObjSize == 1 ? MVT::i8 : 2218 (ObjSize == 2 ? MVT::i16 : MVT::i32)); 2219 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 2220 MachinePointerInfo(FuncArg, CurArgOffset), 2221 ObjType, false, false, 0); 2222 } else { 2223 // For sizes that don't fit a truncating store (3, 5, 6, 7), 2224 // store the whole register as-is to the parameter save area 2225 // slot. The address of the parameter was already calculated 2226 // above (InVals.push_back(FIN)) to be the right-justified 2227 // offset within the slot. For this store, we need a new 2228 // frame index that points at the beginning of the slot. 2229 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2230 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2231 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2232 MachinePointerInfo(FuncArg, ArgOffset), 2233 false, false, 0); 2234 } 2235 2236 MemOps.push_back(Store); 2237 ++GPR_idx; 2238 } 2239 // Whether we copied from a register or not, advance the offset 2240 // into the parameter save area by a full doubleword. 2241 ArgOffset += PtrByteSize; 2242 continue; 2243 } 2244 2245 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 2246 // Store whatever pieces of the object are in registers 2247 // to memory. ArgOffset will be the address of the beginning 2248 // of the object. 2249 if (GPR_idx != Num_GPR_Regs) { 2250 unsigned VReg; 2251 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2252 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2253 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2254 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2255 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2256 MachinePointerInfo(FuncArg, ArgOffset), 2257 false, false, 0); 2258 MemOps.push_back(Store); 2259 ++GPR_idx; 2260 ArgOffset += PtrByteSize; 2261 } else { 2262 ArgOffset += ArgSize - j; 2263 break; 2264 } 2265 } 2266 continue; 2267 } 2268 2269 switch (ObjectVT.getSimpleVT().SimpleTy) { 2270 default: llvm_unreachable("Unhandled argument type!"); 2271 case MVT::i32: 2272 case MVT::i64: 2273 if (GPR_idx != Num_GPR_Regs) { 2274 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2275 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2276 2277 if (ObjectVT == MVT::i32) 2278 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 2279 // value to MVT::i64 and then truncate to the correct register size. 2280 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl); 2281 2282 ++GPR_idx; 2283 } else { 2284 needsLoad = true; 2285 ArgSize = PtrByteSize; 2286 } 2287 ArgOffset += 8; 2288 break; 2289 2290 case MVT::f32: 2291 case MVT::f64: 2292 // Every 8 bytes of argument space consumes one of the GPRs available for 2293 // argument passing. 2294 if (GPR_idx != Num_GPR_Regs) { 2295 ++GPR_idx; 2296 } 2297 if (FPR_idx != Num_FPR_Regs) { 2298 unsigned VReg; 2299 2300 if (ObjectVT == MVT::f32) 2301 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 2302 else 2303 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 2304 2305 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2306 ++FPR_idx; 2307 } else { 2308 needsLoad = true; 2309 ArgSize = PtrByteSize; 2310 } 2311 2312 ArgOffset += 8; 2313 break; 2314 case MVT::v4f32: 2315 case MVT::v4i32: 2316 case MVT::v8i16: 2317 case MVT::v16i8: 2318 // Note that vector arguments in registers don't reserve stack space, 2319 // except in varargs functions. 2320 if (VR_idx != Num_VR_Regs) { 2321 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 2322 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2323 if (isVarArg) { 2324 while ((ArgOffset % 16) != 0) { 2325 ArgOffset += PtrByteSize; 2326 if (GPR_idx != Num_GPR_Regs) 2327 GPR_idx++; 2328 } 2329 ArgOffset += 16; 2330 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 2331 } 2332 ++VR_idx; 2333 } else { 2334 // Vectors are aligned. 2335 ArgOffset = ((ArgOffset+15)/16)*16; 2336 CurArgOffset = ArgOffset; 2337 ArgOffset += 16; 2338 needsLoad = true; 2339 } 2340 break; 2341 } 2342 2343 // We need to load the argument to a virtual register if we determined 2344 // above that we ran out of physical registers of the appropriate type. 2345 if (needsLoad) { 2346 int FI = MFI->CreateFixedObject(ObjSize, 2347 CurArgOffset + (ArgSize - ObjSize), 2348 isImmutable); 2349 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2350 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), 2351 false, false, false, 0); 2352 } 2353 2354 InVals.push_back(ArgVal); 2355 } 2356 2357 // Set the size that is at least reserved in caller of this function. Tail 2358 // call optimized functions' reserved stack space needs to be aligned so that 2359 // taking the difference between two stack areas will result in an aligned 2360 // stack. 2361 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true); 2362 2363 // If the function takes variable number of arguments, make a frame index for 2364 // the start of the first vararg value... for expansion of llvm.va_start. 2365 if (isVarArg) { 2366 int Depth = ArgOffset; 2367 2368 FuncInfo->setVarArgsFrameIndex( 2369 MFI->CreateFixedObject(PtrByteSize, Depth, true)); 2370 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2371 2372 // If this function is vararg, store any remaining integer argument regs 2373 // to their spots on the stack so that they may be loaded by deferencing the 2374 // result of va_next. 2375 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2376 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2377 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2378 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2379 MachinePointerInfo(), false, false, 0); 2380 MemOps.push_back(Store); 2381 // Increment the address by four for the next argument to store 2382 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT); 2383 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2384 } 2385 } 2386 2387 if (!MemOps.empty()) 2388 Chain = DAG.getNode(ISD::TokenFactor, dl, 2389 MVT::Other, &MemOps[0], MemOps.size()); 2390 2391 return Chain; 2392} 2393 2394SDValue 2395PPCTargetLowering::LowerFormalArguments_Darwin( 2396 SDValue Chain, 2397 CallingConv::ID CallConv, bool isVarArg, 2398 const SmallVectorImpl<ISD::InputArg> 2399 &Ins, 2400 DebugLoc dl, SelectionDAG &DAG, 2401 SmallVectorImpl<SDValue> &InVals) const { 2402 // TODO: add description of PPC stack frame format, or at least some docs. 2403 // 2404 MachineFunction &MF = DAG.getMachineFunction(); 2405 MachineFrameInfo *MFI = MF.getFrameInfo(); 2406 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 2407 2408 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2409 bool isPPC64 = PtrVT == MVT::i64; 2410 // Potential tail calls could cause overwriting of argument stack slots. 2411 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt && 2412 (CallConv == CallingConv::Fast)); 2413 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2414 2415 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); 2416 // Area that is at least reserved in caller of this function. 2417 unsigned MinReservedArea = ArgOffset; 2418 2419 static const uint16_t GPR_32[] = { // 32-bit registers. 2420 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 2421 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 2422 }; 2423 static const uint16_t GPR_64[] = { // 64-bit registers. 2424 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 2425 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 2426 }; 2427 2428 static const uint16_t *FPR = GetFPR(); 2429 2430 static const uint16_t VR[] = { 2431 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 2432 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 2433 }; 2434 2435 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 2436 const unsigned Num_FPR_Regs = 13; 2437 const unsigned Num_VR_Regs = array_lengthof( VR); 2438 2439 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 2440 2441 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32; 2442 2443 // In 32-bit non-varargs functions, the stack space for vectors is after the 2444 // stack space for non-vectors. We do not use this space unless we have 2445 // too many vectors to fit in registers, something that only occurs in 2446 // constructed examples:), but we have to walk the arglist to figure 2447 // that out...for the pathological case, compute VecArgOffset as the 2448 // start of the vector parameter area. Computing VecArgOffset is the 2449 // entire point of the following loop. 2450 unsigned VecArgOffset = ArgOffset; 2451 if (!isVarArg && !isPPC64) { 2452 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; 2453 ++ArgNo) { 2454 EVT ObjectVT = Ins[ArgNo].VT; 2455 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 2456 2457 if (Flags.isByVal()) { 2458 // ObjSize is the true size, ArgSize rounded up to multiple of regs. 2459 unsigned ObjSize = Flags.getByValSize(); 2460 unsigned ArgSize = 2461 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 2462 VecArgOffset += ArgSize; 2463 continue; 2464 } 2465 2466 switch(ObjectVT.getSimpleVT().SimpleTy) { 2467 default: llvm_unreachable("Unhandled argument type!"); 2468 case MVT::i32: 2469 case MVT::f32: 2470 VecArgOffset += 4; 2471 break; 2472 case MVT::i64: // PPC64 2473 case MVT::f64: 2474 // FIXME: We are guaranteed to be !isPPC64 at this point. 2475 // Does MVT::i64 apply? 2476 VecArgOffset += 8; 2477 break; 2478 case MVT::v4f32: 2479 case MVT::v4i32: 2480 case MVT::v8i16: 2481 case MVT::v16i8: 2482 // Nothing to do, we're only looking at Nonvector args here. 2483 break; 2484 } 2485 } 2486 } 2487 // We've found where the vector parameter area in memory is. Skip the 2488 // first 12 parameters; these don't use that memory. 2489 VecArgOffset = ((VecArgOffset+15)/16)*16; 2490 VecArgOffset += 12*16; 2491 2492 // Add DAG nodes to load the arguments or copy them out of registers. On 2493 // entry to a function on PPC, the arguments start after the linkage area, 2494 // although the first ones are often in registers. 2495 2496 SmallVector<SDValue, 8> MemOps; 2497 unsigned nAltivecParamsAtEnd = 0; 2498 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin(); 2499 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo, ++FuncArg) { 2500 SDValue ArgVal; 2501 bool needsLoad = false; 2502 EVT ObjectVT = Ins[ArgNo].VT; 2503 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 2504 unsigned ArgSize = ObjSize; 2505 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 2506 2507 unsigned CurArgOffset = ArgOffset; 2508 2509 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 2510 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 2511 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 2512 if (isVarArg || isPPC64) { 2513 MinReservedArea = ((MinReservedArea+15)/16)*16; 2514 MinReservedArea += CalculateStackSlotSize(ObjectVT, 2515 Flags, 2516 PtrByteSize); 2517 } else nAltivecParamsAtEnd++; 2518 } else 2519 // Calculate min reserved area. 2520 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 2521 Flags, 2522 PtrByteSize); 2523 2524 // FIXME the codegen can be much improved in some cases. 2525 // We do not have to keep everything in memory. 2526 if (Flags.isByVal()) { 2527 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 2528 ObjSize = Flags.getByValSize(); 2529 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 2530 // Objects of size 1 and 2 are right justified, everything else is 2531 // left justified. This means the memory address is adjusted forwards. 2532 if (ObjSize==1 || ObjSize==2) { 2533 CurArgOffset = CurArgOffset + (4 - ObjSize); 2534 } 2535 // The value of the object is its address. 2536 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true); 2537 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2538 InVals.push_back(FIN); 2539 if (ObjSize==1 || ObjSize==2) { 2540 if (GPR_idx != Num_GPR_Regs) { 2541 unsigned VReg; 2542 if (isPPC64) 2543 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2544 else 2545 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2546 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2547 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16; 2548 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 2549 MachinePointerInfo(FuncArg, 2550 CurArgOffset), 2551 ObjType, false, false, 0); 2552 MemOps.push_back(Store); 2553 ++GPR_idx; 2554 } 2555 2556 ArgOffset += PtrByteSize; 2557 2558 continue; 2559 } 2560 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 2561 // Store whatever pieces of the object are in registers 2562 // to memory. ArgOffset will be the address of the beginning 2563 // of the object. 2564 if (GPR_idx != Num_GPR_Regs) { 2565 unsigned VReg; 2566 if (isPPC64) 2567 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2568 else 2569 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2570 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2571 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2572 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2573 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2574 MachinePointerInfo(FuncArg, ArgOffset), 2575 false, false, 0); 2576 MemOps.push_back(Store); 2577 ++GPR_idx; 2578 ArgOffset += PtrByteSize; 2579 } else { 2580 ArgOffset += ArgSize - (ArgOffset-CurArgOffset); 2581 break; 2582 } 2583 } 2584 continue; 2585 } 2586 2587 switch (ObjectVT.getSimpleVT().SimpleTy) { 2588 default: llvm_unreachable("Unhandled argument type!"); 2589 case MVT::i32: 2590 if (!isPPC64) { 2591 if (GPR_idx != Num_GPR_Regs) { 2592 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2593 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2594 ++GPR_idx; 2595 } else { 2596 needsLoad = true; 2597 ArgSize = PtrByteSize; 2598 } 2599 // All int arguments reserve stack space in the Darwin ABI. 2600 ArgOffset += PtrByteSize; 2601 break; 2602 } 2603 // FALLTHROUGH 2604 case MVT::i64: // PPC64 2605 if (GPR_idx != Num_GPR_Regs) { 2606 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2607 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2608 2609 if (ObjectVT == MVT::i32) 2610 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 2611 // value to MVT::i64 and then truncate to the correct register size. 2612 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl); 2613 2614 ++GPR_idx; 2615 } else { 2616 needsLoad = true; 2617 ArgSize = PtrByteSize; 2618 } 2619 // All int arguments reserve stack space in the Darwin ABI. 2620 ArgOffset += 8; 2621 break; 2622 2623 case MVT::f32: 2624 case MVT::f64: 2625 // Every 4 bytes of argument space consumes one of the GPRs available for 2626 // argument passing. 2627 if (GPR_idx != Num_GPR_Regs) { 2628 ++GPR_idx; 2629 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 2630 ++GPR_idx; 2631 } 2632 if (FPR_idx != Num_FPR_Regs) { 2633 unsigned VReg; 2634 2635 if (ObjectVT == MVT::f32) 2636 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 2637 else 2638 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 2639 2640 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2641 ++FPR_idx; 2642 } else { 2643 needsLoad = true; 2644 } 2645 2646 // All FP arguments reserve stack space in the Darwin ABI. 2647 ArgOffset += isPPC64 ? 8 : ObjSize; 2648 break; 2649 case MVT::v4f32: 2650 case MVT::v4i32: 2651 case MVT::v8i16: 2652 case MVT::v16i8: 2653 // Note that vector arguments in registers don't reserve stack space, 2654 // except in varargs functions. 2655 if (VR_idx != Num_VR_Regs) { 2656 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 2657 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2658 if (isVarArg) { 2659 while ((ArgOffset % 16) != 0) { 2660 ArgOffset += PtrByteSize; 2661 if (GPR_idx != Num_GPR_Regs) 2662 GPR_idx++; 2663 } 2664 ArgOffset += 16; 2665 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 2666 } 2667 ++VR_idx; 2668 } else { 2669 if (!isVarArg && !isPPC64) { 2670 // Vectors go after all the nonvectors. 2671 CurArgOffset = VecArgOffset; 2672 VecArgOffset += 16; 2673 } else { 2674 // Vectors are aligned. 2675 ArgOffset = ((ArgOffset+15)/16)*16; 2676 CurArgOffset = ArgOffset; 2677 ArgOffset += 16; 2678 } 2679 needsLoad = true; 2680 } 2681 break; 2682 } 2683 2684 // We need to load the argument to a virtual register if we determined above 2685 // that we ran out of physical registers of the appropriate type. 2686 if (needsLoad) { 2687 int FI = MFI->CreateFixedObject(ObjSize, 2688 CurArgOffset + (ArgSize - ObjSize), 2689 isImmutable); 2690 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2691 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), 2692 false, false, false, 0); 2693 } 2694 2695 InVals.push_back(ArgVal); 2696 } 2697 2698 // Set the size that is at least reserved in caller of this function. Tail 2699 // call optimized functions' reserved stack space needs to be aligned so that 2700 // taking the difference between two stack areas will result in an aligned 2701 // stack. 2702 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64); 2703 2704 // If the function takes variable number of arguments, make a frame index for 2705 // the start of the first vararg value... for expansion of llvm.va_start. 2706 if (isVarArg) { 2707 int Depth = ArgOffset; 2708 2709 FuncInfo->setVarArgsFrameIndex( 2710 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2711 Depth, true)); 2712 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2713 2714 // If this function is vararg, store any remaining integer argument regs 2715 // to their spots on the stack so that they may be loaded by deferencing the 2716 // result of va_next. 2717 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2718 unsigned VReg; 2719 2720 if (isPPC64) 2721 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2722 else 2723 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2724 2725 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2726 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2727 MachinePointerInfo(), false, false, 0); 2728 MemOps.push_back(Store); 2729 // Increment the address by four for the next argument to store 2730 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2731 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2732 } 2733 } 2734 2735 if (!MemOps.empty()) 2736 Chain = DAG.getNode(ISD::TokenFactor, dl, 2737 MVT::Other, &MemOps[0], MemOps.size()); 2738 2739 return Chain; 2740} 2741 2742/// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus 2743/// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI. 2744static unsigned 2745CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, 2746 bool isPPC64, 2747 bool isVarArg, 2748 unsigned CC, 2749 const SmallVectorImpl<ISD::OutputArg> 2750 &Outs, 2751 const SmallVectorImpl<SDValue> &OutVals, 2752 unsigned &nAltivecParamsAtEnd) { 2753 // Count how many bytes are to be pushed on the stack, including the linkage 2754 // area, and parameter passing area. We start with 24/48 bytes, which is 2755 // prereserved space for [SP][CR][LR][3 x unused]. 2756 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true); 2757 unsigned NumOps = Outs.size(); 2758 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2759 2760 // Add up all the space actually used. 2761 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually 2762 // they all go in registers, but we must reserve stack space for them for 2763 // possible use by the caller. In varargs or 64-bit calls, parameters are 2764 // assigned stack space in order, with padding so Altivec parameters are 2765 // 16-byte aligned. 2766 nAltivecParamsAtEnd = 0; 2767 for (unsigned i = 0; i != NumOps; ++i) { 2768 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2769 EVT ArgVT = Outs[i].VT; 2770 // Varargs Altivec parameters are padded to a 16 byte boundary. 2771 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 2772 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { 2773 if (!isVarArg && !isPPC64) { 2774 // Non-varargs Altivec parameters go after all the non-Altivec 2775 // parameters; handle those later so we know how much padding we need. 2776 nAltivecParamsAtEnd++; 2777 continue; 2778 } 2779 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. 2780 NumBytes = ((NumBytes+15)/16)*16; 2781 } 2782 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); 2783 } 2784 2785 // Allow for Altivec parameters at the end, if needed. 2786 if (nAltivecParamsAtEnd) { 2787 NumBytes = ((NumBytes+15)/16)*16; 2788 NumBytes += 16*nAltivecParamsAtEnd; 2789 } 2790 2791 // The prolog code of the callee may store up to 8 GPR argument registers to 2792 // the stack, allowing va_start to index over them in memory if its varargs. 2793 // Because we cannot tell if this is needed on the caller side, we have to 2794 // conservatively assume that it is needed. As such, make sure we have at 2795 // least enough stack space for the caller to store the 8 GPRs. 2796 NumBytes = std::max(NumBytes, 2797 PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); 2798 2799 // Tail call needs the stack to be aligned. 2800 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){ 2801 unsigned TargetAlign = DAG.getMachineFunction().getTarget(). 2802 getFrameLowering()->getStackAlignment(); 2803 unsigned AlignMask = TargetAlign-1; 2804 NumBytes = (NumBytes + AlignMask) & ~AlignMask; 2805 } 2806 2807 return NumBytes; 2808} 2809 2810/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be 2811/// adjusted to accommodate the arguments for the tailcall. 2812static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, 2813 unsigned ParamSize) { 2814 2815 if (!isTailCall) return 0; 2816 2817 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>(); 2818 unsigned CallerMinReservedArea = FI->getMinReservedArea(); 2819 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize; 2820 // Remember only if the new adjustement is bigger. 2821 if (SPDiff < FI->getTailCallSPDelta()) 2822 FI->setTailCallSPDelta(SPDiff); 2823 2824 return SPDiff; 2825} 2826 2827/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2828/// for tail call optimization. Targets which want to do tail call 2829/// optimization should implement this function. 2830bool 2831PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2832 CallingConv::ID CalleeCC, 2833 bool isVarArg, 2834 const SmallVectorImpl<ISD::InputArg> &Ins, 2835 SelectionDAG& DAG) const { 2836 if (!getTargetMachine().Options.GuaranteedTailCallOpt) 2837 return false; 2838 2839 // Variable argument functions are not supported. 2840 if (isVarArg) 2841 return false; 2842 2843 MachineFunction &MF = DAG.getMachineFunction(); 2844 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv(); 2845 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 2846 // Functions containing by val parameters are not supported. 2847 for (unsigned i = 0; i != Ins.size(); i++) { 2848 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2849 if (Flags.isByVal()) return false; 2850 } 2851 2852 // Non PIC/GOT tail calls are supported. 2853 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 2854 return true; 2855 2856 // At the moment we can only do local tail calls (in same module, hidden 2857 // or protected) if we are generating PIC. 2858 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2859 return G->getGlobal()->hasHiddenVisibility() 2860 || G->getGlobal()->hasProtectedVisibility(); 2861 } 2862 2863 return false; 2864} 2865 2866/// isCallCompatibleAddress - Return the immediate to use if the specified 2867/// 32-bit value is representable in the immediate field of a BxA instruction. 2868static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { 2869 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2870 if (!C) return 0; 2871 2872 int Addr = C->getZExtValue(); 2873 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 2874 SignExtend32<26>(Addr) != Addr) 2875 return 0; // Top 6 bits have to be sext of immediate. 2876 2877 return DAG.getConstant((int)C->getZExtValue() >> 2, 2878 DAG.getTargetLoweringInfo().getPointerTy()).getNode(); 2879} 2880 2881namespace { 2882 2883struct TailCallArgumentInfo { 2884 SDValue Arg; 2885 SDValue FrameIdxOp; 2886 int FrameIdx; 2887 2888 TailCallArgumentInfo() : FrameIdx(0) {} 2889}; 2890 2891} 2892 2893/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. 2894static void 2895StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, 2896 SDValue Chain, 2897 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, 2898 SmallVector<SDValue, 8> &MemOpChains, 2899 DebugLoc dl) { 2900 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { 2901 SDValue Arg = TailCallArgs[i].Arg; 2902 SDValue FIN = TailCallArgs[i].FrameIdxOp; 2903 int FI = TailCallArgs[i].FrameIdx; 2904 // Store relative to framepointer. 2905 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN, 2906 MachinePointerInfo::getFixedStack(FI), 2907 false, false, 0)); 2908 } 2909} 2910 2911/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to 2912/// the appropriate stack slot for the tail call optimized function call. 2913static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, 2914 MachineFunction &MF, 2915 SDValue Chain, 2916 SDValue OldRetAddr, 2917 SDValue OldFP, 2918 int SPDiff, 2919 bool isPPC64, 2920 bool isDarwinABI, 2921 DebugLoc dl) { 2922 if (SPDiff) { 2923 // Calculate the new stack slot for the return address. 2924 int SlotSize = isPPC64 ? 8 : 4; 2925 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64, 2926 isDarwinABI); 2927 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, 2928 NewRetAddrLoc, true); 2929 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2930 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); 2931 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, 2932 MachinePointerInfo::getFixedStack(NewRetAddr), 2933 false, false, 0); 2934 2935 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack 2936 // slot as the FP is never overwritten. 2937 if (isDarwinABI) { 2938 int NewFPLoc = 2939 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 2940 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc, 2941 true); 2942 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); 2943 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, 2944 MachinePointerInfo::getFixedStack(NewFPIdx), 2945 false, false, 0); 2946 } 2947 } 2948 return Chain; 2949} 2950 2951/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate 2952/// the position of the argument. 2953static void 2954CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, 2955 SDValue Arg, int SPDiff, unsigned ArgOffset, 2956 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 2957 int Offset = ArgOffset + SPDiff; 2958 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; 2959 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2960 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2961 SDValue FIN = DAG.getFrameIndex(FI, VT); 2962 TailCallArgumentInfo Info; 2963 Info.Arg = Arg; 2964 Info.FrameIdxOp = FIN; 2965 Info.FrameIdx = FI; 2966 TailCallArguments.push_back(Info); 2967} 2968 2969/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address 2970/// stack slot. Returns the chain as result and the loaded frame pointers in 2971/// LROpOut/FPOpout. Used when tail calling. 2972SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 2973 int SPDiff, 2974 SDValue Chain, 2975 SDValue &LROpOut, 2976 SDValue &FPOpOut, 2977 bool isDarwinABI, 2978 DebugLoc dl) const { 2979 if (SPDiff) { 2980 // Load the LR and FP stack slot for later adjusting. 2981 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; 2982 LROpOut = getReturnAddrFrameIndex(DAG); 2983 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(), 2984 false, false, false, 0); 2985 Chain = SDValue(LROpOut.getNode(), 1); 2986 2987 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack 2988 // slot as the FP is never overwritten. 2989 if (isDarwinABI) { 2990 FPOpOut = getFramePointerFrameIndex(DAG); 2991 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(), 2992 false, false, false, 0); 2993 Chain = SDValue(FPOpOut.getNode(), 1); 2994 } 2995 } 2996 return Chain; 2997} 2998 2999/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 3000/// by "Src" to address "Dst" of size "Size". Alignment information is 3001/// specified by the specific parameter attribute. The copy will be passed as 3002/// a byval function parameter. 3003/// Sometimes what we are copying is the end of a larger object, the part that 3004/// does not fit in registers. 3005static SDValue 3006CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 3007 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 3008 DebugLoc dl) { 3009 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 3010 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 3011 false, false, MachinePointerInfo(0), 3012 MachinePointerInfo(0)); 3013} 3014 3015/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of 3016/// tail calls. 3017static void 3018LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, 3019 SDValue Arg, SDValue PtrOff, int SPDiff, 3020 unsigned ArgOffset, bool isPPC64, bool isTailCall, 3021 bool isVector, SmallVector<SDValue, 8> &MemOpChains, 3022 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments, 3023 DebugLoc dl) { 3024 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3025 if (!isTailCall) { 3026 if (isVector) { 3027 SDValue StackPtr; 3028 if (isPPC64) 3029 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 3030 else 3031 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 3032 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 3033 DAG.getConstant(ArgOffset, PtrVT)); 3034 } 3035 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 3036 MachinePointerInfo(), false, false, 0)); 3037 // Calculate and remember argument location. 3038 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, 3039 TailCallArguments); 3040} 3041 3042static 3043void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, 3044 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, 3045 SDValue LROp, SDValue FPOp, bool isDarwinABI, 3046 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) { 3047 MachineFunction &MF = DAG.getMachineFunction(); 3048 3049 // Emit a sequence of copyto/copyfrom virtual registers for arguments that 3050 // might overwrite each other in case of tail call optimization. 3051 SmallVector<SDValue, 8> MemOpChains2; 3052 // Do not flag preceding copytoreg stuff together with the following stuff. 3053 InFlag = SDValue(); 3054 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, 3055 MemOpChains2, dl); 3056 if (!MemOpChains2.empty()) 3057 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3058 &MemOpChains2[0], MemOpChains2.size()); 3059 3060 // Store the return address to the appropriate stack slot. 3061 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, 3062 isPPC64, isDarwinABI, dl); 3063 3064 // Emit callseq_end just before tailcall node. 3065 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 3066 DAG.getIntPtrConstant(0, true), InFlag); 3067 InFlag = Chain.getValue(1); 3068} 3069 3070static 3071unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, 3072 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall, 3073 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 3074 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys, 3075 const PPCSubtarget &PPCSubTarget) { 3076 3077 bool isPPC64 = PPCSubTarget.isPPC64(); 3078 bool isSVR4ABI = PPCSubTarget.isSVR4ABI(); 3079 3080 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3081 NodeTys.push_back(MVT::Other); // Returns a chain 3082 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use. 3083 3084 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin; 3085 3086 bool needIndirectCall = true; 3087 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) { 3088 // If this is an absolute destination address, use the munged value. 3089 Callee = SDValue(Dest, 0); 3090 needIndirectCall = false; 3091 } 3092 3093 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3094 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201 3095 // Use indirect calls for ALL functions calls in JIT mode, since the 3096 // far-call stubs may be outside relocation limits for a BL instruction. 3097 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) { 3098 unsigned OpFlags = 0; 3099 if (DAG.getTarget().getRelocationModel() != Reloc::Static && 3100 (PPCSubTarget.getTargetTriple().isMacOSX() && 3101 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) && 3102 (G->getGlobal()->isDeclaration() || 3103 G->getGlobal()->isWeakForLinker())) { 3104 // PC-relative references to external symbols should go through $stub, 3105 // unless we're building with the leopard linker or later, which 3106 // automatically synthesizes these stubs. 3107 OpFlags = PPCII::MO_DARWIN_STUB; 3108 } 3109 3110 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, 3111 // every direct call is) turn it into a TargetGlobalAddress / 3112 // TargetExternalSymbol node so that legalize doesn't hack it. 3113 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 3114 Callee.getValueType(), 3115 0, OpFlags); 3116 needIndirectCall = false; 3117 } 3118 } 3119 3120 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3121 unsigned char OpFlags = 0; 3122 3123 if (DAG.getTarget().getRelocationModel() != Reloc::Static && 3124 (PPCSubTarget.getTargetTriple().isMacOSX() && 3125 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) { 3126 // PC-relative references to external symbols should go through $stub, 3127 // unless we're building with the leopard linker or later, which 3128 // automatically synthesizes these stubs. 3129 OpFlags = PPCII::MO_DARWIN_STUB; 3130 } 3131 3132 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(), 3133 OpFlags); 3134 needIndirectCall = false; 3135 } 3136 3137 if (needIndirectCall) { 3138 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 3139 // to do the call, we can't use PPCISD::CALL. 3140 SDValue MTCTROps[] = {Chain, Callee, InFlag}; 3141 3142 if (isSVR4ABI && isPPC64) { 3143 // Function pointers in the 64-bit SVR4 ABI do not point to the function 3144 // entry point, but to the function descriptor (the function entry point 3145 // address is part of the function descriptor though). 3146 // The function descriptor is a three doubleword structure with the 3147 // following fields: function entry point, TOC base address and 3148 // environment pointer. 3149 // Thus for a call through a function pointer, the following actions need 3150 // to be performed: 3151 // 1. Save the TOC of the caller in the TOC save area of its stack 3152 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()). 3153 // 2. Load the address of the function entry point from the function 3154 // descriptor. 3155 // 3. Load the TOC of the callee from the function descriptor into r2. 3156 // 4. Load the environment pointer from the function descriptor into 3157 // r11. 3158 // 5. Branch to the function entry point address. 3159 // 6. On return of the callee, the TOC of the caller needs to be 3160 // restored (this is done in FinishCall()). 3161 // 3162 // All those operations are flagged together to ensure that no other 3163 // operations can be scheduled in between. E.g. without flagging the 3164 // operations together, a TOC access in the caller could be scheduled 3165 // between the load of the callee TOC and the branch to the callee, which 3166 // results in the TOC access going through the TOC of the callee instead 3167 // of going through the TOC of the caller, which leads to incorrect code. 3168 3169 // Load the address of the function entry point from the function 3170 // descriptor. 3171 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue); 3172 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps, 3173 InFlag.getNode() ? 3 : 2); 3174 Chain = LoadFuncPtr.getValue(1); 3175 InFlag = LoadFuncPtr.getValue(2); 3176 3177 // Load environment pointer into r11. 3178 // Offset of the environment pointer within the function descriptor. 3179 SDValue PtrOff = DAG.getIntPtrConstant(16); 3180 3181 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff); 3182 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr, 3183 InFlag); 3184 Chain = LoadEnvPtr.getValue(1); 3185 InFlag = LoadEnvPtr.getValue(2); 3186 3187 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr, 3188 InFlag); 3189 Chain = EnvVal.getValue(0); 3190 InFlag = EnvVal.getValue(1); 3191 3192 // Load TOC of the callee into r2. We are using a target-specific load 3193 // with r2 hard coded, because the result of a target-independent load 3194 // would never go directly into r2, since r2 is a reserved register (which 3195 // prevents the register allocator from allocating it), resulting in an 3196 // additional register being allocated and an unnecessary move instruction 3197 // being generated. 3198 VTs = DAG.getVTList(MVT::Other, MVT::Glue); 3199 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, 3200 Callee, InFlag); 3201 Chain = LoadTOCPtr.getValue(0); 3202 InFlag = LoadTOCPtr.getValue(1); 3203 3204 MTCTROps[0] = Chain; 3205 MTCTROps[1] = LoadFuncPtr; 3206 MTCTROps[2] = InFlag; 3207 } 3208 3209 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps, 3210 2 + (InFlag.getNode() != 0)); 3211 InFlag = Chain.getValue(1); 3212 3213 NodeTys.clear(); 3214 NodeTys.push_back(MVT::Other); 3215 NodeTys.push_back(MVT::Glue); 3216 Ops.push_back(Chain); 3217 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin; 3218 Callee.setNode(0); 3219 // Add CTR register as callee so a bctr can be emitted later. 3220 if (isTailCall) 3221 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT)); 3222 } 3223 3224 // If this is a direct call, pass the chain and the callee. 3225 if (Callee.getNode()) { 3226 Ops.push_back(Chain); 3227 Ops.push_back(Callee); 3228 } 3229 // If this is a tail call add stack pointer delta. 3230 if (isTailCall) 3231 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); 3232 3233 // Add argument registers to the end of the list so that they are known live 3234 // into the call. 3235 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 3236 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 3237 RegsToPass[i].second.getValueType())); 3238 3239 return CallOpc; 3240} 3241 3242static 3243bool isLocalCall(const SDValue &Callee) 3244{ 3245 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 3246 return !G->getGlobal()->isDeclaration() && 3247 !G->getGlobal()->isWeakForLinker(); 3248 return false; 3249} 3250 3251SDValue 3252PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 3253 CallingConv::ID CallConv, bool isVarArg, 3254 const SmallVectorImpl<ISD::InputArg> &Ins, 3255 DebugLoc dl, SelectionDAG &DAG, 3256 SmallVectorImpl<SDValue> &InVals) const { 3257 3258 SmallVector<CCValAssign, 16> RVLocs; 3259 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3260 getTargetMachine(), RVLocs, *DAG.getContext()); 3261 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC); 3262 3263 // Copy all of the result registers out of their specified physreg. 3264 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 3265 CCValAssign &VA = RVLocs[i]; 3266 assert(VA.isRegLoc() && "Can only return in registers!"); 3267 3268 SDValue Val = DAG.getCopyFromReg(Chain, dl, 3269 VA.getLocReg(), VA.getLocVT(), InFlag); 3270 Chain = Val.getValue(1); 3271 InFlag = Val.getValue(2); 3272 3273 switch (VA.getLocInfo()) { 3274 default: llvm_unreachable("Unknown loc info!"); 3275 case CCValAssign::Full: break; 3276 case CCValAssign::AExt: 3277 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); 3278 break; 3279 case CCValAssign::ZExt: 3280 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val, 3281 DAG.getValueType(VA.getValVT())); 3282 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); 3283 break; 3284 case CCValAssign::SExt: 3285 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val, 3286 DAG.getValueType(VA.getValVT())); 3287 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); 3288 break; 3289 } 3290 3291 InVals.push_back(Val); 3292 } 3293 3294 return Chain; 3295} 3296 3297SDValue 3298PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl, 3299 bool isTailCall, bool isVarArg, 3300 SelectionDAG &DAG, 3301 SmallVector<std::pair<unsigned, SDValue>, 8> 3302 &RegsToPass, 3303 SDValue InFlag, SDValue Chain, 3304 SDValue &Callee, 3305 int SPDiff, unsigned NumBytes, 3306 const SmallVectorImpl<ISD::InputArg> &Ins, 3307 SmallVectorImpl<SDValue> &InVals) const { 3308 std::vector<EVT> NodeTys; 3309 SmallVector<SDValue, 8> Ops; 3310 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff, 3311 isTailCall, RegsToPass, Ops, NodeTys, 3312 PPCSubTarget); 3313 3314 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls 3315 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) 3316 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32)); 3317 3318 // When performing tail call optimization the callee pops its arguments off 3319 // the stack. Account for this here so these bytes can be pushed back on in 3320 // PPCRegisterInfo::eliminateCallFramePseudoInstr. 3321 int BytesCalleePops = 3322 (CallConv == CallingConv::Fast && 3323 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0; 3324 3325 // Add a register mask operand representing the call-preserved registers. 3326 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 3327 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 3328 assert(Mask && "Missing call preserved mask for calling convention"); 3329 Ops.push_back(DAG.getRegisterMask(Mask)); 3330 3331 if (InFlag.getNode()) 3332 Ops.push_back(InFlag); 3333 3334 // Emit tail call. 3335 if (isTailCall) { 3336 // If this is the first return lowered for this function, add the regs 3337 // to the liveout set for the function. 3338 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 3339 SmallVector<CCValAssign, 16> RVLocs; 3340 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3341 getTargetMachine(), RVLocs, *DAG.getContext()); 3342 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC); 3343 for (unsigned i = 0; i != RVLocs.size(); ++i) 3344 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 3345 } 3346 3347 assert(((Callee.getOpcode() == ISD::Register && 3348 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || 3349 Callee.getOpcode() == ISD::TargetExternalSymbol || 3350 Callee.getOpcode() == ISD::TargetGlobalAddress || 3351 isa<ConstantSDNode>(Callee)) && 3352 "Expecting an global address, external symbol, absolute value or register"); 3353 3354 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size()); 3355 } 3356 3357 // Add a NOP immediately after the branch instruction when using the 64-bit 3358 // SVR4 ABI. At link time, if caller and callee are in a different module and 3359 // thus have a different TOC, the call will be replaced with a call to a stub 3360 // function which saves the current TOC, loads the TOC of the callee and 3361 // branches to the callee. The NOP will be replaced with a load instruction 3362 // which restores the TOC of the caller from the TOC save slot of the current 3363 // stack frame. If caller and callee belong to the same module (and have the 3364 // same TOC), the NOP will remain unchanged. 3365 3366 bool needsTOCRestore = false; 3367 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) { 3368 if (CallOpc == PPCISD::BCTRL_SVR4) { 3369 // This is a call through a function pointer. 3370 // Restore the caller TOC from the save area into R2. 3371 // See PrepareCall() for more information about calls through function 3372 // pointers in the 64-bit SVR4 ABI. 3373 // We are using a target-specific load with r2 hard coded, because the 3374 // result of a target-independent load would never go directly into r2, 3375 // since r2 is a reserved register (which prevents the register allocator 3376 // from allocating it), resulting in an additional register being 3377 // allocated and an unnecessary move instruction being generated. 3378 needsTOCRestore = true; 3379 } else if ((CallOpc == PPCISD::CALL_SVR4) && !isLocalCall(Callee)) { 3380 // Otherwise insert NOP for non-local calls. 3381 CallOpc = PPCISD::CALL_NOP_SVR4; 3382 } 3383 } 3384 3385 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 3386 InFlag = Chain.getValue(1); 3387 3388 if (needsTOCRestore) { 3389 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); 3390 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag); 3391 InFlag = Chain.getValue(1); 3392 } 3393 3394 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 3395 DAG.getIntPtrConstant(BytesCalleePops, true), 3396 InFlag); 3397 if (!Ins.empty()) 3398 InFlag = Chain.getValue(1); 3399 3400 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 3401 Ins, dl, DAG, InVals); 3402} 3403 3404SDValue 3405PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 3406 SmallVectorImpl<SDValue> &InVals) const { 3407 SelectionDAG &DAG = CLI.DAG; 3408 DebugLoc &dl = CLI.DL; 3409 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 3410 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 3411 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 3412 SDValue Chain = CLI.Chain; 3413 SDValue Callee = CLI.Callee; 3414 bool &isTailCall = CLI.IsTailCall; 3415 CallingConv::ID CallConv = CLI.CallConv; 3416 bool isVarArg = CLI.IsVarArg; 3417 3418 if (isTailCall) 3419 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, 3420 Ins, DAG); 3421 3422 if (PPCSubTarget.isSVR4ABI()) { 3423 if (PPCSubTarget.isPPC64()) 3424 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg, 3425 isTailCall, Outs, OutVals, Ins, 3426 dl, DAG, InVals); 3427 else 3428 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg, 3429 isTailCall, Outs, OutVals, Ins, 3430 dl, DAG, InVals); 3431 } 3432 3433 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg, 3434 isTailCall, Outs, OutVals, Ins, 3435 dl, DAG, InVals); 3436} 3437 3438SDValue 3439PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee, 3440 CallingConv::ID CallConv, bool isVarArg, 3441 bool isTailCall, 3442 const SmallVectorImpl<ISD::OutputArg> &Outs, 3443 const SmallVectorImpl<SDValue> &OutVals, 3444 const SmallVectorImpl<ISD::InputArg> &Ins, 3445 DebugLoc dl, SelectionDAG &DAG, 3446 SmallVectorImpl<SDValue> &InVals) const { 3447 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description 3448 // of the 32-bit SVR4 ABI stack frame layout. 3449 3450 assert((CallConv == CallingConv::C || 3451 CallConv == CallingConv::Fast) && "Unknown calling convention!"); 3452 3453 unsigned PtrByteSize = 4; 3454 3455 MachineFunction &MF = DAG.getMachineFunction(); 3456 3457 // Mark this function as potentially containing a function that contains a 3458 // tail call. As a consequence the frame pointer will be used for dynamicalloc 3459 // and restoring the callers stack pointer in this functions epilog. This is 3460 // done because by tail calling the called function might overwrite the value 3461 // in this function's (MF) stack pointer stack slot 0(SP). 3462 if (getTargetMachine().Options.GuaranteedTailCallOpt && 3463 CallConv == CallingConv::Fast) 3464 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 3465 3466 // Count how many bytes are to be pushed on the stack, including the linkage 3467 // area, parameter list area and the part of the local variable space which 3468 // contains copies of aggregates which are passed by value. 3469 3470 // Assign locations to all of the outgoing arguments. 3471 SmallVector<CCValAssign, 16> ArgLocs; 3472 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3473 getTargetMachine(), ArgLocs, *DAG.getContext()); 3474 3475 // Reserve space for the linkage area on the stack. 3476 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); 3477 3478 if (isVarArg) { 3479 // Handle fixed and variable vector arguments differently. 3480 // Fixed vector arguments go into registers as long as registers are 3481 // available. Variable vector arguments always go into memory. 3482 unsigned NumArgs = Outs.size(); 3483 3484 for (unsigned i = 0; i != NumArgs; ++i) { 3485 MVT ArgVT = Outs[i].VT; 3486 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 3487 bool Result; 3488 3489 if (Outs[i].IsFixed) { 3490 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, 3491 CCInfo); 3492 } else { 3493 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, 3494 ArgFlags, CCInfo); 3495 } 3496 3497 if (Result) { 3498#ifndef NDEBUG 3499 errs() << "Call operand #" << i << " has unhandled type " 3500 << EVT(ArgVT).getEVTString() << "\n"; 3501#endif 3502 llvm_unreachable(0); 3503 } 3504 } 3505 } else { 3506 // All arguments are treated the same. 3507 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4); 3508 } 3509 3510 // Assign locations to all of the outgoing aggregate by value arguments. 3511 SmallVector<CCValAssign, 16> ByValArgLocs; 3512 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3513 getTargetMachine(), ByValArgLocs, *DAG.getContext()); 3514 3515 // Reserve stack space for the allocations in CCInfo. 3516 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 3517 3518 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal); 3519 3520 // Size of the linkage area, parameter list area and the part of the local 3521 // space variable where copies of aggregates which are passed by value are 3522 // stored. 3523 unsigned NumBytes = CCByValInfo.getNextStackOffset(); 3524 3525 // Calculate by how many bytes the stack has to be adjusted in case of tail 3526 // call optimization. 3527 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 3528 3529 // Adjust the stack pointer for the new arguments... 3530 // These operations are automatically eliminated by the prolog/epilog pass 3531 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 3532 SDValue CallSeqStart = Chain; 3533 3534 // Load the return address and frame pointer so it can be moved somewhere else 3535 // later. 3536 SDValue LROp, FPOp; 3537 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false, 3538 dl); 3539 3540 // Set up a copy of the stack pointer for use loading and storing any 3541 // arguments that may not fit in the registers available for argument 3542 // passing. 3543 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 3544 3545 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3546 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3547 SmallVector<SDValue, 8> MemOpChains; 3548 3549 bool seenFloatArg = false; 3550 // Walk the register/memloc assignments, inserting copies/loads. 3551 for (unsigned i = 0, j = 0, e = ArgLocs.size(); 3552 i != e; 3553 ++i) { 3554 CCValAssign &VA = ArgLocs[i]; 3555 SDValue Arg = OutVals[i]; 3556 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3557 3558 if (Flags.isByVal()) { 3559 // Argument is an aggregate which is passed by value, thus we need to 3560 // create a copy of it in the local variable space of the current stack 3561 // frame (which is the stack frame of the caller) and pass the address of 3562 // this copy to the callee. 3563 assert((j < ByValArgLocs.size()) && "Index out of bounds!"); 3564 CCValAssign &ByValVA = ByValArgLocs[j++]; 3565 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"); 3566 3567 // Memory reserved in the local variable space of the callers stack frame. 3568 unsigned LocMemOffset = ByValVA.getLocMemOffset(); 3569 3570 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 3571 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 3572 3573 // Create a copy of the argument in the local area of the current 3574 // stack frame. 3575 SDValue MemcpyCall = 3576 CreateCopyOfByValArgument(Arg, PtrOff, 3577 CallSeqStart.getNode()->getOperand(0), 3578 Flags, DAG, dl); 3579 3580 // This must go outside the CALLSEQ_START..END. 3581 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3582 CallSeqStart.getNode()->getOperand(1)); 3583 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3584 NewCallSeqStart.getNode()); 3585 Chain = CallSeqStart = NewCallSeqStart; 3586 3587 // Pass the address of the aggregate copy on the stack either in a 3588 // physical register or in the parameter list area of the current stack 3589 // frame to the callee. 3590 Arg = PtrOff; 3591 } 3592 3593 if (VA.isRegLoc()) { 3594 seenFloatArg |= VA.getLocVT().isFloatingPoint(); 3595 // Put argument in a physical register. 3596 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3597 } else { 3598 // Put argument in the parameter list area of the current stack frame. 3599 assert(VA.isMemLoc()); 3600 unsigned LocMemOffset = VA.getLocMemOffset(); 3601 3602 if (!isTailCall) { 3603 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 3604 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 3605 3606 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 3607 MachinePointerInfo(), 3608 false, false, 0)); 3609 } else { 3610 // Calculate and remember argument location. 3611 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset, 3612 TailCallArguments); 3613 } 3614 } 3615 } 3616 3617 if (!MemOpChains.empty()) 3618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3619 &MemOpChains[0], MemOpChains.size()); 3620 3621 // Build a sequence of copy-to-reg nodes chained together with token chain 3622 // and flag operands which copy the outgoing args into the appropriate regs. 3623 SDValue InFlag; 3624 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3625 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3626 RegsToPass[i].second, InFlag); 3627 InFlag = Chain.getValue(1); 3628 } 3629 3630 // Set CR bit 6 to true if this is a vararg call with floating args passed in 3631 // registers. 3632 if (isVarArg) { 3633 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); 3634 SDValue Ops[] = { Chain, InFlag }; 3635 3636 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET, 3637 dl, VTs, Ops, InFlag.getNode() ? 2 : 1); 3638 3639 InFlag = Chain.getValue(1); 3640 } 3641 3642 if (isTailCall) 3643 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp, 3644 false, TailCallArguments); 3645 3646 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 3647 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 3648 Ins, InVals); 3649} 3650 3651// Copy an argument into memory, being careful to do this outside the 3652// call sequence for the call to which the argument belongs. 3653SDValue 3654PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 3655 SDValue CallSeqStart, 3656 ISD::ArgFlagsTy Flags, 3657 SelectionDAG &DAG, 3658 DebugLoc dl) const { 3659 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, 3660 CallSeqStart.getNode()->getOperand(0), 3661 Flags, DAG, dl); 3662 // The MEMCPY must go outside the CALLSEQ_START..END. 3663 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3664 CallSeqStart.getNode()->getOperand(1)); 3665 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3666 NewCallSeqStart.getNode()); 3667 return NewCallSeqStart; 3668} 3669 3670SDValue 3671PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee, 3672 CallingConv::ID CallConv, bool isVarArg, 3673 bool isTailCall, 3674 const SmallVectorImpl<ISD::OutputArg> &Outs, 3675 const SmallVectorImpl<SDValue> &OutVals, 3676 const SmallVectorImpl<ISD::InputArg> &Ins, 3677 DebugLoc dl, SelectionDAG &DAG, 3678 SmallVectorImpl<SDValue> &InVals) const { 3679 3680 unsigned NumOps = Outs.size(); 3681 3682 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3683 unsigned PtrByteSize = 8; 3684 3685 MachineFunction &MF = DAG.getMachineFunction(); 3686 3687 // Mark this function as potentially containing a function that contains a 3688 // tail call. As a consequence the frame pointer will be used for dynamicalloc 3689 // and restoring the callers stack pointer in this functions epilog. This is 3690 // done because by tail calling the called function might overwrite the value 3691 // in this function's (MF) stack pointer stack slot 0(SP). 3692 if (getTargetMachine().Options.GuaranteedTailCallOpt && 3693 CallConv == CallingConv::Fast) 3694 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 3695 3696 unsigned nAltivecParamsAtEnd = 0; 3697 3698 // Count how many bytes are to be pushed on the stack, including the linkage 3699 // area, and parameter passing area. We start with at least 48 bytes, which 3700 // is reserved space for [SP][CR][LR][3 x unused]. 3701 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result 3702 // of this call. 3703 unsigned NumBytes = 3704 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv, 3705 Outs, OutVals, nAltivecParamsAtEnd); 3706 3707 // Calculate by how many bytes the stack has to be adjusted in case of tail 3708 // call optimization. 3709 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 3710 3711 // To protect arguments on the stack from being clobbered in a tail call, 3712 // force all the loads to happen before doing any other lowering. 3713 if (isTailCall) 3714 Chain = DAG.getStackArgumentTokenFactor(Chain); 3715 3716 // Adjust the stack pointer for the new arguments... 3717 // These operations are automatically eliminated by the prolog/epilog pass 3718 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 3719 SDValue CallSeqStart = Chain; 3720 3721 // Load the return address and frame pointer so it can be move somewhere else 3722 // later. 3723 SDValue LROp, FPOp; 3724 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 3725 dl); 3726 3727 // Set up a copy of the stack pointer for use loading and storing any 3728 // arguments that may not fit in the registers available for argument 3729 // passing. 3730 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 3731 3732 // Figure out which arguments are going to go in registers, and which in 3733 // memory. Also, if this is a vararg function, floating point operations 3734 // must be stored to our stack, and loaded into integer regs as well, if 3735 // any integer regs are available for argument passing. 3736 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true); 3737 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 3738 3739 static const uint16_t GPR[] = { 3740 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 3741 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 3742 }; 3743 static const uint16_t *FPR = GetFPR(); 3744 3745 static const uint16_t VR[] = { 3746 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 3747 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 3748 }; 3749 const unsigned NumGPRs = array_lengthof(GPR); 3750 const unsigned NumFPRs = 13; 3751 const unsigned NumVRs = array_lengthof(VR); 3752 3753 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3754 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3755 3756 SmallVector<SDValue, 8> MemOpChains; 3757 for (unsigned i = 0; i != NumOps; ++i) { 3758 SDValue Arg = OutVals[i]; 3759 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3760 3761 // PtrOff will be used to store the current argument to the stack if a 3762 // register cannot be found for it. 3763 SDValue PtrOff; 3764 3765 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 3766 3767 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3768 3769 // Promote integers to 64-bit values. 3770 if (Arg.getValueType() == MVT::i32) { 3771 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 3772 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3773 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 3774 } 3775 3776 // FIXME memcpy is used way more than necessary. Correctness first. 3777 // Note: "by value" is code for passing a structure by value, not 3778 // basic types. 3779 if (Flags.isByVal()) { 3780 // Note: Size includes alignment padding, so 3781 // struct x { short a; char b; } 3782 // will have Size = 4. With #pragma pack(1), it will have Size = 3. 3783 // These are the proper values we need for right-justifying the 3784 // aggregate in a parameter register. 3785 unsigned Size = Flags.getByValSize(); 3786 3787 // An empty aggregate parameter takes up no storage and no 3788 // registers. 3789 if (Size == 0) 3790 continue; 3791 3792 // All aggregates smaller than 8 bytes must be passed right-justified. 3793 if (Size==1 || Size==2 || Size==4) { 3794 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32); 3795 if (GPR_idx != NumGPRs) { 3796 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, 3797 MachinePointerInfo(), VT, 3798 false, false, 0); 3799 MemOpChains.push_back(Load.getValue(1)); 3800 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3801 3802 ArgOffset += PtrByteSize; 3803 continue; 3804 } 3805 } 3806 3807 if (GPR_idx == NumGPRs && Size < 8) { 3808 SDValue Const = DAG.getConstant(PtrByteSize - Size, 3809 PtrOff.getValueType()); 3810 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3811 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, 3812 CallSeqStart, 3813 Flags, DAG, dl); 3814 ArgOffset += PtrByteSize; 3815 continue; 3816 } 3817 // Copy entire object into memory. There are cases where gcc-generated 3818 // code assumes it is there, even if it could be put entirely into 3819 // registers. (This is not what the doc says.) 3820 3821 // FIXME: The above statement is likely due to a misunderstanding of the 3822 // documents. All arguments must be copied into the parameter area BY 3823 // THE CALLEE in the event that the callee takes the address of any 3824 // formal argument. That has not yet been implemented. However, it is 3825 // reasonable to use the stack area as a staging area for the register 3826 // load. 3827 3828 // Skip this for small aggregates, as we will use the same slot for a 3829 // right-justified copy, below. 3830 if (Size >= 8) 3831 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff, 3832 CallSeqStart, 3833 Flags, DAG, dl); 3834 3835 // When a register is available, pass a small aggregate right-justified. 3836 if (Size < 8 && GPR_idx != NumGPRs) { 3837 // The easiest way to get this right-justified in a register 3838 // is to copy the structure into the rightmost portion of a 3839 // local variable slot, then load the whole slot into the 3840 // register. 3841 // FIXME: The memcpy seems to produce pretty awful code for 3842 // small aggregates, particularly for packed ones. 3843 // FIXME: It would be preferable to use the slot in the 3844 // parameter save area instead of a new local variable. 3845 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType()); 3846 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3847 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, 3848 CallSeqStart, 3849 Flags, DAG, dl); 3850 3851 // Load the slot into the register. 3852 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff, 3853 MachinePointerInfo(), 3854 false, false, false, 0); 3855 MemOpChains.push_back(Load.getValue(1)); 3856 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3857 3858 // Done with this argument. 3859 ArgOffset += PtrByteSize; 3860 continue; 3861 } 3862 3863 // For aggregates larger than PtrByteSize, copy the pieces of the 3864 // object that fit into registers from the parameter save area. 3865 for (unsigned j=0; j<Size; j+=PtrByteSize) { 3866 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 3867 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 3868 if (GPR_idx != NumGPRs) { 3869 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 3870 MachinePointerInfo(), 3871 false, false, false, 0); 3872 MemOpChains.push_back(Load.getValue(1)); 3873 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3874 ArgOffset += PtrByteSize; 3875 } else { 3876 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 3877 break; 3878 } 3879 } 3880 continue; 3881 } 3882 3883 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 3884 default: llvm_unreachable("Unexpected ValueType for argument!"); 3885 case MVT::i32: 3886 case MVT::i64: 3887 if (GPR_idx != NumGPRs) { 3888 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 3889 } else { 3890 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3891 true, isTailCall, false, MemOpChains, 3892 TailCallArguments, dl); 3893 } 3894 ArgOffset += PtrByteSize; 3895 break; 3896 case MVT::f32: 3897 case MVT::f64: 3898 if (FPR_idx != NumFPRs) { 3899 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 3900 3901 if (isVarArg) { 3902 // A single float or an aggregate containing only a single float 3903 // must be passed right-justified in the stack doubleword, and 3904 // in the GPR, if one is available. 3905 SDValue StoreOff; 3906 if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) { 3907 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3908 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 3909 } else 3910 StoreOff = PtrOff; 3911 3912 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff, 3913 MachinePointerInfo(), false, false, 0); 3914 MemOpChains.push_back(Store); 3915 3916 // Float varargs are always shadowed in available integer registers 3917 if (GPR_idx != NumGPRs) { 3918 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 3919 MachinePointerInfo(), false, false, 3920 false, 0); 3921 MemOpChains.push_back(Load.getValue(1)); 3922 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3923 } 3924 } else if (GPR_idx != NumGPRs) 3925 // If we have any FPRs remaining, we may also have GPRs remaining. 3926 ++GPR_idx; 3927 } else { 3928 // Single-precision floating-point values are mapped to the 3929 // second (rightmost) word of the stack doubleword. 3930 if (Arg.getValueType() == MVT::f32) { 3931 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3932 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 3933 } 3934 3935 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3936 true, isTailCall, false, MemOpChains, 3937 TailCallArguments, dl); 3938 } 3939 ArgOffset += 8; 3940 break; 3941 case MVT::v4f32: 3942 case MVT::v4i32: 3943 case MVT::v8i16: 3944 case MVT::v16i8: 3945 if (isVarArg) { 3946 // These go aligned on the stack, or in the corresponding R registers 3947 // when within range. The Darwin PPC ABI doc claims they also go in 3948 // V registers; in fact gcc does this only for arguments that are 3949 // prototyped, not for those that match the ... We do it for all 3950 // arguments, seems to work. 3951 while (ArgOffset % 16 !=0) { 3952 ArgOffset += PtrByteSize; 3953 if (GPR_idx != NumGPRs) 3954 GPR_idx++; 3955 } 3956 // We could elide this store in the case where the object fits 3957 // entirely in R registers. Maybe later. 3958 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 3959 DAG.getConstant(ArgOffset, PtrVT)); 3960 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 3961 MachinePointerInfo(), false, false, 0); 3962 MemOpChains.push_back(Store); 3963 if (VR_idx != NumVRs) { 3964 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, 3965 MachinePointerInfo(), 3966 false, false, false, 0); 3967 MemOpChains.push_back(Load.getValue(1)); 3968 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 3969 } 3970 ArgOffset += 16; 3971 for (unsigned i=0; i<16; i+=PtrByteSize) { 3972 if (GPR_idx == NumGPRs) 3973 break; 3974 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 3975 DAG.getConstant(i, PtrVT)); 3976 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(), 3977 false, false, false, 0); 3978 MemOpChains.push_back(Load.getValue(1)); 3979 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3980 } 3981 break; 3982 } 3983 3984 // Non-varargs Altivec params generally go in registers, but have 3985 // stack space allocated at the end. 3986 if (VR_idx != NumVRs) { 3987 // Doesn't have GPR space allocated. 3988 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 3989 } else { 3990 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3991 true, isTailCall, true, MemOpChains, 3992 TailCallArguments, dl); 3993 ArgOffset += 16; 3994 } 3995 break; 3996 } 3997 } 3998 3999 if (!MemOpChains.empty()) 4000 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 4001 &MemOpChains[0], MemOpChains.size()); 4002 4003 // Check if this is an indirect call (MTCTR/BCTRL). 4004 // See PrepareCall() for more information about calls through function 4005 // pointers in the 64-bit SVR4 ABI. 4006 if (!isTailCall && 4007 !dyn_cast<GlobalAddressSDNode>(Callee) && 4008 !dyn_cast<ExternalSymbolSDNode>(Callee) && 4009 !isBLACompatibleAddress(Callee, DAG)) { 4010 // Load r2 into a virtual register and store it to the TOC save area. 4011 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); 4012 // TOC save area offset. 4013 SDValue PtrOff = DAG.getIntPtrConstant(40); 4014 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 4015 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(), 4016 false, false, 0); 4017 // R12 must contain the address of an indirect callee. This does not 4018 // mean the MTCTR instruction must use R12; it's easier to model this 4019 // as an extra parameter, so do that. 4020 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee)); 4021 } 4022 4023 // Build a sequence of copy-to-reg nodes chained together with token chain 4024 // and flag operands which copy the outgoing args into the appropriate regs. 4025 SDValue InFlag; 4026 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 4027 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 4028 RegsToPass[i].second, InFlag); 4029 InFlag = Chain.getValue(1); 4030 } 4031 4032 if (isTailCall) 4033 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp, 4034 FPOp, true, TailCallArguments); 4035 4036 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 4037 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 4038 Ins, InVals); 4039} 4040 4041SDValue 4042PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, 4043 CallingConv::ID CallConv, bool isVarArg, 4044 bool isTailCall, 4045 const SmallVectorImpl<ISD::OutputArg> &Outs, 4046 const SmallVectorImpl<SDValue> &OutVals, 4047 const SmallVectorImpl<ISD::InputArg> &Ins, 4048 DebugLoc dl, SelectionDAG &DAG, 4049 SmallVectorImpl<SDValue> &InVals) const { 4050 4051 unsigned NumOps = Outs.size(); 4052 4053 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4054 bool isPPC64 = PtrVT == MVT::i64; 4055 unsigned PtrByteSize = isPPC64 ? 8 : 4; 4056 4057 MachineFunction &MF = DAG.getMachineFunction(); 4058 4059 // Mark this function as potentially containing a function that contains a 4060 // tail call. As a consequence the frame pointer will be used for dynamicalloc 4061 // and restoring the callers stack pointer in this functions epilog. This is 4062 // done because by tail calling the called function might overwrite the value 4063 // in this function's (MF) stack pointer stack slot 0(SP). 4064 if (getTargetMachine().Options.GuaranteedTailCallOpt && 4065 CallConv == CallingConv::Fast) 4066 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 4067 4068 unsigned nAltivecParamsAtEnd = 0; 4069 4070 // Count how many bytes are to be pushed on the stack, including the linkage 4071 // area, and parameter passing area. We start with 24/48 bytes, which is 4072 // prereserved space for [SP][CR][LR][3 x unused]. 4073 unsigned NumBytes = 4074 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv, 4075 Outs, OutVals, 4076 nAltivecParamsAtEnd); 4077 4078 // Calculate by how many bytes the stack has to be adjusted in case of tail 4079 // call optimization. 4080 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 4081 4082 // To protect arguments on the stack from being clobbered in a tail call, 4083 // force all the loads to happen before doing any other lowering. 4084 if (isTailCall) 4085 Chain = DAG.getStackArgumentTokenFactor(Chain); 4086 4087 // Adjust the stack pointer for the new arguments... 4088 // These operations are automatically eliminated by the prolog/epilog pass 4089 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 4090 SDValue CallSeqStart = Chain; 4091 4092 // Load the return address and frame pointer so it can be move somewhere else 4093 // later. 4094 SDValue LROp, FPOp; 4095 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 4096 dl); 4097 4098 // Set up a copy of the stack pointer for use loading and storing any 4099 // arguments that may not fit in the registers available for argument 4100 // passing. 4101 SDValue StackPtr; 4102 if (isPPC64) 4103 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 4104 else 4105 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 4106 4107 // Figure out which arguments are going to go in registers, and which in 4108 // memory. Also, if this is a vararg function, floating point operations 4109 // must be stored to our stack, and loaded into integer regs as well, if 4110 // any integer regs are available for argument passing. 4111 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); 4112 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 4113 4114 static const uint16_t GPR_32[] = { // 32-bit registers. 4115 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 4116 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 4117 }; 4118 static const uint16_t GPR_64[] = { // 64-bit registers. 4119 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 4120 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 4121 }; 4122 static const uint16_t *FPR = GetFPR(); 4123 4124 static const uint16_t VR[] = { 4125 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 4126 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 4127 }; 4128 const unsigned NumGPRs = array_lengthof(GPR_32); 4129 const unsigned NumFPRs = 13; 4130 const unsigned NumVRs = array_lengthof(VR); 4131 4132 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32; 4133 4134 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 4135 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 4136 4137 SmallVector<SDValue, 8> MemOpChains; 4138 for (unsigned i = 0; i != NumOps; ++i) { 4139 SDValue Arg = OutVals[i]; 4140 ISD::ArgFlagsTy Flags = Outs[i].Flags; 4141 4142 // PtrOff will be used to store the current argument to the stack if a 4143 // register cannot be found for it. 4144 SDValue PtrOff; 4145 4146 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 4147 4148 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 4149 4150 // On PPC64, promote integers to 64-bit values. 4151 if (isPPC64 && Arg.getValueType() == MVT::i32) { 4152 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 4153 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 4154 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 4155 } 4156 4157 // FIXME memcpy is used way more than necessary. Correctness first. 4158 // Note: "by value" is code for passing a structure by value, not 4159 // basic types. 4160 if (Flags.isByVal()) { 4161 unsigned Size = Flags.getByValSize(); 4162 // Very small objects are passed right-justified. Everything else is 4163 // passed left-justified. 4164 if (Size==1 || Size==2) { 4165 EVT VT = (Size==1) ? MVT::i8 : MVT::i16; 4166 if (GPR_idx != NumGPRs) { 4167 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, 4168 MachinePointerInfo(), VT, 4169 false, false, 0); 4170 MemOpChains.push_back(Load.getValue(1)); 4171 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4172 4173 ArgOffset += PtrByteSize; 4174 } else { 4175 SDValue Const = DAG.getConstant(PtrByteSize - Size, 4176 PtrOff.getValueType()); 4177 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 4178 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, 4179 CallSeqStart, 4180 Flags, DAG, dl); 4181 ArgOffset += PtrByteSize; 4182 } 4183 continue; 4184 } 4185 // Copy entire object into memory. There are cases where gcc-generated 4186 // code assumes it is there, even if it could be put entirely into 4187 // registers. (This is not what the doc says.) 4188 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff, 4189 CallSeqStart, 4190 Flags, DAG, dl); 4191 4192 // For small aggregates (Darwin only) and aggregates >= PtrByteSize, 4193 // copy the pieces of the object that fit into registers from the 4194 // parameter save area. 4195 for (unsigned j=0; j<Size; j+=PtrByteSize) { 4196 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 4197 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 4198 if (GPR_idx != NumGPRs) { 4199 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 4200 MachinePointerInfo(), 4201 false, false, false, 0); 4202 MemOpChains.push_back(Load.getValue(1)); 4203 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4204 ArgOffset += PtrByteSize; 4205 } else { 4206 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 4207 break; 4208 } 4209 } 4210 continue; 4211 } 4212 4213 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 4214 default: llvm_unreachable("Unexpected ValueType for argument!"); 4215 case MVT::i32: 4216 case MVT::i64: 4217 if (GPR_idx != NumGPRs) { 4218 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 4219 } else { 4220 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4221 isPPC64, isTailCall, false, MemOpChains, 4222 TailCallArguments, dl); 4223 } 4224 ArgOffset += PtrByteSize; 4225 break; 4226 case MVT::f32: 4227 case MVT::f64: 4228 if (FPR_idx != NumFPRs) { 4229 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 4230 4231 if (isVarArg) { 4232 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 4233 MachinePointerInfo(), false, false, 0); 4234 MemOpChains.push_back(Store); 4235 4236 // Float varargs are always shadowed in available integer registers 4237 if (GPR_idx != NumGPRs) { 4238 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 4239 MachinePointerInfo(), false, false, 4240 false, 0); 4241 MemOpChains.push_back(Load.getValue(1)); 4242 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4243 } 4244 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 4245 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 4246 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 4247 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 4248 MachinePointerInfo(), 4249 false, false, false, 0); 4250 MemOpChains.push_back(Load.getValue(1)); 4251 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4252 } 4253 } else { 4254 // If we have any FPRs remaining, we may also have GPRs remaining. 4255 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 4256 // GPRs. 4257 if (GPR_idx != NumGPRs) 4258 ++GPR_idx; 4259 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 4260 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 4261 ++GPR_idx; 4262 } 4263 } else 4264 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4265 isPPC64, isTailCall, false, MemOpChains, 4266 TailCallArguments, dl); 4267 if (isPPC64) 4268 ArgOffset += 8; 4269 else 4270 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 4271 break; 4272 case MVT::v4f32: 4273 case MVT::v4i32: 4274 case MVT::v8i16: 4275 case MVT::v16i8: 4276 if (isVarArg) { 4277 // These go aligned on the stack, or in the corresponding R registers 4278 // when within range. The Darwin PPC ABI doc claims they also go in 4279 // V registers; in fact gcc does this only for arguments that are 4280 // prototyped, not for those that match the ... We do it for all 4281 // arguments, seems to work. 4282 while (ArgOffset % 16 !=0) { 4283 ArgOffset += PtrByteSize; 4284 if (GPR_idx != NumGPRs) 4285 GPR_idx++; 4286 } 4287 // We could elide this store in the case where the object fits 4288 // entirely in R registers. Maybe later. 4289 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 4290 DAG.getConstant(ArgOffset, PtrVT)); 4291 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 4292 MachinePointerInfo(), false, false, 0); 4293 MemOpChains.push_back(Store); 4294 if (VR_idx != NumVRs) { 4295 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, 4296 MachinePointerInfo(), 4297 false, false, false, 0); 4298 MemOpChains.push_back(Load.getValue(1)); 4299 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 4300 } 4301 ArgOffset += 16; 4302 for (unsigned i=0; i<16; i+=PtrByteSize) { 4303 if (GPR_idx == NumGPRs) 4304 break; 4305 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 4306 DAG.getConstant(i, PtrVT)); 4307 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(), 4308 false, false, false, 0); 4309 MemOpChains.push_back(Load.getValue(1)); 4310 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4311 } 4312 break; 4313 } 4314 4315 // Non-varargs Altivec params generally go in registers, but have 4316 // stack space allocated at the end. 4317 if (VR_idx != NumVRs) { 4318 // Doesn't have GPR space allocated. 4319 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 4320 } else if (nAltivecParamsAtEnd==0) { 4321 // We are emitting Altivec params in order. 4322 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4323 isPPC64, isTailCall, true, MemOpChains, 4324 TailCallArguments, dl); 4325 ArgOffset += 16; 4326 } 4327 break; 4328 } 4329 } 4330 // If all Altivec parameters fit in registers, as they usually do, 4331 // they get stack space following the non-Altivec parameters. We 4332 // don't track this here because nobody below needs it. 4333 // If there are more Altivec parameters than fit in registers emit 4334 // the stores here. 4335 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) { 4336 unsigned j = 0; 4337 // Offset is aligned; skip 1st 12 params which go in V registers. 4338 ArgOffset = ((ArgOffset+15)/16)*16; 4339 ArgOffset += 12*16; 4340 for (unsigned i = 0; i != NumOps; ++i) { 4341 SDValue Arg = OutVals[i]; 4342 EVT ArgType = Outs[i].VT; 4343 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || 4344 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { 4345 if (++j > NumVRs) { 4346 SDValue PtrOff; 4347 // We are emitting Altivec params in order. 4348 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4349 isPPC64, isTailCall, true, MemOpChains, 4350 TailCallArguments, dl); 4351 ArgOffset += 16; 4352 } 4353 } 4354 } 4355 } 4356 4357 if (!MemOpChains.empty()) 4358 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 4359 &MemOpChains[0], MemOpChains.size()); 4360 4361 // On Darwin, R12 must contain the address of an indirect callee. This does 4362 // not mean the MTCTR instruction must use R12; it's easier to model this as 4363 // an extra parameter, so do that. 4364 if (!isTailCall && 4365 !dyn_cast<GlobalAddressSDNode>(Callee) && 4366 !dyn_cast<ExternalSymbolSDNode>(Callee) && 4367 !isBLACompatibleAddress(Callee, DAG)) 4368 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 : 4369 PPC::R12), Callee)); 4370 4371 // Build a sequence of copy-to-reg nodes chained together with token chain 4372 // and flag operands which copy the outgoing args into the appropriate regs. 4373 SDValue InFlag; 4374 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 4375 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 4376 RegsToPass[i].second, InFlag); 4377 InFlag = Chain.getValue(1); 4378 } 4379 4380 if (isTailCall) 4381 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp, 4382 FPOp, true, TailCallArguments); 4383 4384 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 4385 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 4386 Ins, InVals); 4387} 4388 4389bool 4390PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 4391 MachineFunction &MF, bool isVarArg, 4392 const SmallVectorImpl<ISD::OutputArg> &Outs, 4393 LLVMContext &Context) const { 4394 SmallVector<CCValAssign, 16> RVLocs; 4395 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 4396 RVLocs, Context); 4397 return CCInfo.CheckReturn(Outs, RetCC_PPC); 4398} 4399 4400SDValue 4401PPCTargetLowering::LowerReturn(SDValue Chain, 4402 CallingConv::ID CallConv, bool isVarArg, 4403 const SmallVectorImpl<ISD::OutputArg> &Outs, 4404 const SmallVectorImpl<SDValue> &OutVals, 4405 DebugLoc dl, SelectionDAG &DAG) const { 4406 4407 SmallVector<CCValAssign, 16> RVLocs; 4408 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 4409 getTargetMachine(), RVLocs, *DAG.getContext()); 4410 CCInfo.AnalyzeReturn(Outs, RetCC_PPC); 4411 4412 // If this is the first return lowered for this function, add the regs to the 4413 // liveout set for the function. 4414 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 4415 for (unsigned i = 0; i != RVLocs.size(); ++i) 4416 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 4417 } 4418 4419 SDValue Flag; 4420 4421 // Copy the result values into the output registers. 4422 for (unsigned i = 0; i != RVLocs.size(); ++i) { 4423 CCValAssign &VA = RVLocs[i]; 4424 assert(VA.isRegLoc() && "Can only return in registers!"); 4425 4426 SDValue Arg = OutVals[i]; 4427 4428 switch (VA.getLocInfo()) { 4429 default: llvm_unreachable("Unknown loc info!"); 4430 case CCValAssign::Full: break; 4431 case CCValAssign::AExt: 4432 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 4433 break; 4434 case CCValAssign::ZExt: 4435 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 4436 break; 4437 case CCValAssign::SExt: 4438 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 4439 break; 4440 } 4441 4442 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 4443 Flag = Chain.getValue(1); 4444 } 4445 4446 if (Flag.getNode()) 4447 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 4448 else 4449 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain); 4450} 4451 4452SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 4453 const PPCSubtarget &Subtarget) const { 4454 // When we pop the dynamic allocation we need to restore the SP link. 4455 DebugLoc dl = Op.getDebugLoc(); 4456 4457 // Get the corect type for pointers. 4458 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4459 4460 // Construct the stack pointer operand. 4461 bool isPPC64 = Subtarget.isPPC64(); 4462 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; 4463 SDValue StackPtr = DAG.getRegister(SP, PtrVT); 4464 4465 // Get the operands for the STACKRESTORE. 4466 SDValue Chain = Op.getOperand(0); 4467 SDValue SaveSP = Op.getOperand(1); 4468 4469 // Load the old link SP. 4470 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, 4471 MachinePointerInfo(), 4472 false, false, false, 0); 4473 4474 // Restore the stack pointer. 4475 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); 4476 4477 // Store the old link SP. 4478 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(), 4479 false, false, 0); 4480} 4481 4482 4483 4484SDValue 4485PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { 4486 MachineFunction &MF = DAG.getMachineFunction(); 4487 bool isPPC64 = PPCSubTarget.isPPC64(); 4488 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 4489 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4490 4491 // Get current frame pointer save index. The users of this index will be 4492 // primarily DYNALLOC instructions. 4493 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 4494 int RASI = FI->getReturnAddrSaveIndex(); 4495 4496 // If the frame pointer save index hasn't been defined yet. 4497 if (!RASI) { 4498 // Find out what the fix offset of the frame pointer save area. 4499 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 4500 // Allocate the frame index for frame pointer save area. 4501 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true); 4502 // Save the result. 4503 FI->setReturnAddrSaveIndex(RASI); 4504 } 4505 return DAG.getFrameIndex(RASI, PtrVT); 4506} 4507 4508SDValue 4509PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { 4510 MachineFunction &MF = DAG.getMachineFunction(); 4511 bool isPPC64 = PPCSubTarget.isPPC64(); 4512 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 4513 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4514 4515 // Get current frame pointer save index. The users of this index will be 4516 // primarily DYNALLOC instructions. 4517 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 4518 int FPSI = FI->getFramePointerSaveIndex(); 4519 4520 // If the frame pointer save index hasn't been defined yet. 4521 if (!FPSI) { 4522 // Find out what the fix offset of the frame pointer save area. 4523 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, 4524 isDarwinABI); 4525 4526 // Allocate the frame index for frame pointer save area. 4527 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 4528 // Save the result. 4529 FI->setFramePointerSaveIndex(FPSI); 4530 } 4531 return DAG.getFrameIndex(FPSI, PtrVT); 4532} 4533 4534SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 4535 SelectionDAG &DAG, 4536 const PPCSubtarget &Subtarget) const { 4537 // Get the inputs. 4538 SDValue Chain = Op.getOperand(0); 4539 SDValue Size = Op.getOperand(1); 4540 DebugLoc dl = Op.getDebugLoc(); 4541 4542 // Get the corect type for pointers. 4543 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4544 // Negate the size. 4545 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, 4546 DAG.getConstant(0, PtrVT), Size); 4547 // Construct a node for the frame pointer save index. 4548 SDValue FPSIdx = getFramePointerFrameIndex(DAG); 4549 // Build a DYNALLOC node. 4550 SDValue Ops[3] = { Chain, NegSize, FPSIdx }; 4551 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 4552 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3); 4553} 4554 4555/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 4556/// possible. 4557SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 4558 // Not FP? Not a fsel. 4559 if (!Op.getOperand(0).getValueType().isFloatingPoint() || 4560 !Op.getOperand(2).getValueType().isFloatingPoint()) 4561 return Op; 4562 4563 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 4564 4565 // Cannot handle SETEQ/SETNE. 4566 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op; 4567 4568 EVT ResVT = Op.getValueType(); 4569 EVT CmpVT = Op.getOperand(0).getValueType(); 4570 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4571 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); 4572 DebugLoc dl = Op.getDebugLoc(); 4573 4574 // If the RHS of the comparison is a 0.0, we don't need to do the 4575 // subtraction at all. 4576 if (isFloatingPointZero(RHS)) 4577 switch (CC) { 4578 default: break; // SETUO etc aren't handled by fsel. 4579 case ISD::SETULT: 4580 case ISD::SETLT: 4581 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 4582 case ISD::SETOGE: 4583 case ISD::SETGE: 4584 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 4585 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 4586 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); 4587 case ISD::SETUGT: 4588 case ISD::SETGT: 4589 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 4590 case ISD::SETOLE: 4591 case ISD::SETLE: 4592 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 4593 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 4594 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 4595 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); 4596 } 4597 4598 SDValue Cmp; 4599 switch (CC) { 4600 default: break; // SETUO etc aren't handled by fsel. 4601 case ISD::SETULT: 4602 case ISD::SETLT: 4603 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 4604 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4605 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4606 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 4607 case ISD::SETOGE: 4608 case ISD::SETGE: 4609 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 4610 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4611 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4612 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 4613 case ISD::SETUGT: 4614 case ISD::SETGT: 4615 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 4616 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4617 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4618 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 4619 case ISD::SETOLE: 4620 case ISD::SETLE: 4621 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 4622 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4623 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4624 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 4625 } 4626 return Op; 4627} 4628 4629// FIXME: Split this code up when LegalizeDAGTypes lands. 4630SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 4631 DebugLoc dl) const { 4632 assert(Op.getOperand(0).getValueType().isFloatingPoint()); 4633 SDValue Src = Op.getOperand(0); 4634 if (Src.getValueType() == MVT::f32) 4635 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); 4636 4637 SDValue Tmp; 4638 switch (Op.getValueType().getSimpleVT().SimpleTy) { 4639 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); 4640 case MVT::i32: 4641 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : 4642 PPCISD::FCTIDZ, 4643 dl, MVT::f64, Src); 4644 break; 4645 case MVT::i64: 4646 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src); 4647 break; 4648 } 4649 4650 // Convert the FP value to an int value through memory. 4651 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); 4652 4653 // Emit a store to the stack slot. 4654 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, 4655 MachinePointerInfo(), false, false, 0); 4656 4657 // Result is a load from the stack slot. If loading 4 bytes, make sure to 4658 // add in a bias. 4659 if (Op.getValueType() == MVT::i32) 4660 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, 4661 DAG.getConstant(4, FIPtr.getValueType())); 4662 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(), 4663 false, false, false, 0); 4664} 4665 4666SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, 4667 SelectionDAG &DAG) const { 4668 DebugLoc dl = Op.getDebugLoc(); 4669 // Don't handle ppc_fp128 here; let it be lowered to a libcall. 4670 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) 4671 return SDValue(); 4672 4673 if (Op.getOperand(0).getValueType() == MVT::i64) { 4674 SDValue SINT = Op.getOperand(0); 4675 // When converting to single-precision, we actually need to convert 4676 // to double-precision first and then round to single-precision. 4677 // To avoid double-rounding effects during that operation, we have 4678 // to prepare the input operand. Bits that might be truncated when 4679 // converting to double-precision are replaced by a bit that won't 4680 // be lost at this stage, but is below the single-precision rounding 4681 // position. 4682 // 4683 // However, if -enable-unsafe-fp-math is in effect, accept double 4684 // rounding to avoid the extra overhead. 4685 if (Op.getValueType() == MVT::f32 && 4686 !DAG.getTarget().Options.UnsafeFPMath) { 4687 4688 // Twiddle input to make sure the low 11 bits are zero. (If this 4689 // is the case, we are guaranteed the value will fit into the 53 bit 4690 // mantissa of an IEEE double-precision value without rounding.) 4691 // If any of those low 11 bits were not zero originally, make sure 4692 // bit 12 (value 2048) is set instead, so that the final rounding 4693 // to single-precision gets the correct result. 4694 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64, 4695 SINT, DAG.getConstant(2047, MVT::i64)); 4696 Round = DAG.getNode(ISD::ADD, dl, MVT::i64, 4697 Round, DAG.getConstant(2047, MVT::i64)); 4698 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT); 4699 Round = DAG.getNode(ISD::AND, dl, MVT::i64, 4700 Round, DAG.getConstant(-2048, MVT::i64)); 4701 4702 // However, we cannot use that value unconditionally: if the magnitude 4703 // of the input value is small, the bit-twiddling we did above might 4704 // end up visibly changing the output. Fortunately, in that case, we 4705 // don't need to twiddle bits since the original input will convert 4706 // exactly to double-precision floating-point already. Therefore, 4707 // construct a conditional to use the original value if the top 11 4708 // bits are all sign-bit copies, and use the rounded value computed 4709 // above otherwise. 4710 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64, 4711 SINT, DAG.getConstant(53, MVT::i32)); 4712 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64, 4713 Cond, DAG.getConstant(1, MVT::i64)); 4714 Cond = DAG.getSetCC(dl, MVT::i32, 4715 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT); 4716 4717 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT); 4718 } 4719 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT); 4720 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); 4721 if (Op.getValueType() == MVT::f32) 4722 FP = DAG.getNode(ISD::FP_ROUND, dl, 4723 MVT::f32, FP, DAG.getIntPtrConstant(0)); 4724 return FP; 4725 } 4726 4727 assert(Op.getOperand(0).getValueType() == MVT::i32 && 4728 "Unhandled SINT_TO_FP type in custom expander!"); 4729 // Since we only generate this in 64-bit mode, we can take advantage of 4730 // 64-bit registers. In particular, sign extend the input value into the 4731 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 4732 // then lfd it and fcfid it. 4733 MachineFunction &MF = DAG.getMachineFunction(); 4734 MachineFrameInfo *FrameInfo = MF.getFrameInfo(); 4735 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false); 4736 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4737 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 4738 4739 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32, 4740 Op.getOperand(0)); 4741 4742 // STD the extended value into the stack slot. 4743 MachineMemOperand *MMO = 4744 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 4745 MachineMemOperand::MOStore, 8, 8); 4746 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx }; 4747 SDValue Store = 4748 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other), 4749 Ops, 4, MVT::i64, MMO); 4750 // Load the value as a double. 4751 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(), 4752 false, false, false, 0); 4753 4754 // FCFID it and return it. 4755 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); 4756 if (Op.getValueType() == MVT::f32) 4757 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); 4758 return FP; 4759} 4760 4761SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 4762 SelectionDAG &DAG) const { 4763 DebugLoc dl = Op.getDebugLoc(); 4764 /* 4765 The rounding mode is in bits 30:31 of FPSR, and has the following 4766 settings: 4767 00 Round to nearest 4768 01 Round to 0 4769 10 Round to +inf 4770 11 Round to -inf 4771 4772 FLT_ROUNDS, on the other hand, expects the following: 4773 -1 Undefined 4774 0 Round to 0 4775 1 Round to nearest 4776 2 Round to +inf 4777 3 Round to -inf 4778 4779 To perform the conversion, we do: 4780 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 4781 */ 4782 4783 MachineFunction &MF = DAG.getMachineFunction(); 4784 EVT VT = Op.getValueType(); 4785 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4786 std::vector<EVT> NodeTys; 4787 SDValue MFFSreg, InFlag; 4788 4789 // Save FP Control Word to register 4790 NodeTys.push_back(MVT::f64); // return register 4791 NodeTys.push_back(MVT::Glue); // unused in this context 4792 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 4793 4794 // Save FP register to stack slot 4795 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 4796 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 4797 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, 4798 StackSlot, MachinePointerInfo(), false, false,0); 4799 4800 // Load FP Control Word from low 32 bits of stack slot. 4801 SDValue Four = DAG.getConstant(4, PtrVT); 4802 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); 4803 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(), 4804 false, false, false, 0); 4805 4806 // Transform as necessary 4807 SDValue CWD1 = 4808 DAG.getNode(ISD::AND, dl, MVT::i32, 4809 CWD, DAG.getConstant(3, MVT::i32)); 4810 SDValue CWD2 = 4811 DAG.getNode(ISD::SRL, dl, MVT::i32, 4812 DAG.getNode(ISD::AND, dl, MVT::i32, 4813 DAG.getNode(ISD::XOR, dl, MVT::i32, 4814 CWD, DAG.getConstant(3, MVT::i32)), 4815 DAG.getConstant(3, MVT::i32)), 4816 DAG.getConstant(1, MVT::i32)); 4817 4818 SDValue RetVal = 4819 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); 4820 4821 return DAG.getNode((VT.getSizeInBits() < 16 ? 4822 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 4823} 4824 4825SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const { 4826 EVT VT = Op.getValueType(); 4827 unsigned BitWidth = VT.getSizeInBits(); 4828 DebugLoc dl = Op.getDebugLoc(); 4829 assert(Op.getNumOperands() == 3 && 4830 VT == Op.getOperand(1).getValueType() && 4831 "Unexpected SHL!"); 4832 4833 // Expand into a bunch of logical ops. Note that these ops 4834 // depend on the PPC behavior for oversized shift amounts. 4835 SDValue Lo = Op.getOperand(0); 4836 SDValue Hi = Op.getOperand(1); 4837 SDValue Amt = Op.getOperand(2); 4838 EVT AmtVT = Amt.getValueType(); 4839 4840 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 4841 DAG.getConstant(BitWidth, AmtVT), Amt); 4842 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); 4843 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); 4844 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); 4845 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 4846 DAG.getConstant(-BitWidth, AmtVT)); 4847 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); 4848 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 4849 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); 4850 SDValue OutOps[] = { OutLo, OutHi }; 4851 return DAG.getMergeValues(OutOps, 2, dl); 4852} 4853 4854SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const { 4855 EVT VT = Op.getValueType(); 4856 DebugLoc dl = Op.getDebugLoc(); 4857 unsigned BitWidth = VT.getSizeInBits(); 4858 assert(Op.getNumOperands() == 3 && 4859 VT == Op.getOperand(1).getValueType() && 4860 "Unexpected SRL!"); 4861 4862 // Expand into a bunch of logical ops. Note that these ops 4863 // depend on the PPC behavior for oversized shift amounts. 4864 SDValue Lo = Op.getOperand(0); 4865 SDValue Hi = Op.getOperand(1); 4866 SDValue Amt = Op.getOperand(2); 4867 EVT AmtVT = Amt.getValueType(); 4868 4869 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 4870 DAG.getConstant(BitWidth, AmtVT), Amt); 4871 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 4872 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 4873 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 4874 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 4875 DAG.getConstant(-BitWidth, AmtVT)); 4876 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); 4877 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 4878 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); 4879 SDValue OutOps[] = { OutLo, OutHi }; 4880 return DAG.getMergeValues(OutOps, 2, dl); 4881} 4882 4883SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const { 4884 DebugLoc dl = Op.getDebugLoc(); 4885 EVT VT = Op.getValueType(); 4886 unsigned BitWidth = VT.getSizeInBits(); 4887 assert(Op.getNumOperands() == 3 && 4888 VT == Op.getOperand(1).getValueType() && 4889 "Unexpected SRA!"); 4890 4891 // Expand into a bunch of logical ops, followed by a select_cc. 4892 SDValue Lo = Op.getOperand(0); 4893 SDValue Hi = Op.getOperand(1); 4894 SDValue Amt = Op.getOperand(2); 4895 EVT AmtVT = Amt.getValueType(); 4896 4897 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 4898 DAG.getConstant(BitWidth, AmtVT), Amt); 4899 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 4900 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 4901 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 4902 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 4903 DAG.getConstant(-BitWidth, AmtVT)); 4904 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); 4905 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); 4906 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), 4907 Tmp4, Tmp6, ISD::SETLE); 4908 SDValue OutOps[] = { OutLo, OutHi }; 4909 return DAG.getMergeValues(OutOps, 2, dl); 4910} 4911 4912//===----------------------------------------------------------------------===// 4913// Vector related lowering. 4914// 4915 4916/// BuildSplatI - Build a canonical splati of Val with an element size of 4917/// SplatSize. Cast the result to VT. 4918static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT, 4919 SelectionDAG &DAG, DebugLoc dl) { 4920 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 4921 4922 static const EVT VTys[] = { // canonical VT to use for each size. 4923 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 4924 }; 4925 4926 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 4927 4928 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 4929 if (Val == -1) 4930 SplatSize = 1; 4931 4932 EVT CanonicalVT = VTys[SplatSize-1]; 4933 4934 // Build a canonical splat for this value. 4935 SDValue Elt = DAG.getConstant(Val, MVT::i32); 4936 SmallVector<SDValue, 8> Ops; 4937 Ops.assign(CanonicalVT.getVectorNumElements(), Elt); 4938 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, 4939 &Ops[0], Ops.size()); 4940 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res); 4941} 4942 4943/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 4944/// specified intrinsic ID. 4945static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, 4946 SelectionDAG &DAG, DebugLoc dl, 4947 EVT DestVT = MVT::Other) { 4948 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 4949 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4950 DAG.getConstant(IID, MVT::i32), LHS, RHS); 4951} 4952 4953/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 4954/// specified intrinsic ID. 4955static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, 4956 SDValue Op2, SelectionDAG &DAG, 4957 DebugLoc dl, EVT DestVT = MVT::Other) { 4958 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 4959 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4960 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 4961} 4962 4963 4964/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 4965/// amount. The result has the specified value type. 4966static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, 4967 EVT VT, SelectionDAG &DAG, DebugLoc dl) { 4968 // Force LHS/RHS to be the right type. 4969 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS); 4970 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS); 4971 4972 int Ops[16]; 4973 for (unsigned i = 0; i != 16; ++i) 4974 Ops[i] = i + Amt; 4975 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); 4976 return DAG.getNode(ISD::BITCAST, dl, VT, T); 4977} 4978 4979// If this is a case we can't handle, return null and let the default 4980// expansion code take care of it. If we CAN select this case, and if it 4981// selects to a single instruction, return Op. Otherwise, if we can codegen 4982// this case more efficiently than a constant pool load, lower it to the 4983// sequence of ops that should be used. 4984SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, 4985 SelectionDAG &DAG) const { 4986 DebugLoc dl = Op.getDebugLoc(); 4987 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 4988 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR"); 4989 4990 // Check if this is a splat of a constant value. 4991 APInt APSplatBits, APSplatUndef; 4992 unsigned SplatBitSize; 4993 bool HasAnyUndefs; 4994 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize, 4995 HasAnyUndefs, 0, true) || SplatBitSize > 32) 4996 return SDValue(); 4997 4998 unsigned SplatBits = APSplatBits.getZExtValue(); 4999 unsigned SplatUndef = APSplatUndef.getZExtValue(); 5000 unsigned SplatSize = SplatBitSize / 8; 5001 5002 // First, handle single instruction cases. 5003 5004 // All zeros? 5005 if (SplatBits == 0) { 5006 // Canonicalize all zero vectors to be v4i32. 5007 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 5008 SDValue Z = DAG.getConstant(0, MVT::i32); 5009 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); 5010 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z); 5011 } 5012 return Op; 5013 } 5014 5015 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 5016 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >> 5017 (32-SplatBitSize)); 5018 if (SextVal >= -16 && SextVal <= 15) 5019 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl); 5020 5021 5022 // Two instruction sequences. 5023 5024 // If this value is in the range [-32,30] and is even, use: 5025 // tmp = VSPLTI[bhw], result = add tmp, tmp 5026 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 5027 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl); 5028 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res); 5029 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5030 } 5031 5032 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 5033 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 5034 // for fneg/fabs. 5035 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 5036 // Make -1 and vspltisw -1: 5037 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); 5038 5039 // Make the VSLW intrinsic, computing 0x8000_0000. 5040 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 5041 OnesV, DAG, dl); 5042 5043 // xor by OnesV to invert it. 5044 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); 5045 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5046 } 5047 5048 // Check to see if this is a wide variety of vsplti*, binop self cases. 5049 static const signed char SplatCsts[] = { 5050 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 5051 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 5052 }; 5053 5054 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 5055 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 5056 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 5057 int i = SplatCsts[idx]; 5058 5059 // Figure out what shift amount will be used by altivec if shifted by i in 5060 // this splat size. 5061 unsigned TypeShiftAmt = i & (SplatBitSize-1); 5062 5063 // vsplti + shl self. 5064 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) { 5065 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5066 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5067 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 5068 Intrinsic::ppc_altivec_vslw 5069 }; 5070 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5071 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5072 } 5073 5074 // vsplti + srl self. 5075 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 5076 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5077 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5078 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 5079 Intrinsic::ppc_altivec_vsrw 5080 }; 5081 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5082 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5083 } 5084 5085 // vsplti + sra self. 5086 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 5087 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5088 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5089 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 5090 Intrinsic::ppc_altivec_vsraw 5091 }; 5092 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5093 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5094 } 5095 5096 // vsplti + rol self. 5097 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 5098 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 5099 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5100 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5101 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 5102 Intrinsic::ppc_altivec_vrlw 5103 }; 5104 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5105 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5106 } 5107 5108 // t = vsplti c, result = vsldoi t, t, 1 5109 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) { 5110 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 5111 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); 5112 } 5113 // t = vsplti c, result = vsldoi t, t, 2 5114 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) { 5115 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 5116 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); 5117 } 5118 // t = vsplti c, result = vsldoi t, t, 3 5119 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) { 5120 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 5121 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); 5122 } 5123 } 5124 5125 // Three instruction sequences. 5126 5127 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 5128 if (SextVal >= 0 && SextVal <= 31) { 5129 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl); 5130 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 5131 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS); 5132 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS); 5133 } 5134 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 5135 if (SextVal >= -31 && SextVal <= 0) { 5136 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl); 5137 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 5138 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS); 5139 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS); 5140 } 5141 5142 return SDValue(); 5143} 5144 5145/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 5146/// the specified operations to build the shuffle. 5147static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 5148 SDValue RHS, SelectionDAG &DAG, 5149 DebugLoc dl) { 5150 unsigned OpNum = (PFEntry >> 26) & 0x0F; 5151 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 5152 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 5153 5154 enum { 5155 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 5156 OP_VMRGHW, 5157 OP_VMRGLW, 5158 OP_VSPLTISW0, 5159 OP_VSPLTISW1, 5160 OP_VSPLTISW2, 5161 OP_VSPLTISW3, 5162 OP_VSLDOI4, 5163 OP_VSLDOI8, 5164 OP_VSLDOI12 5165 }; 5166 5167 if (OpNum == OP_COPY) { 5168 if (LHSID == (1*9+2)*9+3) return LHS; 5169 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 5170 return RHS; 5171 } 5172 5173 SDValue OpLHS, OpRHS; 5174 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 5175 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 5176 5177 int ShufIdxs[16]; 5178 switch (OpNum) { 5179 default: llvm_unreachable("Unknown i32 permute!"); 5180 case OP_VMRGHW: 5181 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 5182 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 5183 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 5184 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 5185 break; 5186 case OP_VMRGLW: 5187 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 5188 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 5189 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 5190 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 5191 break; 5192 case OP_VSPLTISW0: 5193 for (unsigned i = 0; i != 16; ++i) 5194 ShufIdxs[i] = (i&3)+0; 5195 break; 5196 case OP_VSPLTISW1: 5197 for (unsigned i = 0; i != 16; ++i) 5198 ShufIdxs[i] = (i&3)+4; 5199 break; 5200 case OP_VSPLTISW2: 5201 for (unsigned i = 0; i != 16; ++i) 5202 ShufIdxs[i] = (i&3)+8; 5203 break; 5204 case OP_VSPLTISW3: 5205 for (unsigned i = 0; i != 16; ++i) 5206 ShufIdxs[i] = (i&3)+12; 5207 break; 5208 case OP_VSLDOI4: 5209 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl); 5210 case OP_VSLDOI8: 5211 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl); 5212 case OP_VSLDOI12: 5213 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl); 5214 } 5215 EVT VT = OpLHS.getValueType(); 5216 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS); 5217 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS); 5218 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); 5219 return DAG.getNode(ISD::BITCAST, dl, VT, T); 5220} 5221 5222/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 5223/// is a shuffle we can handle in a single instruction, return it. Otherwise, 5224/// return the code it can be lowered into. Worst case, it can always be 5225/// lowered into a vperm. 5226SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 5227 SelectionDAG &DAG) const { 5228 DebugLoc dl = Op.getDebugLoc(); 5229 SDValue V1 = Op.getOperand(0); 5230 SDValue V2 = Op.getOperand(1); 5231 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5232 EVT VT = Op.getValueType(); 5233 5234 // Cases that are handled by instructions that take permute immediates 5235 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 5236 // selected by the instruction selector. 5237 if (V2.getOpcode() == ISD::UNDEF) { 5238 if (PPC::isSplatShuffleMask(SVOp, 1) || 5239 PPC::isSplatShuffleMask(SVOp, 2) || 5240 PPC::isSplatShuffleMask(SVOp, 4) || 5241 PPC::isVPKUWUMShuffleMask(SVOp, true) || 5242 PPC::isVPKUHUMShuffleMask(SVOp, true) || 5243 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 || 5244 PPC::isVMRGLShuffleMask(SVOp, 1, true) || 5245 PPC::isVMRGLShuffleMask(SVOp, 2, true) || 5246 PPC::isVMRGLShuffleMask(SVOp, 4, true) || 5247 PPC::isVMRGHShuffleMask(SVOp, 1, true) || 5248 PPC::isVMRGHShuffleMask(SVOp, 2, true) || 5249 PPC::isVMRGHShuffleMask(SVOp, 4, true)) { 5250 return Op; 5251 } 5252 } 5253 5254 // Altivec has a variety of "shuffle immediates" that take two vector inputs 5255 // and produce a fixed permutation. If any of these match, do not lower to 5256 // VPERM. 5257 if (PPC::isVPKUWUMShuffleMask(SVOp, false) || 5258 PPC::isVPKUHUMShuffleMask(SVOp, false) || 5259 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 || 5260 PPC::isVMRGLShuffleMask(SVOp, 1, false) || 5261 PPC::isVMRGLShuffleMask(SVOp, 2, false) || 5262 PPC::isVMRGLShuffleMask(SVOp, 4, false) || 5263 PPC::isVMRGHShuffleMask(SVOp, 1, false) || 5264 PPC::isVMRGHShuffleMask(SVOp, 2, false) || 5265 PPC::isVMRGHShuffleMask(SVOp, 4, false)) 5266 return Op; 5267 5268 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 5269 // perfect shuffle table to emit an optimal matching sequence. 5270 ArrayRef<int> PermMask = SVOp->getMask(); 5271 5272 unsigned PFIndexes[4]; 5273 bool isFourElementShuffle = true; 5274 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 5275 unsigned EltNo = 8; // Start out undef. 5276 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 5277 if (PermMask[i*4+j] < 0) 5278 continue; // Undef, ignore it. 5279 5280 unsigned ByteSource = PermMask[i*4+j]; 5281 if ((ByteSource & 3) != j) { 5282 isFourElementShuffle = false; 5283 break; 5284 } 5285 5286 if (EltNo == 8) { 5287 EltNo = ByteSource/4; 5288 } else if (EltNo != ByteSource/4) { 5289 isFourElementShuffle = false; 5290 break; 5291 } 5292 } 5293 PFIndexes[i] = EltNo; 5294 } 5295 5296 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 5297 // perfect shuffle vector to determine if it is cost effective to do this as 5298 // discrete instructions, or whether we should use a vperm. 5299 if (isFourElementShuffle) { 5300 // Compute the index in the perfect shuffle table. 5301 unsigned PFTableIndex = 5302 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 5303 5304 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 5305 unsigned Cost = (PFEntry >> 30); 5306 5307 // Determining when to avoid vperm is tricky. Many things affect the cost 5308 // of vperm, particularly how many times the perm mask needs to be computed. 5309 // For example, if the perm mask can be hoisted out of a loop or is already 5310 // used (perhaps because there are multiple permutes with the same shuffle 5311 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 5312 // the loop requires an extra register. 5313 // 5314 // As a compromise, we only emit discrete instructions if the shuffle can be 5315 // generated in 3 or fewer operations. When we have loop information 5316 // available, if this block is within a loop, we should avoid using vperm 5317 // for 3-operation perms and use a constant pool load instead. 5318 if (Cost < 3) 5319 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 5320 } 5321 5322 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 5323 // vector that will get spilled to the constant pool. 5324 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 5325 5326 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 5327 // that it is in input element units, not in bytes. Convert now. 5328 EVT EltVT = V1.getValueType().getVectorElementType(); 5329 unsigned BytesPerElement = EltVT.getSizeInBits()/8; 5330 5331 SmallVector<SDValue, 16> ResultMask; 5332 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { 5333 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i]; 5334 5335 for (unsigned j = 0; j != BytesPerElement; ++j) 5336 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 5337 MVT::i32)); 5338 } 5339 5340 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, 5341 &ResultMask[0], ResultMask.size()); 5342 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); 5343} 5344 5345/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 5346/// altivec comparison. If it is, return true and fill in Opc/isDot with 5347/// information about the intrinsic. 5348static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, 5349 bool &isDot) { 5350 unsigned IntrinsicID = 5351 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue(); 5352 CompareOpc = -1; 5353 isDot = false; 5354 switch (IntrinsicID) { 5355 default: return false; 5356 // Comparison predicates. 5357 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 5358 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 5359 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 5360 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 5361 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 5362 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 5363 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 5364 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 5365 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 5366 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 5367 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 5368 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 5369 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 5370 5371 // Normal Comparisons. 5372 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 5373 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 5374 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 5375 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 5376 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 5377 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 5378 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 5379 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 5380 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 5381 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 5382 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 5383 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 5384 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 5385 } 5386 return true; 5387} 5388 5389/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 5390/// lower, do it, otherwise return null. 5391SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 5392 SelectionDAG &DAG) const { 5393 // If this is a lowered altivec predicate compare, CompareOpc is set to the 5394 // opcode number of the comparison. 5395 DebugLoc dl = Op.getDebugLoc(); 5396 int CompareOpc; 5397 bool isDot; 5398 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 5399 return SDValue(); // Don't custom lower most intrinsics. 5400 5401 // If this is a non-dot comparison, make the VCMP node and we are done. 5402 if (!isDot) { 5403 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), 5404 Op.getOperand(1), Op.getOperand(2), 5405 DAG.getConstant(CompareOpc, MVT::i32)); 5406 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp); 5407 } 5408 5409 // Create the PPCISD altivec 'dot' comparison node. 5410 SDValue Ops[] = { 5411 Op.getOperand(2), // LHS 5412 Op.getOperand(3), // RHS 5413 DAG.getConstant(CompareOpc, MVT::i32) 5414 }; 5415 std::vector<EVT> VTs; 5416 VTs.push_back(Op.getOperand(2).getValueType()); 5417 VTs.push_back(MVT::Glue); 5418 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 5419 5420 // Now that we have the comparison, emit a copy from the CR to a GPR. 5421 // This is flagged to the above dot comparison. 5422 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32, 5423 DAG.getRegister(PPC::CR6, MVT::i32), 5424 CompNode.getValue(1)); 5425 5426 // Unpack the result based on how the target uses it. 5427 unsigned BitNo; // Bit # of CR6. 5428 bool InvertBit; // Invert result? 5429 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) { 5430 default: // Can't happen, don't crash on invalid number though. 5431 case 0: // Return the value of the EQ bit of CR6. 5432 BitNo = 0; InvertBit = false; 5433 break; 5434 case 1: // Return the inverted value of the EQ bit of CR6. 5435 BitNo = 0; InvertBit = true; 5436 break; 5437 case 2: // Return the value of the LT bit of CR6. 5438 BitNo = 2; InvertBit = false; 5439 break; 5440 case 3: // Return the inverted value of the LT bit of CR6. 5441 BitNo = 2; InvertBit = true; 5442 break; 5443 } 5444 5445 // Shift the bit into the low position. 5446 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, 5447 DAG.getConstant(8-(3-BitNo), MVT::i32)); 5448 // Isolate the bit. 5449 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, 5450 DAG.getConstant(1, MVT::i32)); 5451 5452 // If we are supposed to, toggle the bit. 5453 if (InvertBit) 5454 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, 5455 DAG.getConstant(1, MVT::i32)); 5456 return Flags; 5457} 5458 5459SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, 5460 SelectionDAG &DAG) const { 5461 DebugLoc dl = Op.getDebugLoc(); 5462 // Create a stack slot that is 16-byte aligned. 5463 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 5464 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false); 5465 EVT PtrVT = getPointerTy(); 5466 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 5467 5468 // Store the input value into Value#0 of the stack slot. 5469 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 5470 Op.getOperand(0), FIdx, MachinePointerInfo(), 5471 false, false, 0); 5472 // Load it out. 5473 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(), 5474 false, false, false, 0); 5475} 5476 5477SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 5478 DebugLoc dl = Op.getDebugLoc(); 5479 if (Op.getValueType() == MVT::v4i32) { 5480 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 5481 5482 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); 5483 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. 5484 5485 SDValue RHSSwap = // = vrlw RHS, 16 5486 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); 5487 5488 // Shrinkify inputs to v8i16. 5489 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS); 5490 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS); 5491 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap); 5492 5493 // Low parts multiplied together, generating 32-bit results (we ignore the 5494 // top parts). 5495 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 5496 LHS, RHS, DAG, dl, MVT::v4i32); 5497 5498 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 5499 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); 5500 // Shift the high parts up 16 bits. 5501 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, 5502 Neg16, DAG, dl); 5503 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); 5504 } else if (Op.getValueType() == MVT::v8i16) { 5505 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 5506 5507 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); 5508 5509 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 5510 LHS, RHS, Zero, DAG, dl); 5511 } else if (Op.getValueType() == MVT::v16i8) { 5512 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 5513 5514 // Multiply the even 8-bit parts, producing 16-bit sums. 5515 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 5516 LHS, RHS, DAG, dl, MVT::v8i16); 5517 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts); 5518 5519 // Multiply the odd 8-bit parts, producing 16-bit sums. 5520 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 5521 LHS, RHS, DAG, dl, MVT::v8i16); 5522 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts); 5523 5524 // Merge the results together. 5525 int Ops[16]; 5526 for (unsigned i = 0; i != 8; ++i) { 5527 Ops[i*2 ] = 2*i+1; 5528 Ops[i*2+1] = 2*i+1+16; 5529 } 5530 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); 5531 } else { 5532 llvm_unreachable("Unknown mul to lower!"); 5533 } 5534} 5535 5536/// LowerOperation - Provide custom lowering hooks for some operations. 5537/// 5538SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 5539 switch (Op.getOpcode()) { 5540 default: llvm_unreachable("Wasn't expecting to be able to lower this!"); 5541 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 5542 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 5543 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 5544 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 5545 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 5546 case ISD::SETCC: return LowerSETCC(Op, DAG); 5547 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 5548 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 5549 case ISD::VASTART: 5550 return LowerVASTART(Op, DAG, PPCSubTarget); 5551 5552 case ISD::VAARG: 5553 return LowerVAARG(Op, DAG, PPCSubTarget); 5554 5555 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 5556 case ISD::DYNAMIC_STACKALLOC: 5557 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 5558 5559 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 5560 case ISD::FP_TO_UINT: 5561 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, 5562 Op.getDebugLoc()); 5563 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 5564 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 5565 5566 // Lower 64-bit shifts. 5567 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 5568 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 5569 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 5570 5571 // Vector-related lowering. 5572 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 5573 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 5574 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 5575 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 5576 case ISD::MUL: return LowerMUL(Op, DAG); 5577 5578 // Frame & Return address. 5579 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 5580 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 5581 } 5582} 5583 5584void PPCTargetLowering::ReplaceNodeResults(SDNode *N, 5585 SmallVectorImpl<SDValue>&Results, 5586 SelectionDAG &DAG) const { 5587 const TargetMachine &TM = getTargetMachine(); 5588 DebugLoc dl = N->getDebugLoc(); 5589 switch (N->getOpcode()) { 5590 default: 5591 llvm_unreachable("Do not know how to custom type legalize this operation!"); 5592 case ISD::VAARG: { 5593 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI() 5594 || TM.getSubtarget<PPCSubtarget>().isPPC64()) 5595 return; 5596 5597 EVT VT = N->getValueType(0); 5598 5599 if (VT == MVT::i64) { 5600 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget); 5601 5602 Results.push_back(NewNode); 5603 Results.push_back(NewNode.getValue(1)); 5604 } 5605 return; 5606 } 5607 case ISD::FP_ROUND_INREG: { 5608 assert(N->getValueType(0) == MVT::ppcf128); 5609 assert(N->getOperand(0).getValueType() == MVT::ppcf128); 5610 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 5611 MVT::f64, N->getOperand(0), 5612 DAG.getIntPtrConstant(0)); 5613 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 5614 MVT::f64, N->getOperand(0), 5615 DAG.getIntPtrConstant(1)); 5616 5617 // This sequence changes FPSCR to do round-to-zero, adds the two halves 5618 // of the long double, and puts FPSCR back the way it was. We do not 5619 // actually model FPSCR. 5620 std::vector<EVT> NodeTys; 5621 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg; 5622 5623 NodeTys.push_back(MVT::f64); // Return register 5624 NodeTys.push_back(MVT::Glue); // Returns a flag for later insns 5625 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 5626 MFFSreg = Result.getValue(0); 5627 InFlag = Result.getValue(1); 5628 5629 NodeTys.clear(); 5630 NodeTys.push_back(MVT::Glue); // Returns a flag 5631 Ops[0] = DAG.getConstant(31, MVT::i32); 5632 Ops[1] = InFlag; 5633 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2); 5634 InFlag = Result.getValue(0); 5635 5636 NodeTys.clear(); 5637 NodeTys.push_back(MVT::Glue); // Returns a flag 5638 Ops[0] = DAG.getConstant(30, MVT::i32); 5639 Ops[1] = InFlag; 5640 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2); 5641 InFlag = Result.getValue(0); 5642 5643 NodeTys.clear(); 5644 NodeTys.push_back(MVT::f64); // result of add 5645 NodeTys.push_back(MVT::Glue); // Returns a flag 5646 Ops[0] = Lo; 5647 Ops[1] = Hi; 5648 Ops[2] = InFlag; 5649 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3); 5650 FPreg = Result.getValue(0); 5651 InFlag = Result.getValue(1); 5652 5653 NodeTys.clear(); 5654 NodeTys.push_back(MVT::f64); 5655 Ops[0] = DAG.getConstant(1, MVT::i32); 5656 Ops[1] = MFFSreg; 5657 Ops[2] = FPreg; 5658 Ops[3] = InFlag; 5659 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4); 5660 FPreg = Result.getValue(0); 5661 5662 // We know the low half is about to be thrown away, so just use something 5663 // convenient. 5664 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, 5665 FPreg, FPreg)); 5666 return; 5667 } 5668 case ISD::FP_TO_SINT: 5669 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl)); 5670 return; 5671 } 5672} 5673 5674 5675//===----------------------------------------------------------------------===// 5676// Other Lowering Code 5677//===----------------------------------------------------------------------===// 5678 5679MachineBasicBlock * 5680PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 5681 bool is64bit, unsigned BinOpcode) const { 5682 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 5683 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5684 5685 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5686 MachineFunction *F = BB->getParent(); 5687 MachineFunction::iterator It = BB; 5688 ++It; 5689 5690 unsigned dest = MI->getOperand(0).getReg(); 5691 unsigned ptrA = MI->getOperand(1).getReg(); 5692 unsigned ptrB = MI->getOperand(2).getReg(); 5693 unsigned incr = MI->getOperand(3).getReg(); 5694 DebugLoc dl = MI->getDebugLoc(); 5695 5696 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 5697 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 5698 F->insert(It, loopMBB); 5699 F->insert(It, exitMBB); 5700 exitMBB->splice(exitMBB->begin(), BB, 5701 llvm::next(MachineBasicBlock::iterator(MI)), 5702 BB->end()); 5703 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5704 5705 MachineRegisterInfo &RegInfo = F->getRegInfo(); 5706 unsigned TmpReg = (!BinOpcode) ? incr : 5707 RegInfo.createVirtualRegister( 5708 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 5709 (const TargetRegisterClass *) &PPC::GPRCRegClass); 5710 5711 // thisMBB: 5712 // ... 5713 // fallthrough --> loopMBB 5714 BB->addSuccessor(loopMBB); 5715 5716 // loopMBB: 5717 // l[wd]arx dest, ptr 5718 // add r0, dest, incr 5719 // st[wd]cx. r0, ptr 5720 // bne- loopMBB 5721 // fallthrough --> exitMBB 5722 BB = loopMBB; 5723 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 5724 .addReg(ptrA).addReg(ptrB); 5725 if (BinOpcode) 5726 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); 5727 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 5728 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); 5729 BuildMI(BB, dl, TII->get(PPC::BCC)) 5730 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 5731 BB->addSuccessor(loopMBB); 5732 BB->addSuccessor(exitMBB); 5733 5734 // exitMBB: 5735 // ... 5736 BB = exitMBB; 5737 return BB; 5738} 5739 5740MachineBasicBlock * 5741PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, 5742 MachineBasicBlock *BB, 5743 bool is8bit, // operation 5744 unsigned BinOpcode) const { 5745 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 5746 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5747 // In 64 bit mode we have to use 64 bits for addresses, even though the 5748 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address 5749 // registers without caring whether they're 32 or 64, but here we're 5750 // doing actual arithmetic on the addresses. 5751 bool is64bit = PPCSubTarget.isPPC64(); 5752 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; 5753 5754 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5755 MachineFunction *F = BB->getParent(); 5756 MachineFunction::iterator It = BB; 5757 ++It; 5758 5759 unsigned dest = MI->getOperand(0).getReg(); 5760 unsigned ptrA = MI->getOperand(1).getReg(); 5761 unsigned ptrB = MI->getOperand(2).getReg(); 5762 unsigned incr = MI->getOperand(3).getReg(); 5763 DebugLoc dl = MI->getDebugLoc(); 5764 5765 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 5766 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 5767 F->insert(It, loopMBB); 5768 F->insert(It, exitMBB); 5769 exitMBB->splice(exitMBB->begin(), BB, 5770 llvm::next(MachineBasicBlock::iterator(MI)), 5771 BB->end()); 5772 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5773 5774 MachineRegisterInfo &RegInfo = F->getRegInfo(); 5775 const TargetRegisterClass *RC = 5776 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 5777 (const TargetRegisterClass *) &PPC::GPRCRegClass; 5778 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 5779 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 5780 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 5781 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC); 5782 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 5783 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 5784 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 5785 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 5786 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC); 5787 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 5788 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 5789 unsigned Ptr1Reg; 5790 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); 5791 5792 // thisMBB: 5793 // ... 5794 // fallthrough --> loopMBB 5795 BB->addSuccessor(loopMBB); 5796 5797 // The 4-byte load must be aligned, while a char or short may be 5798 // anywhere in the word. Hence all this nasty bookkeeping code. 5799 // add ptr1, ptrA, ptrB [copy if ptrA==0] 5800 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 5801 // xori shift, shift1, 24 [16] 5802 // rlwinm ptr, ptr1, 0, 0, 29 5803 // slw incr2, incr, shift 5804 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 5805 // slw mask, mask2, shift 5806 // loopMBB: 5807 // lwarx tmpDest, ptr 5808 // add tmp, tmpDest, incr2 5809 // andc tmp2, tmpDest, mask 5810 // and tmp3, tmp, mask 5811 // or tmp4, tmp3, tmp2 5812 // stwcx. tmp4, ptr 5813 // bne- loopMBB 5814 // fallthrough --> exitMBB 5815 // srw dest, tmpDest, shift 5816 if (ptrA != ZeroReg) { 5817 Ptr1Reg = RegInfo.createVirtualRegister(RC); 5818 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 5819 .addReg(ptrA).addReg(ptrB); 5820 } else { 5821 Ptr1Reg = ptrB; 5822 } 5823 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 5824 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 5825 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 5826 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 5827 if (is64bit) 5828 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 5829 .addReg(Ptr1Reg).addImm(0).addImm(61); 5830 else 5831 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 5832 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 5833 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg) 5834 .addReg(incr).addReg(ShiftReg); 5835 if (is8bit) 5836 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 5837 else { 5838 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 5839 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535); 5840 } 5841 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 5842 .addReg(Mask2Reg).addReg(ShiftReg); 5843 5844 BB = loopMBB; 5845 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 5846 .addReg(ZeroReg).addReg(PtrReg); 5847 if (BinOpcode) 5848 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) 5849 .addReg(Incr2Reg).addReg(TmpDestReg); 5850 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) 5851 .addReg(TmpDestReg).addReg(MaskReg); 5852 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) 5853 .addReg(TmpReg).addReg(MaskReg); 5854 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) 5855 .addReg(Tmp3Reg).addReg(Tmp2Reg); 5856 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 5857 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg); 5858 BuildMI(BB, dl, TII->get(PPC::BCC)) 5859 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 5860 BB->addSuccessor(loopMBB); 5861 BB->addSuccessor(exitMBB); 5862 5863 // exitMBB: 5864 // ... 5865 BB = exitMBB; 5866 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg) 5867 .addReg(ShiftReg); 5868 return BB; 5869} 5870 5871MachineBasicBlock * 5872PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 5873 MachineBasicBlock *BB) const { 5874 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5875 5876 // To "insert" these instructions we actually have to insert their 5877 // control-flow patterns. 5878 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5879 MachineFunction::iterator It = BB; 5880 ++It; 5881 5882 MachineFunction *F = BB->getParent(); 5883 5884 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 || 5885 MI->getOpcode() == PPC::SELECT_CC_I8)) { 5886 unsigned OpCode = MI->getOpcode() == PPC::SELECT_CC_I8 ? 5887 PPC::ISEL8 : PPC::ISEL; 5888 unsigned SelectPred = MI->getOperand(4).getImm(); 5889 DebugLoc dl = MI->getDebugLoc(); 5890 5891 // The SelectPred is ((BI << 5) | BO) for a BCC 5892 unsigned BO = SelectPred & 0xF; 5893 assert((BO == 12 || BO == 4) && "invalid predicate BO field for isel"); 5894 5895 unsigned TrueOpNo, FalseOpNo; 5896 if (BO == 12) { 5897 TrueOpNo = 2; 5898 FalseOpNo = 3; 5899 } else { 5900 TrueOpNo = 3; 5901 FalseOpNo = 2; 5902 SelectPred = PPC::InvertPredicate((PPC::Predicate)SelectPred); 5903 } 5904 5905 BuildMI(*BB, MI, dl, TII->get(OpCode), MI->getOperand(0).getReg()) 5906 .addReg(MI->getOperand(TrueOpNo).getReg()) 5907 .addReg(MI->getOperand(FalseOpNo).getReg()) 5908 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()); 5909 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 || 5910 MI->getOpcode() == PPC::SELECT_CC_I8 || 5911 MI->getOpcode() == PPC::SELECT_CC_F4 || 5912 MI->getOpcode() == PPC::SELECT_CC_F8 || 5913 MI->getOpcode() == PPC::SELECT_CC_VRRC) { 5914 5915 5916 // The incoming instruction knows the destination vreg to set, the 5917 // condition code register to branch on, the true/false values to 5918 // select between, and a branch opcode to use. 5919 5920 // thisMBB: 5921 // ... 5922 // TrueVal = ... 5923 // cmpTY ccX, r1, r2 5924 // bCC copy1MBB 5925 // fallthrough --> copy0MBB 5926 MachineBasicBlock *thisMBB = BB; 5927 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 5928 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 5929 unsigned SelectPred = MI->getOperand(4).getImm(); 5930 DebugLoc dl = MI->getDebugLoc(); 5931 F->insert(It, copy0MBB); 5932 F->insert(It, sinkMBB); 5933 5934 // Transfer the remainder of BB and its successor edges to sinkMBB. 5935 sinkMBB->splice(sinkMBB->begin(), BB, 5936 llvm::next(MachineBasicBlock::iterator(MI)), 5937 BB->end()); 5938 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 5939 5940 // Next, add the true and fallthrough blocks as its successors. 5941 BB->addSuccessor(copy0MBB); 5942 BB->addSuccessor(sinkMBB); 5943 5944 BuildMI(BB, dl, TII->get(PPC::BCC)) 5945 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 5946 5947 // copy0MBB: 5948 // %FalseValue = ... 5949 // # fallthrough to sinkMBB 5950 BB = copy0MBB; 5951 5952 // Update machine-CFG edges 5953 BB->addSuccessor(sinkMBB); 5954 5955 // sinkMBB: 5956 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 5957 // ... 5958 BB = sinkMBB; 5959 BuildMI(*BB, BB->begin(), dl, 5960 TII->get(PPC::PHI), MI->getOperand(0).getReg()) 5961 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 5962 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 5963 } 5964 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) 5965 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); 5966 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) 5967 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); 5968 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) 5969 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4); 5970 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) 5971 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8); 5972 5973 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8) 5974 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); 5975 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16) 5976 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); 5977 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32) 5978 BB = EmitAtomicBinary(MI, BB, false, PPC::AND); 5979 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64) 5980 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8); 5981 5982 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8) 5983 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); 5984 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16) 5985 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); 5986 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32) 5987 BB = EmitAtomicBinary(MI, BB, false, PPC::OR); 5988 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64) 5989 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8); 5990 5991 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) 5992 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); 5993 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) 5994 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); 5995 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) 5996 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR); 5997 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) 5998 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8); 5999 6000 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) 6001 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC); 6002 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) 6003 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC); 6004 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) 6005 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC); 6006 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) 6007 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8); 6008 6009 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) 6010 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); 6011 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) 6012 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); 6013 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) 6014 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF); 6015 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) 6016 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8); 6017 6018 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8) 6019 BB = EmitPartwordAtomicBinary(MI, BB, true, 0); 6020 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16) 6021 BB = EmitPartwordAtomicBinary(MI, BB, false, 0); 6022 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32) 6023 BB = EmitAtomicBinary(MI, BB, false, 0); 6024 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64) 6025 BB = EmitAtomicBinary(MI, BB, true, 0); 6026 6027 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || 6028 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) { 6029 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; 6030 6031 unsigned dest = MI->getOperand(0).getReg(); 6032 unsigned ptrA = MI->getOperand(1).getReg(); 6033 unsigned ptrB = MI->getOperand(2).getReg(); 6034 unsigned oldval = MI->getOperand(3).getReg(); 6035 unsigned newval = MI->getOperand(4).getReg(); 6036 DebugLoc dl = MI->getDebugLoc(); 6037 6038 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 6039 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 6040 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 6041 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 6042 F->insert(It, loop1MBB); 6043 F->insert(It, loop2MBB); 6044 F->insert(It, midMBB); 6045 F->insert(It, exitMBB); 6046 exitMBB->splice(exitMBB->begin(), BB, 6047 llvm::next(MachineBasicBlock::iterator(MI)), 6048 BB->end()); 6049 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 6050 6051 // thisMBB: 6052 // ... 6053 // fallthrough --> loopMBB 6054 BB->addSuccessor(loop1MBB); 6055 6056 // loop1MBB: 6057 // l[wd]arx dest, ptr 6058 // cmp[wd] dest, oldval 6059 // bne- midMBB 6060 // loop2MBB: 6061 // st[wd]cx. newval, ptr 6062 // bne- loopMBB 6063 // b exitBB 6064 // midMBB: 6065 // st[wd]cx. dest, ptr 6066 // exitBB: 6067 BB = loop1MBB; 6068 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 6069 .addReg(ptrA).addReg(ptrB); 6070 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) 6071 .addReg(oldval).addReg(dest); 6072 BuildMI(BB, dl, TII->get(PPC::BCC)) 6073 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 6074 BB->addSuccessor(loop2MBB); 6075 BB->addSuccessor(midMBB); 6076 6077 BB = loop2MBB; 6078 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 6079 .addReg(newval).addReg(ptrA).addReg(ptrB); 6080 BuildMI(BB, dl, TII->get(PPC::BCC)) 6081 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 6082 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 6083 BB->addSuccessor(loop1MBB); 6084 BB->addSuccessor(exitMBB); 6085 6086 BB = midMBB; 6087 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 6088 .addReg(dest).addReg(ptrA).addReg(ptrB); 6089 BB->addSuccessor(exitMBB); 6090 6091 // exitMBB: 6092 // ... 6093 BB = exitMBB; 6094 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || 6095 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { 6096 // We must use 64-bit registers for addresses when targeting 64-bit, 6097 // since we're actually doing arithmetic on them. Other registers 6098 // can be 32-bit. 6099 bool is64bit = PPCSubTarget.isPPC64(); 6100 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; 6101 6102 unsigned dest = MI->getOperand(0).getReg(); 6103 unsigned ptrA = MI->getOperand(1).getReg(); 6104 unsigned ptrB = MI->getOperand(2).getReg(); 6105 unsigned oldval = MI->getOperand(3).getReg(); 6106 unsigned newval = MI->getOperand(4).getReg(); 6107 DebugLoc dl = MI->getDebugLoc(); 6108 6109 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 6110 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 6111 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 6112 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 6113 F->insert(It, loop1MBB); 6114 F->insert(It, loop2MBB); 6115 F->insert(It, midMBB); 6116 F->insert(It, exitMBB); 6117 exitMBB->splice(exitMBB->begin(), BB, 6118 llvm::next(MachineBasicBlock::iterator(MI)), 6119 BB->end()); 6120 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 6121 6122 MachineRegisterInfo &RegInfo = F->getRegInfo(); 6123 const TargetRegisterClass *RC = 6124 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 6125 (const TargetRegisterClass *) &PPC::GPRCRegClass; 6126 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 6127 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 6128 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 6129 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC); 6130 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC); 6131 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC); 6132 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC); 6133 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 6134 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 6135 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 6136 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 6137 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 6138 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 6139 unsigned Ptr1Reg; 6140 unsigned TmpReg = RegInfo.createVirtualRegister(RC); 6141 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; 6142 // thisMBB: 6143 // ... 6144 // fallthrough --> loopMBB 6145 BB->addSuccessor(loop1MBB); 6146 6147 // The 4-byte load must be aligned, while a char or short may be 6148 // anywhere in the word. Hence all this nasty bookkeeping code. 6149 // add ptr1, ptrA, ptrB [copy if ptrA==0] 6150 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 6151 // xori shift, shift1, 24 [16] 6152 // rlwinm ptr, ptr1, 0, 0, 29 6153 // slw newval2, newval, shift 6154 // slw oldval2, oldval,shift 6155 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 6156 // slw mask, mask2, shift 6157 // and newval3, newval2, mask 6158 // and oldval3, oldval2, mask 6159 // loop1MBB: 6160 // lwarx tmpDest, ptr 6161 // and tmp, tmpDest, mask 6162 // cmpw tmp, oldval3 6163 // bne- midMBB 6164 // loop2MBB: 6165 // andc tmp2, tmpDest, mask 6166 // or tmp4, tmp2, newval3 6167 // stwcx. tmp4, ptr 6168 // bne- loop1MBB 6169 // b exitBB 6170 // midMBB: 6171 // stwcx. tmpDest, ptr 6172 // exitBB: 6173 // srw dest, tmpDest, shift 6174 if (ptrA != ZeroReg) { 6175 Ptr1Reg = RegInfo.createVirtualRegister(RC); 6176 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 6177 .addReg(ptrA).addReg(ptrB); 6178 } else { 6179 Ptr1Reg = ptrB; 6180 } 6181 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 6182 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 6183 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 6184 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 6185 if (is64bit) 6186 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 6187 .addReg(Ptr1Reg).addImm(0).addImm(61); 6188 else 6189 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 6190 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 6191 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) 6192 .addReg(newval).addReg(ShiftReg); 6193 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) 6194 .addReg(oldval).addReg(ShiftReg); 6195 if (is8bit) 6196 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 6197 else { 6198 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 6199 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) 6200 .addReg(Mask3Reg).addImm(65535); 6201 } 6202 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 6203 .addReg(Mask2Reg).addReg(ShiftReg); 6204 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg) 6205 .addReg(NewVal2Reg).addReg(MaskReg); 6206 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg) 6207 .addReg(OldVal2Reg).addReg(MaskReg); 6208 6209 BB = loop1MBB; 6210 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 6211 .addReg(ZeroReg).addReg(PtrReg); 6212 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) 6213 .addReg(TmpDestReg).addReg(MaskReg); 6214 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0) 6215 .addReg(TmpReg).addReg(OldVal3Reg); 6216 BuildMI(BB, dl, TII->get(PPC::BCC)) 6217 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 6218 BB->addSuccessor(loop2MBB); 6219 BB->addSuccessor(midMBB); 6220 6221 BB = loop2MBB; 6222 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg) 6223 .addReg(TmpDestReg).addReg(MaskReg); 6224 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg) 6225 .addReg(Tmp2Reg).addReg(NewVal3Reg); 6226 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg) 6227 .addReg(ZeroReg).addReg(PtrReg); 6228 BuildMI(BB, dl, TII->get(PPC::BCC)) 6229 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 6230 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 6231 BB->addSuccessor(loop1MBB); 6232 BB->addSuccessor(exitMBB); 6233 6234 BB = midMBB; 6235 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg) 6236 .addReg(ZeroReg).addReg(PtrReg); 6237 BB->addSuccessor(exitMBB); 6238 6239 // exitMBB: 6240 // ... 6241 BB = exitMBB; 6242 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg) 6243 .addReg(ShiftReg); 6244 } else { 6245 llvm_unreachable("Unexpected instr type to insert"); 6246 } 6247 6248 MI->eraseFromParent(); // The pseudo instruction is gone now. 6249 return BB; 6250} 6251 6252//===----------------------------------------------------------------------===// 6253// Target Optimization Hooks 6254//===----------------------------------------------------------------------===// 6255 6256SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, 6257 DAGCombinerInfo &DCI) const { 6258 const TargetMachine &TM = getTargetMachine(); 6259 SelectionDAG &DAG = DCI.DAG; 6260 DebugLoc dl = N->getDebugLoc(); 6261 switch (N->getOpcode()) { 6262 default: break; 6263 case PPCISD::SHL: 6264 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 6265 if (C->isNullValue()) // 0 << V -> 0. 6266 return N->getOperand(0); 6267 } 6268 break; 6269 case PPCISD::SRL: 6270 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 6271 if (C->isNullValue()) // 0 >>u V -> 0. 6272 return N->getOperand(0); 6273 } 6274 break; 6275 case PPCISD::SRA: 6276 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 6277 if (C->isNullValue() || // 0 >>s V -> 0. 6278 C->isAllOnesValue()) // -1 >>s V -> -1. 6279 return N->getOperand(0); 6280 } 6281 break; 6282 6283 case ISD::SINT_TO_FP: 6284 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 6285 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 6286 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 6287 // We allow the src/dst to be either f32/f64, but the intermediate 6288 // type must be i64. 6289 if (N->getOperand(0).getValueType() == MVT::i64 && 6290 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 6291 SDValue Val = N->getOperand(0).getOperand(0); 6292 if (Val.getValueType() == MVT::f32) { 6293 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 6294 DCI.AddToWorklist(Val.getNode()); 6295 } 6296 6297 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val); 6298 DCI.AddToWorklist(Val.getNode()); 6299 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val); 6300 DCI.AddToWorklist(Val.getNode()); 6301 if (N->getValueType(0) == MVT::f32) { 6302 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val, 6303 DAG.getIntPtrConstant(0)); 6304 DCI.AddToWorklist(Val.getNode()); 6305 } 6306 return Val; 6307 } else if (N->getOperand(0).getValueType() == MVT::i32) { 6308 // If the intermediate type is i32, we can avoid the load/store here 6309 // too. 6310 } 6311 } 6312 } 6313 break; 6314 case ISD::STORE: 6315 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 6316 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 6317 !cast<StoreSDNode>(N)->isTruncatingStore() && 6318 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 6319 N->getOperand(1).getValueType() == MVT::i32 && 6320 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 6321 SDValue Val = N->getOperand(1).getOperand(0); 6322 if (Val.getValueType() == MVT::f32) { 6323 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 6324 DCI.AddToWorklist(Val.getNode()); 6325 } 6326 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); 6327 DCI.AddToWorklist(Val.getNode()); 6328 6329 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val, 6330 N->getOperand(2), N->getOperand(3)); 6331 DCI.AddToWorklist(Val.getNode()); 6332 return Val; 6333 } 6334 6335 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 6336 if (cast<StoreSDNode>(N)->isUnindexed() && 6337 N->getOperand(1).getOpcode() == ISD::BSWAP && 6338 N->getOperand(1).getNode()->hasOneUse() && 6339 (N->getOperand(1).getValueType() == MVT::i32 || 6340 N->getOperand(1).getValueType() == MVT::i16)) { 6341 SDValue BSwapOp = N->getOperand(1).getOperand(0); 6342 // Do an any-extend to 32-bits if this is a half-word input. 6343 if (BSwapOp.getValueType() == MVT::i16) 6344 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); 6345 6346 SDValue Ops[] = { 6347 N->getOperand(0), BSwapOp, N->getOperand(2), 6348 DAG.getValueType(N->getOperand(1).getValueType()) 6349 }; 6350 return 6351 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), 6352 Ops, array_lengthof(Ops), 6353 cast<StoreSDNode>(N)->getMemoryVT(), 6354 cast<StoreSDNode>(N)->getMemOperand()); 6355 } 6356 break; 6357 case ISD::BSWAP: 6358 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 6359 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) && 6360 N->getOperand(0).hasOneUse() && 6361 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 6362 SDValue Load = N->getOperand(0); 6363 LoadSDNode *LD = cast<LoadSDNode>(Load); 6364 // Create the byte-swapping load. 6365 SDValue Ops[] = { 6366 LD->getChain(), // Chain 6367 LD->getBasePtr(), // Ptr 6368 DAG.getValueType(N->getValueType(0)) // VT 6369 }; 6370 SDValue BSLoad = 6371 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl, 6372 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3, 6373 LD->getMemoryVT(), LD->getMemOperand()); 6374 6375 // If this is an i16 load, insert the truncate. 6376 SDValue ResVal = BSLoad; 6377 if (N->getValueType(0) == MVT::i16) 6378 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); 6379 6380 // First, combine the bswap away. This makes the value produced by the 6381 // load dead. 6382 DCI.CombineTo(N, ResVal); 6383 6384 // Next, combine the load away, we give it a bogus result value but a real 6385 // chain result. The result value is dead because the bswap is dead. 6386 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1)); 6387 6388 // Return N so it doesn't get rechecked! 6389 return SDValue(N, 0); 6390 } 6391 6392 break; 6393 case PPCISD::VCMP: { 6394 // If a VCMPo node already exists with exactly the same operands as this 6395 // node, use its result instead of this node (VCMPo computes both a CR6 and 6396 // a normal output). 6397 // 6398 if (!N->getOperand(0).hasOneUse() && 6399 !N->getOperand(1).hasOneUse() && 6400 !N->getOperand(2).hasOneUse()) { 6401 6402 // Scan all of the users of the LHS, looking for VCMPo's that match. 6403 SDNode *VCMPoNode = 0; 6404 6405 SDNode *LHSN = N->getOperand(0).getNode(); 6406 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 6407 UI != E; ++UI) 6408 if (UI->getOpcode() == PPCISD::VCMPo && 6409 UI->getOperand(1) == N->getOperand(1) && 6410 UI->getOperand(2) == N->getOperand(2) && 6411 UI->getOperand(0) == N->getOperand(0)) { 6412 VCMPoNode = *UI; 6413 break; 6414 } 6415 6416 // If there is no VCMPo node, or if the flag value has a single use, don't 6417 // transform this. 6418 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 6419 break; 6420 6421 // Look at the (necessarily single) use of the flag value. If it has a 6422 // chain, this transformation is more complex. Note that multiple things 6423 // could use the value result, which we should ignore. 6424 SDNode *FlagUser = 0; 6425 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 6426 FlagUser == 0; ++UI) { 6427 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 6428 SDNode *User = *UI; 6429 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 6430 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) { 6431 FlagUser = User; 6432 break; 6433 } 6434 } 6435 } 6436 6437 // If the user is a MFCR instruction, we know this is safe. Otherwise we 6438 // give up for right now. 6439 if (FlagUser->getOpcode() == PPCISD::MFCR) 6440 return SDValue(VCMPoNode, 0); 6441 } 6442 break; 6443 } 6444 case ISD::BR_CC: { 6445 // If this is a branch on an altivec predicate comparison, lower this so 6446 // that we don't have to do a MFCR: instead, branch directly on CR6. This 6447 // lowering is done pre-legalize, because the legalizer lowers the predicate 6448 // compare down to code that is difficult to reassemble. 6449 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 6450 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 6451 int CompareOpc; 6452 bool isDot; 6453 6454 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 6455 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 6456 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 6457 assert(isDot && "Can't compare against a vector result!"); 6458 6459 // If this is a comparison against something other than 0/1, then we know 6460 // that the condition is never/always true. 6461 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue(); 6462 if (Val != 0 && Val != 1) { 6463 if (CC == ISD::SETEQ) // Cond never true, remove branch. 6464 return N->getOperand(0); 6465 // Always !=, turn it into an unconditional branch. 6466 return DAG.getNode(ISD::BR, dl, MVT::Other, 6467 N->getOperand(0), N->getOperand(4)); 6468 } 6469 6470 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 6471 6472 // Create the PPCISD altivec 'dot' comparison node. 6473 std::vector<EVT> VTs; 6474 SDValue Ops[] = { 6475 LHS.getOperand(2), // LHS of compare 6476 LHS.getOperand(3), // RHS of compare 6477 DAG.getConstant(CompareOpc, MVT::i32) 6478 }; 6479 VTs.push_back(LHS.getOperand(2).getValueType()); 6480 VTs.push_back(MVT::Glue); 6481 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 6482 6483 // Unpack the result based on how the target uses it. 6484 PPC::Predicate CompOpc; 6485 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) { 6486 default: // Can't happen, don't crash on invalid number though. 6487 case 0: // Branch on the value of the EQ bit of CR6. 6488 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 6489 break; 6490 case 1: // Branch on the inverted value of the EQ bit of CR6. 6491 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 6492 break; 6493 case 2: // Branch on the value of the LT bit of CR6. 6494 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 6495 break; 6496 case 3: // Branch on the inverted value of the LT bit of CR6. 6497 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 6498 break; 6499 } 6500 6501 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), 6502 DAG.getConstant(CompOpc, MVT::i32), 6503 DAG.getRegister(PPC::CR6, MVT::i32), 6504 N->getOperand(4), CompNode.getValue(1)); 6505 } 6506 break; 6507 } 6508 } 6509 6510 return SDValue(); 6511} 6512 6513//===----------------------------------------------------------------------===// 6514// Inline Assembly Support 6515//===----------------------------------------------------------------------===// 6516 6517void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 6518 APInt &KnownZero, 6519 APInt &KnownOne, 6520 const SelectionDAG &DAG, 6521 unsigned Depth) const { 6522 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); 6523 switch (Op.getOpcode()) { 6524 default: break; 6525 case PPCISD::LBRX: { 6526 // lhbrx is known to have the top bits cleared out. 6527 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) 6528 KnownZero = 0xFFFF0000; 6529 break; 6530 } 6531 case ISD::INTRINSIC_WO_CHAIN: { 6532 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) { 6533 default: break; 6534 case Intrinsic::ppc_altivec_vcmpbfp_p: 6535 case Intrinsic::ppc_altivec_vcmpeqfp_p: 6536 case Intrinsic::ppc_altivec_vcmpequb_p: 6537 case Intrinsic::ppc_altivec_vcmpequh_p: 6538 case Intrinsic::ppc_altivec_vcmpequw_p: 6539 case Intrinsic::ppc_altivec_vcmpgefp_p: 6540 case Intrinsic::ppc_altivec_vcmpgtfp_p: 6541 case Intrinsic::ppc_altivec_vcmpgtsb_p: 6542 case Intrinsic::ppc_altivec_vcmpgtsh_p: 6543 case Intrinsic::ppc_altivec_vcmpgtsw_p: 6544 case Intrinsic::ppc_altivec_vcmpgtub_p: 6545 case Intrinsic::ppc_altivec_vcmpgtuh_p: 6546 case Intrinsic::ppc_altivec_vcmpgtuw_p: 6547 KnownZero = ~1U; // All bits but the low one are known to be zero. 6548 break; 6549 } 6550 } 6551 } 6552} 6553 6554 6555/// getConstraintType - Given a constraint, return the type of 6556/// constraint it is for this target. 6557PPCTargetLowering::ConstraintType 6558PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 6559 if (Constraint.size() == 1) { 6560 switch (Constraint[0]) { 6561 default: break; 6562 case 'b': 6563 case 'r': 6564 case 'f': 6565 case 'v': 6566 case 'y': 6567 return C_RegisterClass; 6568 case 'Z': 6569 // FIXME: While Z does indicate a memory constraint, it specifically 6570 // indicates an r+r address (used in conjunction with the 'y' modifier 6571 // in the replacement string). Currently, we're forcing the base 6572 // register to be r0 in the asm printer (which is interpreted as zero) 6573 // and forming the complete address in the second register. This is 6574 // suboptimal. 6575 return C_Memory; 6576 } 6577 } 6578 return TargetLowering::getConstraintType(Constraint); 6579} 6580 6581/// Examine constraint type and operand type and determine a weight value. 6582/// This object must already have been set up with the operand type 6583/// and the current alternative constraint selected. 6584TargetLowering::ConstraintWeight 6585PPCTargetLowering::getSingleConstraintMatchWeight( 6586 AsmOperandInfo &info, const char *constraint) const { 6587 ConstraintWeight weight = CW_Invalid; 6588 Value *CallOperandVal = info.CallOperandVal; 6589 // If we don't have a value, we can't do a match, 6590 // but allow it at the lowest weight. 6591 if (CallOperandVal == NULL) 6592 return CW_Default; 6593 Type *type = CallOperandVal->getType(); 6594 // Look at the constraint type. 6595 switch (*constraint) { 6596 default: 6597 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 6598 break; 6599 case 'b': 6600 if (type->isIntegerTy()) 6601 weight = CW_Register; 6602 break; 6603 case 'f': 6604 if (type->isFloatTy()) 6605 weight = CW_Register; 6606 break; 6607 case 'd': 6608 if (type->isDoubleTy()) 6609 weight = CW_Register; 6610 break; 6611 case 'v': 6612 if (type->isVectorTy()) 6613 weight = CW_Register; 6614 break; 6615 case 'y': 6616 weight = CW_Register; 6617 break; 6618 case 'Z': 6619 weight = CW_Memory; 6620 break; 6621 } 6622 return weight; 6623} 6624 6625std::pair<unsigned, const TargetRegisterClass*> 6626PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 6627 EVT VT) const { 6628 if (Constraint.size() == 1) { 6629 // GCC RS6000 Constraint Letters 6630 switch (Constraint[0]) { 6631 case 'b': // R1-R31 6632 case 'r': // R0-R31 6633 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 6634 return std::make_pair(0U, &PPC::G8RCRegClass); 6635 return std::make_pair(0U, &PPC::GPRCRegClass); 6636 case 'f': 6637 if (VT == MVT::f32 || VT == MVT::i32) 6638 return std::make_pair(0U, &PPC::F4RCRegClass); 6639 if (VT == MVT::f64 || VT == MVT::i64) 6640 return std::make_pair(0U, &PPC::F8RCRegClass); 6641 break; 6642 case 'v': 6643 return std::make_pair(0U, &PPC::VRRCRegClass); 6644 case 'y': // crrc 6645 return std::make_pair(0U, &PPC::CRRCRegClass); 6646 } 6647 } 6648 6649 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 6650} 6651 6652 6653/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 6654/// vector. If it is invalid, don't add anything to Ops. 6655void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 6656 std::string &Constraint, 6657 std::vector<SDValue>&Ops, 6658 SelectionDAG &DAG) const { 6659 SDValue Result(0,0); 6660 6661 // Only support length 1 constraints. 6662 if (Constraint.length() > 1) return; 6663 6664 char Letter = Constraint[0]; 6665 switch (Letter) { 6666 default: break; 6667 case 'I': 6668 case 'J': 6669 case 'K': 6670 case 'L': 6671 case 'M': 6672 case 'N': 6673 case 'O': 6674 case 'P': { 6675 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 6676 if (!CST) return; // Must be an immediate to match. 6677 unsigned Value = CST->getZExtValue(); 6678 switch (Letter) { 6679 default: llvm_unreachable("Unknown constraint letter!"); 6680 case 'I': // "I" is a signed 16-bit constant. 6681 if ((short)Value == (int)Value) 6682 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6683 break; 6684 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 6685 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 6686 if ((short)Value == 0) 6687 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6688 break; 6689 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 6690 if ((Value >> 16) == 0) 6691 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6692 break; 6693 case 'M': // "M" is a constant that is greater than 31. 6694 if (Value > 31) 6695 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6696 break; 6697 case 'N': // "N" is a positive constant that is an exact power of two. 6698 if ((int)Value > 0 && isPowerOf2_32(Value)) 6699 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6700 break; 6701 case 'O': // "O" is the constant zero. 6702 if (Value == 0) 6703 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6704 break; 6705 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 6706 if ((short)-Value == (int)-Value) 6707 Result = DAG.getTargetConstant(Value, Op.getValueType()); 6708 break; 6709 } 6710 break; 6711 } 6712 } 6713 6714 if (Result.getNode()) { 6715 Ops.push_back(Result); 6716 return; 6717 } 6718 6719 // Handle standard constraint letters. 6720 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 6721} 6722 6723// isLegalAddressingMode - Return true if the addressing mode represented 6724// by AM is legal for this target, for a load/store of the specified type. 6725bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 6726 Type *Ty) const { 6727 // FIXME: PPC does not allow r+i addressing modes for vectors! 6728 6729 // PPC allows a sign-extended 16-bit immediate field. 6730 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 6731 return false; 6732 6733 // No global is ever allowed as a base. 6734 if (AM.BaseGV) 6735 return false; 6736 6737 // PPC only support r+r, 6738 switch (AM.Scale) { 6739 case 0: // "r+i" or just "i", depending on HasBaseReg. 6740 break; 6741 case 1: 6742 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 6743 return false; 6744 // Otherwise we have r+r or r+i. 6745 break; 6746 case 2: 6747 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 6748 return false; 6749 // Allow 2*r as r+r. 6750 break; 6751 default: 6752 // No other scales are supported. 6753 return false; 6754 } 6755 6756 return true; 6757} 6758 6759/// isLegalAddressImmediate - Return true if the integer value can be used 6760/// as the offset of the target addressing mode for load / store of the 6761/// given type. 6762bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{ 6763 // PPC allows a sign-extended 16-bit immediate field. 6764 return (V > -(1 << 16) && V < (1 << 16)-1); 6765} 6766 6767bool PPCTargetLowering::isLegalAddressImmediate(GlobalValue* GV) const { 6768 return false; 6769} 6770 6771SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, 6772 SelectionDAG &DAG) const { 6773 MachineFunction &MF = DAG.getMachineFunction(); 6774 MachineFrameInfo *MFI = MF.getFrameInfo(); 6775 MFI->setReturnAddressIsTaken(true); 6776 6777 DebugLoc dl = Op.getDebugLoc(); 6778 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6779 6780 // Make sure the function does not optimize away the store of the RA to 6781 // the stack. 6782 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 6783 FuncInfo->setLRStoreRequired(); 6784 bool isPPC64 = PPCSubTarget.isPPC64(); 6785 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 6786 6787 if (Depth > 0) { 6788 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 6789 SDValue Offset = 6790 6791 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI), 6792 isPPC64? MVT::i64 : MVT::i32); 6793 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 6794 DAG.getNode(ISD::ADD, dl, getPointerTy(), 6795 FrameAddr, Offset), 6796 MachinePointerInfo(), false, false, false, 0); 6797 } 6798 6799 // Just load the return address off the stack. 6800 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); 6801 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 6802 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 6803} 6804 6805SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, 6806 SelectionDAG &DAG) const { 6807 DebugLoc dl = Op.getDebugLoc(); 6808 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6809 6810 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 6811 bool isPPC64 = PtrVT == MVT::i64; 6812 6813 MachineFunction &MF = DAG.getMachineFunction(); 6814 MachineFrameInfo *MFI = MF.getFrameInfo(); 6815 MFI->setFrameAddressIsTaken(true); 6816 bool is31 = (getTargetMachine().Options.DisableFramePointerElim(MF) || 6817 MFI->hasVarSizedObjects()) && 6818 MFI->getStackSize() && 6819 !MF.getFunction()->getFnAttributes(). 6820 hasAttribute(Attributes::Naked); 6821 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) : 6822 (is31 ? PPC::R31 : PPC::R1); 6823 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, 6824 PtrVT); 6825 while (Depth--) 6826 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(), 6827 FrameAddr, MachinePointerInfo(), false, false, 6828 false, 0); 6829 return FrameAddr; 6830} 6831 6832bool 6833PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 6834 // The PowerPC target isn't yet aware of offsets. 6835 return false; 6836} 6837 6838/// getOptimalMemOpType - Returns the target specific optimal type for load 6839/// and store operations as a result of memset, memcpy, and memmove 6840/// lowering. If DstAlign is zero that means it's safe to destination 6841/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 6842/// means there isn't a need to check it against alignment requirement, 6843/// probably because the source does not need to be loaded. If 'IsMemset' is 6844/// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 6845/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 6846/// source is constant so it does not need to be loaded. 6847/// It returns EVT::Other if the type should be determined using generic 6848/// target-independent logic. 6849EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, 6850 unsigned DstAlign, unsigned SrcAlign, 6851 bool IsMemset, bool ZeroMemset, 6852 bool MemcpyStrSrc, 6853 MachineFunction &MF) const { 6854 if (this->PPCSubTarget.isPPC64()) { 6855 return MVT::i64; 6856 } else { 6857 return MVT::i32; 6858 } 6859} 6860 6861/// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than 6862/// a pair of mul and add instructions. fmuladd intrinsics will be expanded to 6863/// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd 6864/// is expanded to mul + add. 6865bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const { 6866 if (!VT.isSimple()) 6867 return false; 6868 6869 switch (VT.getSimpleVT().SimpleTy) { 6870 case MVT::f32: 6871 case MVT::f64: 6872 case MVT::v4f32: 6873 return true; 6874 default: 6875 break; 6876 } 6877 6878 return false; 6879} 6880 6881Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const { 6882 if (DisableILPPref) 6883 return TargetLowering::getSchedulingPreference(N); 6884 6885 return Sched::ILP; 6886} 6887 6888