PPCISelLowering.cpp revision e754d3fb852abdeaf910c7331eed60f6303597c1
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPerfectShuffle.h" 17#include "PPCPredicates.h" 18#include "PPCTargetMachine.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/ADT/VectorExtras.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 29#include "llvm/CallingConv.h" 30#include "llvm/Constants.h" 31#include "llvm/Function.h" 32#include "llvm/Intrinsics.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Target/TargetOptions.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38#include "llvm/DerivedTypes.h" 39using namespace llvm; 40 41static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 42 CCValAssign::LocInfo &LocInfo, 43 ISD::ArgFlagsTy &ArgFlags, 44 CCState &State); 45static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT, 46 EVT &LocVT, 47 CCValAssign::LocInfo &LocInfo, 48 ISD::ArgFlagsTy &ArgFlags, 49 CCState &State); 50static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT, 51 EVT &LocVT, 52 CCValAssign::LocInfo &LocInfo, 53 ISD::ArgFlagsTy &ArgFlags, 54 CCState &State); 55 56static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", 57cl::desc("enable preincrement load/store generation on PPC (experimental)"), 58 cl::Hidden); 59 60static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) { 61 if (TM.getSubtargetImpl()->isDarwin()) 62 return new TargetLoweringObjectFileMachO(); 63 64 return new TargetLoweringObjectFileELF(); 65} 66 67PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) { 69 70 setPow2DivIsCheap(); 71 72 // Use _setjmp/_longjmp instead of setjmp/longjmp. 73 setUseUnderscoreSetJmp(true); 74 setUseUnderscoreLongJmp(true); 75 76 // Set up the register classes. 77 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 78 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 79 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 80 81 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 82 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 83 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 84 85 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 86 87 // PowerPC has pre-inc load and store's. 88 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 89 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 90 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 91 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 92 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 93 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 94 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 95 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 96 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 97 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 98 99 // This is used in the ppcf128->int sequence. Note it has different semantics 100 // from FP_ROUND: that rounds to nearest, this rounds to zero. 101 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 102 103 // PowerPC has no SREM/UREM instructions 104 setOperationAction(ISD::SREM, MVT::i32, Expand); 105 setOperationAction(ISD::UREM, MVT::i32, Expand); 106 setOperationAction(ISD::SREM, MVT::i64, Expand); 107 setOperationAction(ISD::UREM, MVT::i64, Expand); 108 109 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 110 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 111 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 112 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 113 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 114 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 115 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 116 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 117 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 118 119 // We don't support sin/cos/sqrt/fmod/pow 120 setOperationAction(ISD::FSIN , MVT::f64, Expand); 121 setOperationAction(ISD::FCOS , MVT::f64, Expand); 122 setOperationAction(ISD::FREM , MVT::f64, Expand); 123 setOperationAction(ISD::FPOW , MVT::f64, Expand); 124 setOperationAction(ISD::FSIN , MVT::f32, Expand); 125 setOperationAction(ISD::FCOS , MVT::f32, Expand); 126 setOperationAction(ISD::FREM , MVT::f32, Expand); 127 setOperationAction(ISD::FPOW , MVT::f32, Expand); 128 129 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 130 131 // If we're enabling GP optimizations, use hardware square root 132 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 133 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 134 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 135 } 136 137 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 138 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 139 140 // PowerPC does not have BSWAP, CTPOP or CTTZ 141 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 142 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 143 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 144 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 145 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 146 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 147 148 // PowerPC does not have ROTR 149 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 150 setOperationAction(ISD::ROTR, MVT::i64 , Expand); 151 152 // PowerPC does not have Select 153 setOperationAction(ISD::SELECT, MVT::i32, Expand); 154 setOperationAction(ISD::SELECT, MVT::i64, Expand); 155 setOperationAction(ISD::SELECT, MVT::f32, Expand); 156 setOperationAction(ISD::SELECT, MVT::f64, Expand); 157 158 // PowerPC wants to turn select_cc of FP into fsel when possible. 159 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 160 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 161 162 // PowerPC wants to optimize integer setcc a bit 163 setOperationAction(ISD::SETCC, MVT::i32, Custom); 164 165 // PowerPC does not have BRCOND which requires SetCC 166 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 167 168 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 169 170 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 171 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 172 173 // PowerPC does not have [U|S]INT_TO_FP 174 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 175 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 176 177 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 178 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 179 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 180 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 181 182 // We cannot sextinreg(i1). Expand to shifts. 183 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 184 185 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 186 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 187 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 188 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 189 190 191 // We want to legalize GlobalAddress and ConstantPool nodes into the 192 // appropriate instructions to materialize the address. 193 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 194 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 195 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 196 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 197 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 198 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 199 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 200 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 201 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 202 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 203 204 // TRAP is legal. 205 setOperationAction(ISD::TRAP, MVT::Other, Legal); 206 207 // TRAMPOLINE is custom lowered. 208 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 209 210 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 211 setOperationAction(ISD::VASTART , MVT::Other, Custom); 212 213 // VAARG is custom lowered with the 32-bit SVR4 ABI. 214 if ( TM.getSubtarget<PPCSubtarget>().isSVR4ABI() 215 && !TM.getSubtarget<PPCSubtarget>().isPPC64()) 216 setOperationAction(ISD::VAARG, MVT::Other, Custom); 217 else 218 setOperationAction(ISD::VAARG, MVT::Other, Expand); 219 220 // Use the default implementation. 221 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 222 setOperationAction(ISD::VAEND , MVT::Other, Expand); 223 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 224 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 225 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 226 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 227 228 // We want to custom lower some of our intrinsics. 229 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 230 231 // Comparisons that require checking two conditions. 232 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 233 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); 234 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); 235 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); 236 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); 237 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); 238 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 239 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 240 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 241 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 242 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); 243 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); 244 245 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 246 // They also have instructions for converting between i64 and fp. 247 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 248 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 249 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 250 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 251 // This is just the low 32 bits of a (signed) fp->i64 conversion. 252 // We cannot do this with Promote because i64 is not a legal type. 253 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 254 255 // FIXME: disable this lowered code. This generates 64-bit register values, 256 // and we don't model the fact that the top part is clobbered by calls. We 257 // need to flag these together so that the value isn't live across a call. 258 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 259 } else { 260 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 261 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 262 } 263 264 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 265 // 64-bit PowerPC implementations can support i64 types directly 266 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 267 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 268 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 269 // 64-bit PowerPC wants to expand i128 shifts itself. 270 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 271 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 272 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 273 } else { 274 // 32-bit PowerPC wants to expand i64 shifts itself. 275 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 276 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 277 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 278 } 279 280 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 281 // First set operation action for all vector types to expand. Then we 282 // will selectively turn on ones that can be effectively codegen'd. 283 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 284 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 285 MVT::SimpleValueType VT = (MVT::SimpleValueType)i; 286 287 // add/sub are legal for all supported vector VT's. 288 setOperationAction(ISD::ADD , VT, Legal); 289 setOperationAction(ISD::SUB , VT, Legal); 290 291 // We promote all shuffles to v16i8. 292 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 293 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 294 295 // We promote all non-typed operations to v4i32. 296 setOperationAction(ISD::AND , VT, Promote); 297 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 298 setOperationAction(ISD::OR , VT, Promote); 299 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 300 setOperationAction(ISD::XOR , VT, Promote); 301 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 302 setOperationAction(ISD::LOAD , VT, Promote); 303 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 304 setOperationAction(ISD::SELECT, VT, Promote); 305 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 306 setOperationAction(ISD::STORE, VT, Promote); 307 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 308 309 // No other operations are legal. 310 setOperationAction(ISD::MUL , VT, Expand); 311 setOperationAction(ISD::SDIV, VT, Expand); 312 setOperationAction(ISD::SREM, VT, Expand); 313 setOperationAction(ISD::UDIV, VT, Expand); 314 setOperationAction(ISD::UREM, VT, Expand); 315 setOperationAction(ISD::FDIV, VT, Expand); 316 setOperationAction(ISD::FNEG, VT, Expand); 317 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); 318 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 319 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); 320 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 321 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 322 setOperationAction(ISD::UDIVREM, VT, Expand); 323 setOperationAction(ISD::SDIVREM, VT, Expand); 324 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); 325 setOperationAction(ISD::FPOW, VT, Expand); 326 setOperationAction(ISD::CTPOP, VT, Expand); 327 setOperationAction(ISD::CTLZ, VT, Expand); 328 setOperationAction(ISD::CTTZ, VT, Expand); 329 } 330 331 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 332 // with merges, splats, etc. 333 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 334 335 setOperationAction(ISD::AND , MVT::v4i32, Legal); 336 setOperationAction(ISD::OR , MVT::v4i32, Legal); 337 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 338 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 339 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 340 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 341 342 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 343 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 344 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 345 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 346 347 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 348 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 349 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 350 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 351 352 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 353 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 354 355 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 356 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 357 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 358 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 359 } 360 361 setShiftAmountType(MVT::i32); 362 setBooleanContents(ZeroOrOneBooleanContent); 363 364 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 365 setStackPointerRegisterToSaveRestore(PPC::X1); 366 setExceptionPointerRegister(PPC::X3); 367 setExceptionSelectorRegister(PPC::X4); 368 } else { 369 setStackPointerRegisterToSaveRestore(PPC::R1); 370 setExceptionPointerRegister(PPC::R3); 371 setExceptionSelectorRegister(PPC::R4); 372 } 373 374 // We have target-specific dag combine patterns for the following nodes: 375 setTargetDAGCombine(ISD::SINT_TO_FP); 376 setTargetDAGCombine(ISD::STORE); 377 setTargetDAGCombine(ISD::BR_CC); 378 setTargetDAGCombine(ISD::BSWAP); 379 380 // Darwin long double math library functions have $LDBL128 appended. 381 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) { 382 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 383 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 384 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 385 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 386 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 387 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128"); 388 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128"); 389 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128"); 390 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128"); 391 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128"); 392 } 393 394 computeRegisterProperties(); 395} 396 397/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 398/// function arguments in the caller parameter area. 399unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const { 400 TargetMachine &TM = getTargetMachine(); 401 // Darwin passes everything on 4 byte boundary. 402 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) 403 return 4; 404 // FIXME SVR4 TBD 405 return 4; 406} 407 408const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 409 switch (Opcode) { 410 default: return 0; 411 case PPCISD::FSEL: return "PPCISD::FSEL"; 412 case PPCISD::FCFID: return "PPCISD::FCFID"; 413 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 414 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 415 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 416 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 417 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 418 case PPCISD::VPERM: return "PPCISD::VPERM"; 419 case PPCISD::Hi: return "PPCISD::Hi"; 420 case PPCISD::Lo: return "PPCISD::Lo"; 421 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY"; 422 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE"; 423 case PPCISD::LOAD: return "PPCISD::LOAD"; 424 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC"; 425 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 426 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 427 case PPCISD::SRL: return "PPCISD::SRL"; 428 case PPCISD::SRA: return "PPCISD::SRA"; 429 case PPCISD::SHL: return "PPCISD::SHL"; 430 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 431 case PPCISD::STD_32: return "PPCISD::STD_32"; 432 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4"; 433 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin"; 434 case PPCISD::NOP: return "PPCISD::NOP"; 435 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 436 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin"; 437 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4"; 438 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 439 case PPCISD::MFCR: return "PPCISD::MFCR"; 440 case PPCISD::VCMP: return "PPCISD::VCMP"; 441 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 442 case PPCISD::LBRX: return "PPCISD::LBRX"; 443 case PPCISD::STBRX: return "PPCISD::STBRX"; 444 case PPCISD::LARX: return "PPCISD::LARX"; 445 case PPCISD::STCX: return "PPCISD::STCX"; 446 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 447 case PPCISD::MFFS: return "PPCISD::MFFS"; 448 case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; 449 case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; 450 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 451 case PPCISD::MTFSF: return "PPCISD::MTFSF"; 452 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; 453 } 454} 455 456MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const { 457 return MVT::i32; 458} 459 460/// getFunctionAlignment - Return the Log2 alignment of this function. 461unsigned PPCTargetLowering::getFunctionAlignment(const Function *F) const { 462 if (getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) 463 return F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4; 464 else 465 return 2; 466} 467 468//===----------------------------------------------------------------------===// 469// Node matching predicates, for use by the tblgen matching code. 470//===----------------------------------------------------------------------===// 471 472/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 473static bool isFloatingPointZero(SDValue Op) { 474 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 475 return CFP->getValueAPF().isZero(); 476 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 477 // Maybe this has already been legalized into the constant pool? 478 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 479 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 480 return CFP->getValueAPF().isZero(); 481 } 482 return false; 483} 484 485/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 486/// true if Op is undef or if it matches the specified value. 487static bool isConstantOrUndef(int Op, int Val) { 488 return Op < 0 || Op == Val; 489} 490 491/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 492/// VPKUHUM instruction. 493bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 494 if (!isUnary) { 495 for (unsigned i = 0; i != 16; ++i) 496 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1)) 497 return false; 498 } else { 499 for (unsigned i = 0; i != 8; ++i) 500 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) || 501 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1)) 502 return false; 503 } 504 return true; 505} 506 507/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 508/// VPKUWUM instruction. 509bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 510 if (!isUnary) { 511 for (unsigned i = 0; i != 16; i += 2) 512 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 513 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3)) 514 return false; 515 } else { 516 for (unsigned i = 0; i != 8; i += 2) 517 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 518 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) || 519 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) || 520 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3)) 521 return false; 522 } 523 return true; 524} 525 526/// isVMerge - Common function, used to match vmrg* shuffles. 527/// 528static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, 529 unsigned LHSStart, unsigned RHSStart) { 530 assert(N->getValueType(0) == MVT::v16i8 && 531 "PPC only supports shuffles by bytes!"); 532 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 533 "Unsupported merge size!"); 534 535 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 536 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 537 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j), 538 LHSStart+j+i*UnitSize) || 539 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j), 540 RHSStart+j+i*UnitSize)) 541 return false; 542 } 543 return true; 544} 545 546/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 547/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 548bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 549 bool isUnary) { 550 if (!isUnary) 551 return isVMerge(N, UnitSize, 8, 24); 552 return isVMerge(N, UnitSize, 8, 8); 553} 554 555/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 556/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 557bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 558 bool isUnary) { 559 if (!isUnary) 560 return isVMerge(N, UnitSize, 0, 16); 561 return isVMerge(N, UnitSize, 0, 0); 562} 563 564 565/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 566/// amount, otherwise return -1. 567int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 568 assert(N->getValueType(0) == MVT::v16i8 && 569 "PPC only supports shuffles by bytes!"); 570 571 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 572 573 // Find the first non-undef value in the shuffle mask. 574 unsigned i; 575 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i) 576 /*search*/; 577 578 if (i == 16) return -1; // all undef. 579 580 // Otherwise, check to see if the rest of the elements are consecutively 581 // numbered from this value. 582 unsigned ShiftAmt = SVOp->getMaskElt(i); 583 if (ShiftAmt < i) return -1; 584 ShiftAmt -= i; 585 586 if (!isUnary) { 587 // Check the rest of the elements to see if they are consecutive. 588 for (++i; i != 16; ++i) 589 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) 590 return -1; 591 } else { 592 // Check the rest of the elements to see if they are consecutive. 593 for (++i; i != 16; ++i) 594 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) 595 return -1; 596 } 597 return ShiftAmt; 598} 599 600/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 601/// specifies a splat of a single element that is suitable for input to 602/// VSPLTB/VSPLTH/VSPLTW. 603bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { 604 assert(N->getValueType(0) == MVT::v16i8 && 605 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 606 607 // This is a splat operation if each element of the permute is the same, and 608 // if the value doesn't reference the second vector. 609 unsigned ElementBase = N->getMaskElt(0); 610 611 // FIXME: Handle UNDEF elements too! 612 if (ElementBase >= 16) 613 return false; 614 615 // Check that the indices are consecutive, in the case of a multi-byte element 616 // splatted with a v16i8 mask. 617 for (unsigned i = 1; i != EltSize; ++i) 618 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase)) 619 return false; 620 621 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 622 if (N->getMaskElt(i) < 0) continue; 623 for (unsigned j = 0; j != EltSize; ++j) 624 if (N->getMaskElt(i+j) != N->getMaskElt(j)) 625 return false; 626 } 627 return true; 628} 629 630/// isAllNegativeZeroVector - Returns true if all elements of build_vector 631/// are -0.0. 632bool PPC::isAllNegativeZeroVector(SDNode *N) { 633 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N); 634 635 APInt APVal, APUndef; 636 unsigned BitSize; 637 bool HasAnyUndefs; 638 639 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true)) 640 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 641 return CFP->getValueAPF().isNegZero(); 642 643 return false; 644} 645 646/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 647/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 648unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 649 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 650 assert(isSplatShuffleMask(SVOp, EltSize)); 651 return SVOp->getMaskElt(0) / EltSize; 652} 653 654/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 655/// by using a vspltis[bhw] instruction of the specified element size, return 656/// the constant being splatted. The ByteSize field indicates the number of 657/// bytes of each element [124] -> [bhw]. 658SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 659 SDValue OpVal(0, 0); 660 661 // If ByteSize of the splat is bigger than the element size of the 662 // build_vector, then we have a case where we are checking for a splat where 663 // multiple elements of the buildvector are folded together into a single 664 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 665 unsigned EltSize = 16/N->getNumOperands(); 666 if (EltSize < ByteSize) { 667 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 668 SDValue UniquedVals[4]; 669 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 670 671 // See if all of the elements in the buildvector agree across. 672 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 673 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 674 // If the element isn't a constant, bail fully out. 675 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue(); 676 677 678 if (UniquedVals[i&(Multiple-1)].getNode() == 0) 679 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 680 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 681 return SDValue(); // no match. 682 } 683 684 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 685 // either constant or undef values that are identical for each chunk. See 686 // if these chunks can form into a larger vspltis*. 687 688 // Check to see if all of the leading entries are either 0 or -1. If 689 // neither, then this won't fit into the immediate field. 690 bool LeadingZero = true; 691 bool LeadingOnes = true; 692 for (unsigned i = 0; i != Multiple-1; ++i) { 693 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs. 694 695 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 696 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 697 } 698 // Finally, check the least significant entry. 699 if (LeadingZero) { 700 if (UniquedVals[Multiple-1].getNode() == 0) 701 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 702 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue(); 703 if (Val < 16) 704 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 705 } 706 if (LeadingOnes) { 707 if (UniquedVals[Multiple-1].getNode() == 0) 708 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 709 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue(); 710 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 711 return DAG.getTargetConstant(Val, MVT::i32); 712 } 713 714 return SDValue(); 715 } 716 717 // Check to see if this buildvec has a single non-undef value in its elements. 718 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 719 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 720 if (OpVal.getNode() == 0) 721 OpVal = N->getOperand(i); 722 else if (OpVal != N->getOperand(i)) 723 return SDValue(); 724 } 725 726 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def. 727 728 unsigned ValSizeInBytes = EltSize; 729 uint64_t Value = 0; 730 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 731 Value = CN->getZExtValue(); 732 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 733 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 734 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 735 } 736 737 // If the splat value is larger than the element value, then we can never do 738 // this splat. The only case that we could fit the replicated bits into our 739 // immediate field for would be zero, and we prefer to use vxor for it. 740 if (ValSizeInBytes < ByteSize) return SDValue(); 741 742 // If the element value is larger than the splat value, cut it in half and 743 // check to see if the two halves are equal. Continue doing this until we 744 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 745 while (ValSizeInBytes > ByteSize) { 746 ValSizeInBytes >>= 1; 747 748 // If the top half equals the bottom half, we're still ok. 749 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 750 (Value & ((1 << (8*ValSizeInBytes))-1))) 751 return SDValue(); 752 } 753 754 // Properly sign extend the value. 755 int ShAmt = (4-ByteSize)*8; 756 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 757 758 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 759 if (MaskVal == 0) return SDValue(); 760 761 // Finally, if this value fits in a 5 bit sext field, return it 762 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 763 return DAG.getTargetConstant(MaskVal, MVT::i32); 764 return SDValue(); 765} 766 767//===----------------------------------------------------------------------===// 768// Addressing Mode Selection 769//===----------------------------------------------------------------------===// 770 771/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 772/// or 64-bit immediate, and if the value can be accurately represented as a 773/// sign extension from a 16-bit value. If so, this returns true and the 774/// immediate. 775static bool isIntS16Immediate(SDNode *N, short &Imm) { 776 if (N->getOpcode() != ISD::Constant) 777 return false; 778 779 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 780 if (N->getValueType(0) == MVT::i32) 781 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 782 else 783 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 784} 785static bool isIntS16Immediate(SDValue Op, short &Imm) { 786 return isIntS16Immediate(Op.getNode(), Imm); 787} 788 789 790/// SelectAddressRegReg - Given the specified addressed, check to see if it 791/// can be represented as an indexed [r+r] operation. Returns false if it 792/// can be more efficiently represented with [r+imm]. 793bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, 794 SDValue &Index, 795 SelectionDAG &DAG) const { 796 short imm = 0; 797 if (N.getOpcode() == ISD::ADD) { 798 if (isIntS16Immediate(N.getOperand(1), imm)) 799 return false; // r+i 800 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 801 return false; // r+i 802 803 Base = N.getOperand(0); 804 Index = N.getOperand(1); 805 return true; 806 } else if (N.getOpcode() == ISD::OR) { 807 if (isIntS16Immediate(N.getOperand(1), imm)) 808 return false; // r+i can fold it if we can. 809 810 // If this is an or of disjoint bitfields, we can codegen this as an add 811 // (for better address arithmetic) if the LHS and RHS of the OR are provably 812 // disjoint. 813 APInt LHSKnownZero, LHSKnownOne; 814 APInt RHSKnownZero, RHSKnownOne; 815 DAG.ComputeMaskedBits(N.getOperand(0), 816 APInt::getAllOnesValue(N.getOperand(0) 817 .getValueSizeInBits()), 818 LHSKnownZero, LHSKnownOne); 819 820 if (LHSKnownZero.getBoolValue()) { 821 DAG.ComputeMaskedBits(N.getOperand(1), 822 APInt::getAllOnesValue(N.getOperand(1) 823 .getValueSizeInBits()), 824 RHSKnownZero, RHSKnownOne); 825 // If all of the bits are known zero on the LHS or RHS, the add won't 826 // carry. 827 if (~(LHSKnownZero | RHSKnownZero) == 0) { 828 Base = N.getOperand(0); 829 Index = N.getOperand(1); 830 return true; 831 } 832 } 833 } 834 835 return false; 836} 837 838/// Returns true if the address N can be represented by a base register plus 839/// a signed 16-bit displacement [r+imm], and if it is not better 840/// represented as reg+reg. 841bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, 842 SDValue &Base, 843 SelectionDAG &DAG) const { 844 // FIXME dl should come from parent load or store, not from address 845 DebugLoc dl = N.getDebugLoc(); 846 // If this can be more profitably realized as r+r, fail. 847 if (SelectAddressRegReg(N, Disp, Base, DAG)) 848 return false; 849 850 if (N.getOpcode() == ISD::ADD) { 851 short imm = 0; 852 if (isIntS16Immediate(N.getOperand(1), imm)) { 853 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 854 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 855 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 856 } else { 857 Base = N.getOperand(0); 858 } 859 return true; // [r+i] 860 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 861 // Match LOAD (ADD (X, Lo(G))). 862 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 863 && "Cannot handle constant offsets yet!"); 864 Disp = N.getOperand(1).getOperand(0); // The global address. 865 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 866 Disp.getOpcode() == ISD::TargetConstantPool || 867 Disp.getOpcode() == ISD::TargetJumpTable); 868 Base = N.getOperand(0); 869 return true; // [&g+r] 870 } 871 } else if (N.getOpcode() == ISD::OR) { 872 short imm = 0; 873 if (isIntS16Immediate(N.getOperand(1), imm)) { 874 // If this is an or of disjoint bitfields, we can codegen this as an add 875 // (for better address arithmetic) if the LHS and RHS of the OR are 876 // provably disjoint. 877 APInt LHSKnownZero, LHSKnownOne; 878 DAG.ComputeMaskedBits(N.getOperand(0), 879 APInt::getAllOnesValue(N.getOperand(0) 880 .getValueSizeInBits()), 881 LHSKnownZero, LHSKnownOne); 882 883 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 884 // If all of the bits are known zero on the LHS or RHS, the add won't 885 // carry. 886 Base = N.getOperand(0); 887 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 888 return true; 889 } 890 } 891 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 892 // Loading from a constant address. 893 894 // If this address fits entirely in a 16-bit sext immediate field, codegen 895 // this as "d, 0" 896 short Imm; 897 if (isIntS16Immediate(CN, Imm)) { 898 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 899 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 900 return true; 901 } 902 903 // Handle 32-bit sext immediates with LIS + addr mode. 904 if (CN->getValueType(0) == MVT::i32 || 905 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 906 int Addr = (int)CN->getZExtValue(); 907 908 // Otherwise, break this down into an LIS + disp. 909 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 910 911 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 912 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 913 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); 914 return true; 915 } 916 } 917 918 Disp = DAG.getTargetConstant(0, getPointerTy()); 919 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 920 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 921 else 922 Base = N; 923 return true; // [r+0] 924} 925 926/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 927/// represented as an indexed [r+r] operation. 928bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, 929 SDValue &Index, 930 SelectionDAG &DAG) const { 931 // Check to see if we can easily represent this as an [r+r] address. This 932 // will fail if it thinks that the address is more profitably represented as 933 // reg+imm, e.g. where imm = 0. 934 if (SelectAddressRegReg(N, Base, Index, DAG)) 935 return true; 936 937 // If the operand is an addition, always emit this as [r+r], since this is 938 // better (for code size, and execution, as the memop does the add for free) 939 // than emitting an explicit add. 940 if (N.getOpcode() == ISD::ADD) { 941 Base = N.getOperand(0); 942 Index = N.getOperand(1); 943 return true; 944 } 945 946 // Otherwise, do it the hard way, using R0 as the base register. 947 Base = DAG.getRegister(PPC::R0, N.getValueType()); 948 Index = N; 949 return true; 950} 951 952/// SelectAddressRegImmShift - Returns true if the address N can be 953/// represented by a base register plus a signed 14-bit displacement 954/// [r+imm*4]. Suitable for use by STD and friends. 955bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, 956 SDValue &Base, 957 SelectionDAG &DAG) const { 958 // FIXME dl should come from the parent load or store, not the address 959 DebugLoc dl = N.getDebugLoc(); 960 // If this can be more profitably realized as r+r, fail. 961 if (SelectAddressRegReg(N, Disp, Base, DAG)) 962 return false; 963 964 if (N.getOpcode() == ISD::ADD) { 965 short imm = 0; 966 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 967 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 968 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 969 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 970 } else { 971 Base = N.getOperand(0); 972 } 973 return true; // [r+i] 974 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 975 // Match LOAD (ADD (X, Lo(G))). 976 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 977 && "Cannot handle constant offsets yet!"); 978 Disp = N.getOperand(1).getOperand(0); // The global address. 979 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 980 Disp.getOpcode() == ISD::TargetConstantPool || 981 Disp.getOpcode() == ISD::TargetJumpTable); 982 Base = N.getOperand(0); 983 return true; // [&g+r] 984 } 985 } else if (N.getOpcode() == ISD::OR) { 986 short imm = 0; 987 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 988 // If this is an or of disjoint bitfields, we can codegen this as an add 989 // (for better address arithmetic) if the LHS and RHS of the OR are 990 // provably disjoint. 991 APInt LHSKnownZero, LHSKnownOne; 992 DAG.ComputeMaskedBits(N.getOperand(0), 993 APInt::getAllOnesValue(N.getOperand(0) 994 .getValueSizeInBits()), 995 LHSKnownZero, LHSKnownOne); 996 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 997 // If all of the bits are known zero on the LHS or RHS, the add won't 998 // carry. 999 Base = N.getOperand(0); 1000 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 1001 return true; 1002 } 1003 } 1004 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 1005 // Loading from a constant address. Verify low two bits are clear. 1006 if ((CN->getZExtValue() & 3) == 0) { 1007 // If this address fits entirely in a 14-bit sext immediate field, codegen 1008 // this as "d, 0" 1009 short Imm; 1010 if (isIntS16Immediate(CN, Imm)) { 1011 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 1012 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 1013 return true; 1014 } 1015 1016 // Fold the low-part of 32-bit absolute addresses into addr mode. 1017 if (CN->getValueType(0) == MVT::i32 || 1018 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 1019 int Addr = (int)CN->getZExtValue(); 1020 1021 // Otherwise, break this down into an LIS + disp. 1022 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 1023 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 1024 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1025 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0); 1026 return true; 1027 } 1028 } 1029 } 1030 1031 Disp = DAG.getTargetConstant(0, getPointerTy()); 1032 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1033 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1034 else 1035 Base = N; 1036 return true; // [r+0] 1037} 1038 1039 1040/// getPreIndexedAddressParts - returns true by value, base pointer and 1041/// offset pointer and addressing mode by reference if the node's address 1042/// can be legally represented as pre-indexed load / store address. 1043bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1044 SDValue &Offset, 1045 ISD::MemIndexedMode &AM, 1046 SelectionDAG &DAG) const { 1047 // Disabled by default for now. 1048 if (!EnablePPCPreinc) return false; 1049 1050 SDValue Ptr; 1051 EVT VT; 1052 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1053 Ptr = LD->getBasePtr(); 1054 VT = LD->getMemoryVT(); 1055 1056 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1057 ST = ST; 1058 Ptr = ST->getBasePtr(); 1059 VT = ST->getMemoryVT(); 1060 } else 1061 return false; 1062 1063 // PowerPC doesn't have preinc load/store instructions for vectors. 1064 if (VT.isVector()) 1065 return false; 1066 1067 // TODO: Check reg+reg first. 1068 1069 // LDU/STU use reg+imm*4, others use reg+imm. 1070 if (VT != MVT::i64) { 1071 // reg + imm 1072 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 1073 return false; 1074 } else { 1075 // reg + imm * 4. 1076 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 1077 return false; 1078 } 1079 1080 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1081 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 1082 // sext i32 to i64 when addr mode is r+i. 1083 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 1084 LD->getExtensionType() == ISD::SEXTLOAD && 1085 isa<ConstantSDNode>(Offset)) 1086 return false; 1087 } 1088 1089 AM = ISD::PRE_INC; 1090 return true; 1091} 1092 1093//===----------------------------------------------------------------------===// 1094// LowerOperation implementation 1095//===----------------------------------------------------------------------===// 1096 1097SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, 1098 SelectionDAG &DAG) { 1099 EVT PtrVT = Op.getValueType(); 1100 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1101 Constant *C = CP->getConstVal(); 1102 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 1103 SDValue Zero = DAG.getConstant(0, PtrVT); 1104 // FIXME there isn't really any debug info here 1105 DebugLoc dl = Op.getDebugLoc(); 1106 1107 const TargetMachine &TM = DAG.getTarget(); 1108 1109 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero); 1110 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero); 1111 1112 // If this is a non-darwin platform, we don't support non-static relo models 1113 // yet. 1114 if (TM.getRelocationModel() == Reloc::Static || 1115 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1116 // Generate non-pic code that has direct accesses to the constant pool. 1117 // The address of the global is just (hi(&g)+lo(&g)). 1118 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1119 } 1120 1121 if (TM.getRelocationModel() == Reloc::PIC_) { 1122 // With PIC, the first instruction is actually "GR+hi(&G)". 1123 Hi = DAG.getNode(ISD::ADD, dl, PtrVT, 1124 DAG.getNode(PPCISD::GlobalBaseReg, 1125 DebugLoc::getUnknownLoc(), PtrVT), Hi); 1126 } 1127 1128 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1129 return Lo; 1130} 1131 1132SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { 1133 EVT PtrVT = Op.getValueType(); 1134 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1135 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1136 SDValue Zero = DAG.getConstant(0, PtrVT); 1137 // FIXME there isn't really any debug loc here 1138 DebugLoc dl = Op.getDebugLoc(); 1139 1140 const TargetMachine &TM = DAG.getTarget(); 1141 1142 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero); 1143 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, JTI, Zero); 1144 1145 // If this is a non-darwin platform, we don't support non-static relo models 1146 // yet. 1147 if (TM.getRelocationModel() == Reloc::Static || 1148 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1149 // Generate non-pic code that has direct accesses to the constant pool. 1150 // The address of the global is just (hi(&g)+lo(&g)). 1151 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1152 } 1153 1154 if (TM.getRelocationModel() == Reloc::PIC_) { 1155 // With PIC, the first instruction is actually "GR+hi(&G)". 1156 Hi = DAG.getNode(ISD::ADD, dl, PtrVT, 1157 DAG.getNode(PPCISD::GlobalBaseReg, 1158 DebugLoc::getUnknownLoc(), PtrVT), Hi); 1159 } 1160 1161 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1162 return Lo; 1163} 1164 1165SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, 1166 SelectionDAG &DAG) { 1167 llvm_unreachable("TLS not implemented for PPC."); 1168 return SDValue(); // Not reached 1169} 1170 1171SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) { 1172 EVT PtrVT = Op.getValueType(); 1173 DebugLoc DL = Op.getDebugLoc(); 1174 1175 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1176 SDValue TgtBA = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true); 1177 SDValue Zero = DAG.getConstant(0, PtrVT); 1178 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, TgtBA, Zero); 1179 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, TgtBA, Zero); 1180 1181 // If this is a non-darwin platform, we don't support non-static relo models 1182 // yet. 1183 const TargetMachine &TM = DAG.getTarget(); 1184 if (TM.getRelocationModel() == Reloc::Static || 1185 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1186 // Generate non-pic code that has direct accesses to globals. 1187 // The address of the global is just (hi(&g)+lo(&g)). 1188 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1189 } 1190 1191 if (TM.getRelocationModel() == Reloc::PIC_) { 1192 // With PIC, the first instruction is actually "GR+hi(&G)". 1193 Hi = DAG.getNode(ISD::ADD, DL, PtrVT, 1194 DAG.getNode(PPCISD::GlobalBaseReg, 1195 DebugLoc::getUnknownLoc(), PtrVT), Hi); 1196 } 1197 1198 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1199} 1200 1201SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, 1202 SelectionDAG &DAG) { 1203 EVT PtrVT = Op.getValueType(); 1204 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1205 GlobalValue *GV = GSDN->getGlobal(); 1206 SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); 1207 SDValue Zero = DAG.getConstant(0, PtrVT); 1208 // FIXME there isn't really any debug info here 1209 DebugLoc dl = GSDN->getDebugLoc(); 1210 1211 const TargetMachine &TM = DAG.getTarget(); 1212 1213 // 64-bit SVR4 ABI code is always position-independent. 1214 // The actual address of the GlobalValue is stored in the TOC. 1215 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1216 return DAG.getNode(PPCISD::TOC_ENTRY, dl, MVT::i64, GA, 1217 DAG.getRegister(PPC::X2, MVT::i64)); 1218 } 1219 1220 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero); 1221 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero); 1222 1223 // If this is a non-darwin platform, we don't support non-static relo models 1224 // yet. 1225 if (TM.getRelocationModel() == Reloc::Static || 1226 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1227 // Generate non-pic code that has direct accesses to globals. 1228 // The address of the global is just (hi(&g)+lo(&g)). 1229 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1230 } 1231 1232 if (TM.getRelocationModel() == Reloc::PIC_) { 1233 // With PIC, the first instruction is actually "GR+hi(&G)". 1234 Hi = DAG.getNode(ISD::ADD, dl, PtrVT, 1235 DAG.getNode(PPCISD::GlobalBaseReg, 1236 DebugLoc::getUnknownLoc(), PtrVT), Hi); 1237 } 1238 1239 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1240 1241 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) 1242 return Lo; 1243 1244 // If the global is weak or external, we have to go through the lazy 1245 // resolution stub. 1246 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0, 1247 false, false, 0); 1248} 1249 1250SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { 1251 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1252 DebugLoc dl = Op.getDebugLoc(); 1253 1254 // If we're comparing for equality to zero, expose the fact that this is 1255 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1256 // fold the new nodes. 1257 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1258 if (C->isNullValue() && CC == ISD::SETEQ) { 1259 EVT VT = Op.getOperand(0).getValueType(); 1260 SDValue Zext = Op.getOperand(0); 1261 if (VT.bitsLT(MVT::i32)) { 1262 VT = MVT::i32; 1263 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); 1264 } 1265 unsigned Log2b = Log2_32(VT.getSizeInBits()); 1266 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); 1267 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, 1268 DAG.getConstant(Log2b, MVT::i32)); 1269 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); 1270 } 1271 // Leave comparisons against 0 and -1 alone for now, since they're usually 1272 // optimized. FIXME: revisit this when we can custom lower all setcc 1273 // optimizations. 1274 if (C->isAllOnesValue() || C->isNullValue()) 1275 return SDValue(); 1276 } 1277 1278 // If we have an integer seteq/setne, turn it into a compare against zero 1279 // by xor'ing the rhs with the lhs, which is faster than setting a 1280 // condition register, reading it back out, and masking the correct bit. The 1281 // normal approach here uses sub to do this instead of xor. Using xor exposes 1282 // the result to other bit-twiddling opportunities. 1283 EVT LHSVT = Op.getOperand(0).getValueType(); 1284 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1285 EVT VT = Op.getValueType(); 1286 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), 1287 Op.getOperand(1)); 1288 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); 1289 } 1290 return SDValue(); 1291} 1292 1293SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, 1294 int VarArgsFrameIndex, 1295 int VarArgsStackOffset, 1296 unsigned VarArgsNumGPR, 1297 unsigned VarArgsNumFPR, 1298 const PPCSubtarget &Subtarget) { 1299 1300 llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!"); 1301 return SDValue(); // Not reached 1302} 1303 1304SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) { 1305 SDValue Chain = Op.getOperand(0); 1306 SDValue Trmp = Op.getOperand(1); // trampoline 1307 SDValue FPtr = Op.getOperand(2); // nested function 1308 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 1309 DebugLoc dl = Op.getDebugLoc(); 1310 1311 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1312 bool isPPC64 = (PtrVT == MVT::i64); 1313 const Type *IntPtrTy = 1314 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType( 1315 *DAG.getContext()); 1316 1317 TargetLowering::ArgListTy Args; 1318 TargetLowering::ArgListEntry Entry; 1319 1320 Entry.Ty = IntPtrTy; 1321 Entry.Node = Trmp; Args.push_back(Entry); 1322 1323 // TrampSize == (isPPC64 ? 48 : 40); 1324 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, 1325 isPPC64 ? MVT::i64 : MVT::i32); 1326 Args.push_back(Entry); 1327 1328 Entry.Node = FPtr; Args.push_back(Entry); 1329 Entry.Node = Nest; Args.push_back(Entry); 1330 1331 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) 1332 std::pair<SDValue, SDValue> CallResult = 1333 LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()), 1334 false, false, false, false, 0, CallingConv::C, false, 1335 /*isReturnValueUsed=*/true, 1336 DAG.getExternalSymbol("__trampoline_setup", PtrVT), 1337 Args, DAG, dl); 1338 1339 SDValue Ops[] = 1340 { CallResult.first, CallResult.second }; 1341 1342 return DAG.getMergeValues(Ops, 2, dl); 1343} 1344 1345SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, 1346 int VarArgsFrameIndex, 1347 int VarArgsStackOffset, 1348 unsigned VarArgsNumGPR, 1349 unsigned VarArgsNumFPR, 1350 const PPCSubtarget &Subtarget) { 1351 DebugLoc dl = Op.getDebugLoc(); 1352 1353 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) { 1354 // vastart just stores the address of the VarArgsFrameIndex slot into the 1355 // memory location argument. 1356 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1357 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1358 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1359 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0, 1360 false, false, 0); 1361 } 1362 1363 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct. 1364 // We suppose the given va_list is already allocated. 1365 // 1366 // typedef struct { 1367 // char gpr; /* index into the array of 8 GPRs 1368 // * stored in the register save area 1369 // * gpr=0 corresponds to r3, 1370 // * gpr=1 to r4, etc. 1371 // */ 1372 // char fpr; /* index into the array of 8 FPRs 1373 // * stored in the register save area 1374 // * fpr=0 corresponds to f1, 1375 // * fpr=1 to f2, etc. 1376 // */ 1377 // char *overflow_arg_area; 1378 // /* location on stack that holds 1379 // * the next overflow argument 1380 // */ 1381 // char *reg_save_area; 1382 // /* where r3:r10 and f1:f8 (if saved) 1383 // * are stored 1384 // */ 1385 // } va_list[1]; 1386 1387 1388 SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i32); 1389 SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i32); 1390 1391 1392 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1393 1394 SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); 1395 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1396 1397 uint64_t FrameOffset = PtrVT.getSizeInBits()/8; 1398 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1399 1400 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; 1401 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1402 1403 uint64_t FPROffset = 1; 1404 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1405 1406 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1407 1408 // Store first byte : number of int regs 1409 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, 1410 Op.getOperand(1), SV, 0, MVT::i8, 1411 false, false, 0); 1412 uint64_t nextOffset = FPROffset; 1413 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), 1414 ConstFPROffset); 1415 1416 // Store second byte : number of float regs 1417 SDValue secondStore = 1418 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset, MVT::i8, 1419 false, false, 0); 1420 nextOffset += StackOffset; 1421 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); 1422 1423 // Store second word : arguments given on stack 1424 SDValue thirdStore = 1425 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset, 1426 false, false, 0); 1427 nextOffset += FrameOffset; 1428 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset); 1429 1430 // Store third word : arguments given in registers 1431 return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset, 1432 false, false, 0); 1433 1434} 1435 1436#include "PPCGenCallingConv.inc" 1437 1438static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 1439 CCValAssign::LocInfo &LocInfo, 1440 ISD::ArgFlagsTy &ArgFlags, 1441 CCState &State) { 1442 return true; 1443} 1444 1445static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT, 1446 EVT &LocVT, 1447 CCValAssign::LocInfo &LocInfo, 1448 ISD::ArgFlagsTy &ArgFlags, 1449 CCState &State) { 1450 static const unsigned ArgRegs[] = { 1451 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1452 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1453 }; 1454 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1455 1456 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1457 1458 // Skip one register if the first unallocated register has an even register 1459 // number and there are still argument registers available which have not been 1460 // allocated yet. RegNum is actually an index into ArgRegs, which means we 1461 // need to skip a register if RegNum is odd. 1462 if (RegNum != NumArgRegs && RegNum % 2 == 1) { 1463 State.AllocateReg(ArgRegs[RegNum]); 1464 } 1465 1466 // Always return false here, as this function only makes sure that the first 1467 // unallocated register has an odd register number and does not actually 1468 // allocate a register for the current argument. 1469 return false; 1470} 1471 1472static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT, 1473 EVT &LocVT, 1474 CCValAssign::LocInfo &LocInfo, 1475 ISD::ArgFlagsTy &ArgFlags, 1476 CCState &State) { 1477 static const unsigned ArgRegs[] = { 1478 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1479 PPC::F8 1480 }; 1481 1482 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1483 1484 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1485 1486 // If there is only one Floating-point register left we need to put both f64 1487 // values of a split ppc_fp128 value on the stack. 1488 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { 1489 State.AllocateReg(ArgRegs[RegNum]); 1490 } 1491 1492 // Always return false here, as this function only makes sure that the two f64 1493 // values a ppc_fp128 value is split into are both passed in registers or both 1494 // passed on the stack and does not actually allocate a register for the 1495 // current argument. 1496 return false; 1497} 1498 1499/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1500/// on Darwin. 1501static const unsigned *GetFPR() { 1502 static const unsigned FPR[] = { 1503 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1504 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1505 }; 1506 1507 return FPR; 1508} 1509 1510/// CalculateStackSlotSize - Calculates the size reserved for this argument on 1511/// the stack. 1512static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, 1513 unsigned PtrByteSize) { 1514 unsigned ArgSize = ArgVT.getSizeInBits()/8; 1515 if (Flags.isByVal()) 1516 ArgSize = Flags.getByValSize(); 1517 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1518 1519 return ArgSize; 1520} 1521 1522SDValue 1523PPCTargetLowering::LowerFormalArguments(SDValue Chain, 1524 CallingConv::ID CallConv, bool isVarArg, 1525 const SmallVectorImpl<ISD::InputArg> 1526 &Ins, 1527 DebugLoc dl, SelectionDAG &DAG, 1528 SmallVectorImpl<SDValue> &InVals) { 1529 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) { 1530 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins, 1531 dl, DAG, InVals); 1532 } else { 1533 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, 1534 dl, DAG, InVals); 1535 } 1536} 1537 1538SDValue 1539PPCTargetLowering::LowerFormalArguments_SVR4( 1540 SDValue Chain, 1541 CallingConv::ID CallConv, bool isVarArg, 1542 const SmallVectorImpl<ISD::InputArg> 1543 &Ins, 1544 DebugLoc dl, SelectionDAG &DAG, 1545 SmallVectorImpl<SDValue> &InVals) { 1546 1547 // 32-bit SVR4 ABI Stack Frame Layout: 1548 // +-----------------------------------+ 1549 // +--> | Back chain | 1550 // | +-----------------------------------+ 1551 // | | Floating-point register save area | 1552 // | +-----------------------------------+ 1553 // | | General register save area | 1554 // | +-----------------------------------+ 1555 // | | CR save word | 1556 // | +-----------------------------------+ 1557 // | | VRSAVE save word | 1558 // | +-----------------------------------+ 1559 // | | Alignment padding | 1560 // | +-----------------------------------+ 1561 // | | Vector register save area | 1562 // | +-----------------------------------+ 1563 // | | Local variable space | 1564 // | +-----------------------------------+ 1565 // | | Parameter list area | 1566 // | +-----------------------------------+ 1567 // | | LR save word | 1568 // | +-----------------------------------+ 1569 // SP--> +--- | Back chain | 1570 // +-----------------------------------+ 1571 // 1572 // Specifications: 1573 // System V Application Binary Interface PowerPC Processor Supplement 1574 // AltiVec Technology Programming Interface Manual 1575 1576 MachineFunction &MF = DAG.getMachineFunction(); 1577 MachineFrameInfo *MFI = MF.getFrameInfo(); 1578 1579 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1580 // Potential tail calls could cause overwriting of argument stack slots. 1581 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast)); 1582 unsigned PtrByteSize = 4; 1583 1584 // Assign locations to all of the incoming arguments. 1585 SmallVector<CCValAssign, 16> ArgLocs; 1586 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, 1587 *DAG.getContext()); 1588 1589 // Reserve space for the linkage area on the stack. 1590 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize); 1591 1592 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4); 1593 1594 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1595 CCValAssign &VA = ArgLocs[i]; 1596 1597 // Arguments stored in registers. 1598 if (VA.isRegLoc()) { 1599 TargetRegisterClass *RC; 1600 EVT ValVT = VA.getValVT(); 1601 1602 switch (ValVT.getSimpleVT().SimpleTy) { 1603 default: 1604 llvm_unreachable("ValVT not supported by formal arguments Lowering"); 1605 case MVT::i32: 1606 RC = PPC::GPRCRegisterClass; 1607 break; 1608 case MVT::f32: 1609 RC = PPC::F4RCRegisterClass; 1610 break; 1611 case MVT::f64: 1612 RC = PPC::F8RCRegisterClass; 1613 break; 1614 case MVT::v16i8: 1615 case MVT::v8i16: 1616 case MVT::v4i32: 1617 case MVT::v4f32: 1618 RC = PPC::VRRCRegisterClass; 1619 break; 1620 } 1621 1622 // Transform the arguments stored in physical registers into virtual ones. 1623 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1624 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT); 1625 1626 InVals.push_back(ArgValue); 1627 } else { 1628 // Argument stored in memory. 1629 assert(VA.isMemLoc()); 1630 1631 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; 1632 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), 1633 isImmutable, false); 1634 1635 // Create load nodes to retrieve arguments from the stack. 1636 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1637 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0, 1638 false, false, 0)); 1639 } 1640 } 1641 1642 // Assign locations to all of the incoming aggregate by value arguments. 1643 // Aggregates passed by value are stored in the local variable space of the 1644 // caller's stack frame, right above the parameter list area. 1645 SmallVector<CCValAssign, 16> ByValArgLocs; 1646 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), 1647 ByValArgLocs, *DAG.getContext()); 1648 1649 // Reserve stack space for the allocations in CCInfo. 1650 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 1651 1652 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal); 1653 1654 // Area that is at least reserved in the caller of this function. 1655 unsigned MinReservedArea = CCByValInfo.getNextStackOffset(); 1656 1657 // Set the size that is at least reserved in caller of this function. Tail 1658 // call optimized function's reserved stack space needs to be aligned so that 1659 // taking the difference between two stack areas will result in an aligned 1660 // stack. 1661 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1662 1663 MinReservedArea = 1664 std::max(MinReservedArea, 1665 PPCFrameInfo::getMinCallFrameSize(false, false)); 1666 1667 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 1668 getStackAlignment(); 1669 unsigned AlignMask = TargetAlign-1; 1670 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 1671 1672 FI->setMinReservedArea(MinReservedArea); 1673 1674 SmallVector<SDValue, 8> MemOps; 1675 1676 // If the function takes variable number of arguments, make a frame index for 1677 // the start of the first vararg value... for expansion of llvm.va_start. 1678 if (isVarArg) { 1679 static const unsigned GPArgRegs[] = { 1680 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1681 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1682 }; 1683 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs); 1684 1685 static const unsigned FPArgRegs[] = { 1686 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1687 PPC::F8 1688 }; 1689 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs); 1690 1691 VarArgsNumGPR = CCInfo.getFirstUnallocated(GPArgRegs, NumGPArgRegs); 1692 VarArgsNumFPR = CCInfo.getFirstUnallocated(FPArgRegs, NumFPArgRegs); 1693 1694 // Make room for NumGPArgRegs and NumFPArgRegs. 1695 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 + 1696 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8; 1697 1698 VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 1699 CCInfo.getNextStackOffset(), 1700 true, false); 1701 1702 VarArgsFrameIndex = MFI->CreateStackObject(Depth, 8, false); 1703 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1704 1705 // The fixed integer arguments of a variadic function are 1706 // stored to the VarArgsFrameIndex on the stack. 1707 unsigned GPRIndex = 0; 1708 for (; GPRIndex != VarArgsNumGPR; ++GPRIndex) { 1709 SDValue Val = DAG.getRegister(GPArgRegs[GPRIndex], PtrVT); 1710 SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0, 1711 false, false, 0); 1712 MemOps.push_back(Store); 1713 // Increment the address by four for the next argument to store 1714 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 1715 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1716 } 1717 1718 // If this function is vararg, store any remaining integer argument regs 1719 // to their spots on the stack so that they may be loaded by deferencing the 1720 // result of va_next. 1721 for (; GPRIndex != NumGPArgRegs; ++GPRIndex) { 1722 unsigned VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); 1723 1724 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1725 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0, 1726 false, false, 0); 1727 MemOps.push_back(Store); 1728 // Increment the address by four for the next argument to store 1729 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 1730 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1731 } 1732 1733 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6 1734 // is set. 1735 1736 // The double arguments are stored to the VarArgsFrameIndex 1737 // on the stack. 1738 unsigned FPRIndex = 0; 1739 for (FPRIndex = 0; FPRIndex != VarArgsNumFPR; ++FPRIndex) { 1740 SDValue Val = DAG.getRegister(FPArgRegs[FPRIndex], MVT::f64); 1741 SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0, 1742 false, false, 0); 1743 MemOps.push_back(Store); 1744 // Increment the address by eight for the next argument to store 1745 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8, 1746 PtrVT); 1747 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1748 } 1749 1750 for (; FPRIndex != NumFPArgRegs; ++FPRIndex) { 1751 unsigned VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); 1752 1753 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); 1754 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0, 1755 false, false, 0); 1756 MemOps.push_back(Store); 1757 // Increment the address by eight for the next argument to store 1758 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8, 1759 PtrVT); 1760 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1761 } 1762 } 1763 1764 if (!MemOps.empty()) 1765 Chain = DAG.getNode(ISD::TokenFactor, dl, 1766 MVT::Other, &MemOps[0], MemOps.size()); 1767 1768 return Chain; 1769} 1770 1771SDValue 1772PPCTargetLowering::LowerFormalArguments_Darwin( 1773 SDValue Chain, 1774 CallingConv::ID CallConv, bool isVarArg, 1775 const SmallVectorImpl<ISD::InputArg> 1776 &Ins, 1777 DebugLoc dl, SelectionDAG &DAG, 1778 SmallVectorImpl<SDValue> &InVals) { 1779 // TODO: add description of PPC stack frame format, or at least some docs. 1780 // 1781 MachineFunction &MF = DAG.getMachineFunction(); 1782 MachineFrameInfo *MFI = MF.getFrameInfo(); 1783 1784 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1785 bool isPPC64 = PtrVT == MVT::i64; 1786 // Potential tail calls could cause overwriting of argument stack slots. 1787 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast)); 1788 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1789 1790 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true); 1791 // Area that is at least reserved in caller of this function. 1792 unsigned MinReservedArea = ArgOffset; 1793 1794 static const unsigned GPR_32[] = { // 32-bit registers. 1795 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1796 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1797 }; 1798 static const unsigned GPR_64[] = { // 64-bit registers. 1799 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1800 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1801 }; 1802 1803 static const unsigned *FPR = GetFPR(); 1804 1805 static const unsigned VR[] = { 1806 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1807 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1808 }; 1809 1810 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 1811 const unsigned Num_FPR_Regs = 13; 1812 const unsigned Num_VR_Regs = array_lengthof( VR); 1813 1814 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1815 1816 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1817 1818 // In 32-bit non-varargs functions, the stack space for vectors is after the 1819 // stack space for non-vectors. We do not use this space unless we have 1820 // too many vectors to fit in registers, something that only occurs in 1821 // constructed examples:), but we have to walk the arglist to figure 1822 // that out...for the pathological case, compute VecArgOffset as the 1823 // start of the vector parameter area. Computing VecArgOffset is the 1824 // entire point of the following loop. 1825 unsigned VecArgOffset = ArgOffset; 1826 if (!isVarArg && !isPPC64) { 1827 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; 1828 ++ArgNo) { 1829 EVT ObjectVT = Ins[ArgNo].VT; 1830 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1831 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 1832 1833 if (Flags.isByVal()) { 1834 // ObjSize is the true size, ArgSize rounded up to multiple of regs. 1835 ObjSize = Flags.getByValSize(); 1836 unsigned ArgSize = 1837 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1838 VecArgOffset += ArgSize; 1839 continue; 1840 } 1841 1842 switch(ObjectVT.getSimpleVT().SimpleTy) { 1843 default: llvm_unreachable("Unhandled argument type!"); 1844 case MVT::i32: 1845 case MVT::f32: 1846 VecArgOffset += isPPC64 ? 8 : 4; 1847 break; 1848 case MVT::i64: // PPC64 1849 case MVT::f64: 1850 VecArgOffset += 8; 1851 break; 1852 case MVT::v4f32: 1853 case MVT::v4i32: 1854 case MVT::v8i16: 1855 case MVT::v16i8: 1856 // Nothing to do, we're only looking at Nonvector args here. 1857 break; 1858 } 1859 } 1860 } 1861 // We've found where the vector parameter area in memory is. Skip the 1862 // first 12 parameters; these don't use that memory. 1863 VecArgOffset = ((VecArgOffset+15)/16)*16; 1864 VecArgOffset += 12*16; 1865 1866 // Add DAG nodes to load the arguments or copy them out of registers. On 1867 // entry to a function on PPC, the arguments start after the linkage area, 1868 // although the first ones are often in registers. 1869 1870 SmallVector<SDValue, 8> MemOps; 1871 unsigned nAltivecParamsAtEnd = 0; 1872 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { 1873 SDValue ArgVal; 1874 bool needsLoad = false; 1875 EVT ObjectVT = Ins[ArgNo].VT; 1876 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1877 unsigned ArgSize = ObjSize; 1878 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 1879 1880 unsigned CurArgOffset = ArgOffset; 1881 1882 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 1883 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 1884 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 1885 if (isVarArg || isPPC64) { 1886 MinReservedArea = ((MinReservedArea+15)/16)*16; 1887 MinReservedArea += CalculateStackSlotSize(ObjectVT, 1888 Flags, 1889 PtrByteSize); 1890 } else nAltivecParamsAtEnd++; 1891 } else 1892 // Calculate min reserved area. 1893 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 1894 Flags, 1895 PtrByteSize); 1896 1897 // FIXME the codegen can be much improved in some cases. 1898 // We do not have to keep everything in memory. 1899 if (Flags.isByVal()) { 1900 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 1901 ObjSize = Flags.getByValSize(); 1902 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1903 // Objects of size 1 and 2 are right justified, everything else is 1904 // left justified. This means the memory address is adjusted forwards. 1905 if (ObjSize==1 || ObjSize==2) { 1906 CurArgOffset = CurArgOffset + (4 - ObjSize); 1907 } 1908 // The value of the object is its address. 1909 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true, false); 1910 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1911 InVals.push_back(FIN); 1912 if (ObjSize==1 || ObjSize==2) { 1913 if (GPR_idx != Num_GPR_Regs) { 1914 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1915 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1916 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 1917 NULL, 0, 1918 ObjSize==1 ? MVT::i8 : MVT::i16, 1919 false, false, 0); 1920 MemOps.push_back(Store); 1921 ++GPR_idx; 1922 } 1923 1924 ArgOffset += PtrByteSize; 1925 1926 continue; 1927 } 1928 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 1929 // Store whatever pieces of the object are in registers 1930 // to memory. ArgVal will be address of the beginning of 1931 // the object. 1932 if (GPR_idx != Num_GPR_Regs) { 1933 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1934 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true, false); 1935 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1936 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1937 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0, 1938 false, false, 0); 1939 MemOps.push_back(Store); 1940 ++GPR_idx; 1941 ArgOffset += PtrByteSize; 1942 } else { 1943 ArgOffset += ArgSize - (ArgOffset-CurArgOffset); 1944 break; 1945 } 1946 } 1947 continue; 1948 } 1949 1950 switch (ObjectVT.getSimpleVT().SimpleTy) { 1951 default: llvm_unreachable("Unhandled argument type!"); 1952 case MVT::i32: 1953 if (!isPPC64) { 1954 if (GPR_idx != Num_GPR_Regs) { 1955 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1956 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 1957 ++GPR_idx; 1958 } else { 1959 needsLoad = true; 1960 ArgSize = PtrByteSize; 1961 } 1962 // All int arguments reserve stack space in the Darwin ABI. 1963 ArgOffset += PtrByteSize; 1964 break; 1965 } 1966 // FALLTHROUGH 1967 case MVT::i64: // PPC64 1968 if (GPR_idx != Num_GPR_Regs) { 1969 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 1970 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1971 1972 if (ObjectVT == MVT::i32) { 1973 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 1974 // value to MVT::i64 and then truncate to the correct register size. 1975 if (Flags.isSExt()) 1976 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, 1977 DAG.getValueType(ObjectVT)); 1978 else if (Flags.isZExt()) 1979 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, 1980 DAG.getValueType(ObjectVT)); 1981 1982 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); 1983 } 1984 1985 ++GPR_idx; 1986 } else { 1987 needsLoad = true; 1988 ArgSize = PtrByteSize; 1989 } 1990 // All int arguments reserve stack space in the Darwin ABI. 1991 ArgOffset += 8; 1992 break; 1993 1994 case MVT::f32: 1995 case MVT::f64: 1996 // Every 4 bytes of argument space consumes one of the GPRs available for 1997 // argument passing. 1998 if (GPR_idx != Num_GPR_Regs) { 1999 ++GPR_idx; 2000 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 2001 ++GPR_idx; 2002 } 2003 if (FPR_idx != Num_FPR_Regs) { 2004 unsigned VReg; 2005 2006 if (ObjectVT == MVT::f32) 2007 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 2008 else 2009 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 2010 2011 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2012 ++FPR_idx; 2013 } else { 2014 needsLoad = true; 2015 } 2016 2017 // All FP arguments reserve stack space in the Darwin ABI. 2018 ArgOffset += isPPC64 ? 8 : ObjSize; 2019 break; 2020 case MVT::v4f32: 2021 case MVT::v4i32: 2022 case MVT::v8i16: 2023 case MVT::v16i8: 2024 // Note that vector arguments in registers don't reserve stack space, 2025 // except in varargs functions. 2026 if (VR_idx != Num_VR_Regs) { 2027 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 2028 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2029 if (isVarArg) { 2030 while ((ArgOffset % 16) != 0) { 2031 ArgOffset += PtrByteSize; 2032 if (GPR_idx != Num_GPR_Regs) 2033 GPR_idx++; 2034 } 2035 ArgOffset += 16; 2036 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 2037 } 2038 ++VR_idx; 2039 } else { 2040 if (!isVarArg && !isPPC64) { 2041 // Vectors go after all the nonvectors. 2042 CurArgOffset = VecArgOffset; 2043 VecArgOffset += 16; 2044 } else { 2045 // Vectors are aligned. 2046 ArgOffset = ((ArgOffset+15)/16)*16; 2047 CurArgOffset = ArgOffset; 2048 ArgOffset += 16; 2049 } 2050 needsLoad = true; 2051 } 2052 break; 2053 } 2054 2055 // We need to load the argument to a virtual register if we determined above 2056 // that we ran out of physical registers of the appropriate type. 2057 if (needsLoad) { 2058 int FI = MFI->CreateFixedObject(ObjSize, 2059 CurArgOffset + (ArgSize - ObjSize), 2060 isImmutable, false); 2061 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2062 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0, 2063 false, false, 0); 2064 } 2065 2066 InVals.push_back(ArgVal); 2067 } 2068 2069 // Set the size that is at least reserved in caller of this function. Tail 2070 // call optimized function's reserved stack space needs to be aligned so that 2071 // taking the difference between two stack areas will result in an aligned 2072 // stack. 2073 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2074 // Add the Altivec parameters at the end, if needed. 2075 if (nAltivecParamsAtEnd) { 2076 MinReservedArea = ((MinReservedArea+15)/16)*16; 2077 MinReservedArea += 16*nAltivecParamsAtEnd; 2078 } 2079 MinReservedArea = 2080 std::max(MinReservedArea, 2081 PPCFrameInfo::getMinCallFrameSize(isPPC64, true)); 2082 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 2083 getStackAlignment(); 2084 unsigned AlignMask = TargetAlign-1; 2085 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 2086 FI->setMinReservedArea(MinReservedArea); 2087 2088 // If the function takes variable number of arguments, make a frame index for 2089 // the start of the first vararg value... for expansion of llvm.va_start. 2090 if (isVarArg) { 2091 int Depth = ArgOffset; 2092 2093 VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2094 Depth, true, false); 2095 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 2096 2097 // If this function is vararg, store any remaining integer argument regs 2098 // to their spots on the stack so that they may be loaded by deferencing the 2099 // result of va_next. 2100 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2101 unsigned VReg; 2102 2103 if (isPPC64) 2104 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2105 else 2106 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2107 2108 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2109 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0, 2110 false, false, 0); 2111 MemOps.push_back(Store); 2112 // Increment the address by four for the next argument to store 2113 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2114 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2115 } 2116 } 2117 2118 if (!MemOps.empty()) 2119 Chain = DAG.getNode(ISD::TokenFactor, dl, 2120 MVT::Other, &MemOps[0], MemOps.size()); 2121 2122 return Chain; 2123} 2124 2125/// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus 2126/// linkage area for the Darwin ABI. 2127static unsigned 2128CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, 2129 bool isPPC64, 2130 bool isVarArg, 2131 unsigned CC, 2132 const SmallVectorImpl<ISD::OutputArg> 2133 &Outs, 2134 unsigned &nAltivecParamsAtEnd) { 2135 // Count how many bytes are to be pushed on the stack, including the linkage 2136 // area, and parameter passing area. We start with 24/48 bytes, which is 2137 // prereserved space for [SP][CR][LR][3 x unused]. 2138 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, true); 2139 unsigned NumOps = Outs.size(); 2140 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2141 2142 // Add up all the space actually used. 2143 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually 2144 // they all go in registers, but we must reserve stack space for them for 2145 // possible use by the caller. In varargs or 64-bit calls, parameters are 2146 // assigned stack space in order, with padding so Altivec parameters are 2147 // 16-byte aligned. 2148 nAltivecParamsAtEnd = 0; 2149 for (unsigned i = 0; i != NumOps; ++i) { 2150 SDValue Arg = Outs[i].Val; 2151 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2152 EVT ArgVT = Arg.getValueType(); 2153 // Varargs Altivec parameters are padded to a 16 byte boundary. 2154 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 2155 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { 2156 if (!isVarArg && !isPPC64) { 2157 // Non-varargs Altivec parameters go after all the non-Altivec 2158 // parameters; handle those later so we know how much padding we need. 2159 nAltivecParamsAtEnd++; 2160 continue; 2161 } 2162 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. 2163 NumBytes = ((NumBytes+15)/16)*16; 2164 } 2165 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); 2166 } 2167 2168 // Allow for Altivec parameters at the end, if needed. 2169 if (nAltivecParamsAtEnd) { 2170 NumBytes = ((NumBytes+15)/16)*16; 2171 NumBytes += 16*nAltivecParamsAtEnd; 2172 } 2173 2174 // The prolog code of the callee may store up to 8 GPR argument registers to 2175 // the stack, allowing va_start to index over them in memory if its varargs. 2176 // Because we cannot tell if this is needed on the caller side, we have to 2177 // conservatively assume that it is needed. As such, make sure we have at 2178 // least enough stack space for the caller to store the 8 GPRs. 2179 NumBytes = std::max(NumBytes, 2180 PPCFrameInfo::getMinCallFrameSize(isPPC64, true)); 2181 2182 // Tail call needs the stack to be aligned. 2183 if (CC==CallingConv::Fast && GuaranteedTailCallOpt) { 2184 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 2185 getStackAlignment(); 2186 unsigned AlignMask = TargetAlign-1; 2187 NumBytes = (NumBytes + AlignMask) & ~AlignMask; 2188 } 2189 2190 return NumBytes; 2191} 2192 2193/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be 2194/// adjusted to accomodate the arguments for the tailcall. 2195static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, 2196 unsigned ParamSize) { 2197 2198 if (!isTailCall) return 0; 2199 2200 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>(); 2201 unsigned CallerMinReservedArea = FI->getMinReservedArea(); 2202 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize; 2203 // Remember only if the new adjustement is bigger. 2204 if (SPDiff < FI->getTailCallSPDelta()) 2205 FI->setTailCallSPDelta(SPDiff); 2206 2207 return SPDiff; 2208} 2209 2210/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2211/// for tail call optimization. Targets which want to do tail call 2212/// optimization should implement this function. 2213bool 2214PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2215 CallingConv::ID CalleeCC, 2216 bool isVarArg, 2217 const SmallVectorImpl<ISD::InputArg> &Ins, 2218 SelectionDAG& DAG) const { 2219 if (!GuaranteedTailCallOpt) 2220 return false; 2221 2222 // Variable argument functions are not supported. 2223 if (isVarArg) 2224 return false; 2225 2226 MachineFunction &MF = DAG.getMachineFunction(); 2227 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv(); 2228 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 2229 // Functions containing by val parameters are not supported. 2230 for (unsigned i = 0; i != Ins.size(); i++) { 2231 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2232 if (Flags.isByVal()) return false; 2233 } 2234 2235 // Non PIC/GOT tail calls are supported. 2236 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 2237 return true; 2238 2239 // At the moment we can only do local tail calls (in same module, hidden 2240 // or protected) if we are generating PIC. 2241 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2242 return G->getGlobal()->hasHiddenVisibility() 2243 || G->getGlobal()->hasProtectedVisibility(); 2244 } 2245 2246 return false; 2247} 2248 2249/// isCallCompatibleAddress - Return the immediate to use if the specified 2250/// 32-bit value is representable in the immediate field of a BxA instruction. 2251static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { 2252 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2253 if (!C) return 0; 2254 2255 int Addr = C->getZExtValue(); 2256 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 2257 (Addr << 6 >> 6) != Addr) 2258 return 0; // Top 6 bits have to be sext of immediate. 2259 2260 return DAG.getConstant((int)C->getZExtValue() >> 2, 2261 DAG.getTargetLoweringInfo().getPointerTy()).getNode(); 2262} 2263 2264namespace { 2265 2266struct TailCallArgumentInfo { 2267 SDValue Arg; 2268 SDValue FrameIdxOp; 2269 int FrameIdx; 2270 2271 TailCallArgumentInfo() : FrameIdx(0) {} 2272}; 2273 2274} 2275 2276/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. 2277static void 2278StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, 2279 SDValue Chain, 2280 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, 2281 SmallVector<SDValue, 8> &MemOpChains, 2282 DebugLoc dl) { 2283 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { 2284 SDValue Arg = TailCallArgs[i].Arg; 2285 SDValue FIN = TailCallArgs[i].FrameIdxOp; 2286 int FI = TailCallArgs[i].FrameIdx; 2287 // Store relative to framepointer. 2288 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN, 2289 PseudoSourceValue::getFixedStack(FI), 2290 0, false, false, 0)); 2291 } 2292} 2293 2294/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to 2295/// the appropriate stack slot for the tail call optimized function call. 2296static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, 2297 MachineFunction &MF, 2298 SDValue Chain, 2299 SDValue OldRetAddr, 2300 SDValue OldFP, 2301 int SPDiff, 2302 bool isPPC64, 2303 bool isDarwinABI, 2304 DebugLoc dl) { 2305 if (SPDiff) { 2306 // Calculate the new stack slot for the return address. 2307 int SlotSize = isPPC64 ? 8 : 4; 2308 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64, 2309 isDarwinABI); 2310 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, 2311 NewRetAddrLoc, 2312 true, false); 2313 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2314 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); 2315 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, 2316 PseudoSourceValue::getFixedStack(NewRetAddr), 0, 2317 false, false, 0); 2318 2319 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack 2320 // slot as the FP is never overwritten. 2321 if (isDarwinABI) { 2322 int NewFPLoc = 2323 SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); 2324 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc, 2325 true, false); 2326 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); 2327 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, 2328 PseudoSourceValue::getFixedStack(NewFPIdx), 0, 2329 false, false, 0); 2330 } 2331 } 2332 return Chain; 2333} 2334 2335/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate 2336/// the position of the argument. 2337static void 2338CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, 2339 SDValue Arg, int SPDiff, unsigned ArgOffset, 2340 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 2341 int Offset = ArgOffset + SPDiff; 2342 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; 2343 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true,false); 2344 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2345 SDValue FIN = DAG.getFrameIndex(FI, VT); 2346 TailCallArgumentInfo Info; 2347 Info.Arg = Arg; 2348 Info.FrameIdxOp = FIN; 2349 Info.FrameIdx = FI; 2350 TailCallArguments.push_back(Info); 2351} 2352 2353/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address 2354/// stack slot. Returns the chain as result and the loaded frame pointers in 2355/// LROpOut/FPOpout. Used when tail calling. 2356SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 2357 int SPDiff, 2358 SDValue Chain, 2359 SDValue &LROpOut, 2360 SDValue &FPOpOut, 2361 bool isDarwinABI, 2362 DebugLoc dl) { 2363 if (SPDiff) { 2364 // Load the LR and FP stack slot for later adjusting. 2365 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; 2366 LROpOut = getReturnAddrFrameIndex(DAG); 2367 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0, 2368 false, false, 0); 2369 Chain = SDValue(LROpOut.getNode(), 1); 2370 2371 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack 2372 // slot as the FP is never overwritten. 2373 if (isDarwinABI) { 2374 FPOpOut = getFramePointerFrameIndex(DAG); 2375 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0, 2376 false, false, 0); 2377 Chain = SDValue(FPOpOut.getNode(), 1); 2378 } 2379 } 2380 return Chain; 2381} 2382 2383/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 2384/// by "Src" to address "Dst" of size "Size". Alignment information is 2385/// specified by the specific parameter attribute. The copy will be passed as 2386/// a byval function parameter. 2387/// Sometimes what we are copying is the end of a larger object, the part that 2388/// does not fit in registers. 2389static SDValue 2390CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 2391 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 2392 DebugLoc dl) { 2393 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 2394 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 2395 false, NULL, 0, NULL, 0); 2396} 2397 2398/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of 2399/// tail calls. 2400static void 2401LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, 2402 SDValue Arg, SDValue PtrOff, int SPDiff, 2403 unsigned ArgOffset, bool isPPC64, bool isTailCall, 2404 bool isVector, SmallVector<SDValue, 8> &MemOpChains, 2405 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments, 2406 DebugLoc dl) { 2407 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2408 if (!isTailCall) { 2409 if (isVector) { 2410 SDValue StackPtr; 2411 if (isPPC64) 2412 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2413 else 2414 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2415 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 2416 DAG.getConstant(ArgOffset, PtrVT)); 2417 } 2418 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0, 2419 false, false, 0)); 2420 // Calculate and remember argument location. 2421 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, 2422 TailCallArguments); 2423} 2424 2425static 2426void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, 2427 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, 2428 SDValue LROp, SDValue FPOp, bool isDarwinABI, 2429 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) { 2430 MachineFunction &MF = DAG.getMachineFunction(); 2431 2432 // Emit a sequence of copyto/copyfrom virtual registers for arguments that 2433 // might overwrite each other in case of tail call optimization. 2434 SmallVector<SDValue, 8> MemOpChains2; 2435 // Do not flag preceeding copytoreg stuff together with the following stuff. 2436 InFlag = SDValue(); 2437 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, 2438 MemOpChains2, dl); 2439 if (!MemOpChains2.empty()) 2440 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2441 &MemOpChains2[0], MemOpChains2.size()); 2442 2443 // Store the return address to the appropriate stack slot. 2444 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, 2445 isPPC64, isDarwinABI, dl); 2446 2447 // Emit callseq_end just before tailcall node. 2448 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2449 DAG.getIntPtrConstant(0, true), InFlag); 2450 InFlag = Chain.getValue(1); 2451} 2452 2453static 2454unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, 2455 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall, 2456 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 2457 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys, 2458 bool isPPC64, bool isSVR4ABI) { 2459 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2460 NodeTys.push_back(MVT::Other); // Returns a chain 2461 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 2462 2463 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin; 2464 2465 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2466 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2467 // node so that legalize doesn't hack it. 2468 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2469 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); 2470 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 2471 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); 2472 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) 2473 // If this is an absolute destination address, use the munged value. 2474 Callee = SDValue(Dest, 0); 2475 else { 2476 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 2477 // to do the call, we can't use PPCISD::CALL. 2478 SDValue MTCTROps[] = {Chain, Callee, InFlag}; 2479 2480 if (isSVR4ABI && isPPC64) { 2481 // Function pointers in the 64-bit SVR4 ABI do not point to the function 2482 // entry point, but to the function descriptor (the function entry point 2483 // address is part of the function descriptor though). 2484 // The function descriptor is a three doubleword structure with the 2485 // following fields: function entry point, TOC base address and 2486 // environment pointer. 2487 // Thus for a call through a function pointer, the following actions need 2488 // to be performed: 2489 // 1. Save the TOC of the caller in the TOC save area of its stack 2490 // frame (this is done in LowerCall_Darwin()). 2491 // 2. Load the address of the function entry point from the function 2492 // descriptor. 2493 // 3. Load the TOC of the callee from the function descriptor into r2. 2494 // 4. Load the environment pointer from the function descriptor into 2495 // r11. 2496 // 5. Branch to the function entry point address. 2497 // 6. On return of the callee, the TOC of the caller needs to be 2498 // restored (this is done in FinishCall()). 2499 // 2500 // All those operations are flagged together to ensure that no other 2501 // operations can be scheduled in between. E.g. without flagging the 2502 // operations together, a TOC access in the caller could be scheduled 2503 // between the load of the callee TOC and the branch to the callee, which 2504 // results in the TOC access going through the TOC of the callee instead 2505 // of going through the TOC of the caller, which leads to incorrect code. 2506 2507 // Load the address of the function entry point from the function 2508 // descriptor. 2509 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Flag); 2510 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps, 2511 InFlag.getNode() ? 3 : 2); 2512 Chain = LoadFuncPtr.getValue(1); 2513 InFlag = LoadFuncPtr.getValue(2); 2514 2515 // Load environment pointer into r11. 2516 // Offset of the environment pointer within the function descriptor. 2517 SDValue PtrOff = DAG.getIntPtrConstant(16); 2518 2519 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff); 2520 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr, 2521 InFlag); 2522 Chain = LoadEnvPtr.getValue(1); 2523 InFlag = LoadEnvPtr.getValue(2); 2524 2525 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr, 2526 InFlag); 2527 Chain = EnvVal.getValue(0); 2528 InFlag = EnvVal.getValue(1); 2529 2530 // Load TOC of the callee into r2. We are using a target-specific load 2531 // with r2 hard coded, because the result of a target-independent load 2532 // would never go directly into r2, since r2 is a reserved register (which 2533 // prevents the register allocator from allocating it), resulting in an 2534 // additional register being allocated and an unnecessary move instruction 2535 // being generated. 2536 VTs = DAG.getVTList(MVT::Other, MVT::Flag); 2537 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, 2538 Callee, InFlag); 2539 Chain = LoadTOCPtr.getValue(0); 2540 InFlag = LoadTOCPtr.getValue(1); 2541 2542 MTCTROps[0] = Chain; 2543 MTCTROps[1] = LoadFuncPtr; 2544 MTCTROps[2] = InFlag; 2545 } 2546 2547 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps, 2548 2 + (InFlag.getNode() != 0)); 2549 InFlag = Chain.getValue(1); 2550 2551 NodeTys.clear(); 2552 NodeTys.push_back(MVT::Other); 2553 NodeTys.push_back(MVT::Flag); 2554 Ops.push_back(Chain); 2555 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin; 2556 Callee.setNode(0); 2557 // Add CTR register as callee so a bctr can be emitted later. 2558 if (isTailCall) 2559 Ops.push_back(DAG.getRegister(PPC::CTR, PtrVT)); 2560 } 2561 2562 // If this is a direct call, pass the chain and the callee. 2563 if (Callee.getNode()) { 2564 Ops.push_back(Chain); 2565 Ops.push_back(Callee); 2566 } 2567 // If this is a tail call add stack pointer delta. 2568 if (isTailCall) 2569 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); 2570 2571 // Add argument registers to the end of the list so that they are known live 2572 // into the call. 2573 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2574 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2575 RegsToPass[i].second.getValueType())); 2576 2577 return CallOpc; 2578} 2579 2580SDValue 2581PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2582 CallingConv::ID CallConv, bool isVarArg, 2583 const SmallVectorImpl<ISD::InputArg> &Ins, 2584 DebugLoc dl, SelectionDAG &DAG, 2585 SmallVectorImpl<SDValue> &InVals) { 2586 2587 SmallVector<CCValAssign, 16> RVLocs; 2588 CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(), 2589 RVLocs, *DAG.getContext()); 2590 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC); 2591 2592 // Copy all of the result registers out of their specified physreg. 2593 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2594 CCValAssign &VA = RVLocs[i]; 2595 EVT VT = VA.getValVT(); 2596 assert(VA.isRegLoc() && "Can only return in registers!"); 2597 Chain = DAG.getCopyFromReg(Chain, dl, 2598 VA.getLocReg(), VT, InFlag).getValue(1); 2599 InVals.push_back(Chain.getValue(0)); 2600 InFlag = Chain.getValue(2); 2601 } 2602 2603 return Chain; 2604} 2605 2606SDValue 2607PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl, 2608 bool isTailCall, bool isVarArg, 2609 SelectionDAG &DAG, 2610 SmallVector<std::pair<unsigned, SDValue>, 8> 2611 &RegsToPass, 2612 SDValue InFlag, SDValue Chain, 2613 SDValue &Callee, 2614 int SPDiff, unsigned NumBytes, 2615 const SmallVectorImpl<ISD::InputArg> &Ins, 2616 SmallVectorImpl<SDValue> &InVals) { 2617 std::vector<EVT> NodeTys; 2618 SmallVector<SDValue, 8> Ops; 2619 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff, 2620 isTailCall, RegsToPass, Ops, NodeTys, 2621 PPCSubTarget.isPPC64(), 2622 PPCSubTarget.isSVR4ABI()); 2623 2624 // When performing tail call optimization the callee pops its arguments off 2625 // the stack. Account for this here so these bytes can be pushed back on in 2626 // PPCRegisterInfo::eliminateCallFramePseudoInstr. 2627 int BytesCalleePops = 2628 (CallConv==CallingConv::Fast && GuaranteedTailCallOpt) ? NumBytes : 0; 2629 2630 if (InFlag.getNode()) 2631 Ops.push_back(InFlag); 2632 2633 // Emit tail call. 2634 if (isTailCall) { 2635 // If this is the first return lowered for this function, add the regs 2636 // to the liveout set for the function. 2637 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2638 SmallVector<CCValAssign, 16> RVLocs; 2639 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 2640 *DAG.getContext()); 2641 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC); 2642 for (unsigned i = 0; i != RVLocs.size(); ++i) 2643 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2644 } 2645 2646 assert(((Callee.getOpcode() == ISD::Register && 2647 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || 2648 Callee.getOpcode() == ISD::TargetExternalSymbol || 2649 Callee.getOpcode() == ISD::TargetGlobalAddress || 2650 isa<ConstantSDNode>(Callee)) && 2651 "Expecting an global address, external symbol, absolute value or register"); 2652 2653 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size()); 2654 } 2655 2656 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 2657 InFlag = Chain.getValue(1); 2658 2659 // Add a NOP immediately after the branch instruction when using the 64-bit 2660 // SVR4 ABI. At link time, if caller and callee are in a different module and 2661 // thus have a different TOC, the call will be replaced with a call to a stub 2662 // function which saves the current TOC, loads the TOC of the callee and 2663 // branches to the callee. The NOP will be replaced with a load instruction 2664 // which restores the TOC of the caller from the TOC save slot of the current 2665 // stack frame. If caller and callee belong to the same module (and have the 2666 // same TOC), the NOP will remain unchanged. 2667 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) { 2668 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag); 2669 if (CallOpc == PPCISD::BCTRL_SVR4) { 2670 // This is a call through a function pointer. 2671 // Restore the caller TOC from the save area into R2. 2672 // See PrepareCall() for more information about calls through function 2673 // pointers in the 64-bit SVR4 ABI. 2674 // We are using a target-specific load with r2 hard coded, because the 2675 // result of a target-independent load would never go directly into r2, 2676 // since r2 is a reserved register (which prevents the register allocator 2677 // from allocating it), resulting in an additional register being 2678 // allocated and an unnecessary move instruction being generated. 2679 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag); 2680 InFlag = Chain.getValue(1); 2681 } else { 2682 // Otherwise insert NOP. 2683 InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Flag, InFlag); 2684 } 2685 } 2686 2687 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2688 DAG.getIntPtrConstant(BytesCalleePops, true), 2689 InFlag); 2690 if (!Ins.empty()) 2691 InFlag = Chain.getValue(1); 2692 2693 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2694 Ins, dl, DAG, InVals); 2695} 2696 2697SDValue 2698PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2699 CallingConv::ID CallConv, bool isVarArg, 2700 bool &isTailCall, 2701 const SmallVectorImpl<ISD::OutputArg> &Outs, 2702 const SmallVectorImpl<ISD::InputArg> &Ins, 2703 DebugLoc dl, SelectionDAG &DAG, 2704 SmallVectorImpl<SDValue> &InVals) { 2705 if (isTailCall) 2706 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, 2707 Ins, DAG); 2708 2709 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) { 2710 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg, 2711 isTailCall, Outs, Ins, 2712 dl, DAG, InVals); 2713 } else { 2714 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg, 2715 isTailCall, Outs, Ins, 2716 dl, DAG, InVals); 2717 } 2718} 2719 2720SDValue 2721PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee, 2722 CallingConv::ID CallConv, bool isVarArg, 2723 bool isTailCall, 2724 const SmallVectorImpl<ISD::OutputArg> &Outs, 2725 const SmallVectorImpl<ISD::InputArg> &Ins, 2726 DebugLoc dl, SelectionDAG &DAG, 2727 SmallVectorImpl<SDValue> &InVals) { 2728 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description 2729 // of the 32-bit SVR4 ABI stack frame layout. 2730 2731 assert((CallConv == CallingConv::C || 2732 CallConv == CallingConv::Fast) && "Unknown calling convention!"); 2733 2734 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2735 unsigned PtrByteSize = 4; 2736 2737 MachineFunction &MF = DAG.getMachineFunction(); 2738 2739 // Mark this function as potentially containing a function that contains a 2740 // tail call. As a consequence the frame pointer will be used for dynamicalloc 2741 // and restoring the callers stack pointer in this functions epilog. This is 2742 // done because by tail calling the called function might overwrite the value 2743 // in this function's (MF) stack pointer stack slot 0(SP). 2744 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast) 2745 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 2746 2747 // Count how many bytes are to be pushed on the stack, including the linkage 2748 // area, parameter list area and the part of the local variable space which 2749 // contains copies of aggregates which are passed by value. 2750 2751 // Assign locations to all of the outgoing arguments. 2752 SmallVector<CCValAssign, 16> ArgLocs; 2753 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 2754 ArgLocs, *DAG.getContext()); 2755 2756 // Reserve space for the linkage area on the stack. 2757 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize); 2758 2759 if (isVarArg) { 2760 // Handle fixed and variable vector arguments differently. 2761 // Fixed vector arguments go into registers as long as registers are 2762 // available. Variable vector arguments always go into memory. 2763 unsigned NumArgs = Outs.size(); 2764 2765 for (unsigned i = 0; i != NumArgs; ++i) { 2766 EVT ArgVT = Outs[i].Val.getValueType(); 2767 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 2768 bool Result; 2769 2770 if (Outs[i].IsFixed) { 2771 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, 2772 CCInfo); 2773 } else { 2774 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, 2775 ArgFlags, CCInfo); 2776 } 2777 2778 if (Result) { 2779#ifndef NDEBUG 2780 errs() << "Call operand #" << i << " has unhandled type " 2781 << ArgVT.getEVTString() << "\n"; 2782#endif 2783 llvm_unreachable(0); 2784 } 2785 } 2786 } else { 2787 // All arguments are treated the same. 2788 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4); 2789 } 2790 2791 // Assign locations to all of the outgoing aggregate by value arguments. 2792 SmallVector<CCValAssign, 16> ByValArgLocs; 2793 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), ByValArgLocs, 2794 *DAG.getContext()); 2795 2796 // Reserve stack space for the allocations in CCInfo. 2797 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 2798 2799 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal); 2800 2801 // Size of the linkage area, parameter list area and the part of the local 2802 // space variable where copies of aggregates which are passed by value are 2803 // stored. 2804 unsigned NumBytes = CCByValInfo.getNextStackOffset(); 2805 2806 // Calculate by how many bytes the stack has to be adjusted in case of tail 2807 // call optimization. 2808 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 2809 2810 // Adjust the stack pointer for the new arguments... 2811 // These operations are automatically eliminated by the prolog/epilog pass 2812 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2813 SDValue CallSeqStart = Chain; 2814 2815 // Load the return address and frame pointer so it can be moved somewhere else 2816 // later. 2817 SDValue LROp, FPOp; 2818 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false, 2819 dl); 2820 2821 // Set up a copy of the stack pointer for use loading and storing any 2822 // arguments that may not fit in the registers available for argument 2823 // passing. 2824 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2825 2826 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2827 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 2828 SmallVector<SDValue, 8> MemOpChains; 2829 2830 // Walk the register/memloc assignments, inserting copies/loads. 2831 for (unsigned i = 0, j = 0, e = ArgLocs.size(); 2832 i != e; 2833 ++i) { 2834 CCValAssign &VA = ArgLocs[i]; 2835 SDValue Arg = Outs[i].Val; 2836 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2837 2838 if (Flags.isByVal()) { 2839 // Argument is an aggregate which is passed by value, thus we need to 2840 // create a copy of it in the local variable space of the current stack 2841 // frame (which is the stack frame of the caller) and pass the address of 2842 // this copy to the callee. 2843 assert((j < ByValArgLocs.size()) && "Index out of bounds!"); 2844 CCValAssign &ByValVA = ByValArgLocs[j++]; 2845 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"); 2846 2847 // Memory reserved in the local variable space of the callers stack frame. 2848 unsigned LocMemOffset = ByValVA.getLocMemOffset(); 2849 2850 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2851 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2852 2853 // Create a copy of the argument in the local area of the current 2854 // stack frame. 2855 SDValue MemcpyCall = 2856 CreateCopyOfByValArgument(Arg, PtrOff, 2857 CallSeqStart.getNode()->getOperand(0), 2858 Flags, DAG, dl); 2859 2860 // This must go outside the CALLSEQ_START..END. 2861 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 2862 CallSeqStart.getNode()->getOperand(1)); 2863 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 2864 NewCallSeqStart.getNode()); 2865 Chain = CallSeqStart = NewCallSeqStart; 2866 2867 // Pass the address of the aggregate copy on the stack either in a 2868 // physical register or in the parameter list area of the current stack 2869 // frame to the callee. 2870 Arg = PtrOff; 2871 } 2872 2873 if (VA.isRegLoc()) { 2874 // Put argument in a physical register. 2875 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2876 } else { 2877 // Put argument in the parameter list area of the current stack frame. 2878 assert(VA.isMemLoc()); 2879 unsigned LocMemOffset = VA.getLocMemOffset(); 2880 2881 if (!isTailCall) { 2882 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2883 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2884 2885 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2886 PseudoSourceValue::getStack(), LocMemOffset, 2887 false, false, 0)); 2888 } else { 2889 // Calculate and remember argument location. 2890 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset, 2891 TailCallArguments); 2892 } 2893 } 2894 } 2895 2896 if (!MemOpChains.empty()) 2897 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2898 &MemOpChains[0], MemOpChains.size()); 2899 2900 // Build a sequence of copy-to-reg nodes chained together with token chain 2901 // and flag operands which copy the outgoing args into the appropriate regs. 2902 SDValue InFlag; 2903 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2904 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2905 RegsToPass[i].second, InFlag); 2906 InFlag = Chain.getValue(1); 2907 } 2908 2909 // Set CR6 to true if this is a vararg call. 2910 if (isVarArg) { 2911 SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0); 2912 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag); 2913 InFlag = Chain.getValue(1); 2914 } 2915 2916 if (isTailCall) { 2917 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp, 2918 false, TailCallArguments); 2919 } 2920 2921 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 2922 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 2923 Ins, InVals); 2924} 2925 2926SDValue 2927PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, 2928 CallingConv::ID CallConv, bool isVarArg, 2929 bool isTailCall, 2930 const SmallVectorImpl<ISD::OutputArg> &Outs, 2931 const SmallVectorImpl<ISD::InputArg> &Ins, 2932 DebugLoc dl, SelectionDAG &DAG, 2933 SmallVectorImpl<SDValue> &InVals) { 2934 2935 unsigned NumOps = Outs.size(); 2936 2937 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2938 bool isPPC64 = PtrVT == MVT::i64; 2939 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2940 2941 MachineFunction &MF = DAG.getMachineFunction(); 2942 2943 // Mark this function as potentially containing a function that contains a 2944 // tail call. As a consequence the frame pointer will be used for dynamicalloc 2945 // and restoring the callers stack pointer in this functions epilog. This is 2946 // done because by tail calling the called function might overwrite the value 2947 // in this function's (MF) stack pointer stack slot 0(SP). 2948 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast) 2949 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 2950 2951 unsigned nAltivecParamsAtEnd = 0; 2952 2953 // Count how many bytes are to be pushed on the stack, including the linkage 2954 // area, and parameter passing area. We start with 24/48 bytes, which is 2955 // prereserved space for [SP][CR][LR][3 x unused]. 2956 unsigned NumBytes = 2957 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv, 2958 Outs, 2959 nAltivecParamsAtEnd); 2960 2961 // Calculate by how many bytes the stack has to be adjusted in case of tail 2962 // call optimization. 2963 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 2964 2965 // To protect arguments on the stack from being clobbered in a tail call, 2966 // force all the loads to happen before doing any other lowering. 2967 if (isTailCall) 2968 Chain = DAG.getStackArgumentTokenFactor(Chain); 2969 2970 // Adjust the stack pointer for the new arguments... 2971 // These operations are automatically eliminated by the prolog/epilog pass 2972 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2973 SDValue CallSeqStart = Chain; 2974 2975 // Load the return address and frame pointer so it can be move somewhere else 2976 // later. 2977 SDValue LROp, FPOp; 2978 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 2979 dl); 2980 2981 // Set up a copy of the stack pointer for use loading and storing any 2982 // arguments that may not fit in the registers available for argument 2983 // passing. 2984 SDValue StackPtr; 2985 if (isPPC64) 2986 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2987 else 2988 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2989 2990 // Figure out which arguments are going to go in registers, and which in 2991 // memory. Also, if this is a vararg function, floating point operations 2992 // must be stored to our stack, and loaded into integer regs as well, if 2993 // any integer regs are available for argument passing. 2994 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true); 2995 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 2996 2997 static const unsigned GPR_32[] = { // 32-bit registers. 2998 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 2999 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 3000 }; 3001 static const unsigned GPR_64[] = { // 64-bit registers. 3002 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 3003 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 3004 }; 3005 static const unsigned *FPR = GetFPR(); 3006 3007 static const unsigned VR[] = { 3008 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 3009 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 3010 }; 3011 const unsigned NumGPRs = array_lengthof(GPR_32); 3012 const unsigned NumFPRs = 13; 3013 const unsigned NumVRs = array_lengthof(VR); 3014 3015 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 3016 3017 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3018 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3019 3020 SmallVector<SDValue, 8> MemOpChains; 3021 for (unsigned i = 0; i != NumOps; ++i) { 3022 SDValue Arg = Outs[i].Val; 3023 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3024 3025 // PtrOff will be used to store the current argument to the stack if a 3026 // register cannot be found for it. 3027 SDValue PtrOff; 3028 3029 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 3030 3031 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3032 3033 // On PPC64, promote integers to 64-bit values. 3034 if (isPPC64 && Arg.getValueType() == MVT::i32) { 3035 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 3036 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3037 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 3038 } 3039 3040 // FIXME memcpy is used way more than necessary. Correctness first. 3041 if (Flags.isByVal()) { 3042 unsigned Size = Flags.getByValSize(); 3043 if (Size==1 || Size==2) { 3044 // Very small objects are passed right-justified. 3045 // Everything else is passed left-justified. 3046 EVT VT = (Size==1) ? MVT::i8 : MVT::i16; 3047 if (GPR_idx != NumGPRs) { 3048 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, 3049 NULL, 0, VT, false, false, 0); 3050 MemOpChains.push_back(Load.getValue(1)); 3051 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3052 3053 ArgOffset += PtrByteSize; 3054 } else { 3055 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType()); 3056 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3057 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, 3058 CallSeqStart.getNode()->getOperand(0), 3059 Flags, DAG, dl); 3060 // This must go outside the CALLSEQ_START..END. 3061 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3062 CallSeqStart.getNode()->getOperand(1)); 3063 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3064 NewCallSeqStart.getNode()); 3065 Chain = CallSeqStart = NewCallSeqStart; 3066 ArgOffset += PtrByteSize; 3067 } 3068 continue; 3069 } 3070 // Copy entire object into memory. There are cases where gcc-generated 3071 // code assumes it is there, even if it could be put entirely into 3072 // registers. (This is not what the doc says.) 3073 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, 3074 CallSeqStart.getNode()->getOperand(0), 3075 Flags, DAG, dl); 3076 // This must go outside the CALLSEQ_START..END. 3077 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3078 CallSeqStart.getNode()->getOperand(1)); 3079 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode()); 3080 Chain = CallSeqStart = NewCallSeqStart; 3081 // And copy the pieces of it that fit into registers. 3082 for (unsigned j=0; j<Size; j+=PtrByteSize) { 3083 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 3084 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 3085 if (GPR_idx != NumGPRs) { 3086 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, NULL, 0, 3087 false, false, 0); 3088 MemOpChains.push_back(Load.getValue(1)); 3089 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3090 ArgOffset += PtrByteSize; 3091 } else { 3092 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 3093 break; 3094 } 3095 } 3096 continue; 3097 } 3098 3099 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 3100 default: llvm_unreachable("Unexpected ValueType for argument!"); 3101 case MVT::i32: 3102 case MVT::i64: 3103 if (GPR_idx != NumGPRs) { 3104 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 3105 } else { 3106 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3107 isPPC64, isTailCall, false, MemOpChains, 3108 TailCallArguments, dl); 3109 } 3110 ArgOffset += PtrByteSize; 3111 break; 3112 case MVT::f32: 3113 case MVT::f64: 3114 if (FPR_idx != NumFPRs) { 3115 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 3116 3117 if (isVarArg) { 3118 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0, 3119 false, false, 0); 3120 MemOpChains.push_back(Store); 3121 3122 // Float varargs are always shadowed in available integer registers 3123 if (GPR_idx != NumGPRs) { 3124 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0, 3125 false, false, 0); 3126 MemOpChains.push_back(Load.getValue(1)); 3127 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3128 } 3129 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 3130 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3131 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 3132 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0, 3133 false, false, 0); 3134 MemOpChains.push_back(Load.getValue(1)); 3135 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3136 } 3137 } else { 3138 // If we have any FPRs remaining, we may also have GPRs remaining. 3139 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 3140 // GPRs. 3141 if (GPR_idx != NumGPRs) 3142 ++GPR_idx; 3143 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 3144 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 3145 ++GPR_idx; 3146 } 3147 } else { 3148 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3149 isPPC64, isTailCall, false, MemOpChains, 3150 TailCallArguments, dl); 3151 } 3152 if (isPPC64) 3153 ArgOffset += 8; 3154 else 3155 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 3156 break; 3157 case MVT::v4f32: 3158 case MVT::v4i32: 3159 case MVT::v8i16: 3160 case MVT::v16i8: 3161 if (isVarArg) { 3162 // These go aligned on the stack, or in the corresponding R registers 3163 // when within range. The Darwin PPC ABI doc claims they also go in 3164 // V registers; in fact gcc does this only for arguments that are 3165 // prototyped, not for those that match the ... We do it for all 3166 // arguments, seems to work. 3167 while (ArgOffset % 16 !=0) { 3168 ArgOffset += PtrByteSize; 3169 if (GPR_idx != NumGPRs) 3170 GPR_idx++; 3171 } 3172 // We could elide this store in the case where the object fits 3173 // entirely in R registers. Maybe later. 3174 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 3175 DAG.getConstant(ArgOffset, PtrVT)); 3176 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0, 3177 false, false, 0); 3178 MemOpChains.push_back(Store); 3179 if (VR_idx != NumVRs) { 3180 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0, 3181 false, false, 0); 3182 MemOpChains.push_back(Load.getValue(1)); 3183 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 3184 } 3185 ArgOffset += 16; 3186 for (unsigned i=0; i<16; i+=PtrByteSize) { 3187 if (GPR_idx == NumGPRs) 3188 break; 3189 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 3190 DAG.getConstant(i, PtrVT)); 3191 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, NULL, 0, 3192 false, false, 0); 3193 MemOpChains.push_back(Load.getValue(1)); 3194 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3195 } 3196 break; 3197 } 3198 3199 // Non-varargs Altivec params generally go in registers, but have 3200 // stack space allocated at the end. 3201 if (VR_idx != NumVRs) { 3202 // Doesn't have GPR space allocated. 3203 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 3204 } else if (nAltivecParamsAtEnd==0) { 3205 // We are emitting Altivec params in order. 3206 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3207 isPPC64, isTailCall, true, MemOpChains, 3208 TailCallArguments, dl); 3209 ArgOffset += 16; 3210 } 3211 break; 3212 } 3213 } 3214 // If all Altivec parameters fit in registers, as they usually do, 3215 // they get stack space following the non-Altivec parameters. We 3216 // don't track this here because nobody below needs it. 3217 // If there are more Altivec parameters than fit in registers emit 3218 // the stores here. 3219 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) { 3220 unsigned j = 0; 3221 // Offset is aligned; skip 1st 12 params which go in V registers. 3222 ArgOffset = ((ArgOffset+15)/16)*16; 3223 ArgOffset += 12*16; 3224 for (unsigned i = 0; i != NumOps; ++i) { 3225 SDValue Arg = Outs[i].Val; 3226 EVT ArgType = Arg.getValueType(); 3227 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || 3228 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { 3229 if (++j > NumVRs) { 3230 SDValue PtrOff; 3231 // We are emitting Altivec params in order. 3232 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3233 isPPC64, isTailCall, true, MemOpChains, 3234 TailCallArguments, dl); 3235 ArgOffset += 16; 3236 } 3237 } 3238 } 3239 } 3240 3241 if (!MemOpChains.empty()) 3242 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3243 &MemOpChains[0], MemOpChains.size()); 3244 3245 // Check if this is an indirect call (MTCTR/BCTRL). 3246 // See PrepareCall() for more information about calls through function 3247 // pointers in the 64-bit SVR4 ABI. 3248 if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() && 3249 !dyn_cast<GlobalAddressSDNode>(Callee) && 3250 !dyn_cast<ExternalSymbolSDNode>(Callee) && 3251 !isBLACompatibleAddress(Callee, DAG)) { 3252 // Load r2 into a virtual register and store it to the TOC save area. 3253 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); 3254 // TOC save area offset. 3255 SDValue PtrOff = DAG.getIntPtrConstant(40); 3256 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3257 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, NULL, 0, 3258 false, false, 0); 3259 } 3260 3261 // On Darwin, R12 must contain the address of an indirect callee. This does 3262 // not mean the MTCTR instruction must use R12; it's easier to model this as 3263 // an extra parameter, so do that. 3264 if (!isTailCall && 3265 !dyn_cast<GlobalAddressSDNode>(Callee) && 3266 !dyn_cast<ExternalSymbolSDNode>(Callee) && 3267 !isBLACompatibleAddress(Callee, DAG)) 3268 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 : 3269 PPC::R12), Callee)); 3270 3271 // Build a sequence of copy-to-reg nodes chained together with token chain 3272 // and flag operands which copy the outgoing args into the appropriate regs. 3273 SDValue InFlag; 3274 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3275 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3276 RegsToPass[i].second, InFlag); 3277 InFlag = Chain.getValue(1); 3278 } 3279 3280 if (isTailCall) { 3281 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp, 3282 FPOp, true, TailCallArguments); 3283 } 3284 3285 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 3286 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 3287 Ins, InVals); 3288} 3289 3290SDValue 3291PPCTargetLowering::LowerReturn(SDValue Chain, 3292 CallingConv::ID CallConv, bool isVarArg, 3293 const SmallVectorImpl<ISD::OutputArg> &Outs, 3294 DebugLoc dl, SelectionDAG &DAG) { 3295 3296 SmallVector<CCValAssign, 16> RVLocs; 3297 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 3298 RVLocs, *DAG.getContext()); 3299 CCInfo.AnalyzeReturn(Outs, RetCC_PPC); 3300 3301 // If this is the first return lowered for this function, add the regs to the 3302 // liveout set for the function. 3303 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 3304 for (unsigned i = 0; i != RVLocs.size(); ++i) 3305 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 3306 } 3307 3308 SDValue Flag; 3309 3310 // Copy the result values into the output registers. 3311 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3312 CCValAssign &VA = RVLocs[i]; 3313 assert(VA.isRegLoc() && "Can only return in registers!"); 3314 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 3315 Outs[i].Val, Flag); 3316 Flag = Chain.getValue(1); 3317 } 3318 3319 if (Flag.getNode()) 3320 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 3321 else 3322 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain); 3323} 3324 3325SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 3326 const PPCSubtarget &Subtarget) { 3327 // When we pop the dynamic allocation we need to restore the SP link. 3328 DebugLoc dl = Op.getDebugLoc(); 3329 3330 // Get the corect type for pointers. 3331 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3332 3333 // Construct the stack pointer operand. 3334 bool isPPC64 = Subtarget.isPPC64(); 3335 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; 3336 SDValue StackPtr = DAG.getRegister(SP, PtrVT); 3337 3338 // Get the operands for the STACKRESTORE. 3339 SDValue Chain = Op.getOperand(0); 3340 SDValue SaveSP = Op.getOperand(1); 3341 3342 // Load the old link SP. 3343 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0, 3344 false, false, 0); 3345 3346 // Restore the stack pointer. 3347 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); 3348 3349 // Store the old link SP. 3350 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0, 3351 false, false, 0); 3352} 3353 3354 3355 3356SDValue 3357PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { 3358 MachineFunction &MF = DAG.getMachineFunction(); 3359 bool isPPC64 = PPCSubTarget.isPPC64(); 3360 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 3361 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3362 3363 // Get current frame pointer save index. The users of this index will be 3364 // primarily DYNALLOC instructions. 3365 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3366 int RASI = FI->getReturnAddrSaveIndex(); 3367 3368 // If the frame pointer save index hasn't been defined yet. 3369 if (!RASI) { 3370 // Find out what the fix offset of the frame pointer save area. 3371 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI); 3372 // Allocate the frame index for frame pointer save area. 3373 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, 3374 true, false); 3375 // Save the result. 3376 FI->setReturnAddrSaveIndex(RASI); 3377 } 3378 return DAG.getFrameIndex(RASI, PtrVT); 3379} 3380 3381SDValue 3382PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { 3383 MachineFunction &MF = DAG.getMachineFunction(); 3384 bool isPPC64 = PPCSubTarget.isPPC64(); 3385 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 3386 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3387 3388 // Get current frame pointer save index. The users of this index will be 3389 // primarily DYNALLOC instructions. 3390 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3391 int FPSI = FI->getFramePointerSaveIndex(); 3392 3393 // If the frame pointer save index hasn't been defined yet. 3394 if (!FPSI) { 3395 // Find out what the fix offset of the frame pointer save area. 3396 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, 3397 isDarwinABI); 3398 3399 // Allocate the frame index for frame pointer save area. 3400 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, 3401 true, false); 3402 // Save the result. 3403 FI->setFramePointerSaveIndex(FPSI); 3404 } 3405 return DAG.getFrameIndex(FPSI, PtrVT); 3406} 3407 3408SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 3409 SelectionDAG &DAG, 3410 const PPCSubtarget &Subtarget) { 3411 // Get the inputs. 3412 SDValue Chain = Op.getOperand(0); 3413 SDValue Size = Op.getOperand(1); 3414 DebugLoc dl = Op.getDebugLoc(); 3415 3416 // Get the corect type for pointers. 3417 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3418 // Negate the size. 3419 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, 3420 DAG.getConstant(0, PtrVT), Size); 3421 // Construct a node for the frame pointer save index. 3422 SDValue FPSIdx = getFramePointerFrameIndex(DAG); 3423 // Build a DYNALLOC node. 3424 SDValue Ops[3] = { Chain, NegSize, FPSIdx }; 3425 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 3426 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3); 3427} 3428 3429/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 3430/// possible. 3431SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 3432 // Not FP? Not a fsel. 3433 if (!Op.getOperand(0).getValueType().isFloatingPoint() || 3434 !Op.getOperand(2).getValueType().isFloatingPoint()) 3435 return Op; 3436 3437 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 3438 3439 // Cannot handle SETEQ/SETNE. 3440 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op; 3441 3442 EVT ResVT = Op.getValueType(); 3443 EVT CmpVT = Op.getOperand(0).getValueType(); 3444 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3445 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); 3446 DebugLoc dl = Op.getDebugLoc(); 3447 3448 // If the RHS of the comparison is a 0.0, we don't need to do the 3449 // subtraction at all. 3450 if (isFloatingPointZero(RHS)) 3451 switch (CC) { 3452 default: break; // SETUO etc aren't handled by fsel. 3453 case ISD::SETULT: 3454 case ISD::SETLT: 3455 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 3456 case ISD::SETOGE: 3457 case ISD::SETGE: 3458 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 3459 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 3460 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); 3461 case ISD::SETUGT: 3462 case ISD::SETGT: 3463 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 3464 case ISD::SETOLE: 3465 case ISD::SETLE: 3466 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 3467 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 3468 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 3469 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); 3470 } 3471 3472 SDValue Cmp; 3473 switch (CC) { 3474 default: break; // SETUO etc aren't handled by fsel. 3475 case ISD::SETULT: 3476 case ISD::SETLT: 3477 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 3478 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3479 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3480 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 3481 case ISD::SETOGE: 3482 case ISD::SETGE: 3483 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 3484 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3485 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3486 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 3487 case ISD::SETUGT: 3488 case ISD::SETGT: 3489 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 3490 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3491 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3492 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 3493 case ISD::SETOLE: 3494 case ISD::SETLE: 3495 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 3496 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3497 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3498 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 3499 } 3500 return Op; 3501} 3502 3503// FIXME: Split this code up when LegalizeDAGTypes lands. 3504SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 3505 DebugLoc dl) { 3506 assert(Op.getOperand(0).getValueType().isFloatingPoint()); 3507 SDValue Src = Op.getOperand(0); 3508 if (Src.getValueType() == MVT::f32) 3509 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); 3510 3511 SDValue Tmp; 3512 switch (Op.getValueType().getSimpleVT().SimpleTy) { 3513 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); 3514 case MVT::i32: 3515 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : 3516 PPCISD::FCTIDZ, 3517 dl, MVT::f64, Src); 3518 break; 3519 case MVT::i64: 3520 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src); 3521 break; 3522 } 3523 3524 // Convert the FP value to an int value through memory. 3525 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); 3526 3527 // Emit a store to the stack slot. 3528 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0, 3529 false, false, 0); 3530 3531 // Result is a load from the stack slot. If loading 4 bytes, make sure to 3532 // add in a bias. 3533 if (Op.getValueType() == MVT::i32) 3534 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, 3535 DAG.getConstant(4, FIPtr.getValueType())); 3536 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0, 3537 false, false, 0); 3538} 3539 3540SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 3541 DebugLoc dl = Op.getDebugLoc(); 3542 // Don't handle ppc_fp128 here; let it be lowered to a libcall. 3543 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) 3544 return SDValue(); 3545 3546 if (Op.getOperand(0).getValueType() == MVT::i64) { 3547 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl, 3548 MVT::f64, Op.getOperand(0)); 3549 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); 3550 if (Op.getValueType() == MVT::f32) 3551 FP = DAG.getNode(ISD::FP_ROUND, dl, 3552 MVT::f32, FP, DAG.getIntPtrConstant(0)); 3553 return FP; 3554 } 3555 3556 assert(Op.getOperand(0).getValueType() == MVT::i32 && 3557 "Unhandled SINT_TO_FP type in custom expander!"); 3558 // Since we only generate this in 64-bit mode, we can take advantage of 3559 // 64-bit registers. In particular, sign extend the input value into the 3560 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 3561 // then lfd it and fcfid it. 3562 MachineFunction &MF = DAG.getMachineFunction(); 3563 MachineFrameInfo *FrameInfo = MF.getFrameInfo(); 3564 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false); 3565 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3566 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 3567 3568 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32, 3569 Op.getOperand(0)); 3570 3571 // STD the extended value into the stack slot. 3572 MachineMemOperand *MMO = 3573 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx), 3574 MachineMemOperand::MOStore, 0, 8, 8); 3575 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx }; 3576 SDValue Store = 3577 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other), 3578 Ops, 4, MVT::i64, MMO); 3579 // Load the value as a double. 3580 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0, false, false, 0); 3581 3582 // FCFID it and return it. 3583 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); 3584 if (Op.getValueType() == MVT::f32) 3585 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); 3586 return FP; 3587} 3588 3589SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { 3590 DebugLoc dl = Op.getDebugLoc(); 3591 /* 3592 The rounding mode is in bits 30:31 of FPSR, and has the following 3593 settings: 3594 00 Round to nearest 3595 01 Round to 0 3596 10 Round to +inf 3597 11 Round to -inf 3598 3599 FLT_ROUNDS, on the other hand, expects the following: 3600 -1 Undefined 3601 0 Round to 0 3602 1 Round to nearest 3603 2 Round to +inf 3604 3 Round to -inf 3605 3606 To perform the conversion, we do: 3607 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 3608 */ 3609 3610 MachineFunction &MF = DAG.getMachineFunction(); 3611 EVT VT = Op.getValueType(); 3612 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3613 std::vector<EVT> NodeTys; 3614 SDValue MFFSreg, InFlag; 3615 3616 // Save FP Control Word to register 3617 NodeTys.push_back(MVT::f64); // return register 3618 NodeTys.push_back(MVT::Flag); // unused in this context 3619 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 3620 3621 // Save FP register to stack slot 3622 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 3623 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 3624 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, 3625 StackSlot, NULL, 0, false, false, 0); 3626 3627 // Load FP Control Word from low 32 bits of stack slot. 3628 SDValue Four = DAG.getConstant(4, PtrVT); 3629 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); 3630 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0, 3631 false, false, 0); 3632 3633 // Transform as necessary 3634 SDValue CWD1 = 3635 DAG.getNode(ISD::AND, dl, MVT::i32, 3636 CWD, DAG.getConstant(3, MVT::i32)); 3637 SDValue CWD2 = 3638 DAG.getNode(ISD::SRL, dl, MVT::i32, 3639 DAG.getNode(ISD::AND, dl, MVT::i32, 3640 DAG.getNode(ISD::XOR, dl, MVT::i32, 3641 CWD, DAG.getConstant(3, MVT::i32)), 3642 DAG.getConstant(3, MVT::i32)), 3643 DAG.getConstant(1, MVT::i32)); 3644 3645 SDValue RetVal = 3646 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); 3647 3648 return DAG.getNode((VT.getSizeInBits() < 16 ? 3649 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 3650} 3651 3652SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) { 3653 EVT VT = Op.getValueType(); 3654 unsigned BitWidth = VT.getSizeInBits(); 3655 DebugLoc dl = Op.getDebugLoc(); 3656 assert(Op.getNumOperands() == 3 && 3657 VT == Op.getOperand(1).getValueType() && 3658 "Unexpected SHL!"); 3659 3660 // Expand into a bunch of logical ops. Note that these ops 3661 // depend on the PPC behavior for oversized shift amounts. 3662 SDValue Lo = Op.getOperand(0); 3663 SDValue Hi = Op.getOperand(1); 3664 SDValue Amt = Op.getOperand(2); 3665 EVT AmtVT = Amt.getValueType(); 3666 3667 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3668 DAG.getConstant(BitWidth, AmtVT), Amt); 3669 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); 3670 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); 3671 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); 3672 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3673 DAG.getConstant(-BitWidth, AmtVT)); 3674 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); 3675 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 3676 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); 3677 SDValue OutOps[] = { OutLo, OutHi }; 3678 return DAG.getMergeValues(OutOps, 2, dl); 3679} 3680 3681SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) { 3682 EVT VT = Op.getValueType(); 3683 DebugLoc dl = Op.getDebugLoc(); 3684 unsigned BitWidth = VT.getSizeInBits(); 3685 assert(Op.getNumOperands() == 3 && 3686 VT == Op.getOperand(1).getValueType() && 3687 "Unexpected SRL!"); 3688 3689 // Expand into a bunch of logical ops. Note that these ops 3690 // depend on the PPC behavior for oversized shift amounts. 3691 SDValue Lo = Op.getOperand(0); 3692 SDValue Hi = Op.getOperand(1); 3693 SDValue Amt = Op.getOperand(2); 3694 EVT AmtVT = Amt.getValueType(); 3695 3696 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3697 DAG.getConstant(BitWidth, AmtVT), Amt); 3698 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3699 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 3700 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 3701 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3702 DAG.getConstant(-BitWidth, AmtVT)); 3703 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); 3704 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 3705 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); 3706 SDValue OutOps[] = { OutLo, OutHi }; 3707 return DAG.getMergeValues(OutOps, 2, dl); 3708} 3709 3710SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) { 3711 DebugLoc dl = Op.getDebugLoc(); 3712 EVT VT = Op.getValueType(); 3713 unsigned BitWidth = VT.getSizeInBits(); 3714 assert(Op.getNumOperands() == 3 && 3715 VT == Op.getOperand(1).getValueType() && 3716 "Unexpected SRA!"); 3717 3718 // Expand into a bunch of logical ops, followed by a select_cc. 3719 SDValue Lo = Op.getOperand(0); 3720 SDValue Hi = Op.getOperand(1); 3721 SDValue Amt = Op.getOperand(2); 3722 EVT AmtVT = Amt.getValueType(); 3723 3724 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3725 DAG.getConstant(BitWidth, AmtVT), Amt); 3726 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3727 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 3728 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 3729 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3730 DAG.getConstant(-BitWidth, AmtVT)); 3731 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); 3732 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); 3733 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), 3734 Tmp4, Tmp6, ISD::SETLE); 3735 SDValue OutOps[] = { OutLo, OutHi }; 3736 return DAG.getMergeValues(OutOps, 2, dl); 3737} 3738 3739//===----------------------------------------------------------------------===// 3740// Vector related lowering. 3741// 3742 3743/// BuildSplatI - Build a canonical splati of Val with an element size of 3744/// SplatSize. Cast the result to VT. 3745static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT, 3746 SelectionDAG &DAG, DebugLoc dl) { 3747 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 3748 3749 static const EVT VTys[] = { // canonical VT to use for each size. 3750 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 3751 }; 3752 3753 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 3754 3755 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 3756 if (Val == -1) 3757 SplatSize = 1; 3758 3759 EVT CanonicalVT = VTys[SplatSize-1]; 3760 3761 // Build a canonical splat for this value. 3762 SDValue Elt = DAG.getConstant(Val, MVT::i32); 3763 SmallVector<SDValue, 8> Ops; 3764 Ops.assign(CanonicalVT.getVectorNumElements(), Elt); 3765 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, 3766 &Ops[0], Ops.size()); 3767 return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res); 3768} 3769 3770/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 3771/// specified intrinsic ID. 3772static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, 3773 SelectionDAG &DAG, DebugLoc dl, 3774 EVT DestVT = MVT::Other) { 3775 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 3776 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 3777 DAG.getConstant(IID, MVT::i32), LHS, RHS); 3778} 3779 3780/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 3781/// specified intrinsic ID. 3782static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, 3783 SDValue Op2, SelectionDAG &DAG, 3784 DebugLoc dl, EVT DestVT = MVT::Other) { 3785 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 3786 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 3787 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 3788} 3789 3790 3791/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 3792/// amount. The result has the specified value type. 3793static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, 3794 EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3795 // Force LHS/RHS to be the right type. 3796 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS); 3797 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS); 3798 3799 int Ops[16]; 3800 for (unsigned i = 0; i != 16; ++i) 3801 Ops[i] = i + Amt; 3802 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); 3803 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T); 3804} 3805 3806// If this is a case we can't handle, return null and let the default 3807// expansion code take care of it. If we CAN select this case, and if it 3808// selects to a single instruction, return Op. Otherwise, if we can codegen 3809// this case more efficiently than a constant pool load, lower it to the 3810// sequence of ops that should be used. 3811SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { 3812 DebugLoc dl = Op.getDebugLoc(); 3813 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 3814 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR"); 3815 3816 // Check if this is a splat of a constant value. 3817 APInt APSplatBits, APSplatUndef; 3818 unsigned SplatBitSize; 3819 bool HasAnyUndefs; 3820 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize, 3821 HasAnyUndefs, 0, true) || SplatBitSize > 32) 3822 return SDValue(); 3823 3824 unsigned SplatBits = APSplatBits.getZExtValue(); 3825 unsigned SplatUndef = APSplatUndef.getZExtValue(); 3826 unsigned SplatSize = SplatBitSize / 8; 3827 3828 // First, handle single instruction cases. 3829 3830 // All zeros? 3831 if (SplatBits == 0) { 3832 // Canonicalize all zero vectors to be v4i32. 3833 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 3834 SDValue Z = DAG.getConstant(0, MVT::i32); 3835 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); 3836 Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z); 3837 } 3838 return Op; 3839 } 3840 3841 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 3842 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >> 3843 (32-SplatBitSize)); 3844 if (SextVal >= -16 && SextVal <= 15) 3845 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl); 3846 3847 3848 // Two instruction sequences. 3849 3850 // If this value is in the range [-32,30] and is even, use: 3851 // tmp = VSPLTI[bhw], result = add tmp, tmp 3852 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 3853 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl); 3854 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res); 3855 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3856 } 3857 3858 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 3859 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 3860 // for fneg/fabs. 3861 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 3862 // Make -1 and vspltisw -1: 3863 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); 3864 3865 // Make the VSLW intrinsic, computing 0x8000_0000. 3866 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 3867 OnesV, DAG, dl); 3868 3869 // xor by OnesV to invert it. 3870 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); 3871 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3872 } 3873 3874 // Check to see if this is a wide variety of vsplti*, binop self cases. 3875 static const signed char SplatCsts[] = { 3876 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 3877 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 3878 }; 3879 3880 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 3881 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 3882 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 3883 int i = SplatCsts[idx]; 3884 3885 // Figure out what shift amount will be used by altivec if shifted by i in 3886 // this splat size. 3887 unsigned TypeShiftAmt = i & (SplatBitSize-1); 3888 3889 // vsplti + shl self. 3890 if (SextVal == (i << (int)TypeShiftAmt)) { 3891 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3892 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3893 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 3894 Intrinsic::ppc_altivec_vslw 3895 }; 3896 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3897 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3898 } 3899 3900 // vsplti + srl self. 3901 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 3902 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3903 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3904 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 3905 Intrinsic::ppc_altivec_vsrw 3906 }; 3907 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3908 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3909 } 3910 3911 // vsplti + sra self. 3912 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 3913 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3914 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3915 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 3916 Intrinsic::ppc_altivec_vsraw 3917 }; 3918 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3919 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3920 } 3921 3922 // vsplti + rol self. 3923 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 3924 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 3925 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3926 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3927 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 3928 Intrinsic::ppc_altivec_vrlw 3929 }; 3930 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3931 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3932 } 3933 3934 // t = vsplti c, result = vsldoi t, t, 1 3935 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { 3936 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3937 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); 3938 } 3939 // t = vsplti c, result = vsldoi t, t, 2 3940 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { 3941 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3942 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); 3943 } 3944 // t = vsplti c, result = vsldoi t, t, 3 3945 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { 3946 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3947 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); 3948 } 3949 } 3950 3951 // Three instruction sequences. 3952 3953 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 3954 if (SextVal >= 0 && SextVal <= 31) { 3955 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl); 3956 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 3957 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS); 3958 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS); 3959 } 3960 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 3961 if (SextVal >= -31 && SextVal <= 0) { 3962 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl); 3963 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 3964 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS); 3965 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS); 3966 } 3967 3968 return SDValue(); 3969} 3970 3971/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 3972/// the specified operations to build the shuffle. 3973static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 3974 SDValue RHS, SelectionDAG &DAG, 3975 DebugLoc dl) { 3976 unsigned OpNum = (PFEntry >> 26) & 0x0F; 3977 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 3978 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 3979 3980 enum { 3981 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 3982 OP_VMRGHW, 3983 OP_VMRGLW, 3984 OP_VSPLTISW0, 3985 OP_VSPLTISW1, 3986 OP_VSPLTISW2, 3987 OP_VSPLTISW3, 3988 OP_VSLDOI4, 3989 OP_VSLDOI8, 3990 OP_VSLDOI12 3991 }; 3992 3993 if (OpNum == OP_COPY) { 3994 if (LHSID == (1*9+2)*9+3) return LHS; 3995 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 3996 return RHS; 3997 } 3998 3999 SDValue OpLHS, OpRHS; 4000 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 4001 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 4002 4003 int ShufIdxs[16]; 4004 switch (OpNum) { 4005 default: llvm_unreachable("Unknown i32 permute!"); 4006 case OP_VMRGHW: 4007 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 4008 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 4009 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 4010 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 4011 break; 4012 case OP_VMRGLW: 4013 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 4014 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 4015 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 4016 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 4017 break; 4018 case OP_VSPLTISW0: 4019 for (unsigned i = 0; i != 16; ++i) 4020 ShufIdxs[i] = (i&3)+0; 4021 break; 4022 case OP_VSPLTISW1: 4023 for (unsigned i = 0; i != 16; ++i) 4024 ShufIdxs[i] = (i&3)+4; 4025 break; 4026 case OP_VSPLTISW2: 4027 for (unsigned i = 0; i != 16; ++i) 4028 ShufIdxs[i] = (i&3)+8; 4029 break; 4030 case OP_VSPLTISW3: 4031 for (unsigned i = 0; i != 16; ++i) 4032 ShufIdxs[i] = (i&3)+12; 4033 break; 4034 case OP_VSLDOI4: 4035 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl); 4036 case OP_VSLDOI8: 4037 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl); 4038 case OP_VSLDOI12: 4039 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl); 4040 } 4041 EVT VT = OpLHS.getValueType(); 4042 OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS); 4043 OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS); 4044 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); 4045 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T); 4046} 4047 4048/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 4049/// is a shuffle we can handle in a single instruction, return it. Otherwise, 4050/// return the code it can be lowered into. Worst case, it can always be 4051/// lowered into a vperm. 4052SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 4053 SelectionDAG &DAG) { 4054 DebugLoc dl = Op.getDebugLoc(); 4055 SDValue V1 = Op.getOperand(0); 4056 SDValue V2 = Op.getOperand(1); 4057 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4058 EVT VT = Op.getValueType(); 4059 4060 // Cases that are handled by instructions that take permute immediates 4061 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 4062 // selected by the instruction selector. 4063 if (V2.getOpcode() == ISD::UNDEF) { 4064 if (PPC::isSplatShuffleMask(SVOp, 1) || 4065 PPC::isSplatShuffleMask(SVOp, 2) || 4066 PPC::isSplatShuffleMask(SVOp, 4) || 4067 PPC::isVPKUWUMShuffleMask(SVOp, true) || 4068 PPC::isVPKUHUMShuffleMask(SVOp, true) || 4069 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 || 4070 PPC::isVMRGLShuffleMask(SVOp, 1, true) || 4071 PPC::isVMRGLShuffleMask(SVOp, 2, true) || 4072 PPC::isVMRGLShuffleMask(SVOp, 4, true) || 4073 PPC::isVMRGHShuffleMask(SVOp, 1, true) || 4074 PPC::isVMRGHShuffleMask(SVOp, 2, true) || 4075 PPC::isVMRGHShuffleMask(SVOp, 4, true)) { 4076 return Op; 4077 } 4078 } 4079 4080 // Altivec has a variety of "shuffle immediates" that take two vector inputs 4081 // and produce a fixed permutation. If any of these match, do not lower to 4082 // VPERM. 4083 if (PPC::isVPKUWUMShuffleMask(SVOp, false) || 4084 PPC::isVPKUHUMShuffleMask(SVOp, false) || 4085 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 || 4086 PPC::isVMRGLShuffleMask(SVOp, 1, false) || 4087 PPC::isVMRGLShuffleMask(SVOp, 2, false) || 4088 PPC::isVMRGLShuffleMask(SVOp, 4, false) || 4089 PPC::isVMRGHShuffleMask(SVOp, 1, false) || 4090 PPC::isVMRGHShuffleMask(SVOp, 2, false) || 4091 PPC::isVMRGHShuffleMask(SVOp, 4, false)) 4092 return Op; 4093 4094 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 4095 // perfect shuffle table to emit an optimal matching sequence. 4096 SmallVector<int, 16> PermMask; 4097 SVOp->getMask(PermMask); 4098 4099 unsigned PFIndexes[4]; 4100 bool isFourElementShuffle = true; 4101 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 4102 unsigned EltNo = 8; // Start out undef. 4103 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 4104 if (PermMask[i*4+j] < 0) 4105 continue; // Undef, ignore it. 4106 4107 unsigned ByteSource = PermMask[i*4+j]; 4108 if ((ByteSource & 3) != j) { 4109 isFourElementShuffle = false; 4110 break; 4111 } 4112 4113 if (EltNo == 8) { 4114 EltNo = ByteSource/4; 4115 } else if (EltNo != ByteSource/4) { 4116 isFourElementShuffle = false; 4117 break; 4118 } 4119 } 4120 PFIndexes[i] = EltNo; 4121 } 4122 4123 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 4124 // perfect shuffle vector to determine if it is cost effective to do this as 4125 // discrete instructions, or whether we should use a vperm. 4126 if (isFourElementShuffle) { 4127 // Compute the index in the perfect shuffle table. 4128 unsigned PFTableIndex = 4129 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4130 4131 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4132 unsigned Cost = (PFEntry >> 30); 4133 4134 // Determining when to avoid vperm is tricky. Many things affect the cost 4135 // of vperm, particularly how many times the perm mask needs to be computed. 4136 // For example, if the perm mask can be hoisted out of a loop or is already 4137 // used (perhaps because there are multiple permutes with the same shuffle 4138 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 4139 // the loop requires an extra register. 4140 // 4141 // As a compromise, we only emit discrete instructions if the shuffle can be 4142 // generated in 3 or fewer operations. When we have loop information 4143 // available, if this block is within a loop, we should avoid using vperm 4144 // for 3-operation perms and use a constant pool load instead. 4145 if (Cost < 3) 4146 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 4147 } 4148 4149 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 4150 // vector that will get spilled to the constant pool. 4151 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 4152 4153 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 4154 // that it is in input element units, not in bytes. Convert now. 4155 EVT EltVT = V1.getValueType().getVectorElementType(); 4156 unsigned BytesPerElement = EltVT.getSizeInBits()/8; 4157 4158 SmallVector<SDValue, 16> ResultMask; 4159 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { 4160 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i]; 4161 4162 for (unsigned j = 0; j != BytesPerElement; ++j) 4163 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 4164 MVT::i32)); 4165 } 4166 4167 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, 4168 &ResultMask[0], ResultMask.size()); 4169 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); 4170} 4171 4172/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 4173/// altivec comparison. If it is, return true and fill in Opc/isDot with 4174/// information about the intrinsic. 4175static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, 4176 bool &isDot) { 4177 unsigned IntrinsicID = 4178 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue(); 4179 CompareOpc = -1; 4180 isDot = false; 4181 switch (IntrinsicID) { 4182 default: return false; 4183 // Comparison predicates. 4184 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 4185 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 4186 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 4187 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 4188 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 4189 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 4190 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 4191 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 4192 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 4193 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 4194 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 4195 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 4196 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 4197 4198 // Normal Comparisons. 4199 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 4200 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 4201 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 4202 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 4203 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 4204 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 4205 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 4206 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 4207 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 4208 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 4209 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 4210 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 4211 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 4212 } 4213 return true; 4214} 4215 4216/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 4217/// lower, do it, otherwise return null. 4218SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 4219 SelectionDAG &DAG) { 4220 // If this is a lowered altivec predicate compare, CompareOpc is set to the 4221 // opcode number of the comparison. 4222 DebugLoc dl = Op.getDebugLoc(); 4223 int CompareOpc; 4224 bool isDot; 4225 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 4226 return SDValue(); // Don't custom lower most intrinsics. 4227 4228 // If this is a non-dot comparison, make the VCMP node and we are done. 4229 if (!isDot) { 4230 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), 4231 Op.getOperand(1), Op.getOperand(2), 4232 DAG.getConstant(CompareOpc, MVT::i32)); 4233 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp); 4234 } 4235 4236 // Create the PPCISD altivec 'dot' comparison node. 4237 SDValue Ops[] = { 4238 Op.getOperand(2), // LHS 4239 Op.getOperand(3), // RHS 4240 DAG.getConstant(CompareOpc, MVT::i32) 4241 }; 4242 std::vector<EVT> VTs; 4243 VTs.push_back(Op.getOperand(2).getValueType()); 4244 VTs.push_back(MVT::Flag); 4245 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 4246 4247 // Now that we have the comparison, emit a copy from the CR to a GPR. 4248 // This is flagged to the above dot comparison. 4249 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32, 4250 DAG.getRegister(PPC::CR6, MVT::i32), 4251 CompNode.getValue(1)); 4252 4253 // Unpack the result based on how the target uses it. 4254 unsigned BitNo; // Bit # of CR6. 4255 bool InvertBit; // Invert result? 4256 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) { 4257 default: // Can't happen, don't crash on invalid number though. 4258 case 0: // Return the value of the EQ bit of CR6. 4259 BitNo = 0; InvertBit = false; 4260 break; 4261 case 1: // Return the inverted value of the EQ bit of CR6. 4262 BitNo = 0; InvertBit = true; 4263 break; 4264 case 2: // Return the value of the LT bit of CR6. 4265 BitNo = 2; InvertBit = false; 4266 break; 4267 case 3: // Return the inverted value of the LT bit of CR6. 4268 BitNo = 2; InvertBit = true; 4269 break; 4270 } 4271 4272 // Shift the bit into the low position. 4273 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, 4274 DAG.getConstant(8-(3-BitNo), MVT::i32)); 4275 // Isolate the bit. 4276 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, 4277 DAG.getConstant(1, MVT::i32)); 4278 4279 // If we are supposed to, toggle the bit. 4280 if (InvertBit) 4281 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, 4282 DAG.getConstant(1, MVT::i32)); 4283 return Flags; 4284} 4285 4286SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, 4287 SelectionDAG &DAG) { 4288 DebugLoc dl = Op.getDebugLoc(); 4289 // Create a stack slot that is 16-byte aligned. 4290 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 4291 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false); 4292 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4293 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 4294 4295 // Store the input value into Value#0 of the stack slot. 4296 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 4297 Op.getOperand(0), FIdx, NULL, 0, 4298 false, false, 0); 4299 // Load it out. 4300 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0, 4301 false, false, 0); 4302} 4303 4304SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { 4305 DebugLoc dl = Op.getDebugLoc(); 4306 if (Op.getValueType() == MVT::v4i32) { 4307 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4308 4309 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); 4310 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. 4311 4312 SDValue RHSSwap = // = vrlw RHS, 16 4313 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); 4314 4315 // Shrinkify inputs to v8i16. 4316 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS); 4317 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS); 4318 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap); 4319 4320 // Low parts multiplied together, generating 32-bit results (we ignore the 4321 // top parts). 4322 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 4323 LHS, RHS, DAG, dl, MVT::v4i32); 4324 4325 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 4326 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); 4327 // Shift the high parts up 16 bits. 4328 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, 4329 Neg16, DAG, dl); 4330 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); 4331 } else if (Op.getValueType() == MVT::v8i16) { 4332 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4333 4334 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); 4335 4336 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 4337 LHS, RHS, Zero, DAG, dl); 4338 } else if (Op.getValueType() == MVT::v16i8) { 4339 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4340 4341 // Multiply the even 8-bit parts, producing 16-bit sums. 4342 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 4343 LHS, RHS, DAG, dl, MVT::v8i16); 4344 EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts); 4345 4346 // Multiply the odd 8-bit parts, producing 16-bit sums. 4347 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 4348 LHS, RHS, DAG, dl, MVT::v8i16); 4349 OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts); 4350 4351 // Merge the results together. 4352 int Ops[16]; 4353 for (unsigned i = 0; i != 8; ++i) { 4354 Ops[i*2 ] = 2*i+1; 4355 Ops[i*2+1] = 2*i+1+16; 4356 } 4357 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); 4358 } else { 4359 llvm_unreachable("Unknown mul to lower!"); 4360 } 4361} 4362 4363/// LowerOperation - Provide custom lowering hooks for some operations. 4364/// 4365SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 4366 switch (Op.getOpcode()) { 4367 default: llvm_unreachable("Wasn't expecting to be able to lower this!"); 4368 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 4369 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 4370 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 4371 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 4372 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 4373 case ISD::SETCC: return LowerSETCC(Op, DAG); 4374 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 4375 case ISD::VASTART: 4376 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 4377 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 4378 4379 case ISD::VAARG: 4380 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 4381 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 4382 4383 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 4384 case ISD::DYNAMIC_STACKALLOC: 4385 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 4386 4387 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 4388 case ISD::FP_TO_UINT: 4389 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, 4390 Op.getDebugLoc()); 4391 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 4392 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 4393 4394 // Lower 64-bit shifts. 4395 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 4396 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 4397 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 4398 4399 // Vector-related lowering. 4400 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 4401 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 4402 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 4403 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 4404 case ISD::MUL: return LowerMUL(Op, DAG); 4405 4406 // Frame & Return address. 4407 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 4408 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 4409 } 4410 return SDValue(); 4411} 4412 4413void PPCTargetLowering::ReplaceNodeResults(SDNode *N, 4414 SmallVectorImpl<SDValue>&Results, 4415 SelectionDAG &DAG) { 4416 DebugLoc dl = N->getDebugLoc(); 4417 switch (N->getOpcode()) { 4418 default: 4419 assert(false && "Do not know how to custom type legalize this operation!"); 4420 return; 4421 case ISD::FP_ROUND_INREG: { 4422 assert(N->getValueType(0) == MVT::ppcf128); 4423 assert(N->getOperand(0).getValueType() == MVT::ppcf128); 4424 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 4425 MVT::f64, N->getOperand(0), 4426 DAG.getIntPtrConstant(0)); 4427 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 4428 MVT::f64, N->getOperand(0), 4429 DAG.getIntPtrConstant(1)); 4430 4431 // This sequence changes FPSCR to do round-to-zero, adds the two halves 4432 // of the long double, and puts FPSCR back the way it was. We do not 4433 // actually model FPSCR. 4434 std::vector<EVT> NodeTys; 4435 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg; 4436 4437 NodeTys.push_back(MVT::f64); // Return register 4438 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns 4439 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 4440 MFFSreg = Result.getValue(0); 4441 InFlag = Result.getValue(1); 4442 4443 NodeTys.clear(); 4444 NodeTys.push_back(MVT::Flag); // Returns a flag 4445 Ops[0] = DAG.getConstant(31, MVT::i32); 4446 Ops[1] = InFlag; 4447 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2); 4448 InFlag = Result.getValue(0); 4449 4450 NodeTys.clear(); 4451 NodeTys.push_back(MVT::Flag); // Returns a flag 4452 Ops[0] = DAG.getConstant(30, MVT::i32); 4453 Ops[1] = InFlag; 4454 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2); 4455 InFlag = Result.getValue(0); 4456 4457 NodeTys.clear(); 4458 NodeTys.push_back(MVT::f64); // result of add 4459 NodeTys.push_back(MVT::Flag); // Returns a flag 4460 Ops[0] = Lo; 4461 Ops[1] = Hi; 4462 Ops[2] = InFlag; 4463 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3); 4464 FPreg = Result.getValue(0); 4465 InFlag = Result.getValue(1); 4466 4467 NodeTys.clear(); 4468 NodeTys.push_back(MVT::f64); 4469 Ops[0] = DAG.getConstant(1, MVT::i32); 4470 Ops[1] = MFFSreg; 4471 Ops[2] = FPreg; 4472 Ops[3] = InFlag; 4473 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4); 4474 FPreg = Result.getValue(0); 4475 4476 // We know the low half is about to be thrown away, so just use something 4477 // convenient. 4478 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, 4479 FPreg, FPreg)); 4480 return; 4481 } 4482 case ISD::FP_TO_SINT: 4483 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl)); 4484 return; 4485 } 4486} 4487 4488 4489//===----------------------------------------------------------------------===// 4490// Other Lowering Code 4491//===----------------------------------------------------------------------===// 4492 4493MachineBasicBlock * 4494PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 4495 bool is64bit, unsigned BinOpcode) const { 4496 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4497 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4498 4499 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4500 MachineFunction *F = BB->getParent(); 4501 MachineFunction::iterator It = BB; 4502 ++It; 4503 4504 unsigned dest = MI->getOperand(0).getReg(); 4505 unsigned ptrA = MI->getOperand(1).getReg(); 4506 unsigned ptrB = MI->getOperand(2).getReg(); 4507 unsigned incr = MI->getOperand(3).getReg(); 4508 DebugLoc dl = MI->getDebugLoc(); 4509 4510 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4511 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4512 F->insert(It, loopMBB); 4513 F->insert(It, exitMBB); 4514 exitMBB->transferSuccessors(BB); 4515 4516 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4517 unsigned TmpReg = (!BinOpcode) ? incr : 4518 RegInfo.createVirtualRegister( 4519 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4520 (const TargetRegisterClass *) &PPC::GPRCRegClass); 4521 4522 // thisMBB: 4523 // ... 4524 // fallthrough --> loopMBB 4525 BB->addSuccessor(loopMBB); 4526 4527 // loopMBB: 4528 // l[wd]arx dest, ptr 4529 // add r0, dest, incr 4530 // st[wd]cx. r0, ptr 4531 // bne- loopMBB 4532 // fallthrough --> exitMBB 4533 BB = loopMBB; 4534 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4535 .addReg(ptrA).addReg(ptrB); 4536 if (BinOpcode) 4537 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); 4538 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4539 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); 4540 BuildMI(BB, dl, TII->get(PPC::BCC)) 4541 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4542 BB->addSuccessor(loopMBB); 4543 BB->addSuccessor(exitMBB); 4544 4545 // exitMBB: 4546 // ... 4547 BB = exitMBB; 4548 return BB; 4549} 4550 4551MachineBasicBlock * 4552PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, 4553 MachineBasicBlock *BB, 4554 bool is8bit, // operation 4555 unsigned BinOpcode) const { 4556 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4557 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4558 // In 64 bit mode we have to use 64 bits for addresses, even though the 4559 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address 4560 // registers without caring whether they're 32 or 64, but here we're 4561 // doing actual arithmetic on the addresses. 4562 bool is64bit = PPCSubTarget.isPPC64(); 4563 4564 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4565 MachineFunction *F = BB->getParent(); 4566 MachineFunction::iterator It = BB; 4567 ++It; 4568 4569 unsigned dest = MI->getOperand(0).getReg(); 4570 unsigned ptrA = MI->getOperand(1).getReg(); 4571 unsigned ptrB = MI->getOperand(2).getReg(); 4572 unsigned incr = MI->getOperand(3).getReg(); 4573 DebugLoc dl = MI->getDebugLoc(); 4574 4575 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4576 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4577 F->insert(It, loopMBB); 4578 F->insert(It, exitMBB); 4579 exitMBB->transferSuccessors(BB); 4580 4581 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4582 const TargetRegisterClass *RC = 4583 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4584 (const TargetRegisterClass *) &PPC::GPRCRegClass; 4585 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 4586 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 4587 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 4588 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC); 4589 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 4590 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4591 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4592 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4593 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC); 4594 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4595 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4596 unsigned Ptr1Reg; 4597 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); 4598 4599 // thisMBB: 4600 // ... 4601 // fallthrough --> loopMBB 4602 BB->addSuccessor(loopMBB); 4603 4604 // The 4-byte load must be aligned, while a char or short may be 4605 // anywhere in the word. Hence all this nasty bookkeeping code. 4606 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4607 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4608 // xori shift, shift1, 24 [16] 4609 // rlwinm ptr, ptr1, 0, 0, 29 4610 // slw incr2, incr, shift 4611 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 4612 // slw mask, mask2, shift 4613 // loopMBB: 4614 // lwarx tmpDest, ptr 4615 // add tmp, tmpDest, incr2 4616 // andc tmp2, tmpDest, mask 4617 // and tmp3, tmp, mask 4618 // or tmp4, tmp3, tmp2 4619 // stwcx. tmp4, ptr 4620 // bne- loopMBB 4621 // fallthrough --> exitMBB 4622 // srw dest, tmpDest, shift 4623 4624 if (ptrA!=PPC::R0) { 4625 Ptr1Reg = RegInfo.createVirtualRegister(RC); 4626 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 4627 .addReg(ptrA).addReg(ptrB); 4628 } else { 4629 Ptr1Reg = ptrB; 4630 } 4631 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 4632 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 4633 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 4634 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 4635 if (is64bit) 4636 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 4637 .addReg(Ptr1Reg).addImm(0).addImm(61); 4638 else 4639 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 4640 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 4641 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg) 4642 .addReg(incr).addReg(ShiftReg); 4643 if (is8bit) 4644 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 4645 else { 4646 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 4647 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535); 4648 } 4649 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 4650 .addReg(Mask2Reg).addReg(ShiftReg); 4651 4652 BB = loopMBB; 4653 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 4654 .addReg(PPC::R0).addReg(PtrReg); 4655 if (BinOpcode) 4656 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) 4657 .addReg(Incr2Reg).addReg(TmpDestReg); 4658 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) 4659 .addReg(TmpDestReg).addReg(MaskReg); 4660 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) 4661 .addReg(TmpReg).addReg(MaskReg); 4662 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) 4663 .addReg(Tmp3Reg).addReg(Tmp2Reg); 4664 BuildMI(BB, dl, TII->get(PPC::STWCX)) 4665 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg); 4666 BuildMI(BB, dl, TII->get(PPC::BCC)) 4667 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4668 BB->addSuccessor(loopMBB); 4669 BB->addSuccessor(exitMBB); 4670 4671 // exitMBB: 4672 // ... 4673 BB = exitMBB; 4674 BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg); 4675 return BB; 4676} 4677 4678MachineBasicBlock * 4679PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 4680 MachineBasicBlock *BB, 4681 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 4682 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4683 4684 // To "insert" these instructions we actually have to insert their 4685 // control-flow patterns. 4686 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4687 MachineFunction::iterator It = BB; 4688 ++It; 4689 4690 MachineFunction *F = BB->getParent(); 4691 4692 if (MI->getOpcode() == PPC::SELECT_CC_I4 || 4693 MI->getOpcode() == PPC::SELECT_CC_I8 || 4694 MI->getOpcode() == PPC::SELECT_CC_F4 || 4695 MI->getOpcode() == PPC::SELECT_CC_F8 || 4696 MI->getOpcode() == PPC::SELECT_CC_VRRC) { 4697 4698 // The incoming instruction knows the destination vreg to set, the 4699 // condition code register to branch on, the true/false values to 4700 // select between, and a branch opcode to use. 4701 4702 // thisMBB: 4703 // ... 4704 // TrueVal = ... 4705 // cmpTY ccX, r1, r2 4706 // bCC copy1MBB 4707 // fallthrough --> copy0MBB 4708 MachineBasicBlock *thisMBB = BB; 4709 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4710 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4711 unsigned SelectPred = MI->getOperand(4).getImm(); 4712 DebugLoc dl = MI->getDebugLoc(); 4713 BuildMI(BB, dl, TII->get(PPC::BCC)) 4714 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 4715 F->insert(It, copy0MBB); 4716 F->insert(It, sinkMBB); 4717 // Update machine-CFG edges by first adding all successors of the current 4718 // block to the new block which will contain the Phi node for the select. 4719 // Also inform sdisel of the edge changes. 4720 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), 4721 E = BB->succ_end(); I != E; ++I) { 4722 EM->insert(std::make_pair(*I, sinkMBB)); 4723 sinkMBB->addSuccessor(*I); 4724 } 4725 // Next, remove all successors of the current block, and add the true 4726 // and fallthrough blocks as its successors. 4727 while (!BB->succ_empty()) 4728 BB->removeSuccessor(BB->succ_begin()); 4729 // Next, add the true and fallthrough blocks as its successors. 4730 BB->addSuccessor(copy0MBB); 4731 BB->addSuccessor(sinkMBB); 4732 4733 // copy0MBB: 4734 // %FalseValue = ... 4735 // # fallthrough to sinkMBB 4736 BB = copy0MBB; 4737 4738 // Update machine-CFG edges 4739 BB->addSuccessor(sinkMBB); 4740 4741 // sinkMBB: 4742 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 4743 // ... 4744 BB = sinkMBB; 4745 BuildMI(BB, dl, TII->get(PPC::PHI), MI->getOperand(0).getReg()) 4746 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 4747 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 4748 } 4749 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) 4750 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); 4751 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) 4752 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); 4753 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) 4754 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4); 4755 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) 4756 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8); 4757 4758 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8) 4759 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); 4760 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16) 4761 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); 4762 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32) 4763 BB = EmitAtomicBinary(MI, BB, false, PPC::AND); 4764 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64) 4765 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8); 4766 4767 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8) 4768 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); 4769 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16) 4770 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); 4771 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32) 4772 BB = EmitAtomicBinary(MI, BB, false, PPC::OR); 4773 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64) 4774 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8); 4775 4776 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) 4777 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); 4778 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) 4779 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); 4780 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) 4781 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR); 4782 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) 4783 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8); 4784 4785 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) 4786 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC); 4787 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) 4788 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC); 4789 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) 4790 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC); 4791 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) 4792 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8); 4793 4794 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) 4795 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); 4796 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) 4797 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); 4798 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) 4799 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF); 4800 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) 4801 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8); 4802 4803 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8) 4804 BB = EmitPartwordAtomicBinary(MI, BB, true, 0); 4805 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16) 4806 BB = EmitPartwordAtomicBinary(MI, BB, false, 0); 4807 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32) 4808 BB = EmitAtomicBinary(MI, BB, false, 0); 4809 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64) 4810 BB = EmitAtomicBinary(MI, BB, true, 0); 4811 4812 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || 4813 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) { 4814 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; 4815 4816 unsigned dest = MI->getOperand(0).getReg(); 4817 unsigned ptrA = MI->getOperand(1).getReg(); 4818 unsigned ptrB = MI->getOperand(2).getReg(); 4819 unsigned oldval = MI->getOperand(3).getReg(); 4820 unsigned newval = MI->getOperand(4).getReg(); 4821 DebugLoc dl = MI->getDebugLoc(); 4822 4823 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 4824 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 4825 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 4826 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4827 F->insert(It, loop1MBB); 4828 F->insert(It, loop2MBB); 4829 F->insert(It, midMBB); 4830 F->insert(It, exitMBB); 4831 exitMBB->transferSuccessors(BB); 4832 4833 // thisMBB: 4834 // ... 4835 // fallthrough --> loopMBB 4836 BB->addSuccessor(loop1MBB); 4837 4838 // loop1MBB: 4839 // l[wd]arx dest, ptr 4840 // cmp[wd] dest, oldval 4841 // bne- midMBB 4842 // loop2MBB: 4843 // st[wd]cx. newval, ptr 4844 // bne- loopMBB 4845 // b exitBB 4846 // midMBB: 4847 // st[wd]cx. dest, ptr 4848 // exitBB: 4849 BB = loop1MBB; 4850 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4851 .addReg(ptrA).addReg(ptrB); 4852 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) 4853 .addReg(oldval).addReg(dest); 4854 BuildMI(BB, dl, TII->get(PPC::BCC)) 4855 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 4856 BB->addSuccessor(loop2MBB); 4857 BB->addSuccessor(midMBB); 4858 4859 BB = loop2MBB; 4860 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4861 .addReg(newval).addReg(ptrA).addReg(ptrB); 4862 BuildMI(BB, dl, TII->get(PPC::BCC)) 4863 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 4864 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 4865 BB->addSuccessor(loop1MBB); 4866 BB->addSuccessor(exitMBB); 4867 4868 BB = midMBB; 4869 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4870 .addReg(dest).addReg(ptrA).addReg(ptrB); 4871 BB->addSuccessor(exitMBB); 4872 4873 // exitMBB: 4874 // ... 4875 BB = exitMBB; 4876 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || 4877 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { 4878 // We must use 64-bit registers for addresses when targeting 64-bit, 4879 // since we're actually doing arithmetic on them. Other registers 4880 // can be 32-bit. 4881 bool is64bit = PPCSubTarget.isPPC64(); 4882 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; 4883 4884 unsigned dest = MI->getOperand(0).getReg(); 4885 unsigned ptrA = MI->getOperand(1).getReg(); 4886 unsigned ptrB = MI->getOperand(2).getReg(); 4887 unsigned oldval = MI->getOperand(3).getReg(); 4888 unsigned newval = MI->getOperand(4).getReg(); 4889 DebugLoc dl = MI->getDebugLoc(); 4890 4891 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 4892 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 4893 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 4894 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4895 F->insert(It, loop1MBB); 4896 F->insert(It, loop2MBB); 4897 F->insert(It, midMBB); 4898 F->insert(It, exitMBB); 4899 exitMBB->transferSuccessors(BB); 4900 4901 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4902 const TargetRegisterClass *RC = 4903 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4904 (const TargetRegisterClass *) &PPC::GPRCRegClass; 4905 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 4906 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 4907 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 4908 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC); 4909 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC); 4910 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC); 4911 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC); 4912 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 4913 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4914 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4915 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4916 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4917 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4918 unsigned Ptr1Reg; 4919 unsigned TmpReg = RegInfo.createVirtualRegister(RC); 4920 // thisMBB: 4921 // ... 4922 // fallthrough --> loopMBB 4923 BB->addSuccessor(loop1MBB); 4924 4925 // The 4-byte load must be aligned, while a char or short may be 4926 // anywhere in the word. Hence all this nasty bookkeeping code. 4927 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4928 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4929 // xori shift, shift1, 24 [16] 4930 // rlwinm ptr, ptr1, 0, 0, 29 4931 // slw newval2, newval, shift 4932 // slw oldval2, oldval,shift 4933 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 4934 // slw mask, mask2, shift 4935 // and newval3, newval2, mask 4936 // and oldval3, oldval2, mask 4937 // loop1MBB: 4938 // lwarx tmpDest, ptr 4939 // and tmp, tmpDest, mask 4940 // cmpw tmp, oldval3 4941 // bne- midMBB 4942 // loop2MBB: 4943 // andc tmp2, tmpDest, mask 4944 // or tmp4, tmp2, newval3 4945 // stwcx. tmp4, ptr 4946 // bne- loop1MBB 4947 // b exitBB 4948 // midMBB: 4949 // stwcx. tmpDest, ptr 4950 // exitBB: 4951 // srw dest, tmpDest, shift 4952 if (ptrA!=PPC::R0) { 4953 Ptr1Reg = RegInfo.createVirtualRegister(RC); 4954 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 4955 .addReg(ptrA).addReg(ptrB); 4956 } else { 4957 Ptr1Reg = ptrB; 4958 } 4959 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 4960 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 4961 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 4962 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 4963 if (is64bit) 4964 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 4965 .addReg(Ptr1Reg).addImm(0).addImm(61); 4966 else 4967 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 4968 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 4969 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) 4970 .addReg(newval).addReg(ShiftReg); 4971 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) 4972 .addReg(oldval).addReg(ShiftReg); 4973 if (is8bit) 4974 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 4975 else { 4976 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 4977 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) 4978 .addReg(Mask3Reg).addImm(65535); 4979 } 4980 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 4981 .addReg(Mask2Reg).addReg(ShiftReg); 4982 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg) 4983 .addReg(NewVal2Reg).addReg(MaskReg); 4984 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg) 4985 .addReg(OldVal2Reg).addReg(MaskReg); 4986 4987 BB = loop1MBB; 4988 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 4989 .addReg(PPC::R0).addReg(PtrReg); 4990 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) 4991 .addReg(TmpDestReg).addReg(MaskReg); 4992 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0) 4993 .addReg(TmpReg).addReg(OldVal3Reg); 4994 BuildMI(BB, dl, TII->get(PPC::BCC)) 4995 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 4996 BB->addSuccessor(loop2MBB); 4997 BB->addSuccessor(midMBB); 4998 4999 BB = loop2MBB; 5000 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg) 5001 .addReg(TmpDestReg).addReg(MaskReg); 5002 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg) 5003 .addReg(Tmp2Reg).addReg(NewVal3Reg); 5004 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg) 5005 .addReg(PPC::R0).addReg(PtrReg); 5006 BuildMI(BB, dl, TII->get(PPC::BCC)) 5007 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 5008 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 5009 BB->addSuccessor(loop1MBB); 5010 BB->addSuccessor(exitMBB); 5011 5012 BB = midMBB; 5013 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg) 5014 .addReg(PPC::R0).addReg(PtrReg); 5015 BB->addSuccessor(exitMBB); 5016 5017 // exitMBB: 5018 // ... 5019 BB = exitMBB; 5020 BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg); 5021 } else { 5022 llvm_unreachable("Unexpected instr type to insert"); 5023 } 5024 5025 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 5026 return BB; 5027} 5028 5029//===----------------------------------------------------------------------===// 5030// Target Optimization Hooks 5031//===----------------------------------------------------------------------===// 5032 5033SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, 5034 DAGCombinerInfo &DCI) const { 5035 TargetMachine &TM = getTargetMachine(); 5036 SelectionDAG &DAG = DCI.DAG; 5037 DebugLoc dl = N->getDebugLoc(); 5038 switch (N->getOpcode()) { 5039 default: break; 5040 case PPCISD::SHL: 5041 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5042 if (C->getZExtValue() == 0) // 0 << V -> 0. 5043 return N->getOperand(0); 5044 } 5045 break; 5046 case PPCISD::SRL: 5047 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5048 if (C->getZExtValue() == 0) // 0 >>u V -> 0. 5049 return N->getOperand(0); 5050 } 5051 break; 5052 case PPCISD::SRA: 5053 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5054 if (C->getZExtValue() == 0 || // 0 >>s V -> 0. 5055 C->isAllOnesValue()) // -1 >>s V -> -1. 5056 return N->getOperand(0); 5057 } 5058 break; 5059 5060 case ISD::SINT_TO_FP: 5061 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 5062 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 5063 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 5064 // We allow the src/dst to be either f32/f64, but the intermediate 5065 // type must be i64. 5066 if (N->getOperand(0).getValueType() == MVT::i64 && 5067 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 5068 SDValue Val = N->getOperand(0).getOperand(0); 5069 if (Val.getValueType() == MVT::f32) { 5070 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 5071 DCI.AddToWorklist(Val.getNode()); 5072 } 5073 5074 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val); 5075 DCI.AddToWorklist(Val.getNode()); 5076 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val); 5077 DCI.AddToWorklist(Val.getNode()); 5078 if (N->getValueType(0) == MVT::f32) { 5079 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val, 5080 DAG.getIntPtrConstant(0)); 5081 DCI.AddToWorklist(Val.getNode()); 5082 } 5083 return Val; 5084 } else if (N->getOperand(0).getValueType() == MVT::i32) { 5085 // If the intermediate type is i32, we can avoid the load/store here 5086 // too. 5087 } 5088 } 5089 } 5090 break; 5091 case ISD::STORE: 5092 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 5093 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 5094 !cast<StoreSDNode>(N)->isTruncatingStore() && 5095 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 5096 N->getOperand(1).getValueType() == MVT::i32 && 5097 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 5098 SDValue Val = N->getOperand(1).getOperand(0); 5099 if (Val.getValueType() == MVT::f32) { 5100 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 5101 DCI.AddToWorklist(Val.getNode()); 5102 } 5103 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); 5104 DCI.AddToWorklist(Val.getNode()); 5105 5106 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val, 5107 N->getOperand(2), N->getOperand(3)); 5108 DCI.AddToWorklist(Val.getNode()); 5109 return Val; 5110 } 5111 5112 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 5113 if (cast<StoreSDNode>(N)->isUnindexed() && 5114 N->getOperand(1).getOpcode() == ISD::BSWAP && 5115 N->getOperand(1).getNode()->hasOneUse() && 5116 (N->getOperand(1).getValueType() == MVT::i32 || 5117 N->getOperand(1).getValueType() == MVT::i16)) { 5118 SDValue BSwapOp = N->getOperand(1).getOperand(0); 5119 // Do an any-extend to 32-bits if this is a half-word input. 5120 if (BSwapOp.getValueType() == MVT::i16) 5121 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); 5122 5123 SDValue Ops[] = { 5124 N->getOperand(0), BSwapOp, N->getOperand(2), 5125 DAG.getValueType(N->getOperand(1).getValueType()) 5126 }; 5127 return 5128 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), 5129 Ops, array_lengthof(Ops), 5130 cast<StoreSDNode>(N)->getMemoryVT(), 5131 cast<StoreSDNode>(N)->getMemOperand()); 5132 } 5133 break; 5134 case ISD::BSWAP: 5135 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 5136 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) && 5137 N->getOperand(0).hasOneUse() && 5138 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 5139 SDValue Load = N->getOperand(0); 5140 LoadSDNode *LD = cast<LoadSDNode>(Load); 5141 // Create the byte-swapping load. 5142 SDValue Ops[] = { 5143 LD->getChain(), // Chain 5144 LD->getBasePtr(), // Ptr 5145 DAG.getValueType(N->getValueType(0)) // VT 5146 }; 5147 SDValue BSLoad = 5148 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl, 5149 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3, 5150 LD->getMemoryVT(), LD->getMemOperand()); 5151 5152 // If this is an i16 load, insert the truncate. 5153 SDValue ResVal = BSLoad; 5154 if (N->getValueType(0) == MVT::i16) 5155 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); 5156 5157 // First, combine the bswap away. This makes the value produced by the 5158 // load dead. 5159 DCI.CombineTo(N, ResVal); 5160 5161 // Next, combine the load away, we give it a bogus result value but a real 5162 // chain result. The result value is dead because the bswap is dead. 5163 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1)); 5164 5165 // Return N so it doesn't get rechecked! 5166 return SDValue(N, 0); 5167 } 5168 5169 break; 5170 case PPCISD::VCMP: { 5171 // If a VCMPo node already exists with exactly the same operands as this 5172 // node, use its result instead of this node (VCMPo computes both a CR6 and 5173 // a normal output). 5174 // 5175 if (!N->getOperand(0).hasOneUse() && 5176 !N->getOperand(1).hasOneUse() && 5177 !N->getOperand(2).hasOneUse()) { 5178 5179 // Scan all of the users of the LHS, looking for VCMPo's that match. 5180 SDNode *VCMPoNode = 0; 5181 5182 SDNode *LHSN = N->getOperand(0).getNode(); 5183 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 5184 UI != E; ++UI) 5185 if (UI->getOpcode() == PPCISD::VCMPo && 5186 UI->getOperand(1) == N->getOperand(1) && 5187 UI->getOperand(2) == N->getOperand(2) && 5188 UI->getOperand(0) == N->getOperand(0)) { 5189 VCMPoNode = *UI; 5190 break; 5191 } 5192 5193 // If there is no VCMPo node, or if the flag value has a single use, don't 5194 // transform this. 5195 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 5196 break; 5197 5198 // Look at the (necessarily single) use of the flag value. If it has a 5199 // chain, this transformation is more complex. Note that multiple things 5200 // could use the value result, which we should ignore. 5201 SDNode *FlagUser = 0; 5202 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 5203 FlagUser == 0; ++UI) { 5204 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 5205 SDNode *User = *UI; 5206 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 5207 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) { 5208 FlagUser = User; 5209 break; 5210 } 5211 } 5212 } 5213 5214 // If the user is a MFCR instruction, we know this is safe. Otherwise we 5215 // give up for right now. 5216 if (FlagUser->getOpcode() == PPCISD::MFCR) 5217 return SDValue(VCMPoNode, 0); 5218 } 5219 break; 5220 } 5221 case ISD::BR_CC: { 5222 // If this is a branch on an altivec predicate comparison, lower this so 5223 // that we don't have to do a MFCR: instead, branch directly on CR6. This 5224 // lowering is done pre-legalize, because the legalizer lowers the predicate 5225 // compare down to code that is difficult to reassemble. 5226 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 5227 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 5228 int CompareOpc; 5229 bool isDot; 5230 5231 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 5232 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 5233 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 5234 assert(isDot && "Can't compare against a vector result!"); 5235 5236 // If this is a comparison against something other than 0/1, then we know 5237 // that the condition is never/always true. 5238 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue(); 5239 if (Val != 0 && Val != 1) { 5240 if (CC == ISD::SETEQ) // Cond never true, remove branch. 5241 return N->getOperand(0); 5242 // Always !=, turn it into an unconditional branch. 5243 return DAG.getNode(ISD::BR, dl, MVT::Other, 5244 N->getOperand(0), N->getOperand(4)); 5245 } 5246 5247 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 5248 5249 // Create the PPCISD altivec 'dot' comparison node. 5250 std::vector<EVT> VTs; 5251 SDValue Ops[] = { 5252 LHS.getOperand(2), // LHS of compare 5253 LHS.getOperand(3), // RHS of compare 5254 DAG.getConstant(CompareOpc, MVT::i32) 5255 }; 5256 VTs.push_back(LHS.getOperand(2).getValueType()); 5257 VTs.push_back(MVT::Flag); 5258 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 5259 5260 // Unpack the result based on how the target uses it. 5261 PPC::Predicate CompOpc; 5262 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) { 5263 default: // Can't happen, don't crash on invalid number though. 5264 case 0: // Branch on the value of the EQ bit of CR6. 5265 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 5266 break; 5267 case 1: // Branch on the inverted value of the EQ bit of CR6. 5268 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 5269 break; 5270 case 2: // Branch on the value of the LT bit of CR6. 5271 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 5272 break; 5273 case 3: // Branch on the inverted value of the LT bit of CR6. 5274 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 5275 break; 5276 } 5277 5278 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), 5279 DAG.getConstant(CompOpc, MVT::i32), 5280 DAG.getRegister(PPC::CR6, MVT::i32), 5281 N->getOperand(4), CompNode.getValue(1)); 5282 } 5283 break; 5284 } 5285 } 5286 5287 return SDValue(); 5288} 5289 5290//===----------------------------------------------------------------------===// 5291// Inline Assembly Support 5292//===----------------------------------------------------------------------===// 5293 5294void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 5295 const APInt &Mask, 5296 APInt &KnownZero, 5297 APInt &KnownOne, 5298 const SelectionDAG &DAG, 5299 unsigned Depth) const { 5300 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 5301 switch (Op.getOpcode()) { 5302 default: break; 5303 case PPCISD::LBRX: { 5304 // lhbrx is known to have the top bits cleared out. 5305 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) 5306 KnownZero = 0xFFFF0000; 5307 break; 5308 } 5309 case ISD::INTRINSIC_WO_CHAIN: { 5310 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) { 5311 default: break; 5312 case Intrinsic::ppc_altivec_vcmpbfp_p: 5313 case Intrinsic::ppc_altivec_vcmpeqfp_p: 5314 case Intrinsic::ppc_altivec_vcmpequb_p: 5315 case Intrinsic::ppc_altivec_vcmpequh_p: 5316 case Intrinsic::ppc_altivec_vcmpequw_p: 5317 case Intrinsic::ppc_altivec_vcmpgefp_p: 5318 case Intrinsic::ppc_altivec_vcmpgtfp_p: 5319 case Intrinsic::ppc_altivec_vcmpgtsb_p: 5320 case Intrinsic::ppc_altivec_vcmpgtsh_p: 5321 case Intrinsic::ppc_altivec_vcmpgtsw_p: 5322 case Intrinsic::ppc_altivec_vcmpgtub_p: 5323 case Intrinsic::ppc_altivec_vcmpgtuh_p: 5324 case Intrinsic::ppc_altivec_vcmpgtuw_p: 5325 KnownZero = ~1U; // All bits but the low one are known to be zero. 5326 break; 5327 } 5328 } 5329 } 5330} 5331 5332 5333/// getConstraintType - Given a constraint, return the type of 5334/// constraint it is for this target. 5335PPCTargetLowering::ConstraintType 5336PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 5337 if (Constraint.size() == 1) { 5338 switch (Constraint[0]) { 5339 default: break; 5340 case 'b': 5341 case 'r': 5342 case 'f': 5343 case 'v': 5344 case 'y': 5345 return C_RegisterClass; 5346 } 5347 } 5348 return TargetLowering::getConstraintType(Constraint); 5349} 5350 5351std::pair<unsigned, const TargetRegisterClass*> 5352PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 5353 EVT VT) const { 5354 if (Constraint.size() == 1) { 5355 // GCC RS6000 Constraint Letters 5356 switch (Constraint[0]) { 5357 case 'b': // R1-R31 5358 case 'r': // R0-R31 5359 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 5360 return std::make_pair(0U, PPC::G8RCRegisterClass); 5361 return std::make_pair(0U, PPC::GPRCRegisterClass); 5362 case 'f': 5363 if (VT == MVT::f32) 5364 return std::make_pair(0U, PPC::F4RCRegisterClass); 5365 else if (VT == MVT::f64) 5366 return std::make_pair(0U, PPC::F8RCRegisterClass); 5367 break; 5368 case 'v': 5369 return std::make_pair(0U, PPC::VRRCRegisterClass); 5370 case 'y': // crrc 5371 return std::make_pair(0U, PPC::CRRCRegisterClass); 5372 } 5373 } 5374 5375 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 5376} 5377 5378 5379/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 5380/// vector. If it is invalid, don't add anything to Ops. If hasMemory is true 5381/// it means one of the asm constraint of the inline asm instruction being 5382/// processed is 'm'. 5383void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter, 5384 bool hasMemory, 5385 std::vector<SDValue>&Ops, 5386 SelectionDAG &DAG) const { 5387 SDValue Result(0,0); 5388 switch (Letter) { 5389 default: break; 5390 case 'I': 5391 case 'J': 5392 case 'K': 5393 case 'L': 5394 case 'M': 5395 case 'N': 5396 case 'O': 5397 case 'P': { 5398 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 5399 if (!CST) return; // Must be an immediate to match. 5400 unsigned Value = CST->getZExtValue(); 5401 switch (Letter) { 5402 default: llvm_unreachable("Unknown constraint letter!"); 5403 case 'I': // "I" is a signed 16-bit constant. 5404 if ((short)Value == (int)Value) 5405 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5406 break; 5407 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 5408 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 5409 if ((short)Value == 0) 5410 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5411 break; 5412 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 5413 if ((Value >> 16) == 0) 5414 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5415 break; 5416 case 'M': // "M" is a constant that is greater than 31. 5417 if (Value > 31) 5418 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5419 break; 5420 case 'N': // "N" is a positive constant that is an exact power of two. 5421 if ((int)Value > 0 && isPowerOf2_32(Value)) 5422 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5423 break; 5424 case 'O': // "O" is the constant zero. 5425 if (Value == 0) 5426 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5427 break; 5428 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 5429 if ((short)-Value == (int)-Value) 5430 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5431 break; 5432 } 5433 break; 5434 } 5435 } 5436 5437 if (Result.getNode()) { 5438 Ops.push_back(Result); 5439 return; 5440 } 5441 5442 // Handle standard constraint letters. 5443 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, hasMemory, Ops, DAG); 5444} 5445 5446// isLegalAddressingMode - Return true if the addressing mode represented 5447// by AM is legal for this target, for a load/store of the specified type. 5448bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 5449 const Type *Ty) const { 5450 // FIXME: PPC does not allow r+i addressing modes for vectors! 5451 5452 // PPC allows a sign-extended 16-bit immediate field. 5453 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 5454 return false; 5455 5456 // No global is ever allowed as a base. 5457 if (AM.BaseGV) 5458 return false; 5459 5460 // PPC only support r+r, 5461 switch (AM.Scale) { 5462 case 0: // "r+i" or just "i", depending on HasBaseReg. 5463 break; 5464 case 1: 5465 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 5466 return false; 5467 // Otherwise we have r+r or r+i. 5468 break; 5469 case 2: 5470 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 5471 return false; 5472 // Allow 2*r as r+r. 5473 break; 5474 default: 5475 // No other scales are supported. 5476 return false; 5477 } 5478 5479 return true; 5480} 5481 5482/// isLegalAddressImmediate - Return true if the integer value can be used 5483/// as the offset of the target addressing mode for load / store of the 5484/// given type. 5485bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{ 5486 // PPC allows a sign-extended 16-bit immediate field. 5487 return (V > -(1 << 16) && V < (1 << 16)-1); 5488} 5489 5490bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 5491 return false; 5492} 5493 5494SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 5495 DebugLoc dl = Op.getDebugLoc(); 5496 // Depths > 0 not supported yet! 5497 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) 5498 return SDValue(); 5499 5500 MachineFunction &MF = DAG.getMachineFunction(); 5501 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 5502 5503 // Just load the return address off the stack. 5504 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); 5505 5506 // Make sure the function really does not optimize away the store of the RA 5507 // to the stack. 5508 FuncInfo->setLRStoreRequired(); 5509 return DAG.getLoad(getPointerTy(), dl, 5510 DAG.getEntryNode(), RetAddrFI, NULL, 0, 5511 false, false, 0); 5512} 5513 5514SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 5515 DebugLoc dl = Op.getDebugLoc(); 5516 // Depths > 0 not supported yet! 5517 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) 5518 return SDValue(); 5519 5520 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 5521 bool isPPC64 = PtrVT == MVT::i64; 5522 5523 MachineFunction &MF = DAG.getMachineFunction(); 5524 MachineFrameInfo *MFI = MF.getFrameInfo(); 5525 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects()) 5526 && MFI->getStackSize(); 5527 5528 if (isPPC64) 5529 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1, 5530 MVT::i64); 5531 else 5532 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1, 5533 MVT::i32); 5534} 5535 5536bool 5537PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 5538 // The PowerPC target isn't yet aware of offsets. 5539 return false; 5540} 5541 5542/// getOptimalMemOpType - Returns the target specific optimal type for load 5543/// and store operations as a result of memset, memcpy, and memmove lowering. 5544/// If DstAlign is zero that means it's safe to destination alignment can 5545/// satisfy any constraint. Similarly if SrcAlign is zero it means there 5546/// isn't a need to check it against alignment requirement, probably because 5547/// the source does not need to be loaded. It returns EVT::Other if 5548/// SelectionDAG should be responsible for determining it. 5549EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, 5550 unsigned DstAlign, unsigned SrcAlign, 5551 bool SafeToUseFP, 5552 SelectionDAG &DAG) const { 5553 if (this->PPCSubTarget.isPPC64()) { 5554 return MVT::i64; 5555 } else { 5556 return MVT::i32; 5557 } 5558} 5559