PPCISelLowering.cpp revision ed2eee63a6858312ed17582d8cb85a6856d8eb34
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPredicates.h" 17#include "PPCTargetMachine.h" 18#include "PPCPerfectShuffle.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/ADT/VectorExtras.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/CallingConv.h" 29#include "llvm/Constants.h" 30#include "llvm/Function.h" 31#include "llvm/Intrinsics.h" 32#include "llvm/Support/MathExtras.h" 33#include "llvm/Target/TargetOptions.h" 34#include "llvm/Support/CommandLine.h" 35using namespace llvm; 36 37static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", 38cl::desc("enable preincrement load/store generation on PPC (experimental)"), 39 cl::Hidden); 40 41PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 42 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { 43 44 setPow2DivIsCheap(); 45 46 // Use _setjmp/_longjmp instead of setjmp/longjmp. 47 setUseUnderscoreSetJmp(true); 48 setUseUnderscoreLongJmp(true); 49 50 // Set up the register classes. 51 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 52 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 53 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 54 55 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 56 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 57 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 58 59 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 60 61 // PowerPC has pre-inc load and store's. 62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 65 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 67 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 70 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 72 73 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg) 74 setConvertAction(MVT::ppcf128, MVT::f64, Expand); 75 setConvertAction(MVT::ppcf128, MVT::f32, Expand); 76 // This is used in the ppcf128->int sequence. Note it has different semantics 77 // from FP_ROUND: that rounds to nearest, this rounds to zero. 78 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 79 80 // PowerPC has no SREM/UREM instructions 81 setOperationAction(ISD::SREM, MVT::i32, Expand); 82 setOperationAction(ISD::UREM, MVT::i32, Expand); 83 setOperationAction(ISD::SREM, MVT::i64, Expand); 84 setOperationAction(ISD::UREM, MVT::i64, Expand); 85 86 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 87 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 88 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 89 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 90 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 91 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 92 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 93 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 94 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 95 96 // We don't support sin/cos/sqrt/fmod/pow 97 setOperationAction(ISD::FSIN , MVT::f64, Expand); 98 setOperationAction(ISD::FCOS , MVT::f64, Expand); 99 setOperationAction(ISD::FREM , MVT::f64, Expand); 100 setOperationAction(ISD::FPOW , MVT::f64, Expand); 101 setOperationAction(ISD::FSIN , MVT::f32, Expand); 102 setOperationAction(ISD::FCOS , MVT::f32, Expand); 103 setOperationAction(ISD::FREM , MVT::f32, Expand); 104 setOperationAction(ISD::FPOW , MVT::f32, Expand); 105 106 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 107 108 // If we're enabling GP optimizations, use hardware square root 109 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 110 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 111 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 112 } 113 114 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 115 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 116 117 // PowerPC does not have BSWAP, CTPOP or CTTZ 118 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 119 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 120 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 121 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 122 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 123 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 124 125 // PowerPC does not have ROTR 126 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 127 setOperationAction(ISD::ROTR, MVT::i64 , Expand); 128 129 // PowerPC does not have Select 130 setOperationAction(ISD::SELECT, MVT::i32, Expand); 131 setOperationAction(ISD::SELECT, MVT::i64, Expand); 132 setOperationAction(ISD::SELECT, MVT::f32, Expand); 133 setOperationAction(ISD::SELECT, MVT::f64, Expand); 134 135 // PowerPC wants to turn select_cc of FP into fsel when possible. 136 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 137 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 138 139 // PowerPC wants to optimize integer setcc a bit 140 setOperationAction(ISD::SETCC, MVT::i32, Custom); 141 142 // PowerPC does not have BRCOND which requires SetCC 143 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 144 145 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 146 147 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 148 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 149 150 // PowerPC does not have [U|S]INT_TO_FP 151 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 152 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 153 154 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 155 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 156 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 157 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 158 159 // We cannot sextinreg(i1). Expand to shifts. 160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 161 162 // Support label based line numbers. 163 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 164 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 165 166 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 167 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 168 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 169 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 170 171 172 // We want to legalize GlobalAddress and ConstantPool nodes into the 173 // appropriate instructions to materialize the address. 174 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 175 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 176 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 177 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 178 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 179 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 180 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 181 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 182 183 // RET must be custom lowered, to meet ABI requirements. 184 setOperationAction(ISD::RET , MVT::Other, Custom); 185 186 // TRAP is legal. 187 setOperationAction(ISD::TRAP, MVT::Other, Legal); 188 189 // TRAMPOLINE is custom lowered. 190 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 191 192 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 193 setOperationAction(ISD::VASTART , MVT::Other, Custom); 194 195 // VAARG is custom lowered with ELF 32 ABI 196 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI()) 197 setOperationAction(ISD::VAARG, MVT::Other, Custom); 198 else 199 setOperationAction(ISD::VAARG, MVT::Other, Expand); 200 201 // Use the default implementation. 202 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 203 setOperationAction(ISD::VAEND , MVT::Other, Expand); 204 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 205 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 208 209 // We want to custom lower some of our intrinsics. 210 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 211 212 // Comparisons that require checking two conditions. 213 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 214 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); 215 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); 216 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); 217 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); 218 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); 219 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 220 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 221 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 222 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 223 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); 224 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); 225 226 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 227 // They also have instructions for converting between i64 and fp. 228 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 229 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 230 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 231 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 232 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 233 234 // FIXME: disable this lowered code. This generates 64-bit register values, 235 // and we don't model the fact that the top part is clobbered by calls. We 236 // need to flag these together so that the value isn't live across a call. 237 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 238 239 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 240 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 241 } else { 242 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 243 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 244 } 245 246 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 247 // 64-bit PowerPC implementations can support i64 types directly 248 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 249 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 250 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 251 // 64-bit PowerPC wants to expand i128 shifts itself. 252 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 253 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 254 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 255 } else { 256 // 32-bit PowerPC wants to expand i64 shifts itself. 257 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 258 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 259 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 260 } 261 262 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 263 // First set operation action for all vector types to expand. Then we 264 // will selectively turn on ones that can be effectively codegen'd. 265 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 266 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 267 MVT VT = (MVT::SimpleValueType)i; 268 269 // add/sub are legal for all supported vector VT's. 270 setOperationAction(ISD::ADD , VT, Legal); 271 setOperationAction(ISD::SUB , VT, Legal); 272 273 // We promote all shuffles to v16i8. 274 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 275 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 276 277 // We promote all non-typed operations to v4i32. 278 setOperationAction(ISD::AND , VT, Promote); 279 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 280 setOperationAction(ISD::OR , VT, Promote); 281 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 282 setOperationAction(ISD::XOR , VT, Promote); 283 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 284 setOperationAction(ISD::LOAD , VT, Promote); 285 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 286 setOperationAction(ISD::SELECT, VT, Promote); 287 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 288 setOperationAction(ISD::STORE, VT, Promote); 289 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 290 291 // No other operations are legal. 292 setOperationAction(ISD::MUL , VT, Expand); 293 setOperationAction(ISD::SDIV, VT, Expand); 294 setOperationAction(ISD::SREM, VT, Expand); 295 setOperationAction(ISD::UDIV, VT, Expand); 296 setOperationAction(ISD::UREM, VT, Expand); 297 setOperationAction(ISD::FDIV, VT, Expand); 298 setOperationAction(ISD::FNEG, VT, Expand); 299 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); 300 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 301 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); 302 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 303 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 304 setOperationAction(ISD::UDIVREM, VT, Expand); 305 setOperationAction(ISD::SDIVREM, VT, Expand); 306 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); 307 setOperationAction(ISD::FPOW, VT, Expand); 308 setOperationAction(ISD::CTPOP, VT, Expand); 309 setOperationAction(ISD::CTLZ, VT, Expand); 310 setOperationAction(ISD::CTTZ, VT, Expand); 311 } 312 313 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 314 // with merges, splats, etc. 315 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 316 317 setOperationAction(ISD::AND , MVT::v4i32, Legal); 318 setOperationAction(ISD::OR , MVT::v4i32, Legal); 319 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 320 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 321 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 322 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 323 324 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 325 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 326 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 327 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 328 329 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 330 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 331 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 332 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 333 334 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 335 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 336 337 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 338 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 339 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 340 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 341 } 342 343 setShiftAmountType(MVT::i32); 344 setBooleanContents(ZeroOrOneBooleanContent); 345 346 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 347 setStackPointerRegisterToSaveRestore(PPC::X1); 348 setExceptionPointerRegister(PPC::X3); 349 setExceptionSelectorRegister(PPC::X4); 350 } else { 351 setStackPointerRegisterToSaveRestore(PPC::R1); 352 setExceptionPointerRegister(PPC::R3); 353 setExceptionSelectorRegister(PPC::R4); 354 } 355 356 // We have target-specific dag combine patterns for the following nodes: 357 setTargetDAGCombine(ISD::SINT_TO_FP); 358 setTargetDAGCombine(ISD::STORE); 359 setTargetDAGCombine(ISD::BR_CC); 360 setTargetDAGCombine(ISD::BSWAP); 361 362 // Darwin long double math library functions have $LDBL128 appended. 363 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) { 364 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 365 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 366 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 367 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 368 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 369 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128"); 370 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128"); 371 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128"); 372 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128"); 373 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128"); 374 } 375 376 computeRegisterProperties(); 377} 378 379/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 380/// function arguments in the caller parameter area. 381unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const { 382 TargetMachine &TM = getTargetMachine(); 383 // Darwin passes everything on 4 byte boundary. 384 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) 385 return 4; 386 // FIXME Elf TBD 387 return 4; 388} 389 390const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 391 switch (Opcode) { 392 default: return 0; 393 case PPCISD::FSEL: return "PPCISD::FSEL"; 394 case PPCISD::FCFID: return "PPCISD::FCFID"; 395 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 396 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 397 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 398 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 399 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 400 case PPCISD::VPERM: return "PPCISD::VPERM"; 401 case PPCISD::Hi: return "PPCISD::Hi"; 402 case PPCISD::Lo: return "PPCISD::Lo"; 403 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 404 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 405 case PPCISD::SRL: return "PPCISD::SRL"; 406 case PPCISD::SRA: return "PPCISD::SRA"; 407 case PPCISD::SHL: return "PPCISD::SHL"; 408 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 409 case PPCISD::STD_32: return "PPCISD::STD_32"; 410 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF"; 411 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho"; 412 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 413 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho"; 414 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF"; 415 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 416 case PPCISD::MFCR: return "PPCISD::MFCR"; 417 case PPCISD::VCMP: return "PPCISD::VCMP"; 418 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 419 case PPCISD::LBRX: return "PPCISD::LBRX"; 420 case PPCISD::STBRX: return "PPCISD::STBRX"; 421 case PPCISD::LARX: return "PPCISD::LARX"; 422 case PPCISD::STCX: return "PPCISD::STCX"; 423 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 424 case PPCISD::MFFS: return "PPCISD::MFFS"; 425 case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; 426 case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; 427 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 428 case PPCISD::MTFSF: return "PPCISD::MTFSF"; 429 case PPCISD::TAILCALL: return "PPCISD::TAILCALL"; 430 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; 431 } 432} 433 434 435MVT PPCTargetLowering::getSetCCResultType(MVT VT) const { 436 return MVT::i32; 437} 438 439 440//===----------------------------------------------------------------------===// 441// Node matching predicates, for use by the tblgen matching code. 442//===----------------------------------------------------------------------===// 443 444/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 445static bool isFloatingPointZero(SDValue Op) { 446 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 447 return CFP->getValueAPF().isZero(); 448 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 449 // Maybe this has already been legalized into the constant pool? 450 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 451 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 452 return CFP->getValueAPF().isZero(); 453 } 454 return false; 455} 456 457/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 458/// true if Op is undef or if it matches the specified value. 459static bool isConstantOrUndef(SDValue Op, unsigned Val) { 460 return Op.getOpcode() == ISD::UNDEF || 461 cast<ConstantSDNode>(Op)->getZExtValue() == Val; 462} 463 464/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 465/// VPKUHUM instruction. 466bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { 467 if (!isUnary) { 468 for (unsigned i = 0; i != 16; ++i) 469 if (!isConstantOrUndef(N->getOperand(i), i*2+1)) 470 return false; 471 } else { 472 for (unsigned i = 0; i != 8; ++i) 473 if (!isConstantOrUndef(N->getOperand(i), i*2+1) || 474 !isConstantOrUndef(N->getOperand(i+8), i*2+1)) 475 return false; 476 } 477 return true; 478} 479 480/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 481/// VPKUWUM instruction. 482bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { 483 if (!isUnary) { 484 for (unsigned i = 0; i != 16; i += 2) 485 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 486 !isConstantOrUndef(N->getOperand(i+1), i*2+3)) 487 return false; 488 } else { 489 for (unsigned i = 0; i != 8; i += 2) 490 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 491 !isConstantOrUndef(N->getOperand(i+1), i*2+3) || 492 !isConstantOrUndef(N->getOperand(i+8), i*2+2) || 493 !isConstantOrUndef(N->getOperand(i+9), i*2+3)) 494 return false; 495 } 496 return true; 497} 498 499/// isVMerge - Common function, used to match vmrg* shuffles. 500/// 501static bool isVMerge(SDNode *N, unsigned UnitSize, 502 unsigned LHSStart, unsigned RHSStart) { 503 assert(N->getOpcode() == ISD::BUILD_VECTOR && 504 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 505 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 506 "Unsupported merge size!"); 507 508 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 509 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 510 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), 511 LHSStart+j+i*UnitSize) || 512 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), 513 RHSStart+j+i*UnitSize)) 514 return false; 515 } 516 return true; 517} 518 519/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 520/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 521bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 522 if (!isUnary) 523 return isVMerge(N, UnitSize, 8, 24); 524 return isVMerge(N, UnitSize, 8, 8); 525} 526 527/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 528/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 529bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 530 if (!isUnary) 531 return isVMerge(N, UnitSize, 0, 16); 532 return isVMerge(N, UnitSize, 0, 0); 533} 534 535 536/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 537/// amount, otherwise return -1. 538int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 539 assert(N->getOpcode() == ISD::BUILD_VECTOR && 540 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 541 // Find the first non-undef value in the shuffle mask. 542 unsigned i; 543 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) 544 /*search*/; 545 546 if (i == 16) return -1; // all undef. 547 548 // Otherwise, check to see if the rest of the elements are consequtively 549 // numbered from this value. 550 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getZExtValue(); 551 if (ShiftAmt < i) return -1; 552 ShiftAmt -= i; 553 554 if (!isUnary) { 555 // Check the rest of the elements to see if they are consequtive. 556 for (++i; i != 16; ++i) 557 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) 558 return -1; 559 } else { 560 // Check the rest of the elements to see if they are consequtive. 561 for (++i; i != 16; ++i) 562 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) 563 return -1; 564 } 565 566 return ShiftAmt; 567} 568 569/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 570/// specifies a splat of a single element that is suitable for input to 571/// VSPLTB/VSPLTH/VSPLTW. 572bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { 573 assert(N->getOpcode() == ISD::BUILD_VECTOR && 574 N->getNumOperands() == 16 && 575 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 576 577 // This is a splat operation if each element of the permute is the same, and 578 // if the value doesn't reference the second vector. 579 unsigned ElementBase = 0; 580 SDValue Elt = N->getOperand(0); 581 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) 582 ElementBase = EltV->getZExtValue(); 583 else 584 return false; // FIXME: Handle UNDEF elements too! 585 586 if (cast<ConstantSDNode>(Elt)->getZExtValue() >= 16) 587 return false; 588 589 // Check that they are consequtive. 590 for (unsigned i = 1; i != EltSize; ++i) { 591 if (!isa<ConstantSDNode>(N->getOperand(i)) || 592 cast<ConstantSDNode>(N->getOperand(i))->getZExtValue() != i+ElementBase) 593 return false; 594 } 595 596 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); 597 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 598 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 599 assert(isa<ConstantSDNode>(N->getOperand(i)) && 600 "Invalid VECTOR_SHUFFLE mask!"); 601 for (unsigned j = 0; j != EltSize; ++j) 602 if (N->getOperand(i+j) != N->getOperand(j)) 603 return false; 604 } 605 606 return true; 607} 608 609/// isAllNegativeZeroVector - Returns true if all elements of build_vector 610/// are -0.0. 611bool PPC::isAllNegativeZeroVector(SDNode *N) { 612 assert(N->getOpcode() == ISD::BUILD_VECTOR); 613 if (PPC::isSplatShuffleMask(N, N->getNumOperands())) 614 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N)) 615 return CFP->getValueAPF().isNegZero(); 616 return false; 617} 618 619/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 620/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 621unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 622 assert(isSplatShuffleMask(N, EltSize)); 623 return cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() / EltSize; 624} 625 626/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 627/// by using a vspltis[bhw] instruction of the specified element size, return 628/// the constant being splatted. The ByteSize field indicates the number of 629/// bytes of each element [124] -> [bhw]. 630SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 631 SDValue OpVal(0, 0); 632 633 // If ByteSize of the splat is bigger than the element size of the 634 // build_vector, then we have a case where we are checking for a splat where 635 // multiple elements of the buildvector are folded together into a single 636 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 637 unsigned EltSize = 16/N->getNumOperands(); 638 if (EltSize < ByteSize) { 639 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 640 SDValue UniquedVals[4]; 641 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 642 643 // See if all of the elements in the buildvector agree across. 644 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 645 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 646 // If the element isn't a constant, bail fully out. 647 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue(); 648 649 650 if (UniquedVals[i&(Multiple-1)].getNode() == 0) 651 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 652 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 653 return SDValue(); // no match. 654 } 655 656 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 657 // either constant or undef values that are identical for each chunk. See 658 // if these chunks can form into a larger vspltis*. 659 660 // Check to see if all of the leading entries are either 0 or -1. If 661 // neither, then this won't fit into the immediate field. 662 bool LeadingZero = true; 663 bool LeadingOnes = true; 664 for (unsigned i = 0; i != Multiple-1; ++i) { 665 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs. 666 667 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 668 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 669 } 670 // Finally, check the least significant entry. 671 if (LeadingZero) { 672 if (UniquedVals[Multiple-1].getNode() == 0) 673 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 674 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue(); 675 if (Val < 16) 676 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 677 } 678 if (LeadingOnes) { 679 if (UniquedVals[Multiple-1].getNode() == 0) 680 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 681 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue(); 682 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 683 return DAG.getTargetConstant(Val, MVT::i32); 684 } 685 686 return SDValue(); 687 } 688 689 // Check to see if this buildvec has a single non-undef value in its elements. 690 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 691 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 692 if (OpVal.getNode() == 0) 693 OpVal = N->getOperand(i); 694 else if (OpVal != N->getOperand(i)) 695 return SDValue(); 696 } 697 698 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def. 699 700 unsigned ValSizeInBytes = 0; 701 uint64_t Value = 0; 702 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 703 Value = CN->getZExtValue(); 704 ValSizeInBytes = CN->getValueType(0).getSizeInBits()/8; 705 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 706 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 707 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 708 ValSizeInBytes = 4; 709 } 710 711 // If the splat value is larger than the element value, then we can never do 712 // this splat. The only case that we could fit the replicated bits into our 713 // immediate field for would be zero, and we prefer to use vxor for it. 714 if (ValSizeInBytes < ByteSize) return SDValue(); 715 716 // If the element value is larger than the splat value, cut it in half and 717 // check to see if the two halves are equal. Continue doing this until we 718 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 719 while (ValSizeInBytes > ByteSize) { 720 ValSizeInBytes >>= 1; 721 722 // If the top half equals the bottom half, we're still ok. 723 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 724 (Value & ((1 << (8*ValSizeInBytes))-1))) 725 return SDValue(); 726 } 727 728 // Properly sign extend the value. 729 int ShAmt = (4-ByteSize)*8; 730 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 731 732 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 733 if (MaskVal == 0) return SDValue(); 734 735 // Finally, if this value fits in a 5 bit sext field, return it 736 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 737 return DAG.getTargetConstant(MaskVal, MVT::i32); 738 return SDValue(); 739} 740 741//===----------------------------------------------------------------------===// 742// Addressing Mode Selection 743//===----------------------------------------------------------------------===// 744 745/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 746/// or 64-bit immediate, and if the value can be accurately represented as a 747/// sign extension from a 16-bit value. If so, this returns true and the 748/// immediate. 749static bool isIntS16Immediate(SDNode *N, short &Imm) { 750 if (N->getOpcode() != ISD::Constant) 751 return false; 752 753 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 754 if (N->getValueType(0) == MVT::i32) 755 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 756 else 757 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 758} 759static bool isIntS16Immediate(SDValue Op, short &Imm) { 760 return isIntS16Immediate(Op.getNode(), Imm); 761} 762 763 764/// SelectAddressRegReg - Given the specified addressed, check to see if it 765/// can be represented as an indexed [r+r] operation. Returns false if it 766/// can be more efficiently represented with [r+imm]. 767bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, 768 SDValue &Index, 769 SelectionDAG &DAG) const { 770 short imm = 0; 771 if (N.getOpcode() == ISD::ADD) { 772 if (isIntS16Immediate(N.getOperand(1), imm)) 773 return false; // r+i 774 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 775 return false; // r+i 776 777 Base = N.getOperand(0); 778 Index = N.getOperand(1); 779 return true; 780 } else if (N.getOpcode() == ISD::OR) { 781 if (isIntS16Immediate(N.getOperand(1), imm)) 782 return false; // r+i can fold it if we can. 783 784 // If this is an or of disjoint bitfields, we can codegen this as an add 785 // (for better address arithmetic) if the LHS and RHS of the OR are provably 786 // disjoint. 787 APInt LHSKnownZero, LHSKnownOne; 788 APInt RHSKnownZero, RHSKnownOne; 789 DAG.ComputeMaskedBits(N.getOperand(0), 790 APInt::getAllOnesValue(N.getOperand(0) 791 .getValueSizeInBits()), 792 LHSKnownZero, LHSKnownOne); 793 794 if (LHSKnownZero.getBoolValue()) { 795 DAG.ComputeMaskedBits(N.getOperand(1), 796 APInt::getAllOnesValue(N.getOperand(1) 797 .getValueSizeInBits()), 798 RHSKnownZero, RHSKnownOne); 799 // If all of the bits are known zero on the LHS or RHS, the add won't 800 // carry. 801 if (~(LHSKnownZero | RHSKnownZero) == 0) { 802 Base = N.getOperand(0); 803 Index = N.getOperand(1); 804 return true; 805 } 806 } 807 } 808 809 return false; 810} 811 812/// Returns true if the address N can be represented by a base register plus 813/// a signed 16-bit displacement [r+imm], and if it is not better 814/// represented as reg+reg. 815bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, 816 SDValue &Base, 817 SelectionDAG &DAG) const { 818 // If this can be more profitably realized as r+r, fail. 819 if (SelectAddressRegReg(N, Disp, Base, DAG)) 820 return false; 821 822 if (N.getOpcode() == ISD::ADD) { 823 short imm = 0; 824 if (isIntS16Immediate(N.getOperand(1), imm)) { 825 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 826 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 827 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 828 } else { 829 Base = N.getOperand(0); 830 } 831 return true; // [r+i] 832 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 833 // Match LOAD (ADD (X, Lo(G))). 834 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 835 && "Cannot handle constant offsets yet!"); 836 Disp = N.getOperand(1).getOperand(0); // The global address. 837 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 838 Disp.getOpcode() == ISD::TargetConstantPool || 839 Disp.getOpcode() == ISD::TargetJumpTable); 840 Base = N.getOperand(0); 841 return true; // [&g+r] 842 } 843 } else if (N.getOpcode() == ISD::OR) { 844 short imm = 0; 845 if (isIntS16Immediate(N.getOperand(1), imm)) { 846 // If this is an or of disjoint bitfields, we can codegen this as an add 847 // (for better address arithmetic) if the LHS and RHS of the OR are 848 // provably disjoint. 849 APInt LHSKnownZero, LHSKnownOne; 850 DAG.ComputeMaskedBits(N.getOperand(0), 851 APInt::getAllOnesValue(N.getOperand(0) 852 .getValueSizeInBits()), 853 LHSKnownZero, LHSKnownOne); 854 855 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 856 // If all of the bits are known zero on the LHS or RHS, the add won't 857 // carry. 858 Base = N.getOperand(0); 859 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 860 return true; 861 } 862 } 863 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 864 // Loading from a constant address. 865 866 // If this address fits entirely in a 16-bit sext immediate field, codegen 867 // this as "d, 0" 868 short Imm; 869 if (isIntS16Immediate(CN, Imm)) { 870 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 871 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 872 return true; 873 } 874 875 // Handle 32-bit sext immediates with LIS + addr mode. 876 if (CN->getValueType(0) == MVT::i32 || 877 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 878 int Addr = (int)CN->getZExtValue(); 879 880 // Otherwise, break this down into an LIS + disp. 881 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 882 883 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 884 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 885 Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 886 return true; 887 } 888 } 889 890 Disp = DAG.getTargetConstant(0, getPointerTy()); 891 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 892 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 893 else 894 Base = N; 895 return true; // [r+0] 896} 897 898/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 899/// represented as an indexed [r+r] operation. 900bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, 901 SDValue &Index, 902 SelectionDAG &DAG) const { 903 // Check to see if we can easily represent this as an [r+r] address. This 904 // will fail if it thinks that the address is more profitably represented as 905 // reg+imm, e.g. where imm = 0. 906 if (SelectAddressRegReg(N, Base, Index, DAG)) 907 return true; 908 909 // If the operand is an addition, always emit this as [r+r], since this is 910 // better (for code size, and execution, as the memop does the add for free) 911 // than emitting an explicit add. 912 if (N.getOpcode() == ISD::ADD) { 913 Base = N.getOperand(0); 914 Index = N.getOperand(1); 915 return true; 916 } 917 918 // Otherwise, do it the hard way, using R0 as the base register. 919 Base = DAG.getRegister(PPC::R0, N.getValueType()); 920 Index = N; 921 return true; 922} 923 924/// SelectAddressRegImmShift - Returns true if the address N can be 925/// represented by a base register plus a signed 14-bit displacement 926/// [r+imm*4]. Suitable for use by STD and friends. 927bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, 928 SDValue &Base, 929 SelectionDAG &DAG) const { 930 // If this can be more profitably realized as r+r, fail. 931 if (SelectAddressRegReg(N, Disp, Base, DAG)) 932 return false; 933 934 if (N.getOpcode() == ISD::ADD) { 935 short imm = 0; 936 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 937 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 938 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 939 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 940 } else { 941 Base = N.getOperand(0); 942 } 943 return true; // [r+i] 944 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 945 // Match LOAD (ADD (X, Lo(G))). 946 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 947 && "Cannot handle constant offsets yet!"); 948 Disp = N.getOperand(1).getOperand(0); // The global address. 949 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 950 Disp.getOpcode() == ISD::TargetConstantPool || 951 Disp.getOpcode() == ISD::TargetJumpTable); 952 Base = N.getOperand(0); 953 return true; // [&g+r] 954 } 955 } else if (N.getOpcode() == ISD::OR) { 956 short imm = 0; 957 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 958 // If this is an or of disjoint bitfields, we can codegen this as an add 959 // (for better address arithmetic) if the LHS and RHS of the OR are 960 // provably disjoint. 961 APInt LHSKnownZero, LHSKnownOne; 962 DAG.ComputeMaskedBits(N.getOperand(0), 963 APInt::getAllOnesValue(N.getOperand(0) 964 .getValueSizeInBits()), 965 LHSKnownZero, LHSKnownOne); 966 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 967 // If all of the bits are known zero on the LHS or RHS, the add won't 968 // carry. 969 Base = N.getOperand(0); 970 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 971 return true; 972 } 973 } 974 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 975 // Loading from a constant address. Verify low two bits are clear. 976 if ((CN->getZExtValue() & 3) == 0) { 977 // If this address fits entirely in a 14-bit sext immediate field, codegen 978 // this as "d, 0" 979 short Imm; 980 if (isIntS16Immediate(CN, Imm)) { 981 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 982 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 983 return true; 984 } 985 986 // Fold the low-part of 32-bit absolute addresses into addr mode. 987 if (CN->getValueType(0) == MVT::i32 || 988 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 989 int Addr = (int)CN->getZExtValue(); 990 991 // Otherwise, break this down into an LIS + disp. 992 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 993 994 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 995 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 996 Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 997 return true; 998 } 999 } 1000 } 1001 1002 Disp = DAG.getTargetConstant(0, getPointerTy()); 1003 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1004 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1005 else 1006 Base = N; 1007 return true; // [r+0] 1008} 1009 1010 1011/// getPreIndexedAddressParts - returns true by value, base pointer and 1012/// offset pointer and addressing mode by reference if the node's address 1013/// can be legally represented as pre-indexed load / store address. 1014bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1015 SDValue &Offset, 1016 ISD::MemIndexedMode &AM, 1017 SelectionDAG &DAG) const { 1018 // Disabled by default for now. 1019 if (!EnablePPCPreinc) return false; 1020 1021 SDValue Ptr; 1022 MVT VT; 1023 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1024 Ptr = LD->getBasePtr(); 1025 VT = LD->getMemoryVT(); 1026 1027 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1028 ST = ST; 1029 Ptr = ST->getBasePtr(); 1030 VT = ST->getMemoryVT(); 1031 } else 1032 return false; 1033 1034 // PowerPC doesn't have preinc load/store instructions for vectors. 1035 if (VT.isVector()) 1036 return false; 1037 1038 // TODO: Check reg+reg first. 1039 1040 // LDU/STU use reg+imm*4, others use reg+imm. 1041 if (VT != MVT::i64) { 1042 // reg + imm 1043 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 1044 return false; 1045 } else { 1046 // reg + imm * 4. 1047 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 1048 return false; 1049 } 1050 1051 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1052 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 1053 // sext i32 to i64 when addr mode is r+i. 1054 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 1055 LD->getExtensionType() == ISD::SEXTLOAD && 1056 isa<ConstantSDNode>(Offset)) 1057 return false; 1058 } 1059 1060 AM = ISD::PRE_INC; 1061 return true; 1062} 1063 1064//===----------------------------------------------------------------------===// 1065// LowerOperation implementation 1066//===----------------------------------------------------------------------===// 1067 1068SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, 1069 SelectionDAG &DAG) { 1070 MVT PtrVT = Op.getValueType(); 1071 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1072 Constant *C = CP->getConstVal(); 1073 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 1074 SDValue Zero = DAG.getConstant(0, PtrVT); 1075 1076 const TargetMachine &TM = DAG.getTarget(); 1077 1078 SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); 1079 SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); 1080 1081 // If this is a non-darwin platform, we don't support non-static relo models 1082 // yet. 1083 if (TM.getRelocationModel() == Reloc::Static || 1084 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1085 // Generate non-pic code that has direct accesses to the constant pool. 1086 // The address of the global is just (hi(&g)+lo(&g)). 1087 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1088 } 1089 1090 if (TM.getRelocationModel() == Reloc::PIC_) { 1091 // With PIC, the first instruction is actually "GR+hi(&G)". 1092 Hi = DAG.getNode(ISD::ADD, PtrVT, 1093 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1094 } 1095 1096 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1097 return Lo; 1098} 1099 1100SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { 1101 MVT PtrVT = Op.getValueType(); 1102 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1103 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1104 SDValue Zero = DAG.getConstant(0, PtrVT); 1105 1106 const TargetMachine &TM = DAG.getTarget(); 1107 1108 SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); 1109 SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); 1110 1111 // If this is a non-darwin platform, we don't support non-static relo models 1112 // yet. 1113 if (TM.getRelocationModel() == Reloc::Static || 1114 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1115 // Generate non-pic code that has direct accesses to the constant pool. 1116 // The address of the global is just (hi(&g)+lo(&g)). 1117 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1118 } 1119 1120 if (TM.getRelocationModel() == Reloc::PIC_) { 1121 // With PIC, the first instruction is actually "GR+hi(&G)". 1122 Hi = DAG.getNode(ISD::ADD, PtrVT, 1123 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1124 } 1125 1126 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1127 return Lo; 1128} 1129 1130SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, 1131 SelectionDAG &DAG) { 1132 assert(0 && "TLS not implemented for PPC."); 1133 return SDValue(); // Not reached 1134} 1135 1136SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, 1137 SelectionDAG &DAG) { 1138 MVT PtrVT = Op.getValueType(); 1139 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1140 GlobalValue *GV = GSDN->getGlobal(); 1141 SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); 1142 SDValue Zero = DAG.getConstant(0, PtrVT); 1143 DebugLoc dl = GSDN->getDebugLoc(); 1144 1145 const TargetMachine &TM = DAG.getTarget(); 1146 1147 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero); 1148 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero); 1149 1150 // If this is a non-darwin platform, we don't support non-static relo models 1151 // yet. 1152 if (TM.getRelocationModel() == Reloc::Static || 1153 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1154 // Generate non-pic code that has direct accesses to globals. 1155 // The address of the global is just (hi(&g)+lo(&g)). 1156 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1157 } 1158 1159 if (TM.getRelocationModel() == Reloc::PIC_) { 1160 // With PIC, the first instruction is actually "GR+hi(&G)". 1161 Hi = DAG.getNode(ISD::ADD, dl, PtrVT, 1162 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1163 } 1164 1165 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1166 1167 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV)) 1168 return Lo; 1169 1170 // If the global is weak or external, we have to go through the lazy 1171 // resolution stub. 1172 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0); 1173} 1174 1175SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { 1176 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1177 DebugLoc dl = Op.getNode()->getDebugLoc(); 1178 1179 // If we're comparing for equality to zero, expose the fact that this is 1180 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1181 // fold the new nodes. 1182 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1183 if (C->isNullValue() && CC == ISD::SETEQ) { 1184 MVT VT = Op.getOperand(0).getValueType(); 1185 SDValue Zext = Op.getOperand(0); 1186 if (VT.bitsLT(MVT::i32)) { 1187 VT = MVT::i32; 1188 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); 1189 } 1190 unsigned Log2b = Log2_32(VT.getSizeInBits()); 1191 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); 1192 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, 1193 DAG.getConstant(Log2b, MVT::i32)); 1194 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); 1195 } 1196 // Leave comparisons against 0 and -1 alone for now, since they're usually 1197 // optimized. FIXME: revisit this when we can custom lower all setcc 1198 // optimizations. 1199 if (C->isAllOnesValue() || C->isNullValue()) 1200 return SDValue(); 1201 } 1202 1203 // If we have an integer seteq/setne, turn it into a compare against zero 1204 // by xor'ing the rhs with the lhs, which is faster than setting a 1205 // condition register, reading it back out, and masking the correct bit. The 1206 // normal approach here uses sub to do this instead of xor. Using xor exposes 1207 // the result to other bit-twiddling opportunities. 1208 MVT LHSVT = Op.getOperand(0).getValueType(); 1209 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1210 MVT VT = Op.getValueType(); 1211 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), 1212 Op.getOperand(1)); 1213 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); 1214 } 1215 return SDValue(); 1216} 1217 1218SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, 1219 int VarArgsFrameIndex, 1220 int VarArgsStackOffset, 1221 unsigned VarArgsNumGPR, 1222 unsigned VarArgsNumFPR, 1223 const PPCSubtarget &Subtarget) { 1224 1225 assert(0 && "VAARG in ELF32 ABI not implemented yet!"); 1226 return SDValue(); // Not reached 1227} 1228 1229SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) { 1230 SDValue Chain = Op.getOperand(0); 1231 SDValue Trmp = Op.getOperand(1); // trampoline 1232 SDValue FPtr = Op.getOperand(2); // nested function 1233 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 1234 DebugLoc dl = Op.getNode()->getDebugLoc(); 1235 1236 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1237 bool isPPC64 = (PtrVT == MVT::i64); 1238 const Type *IntPtrTy = 1239 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType(); 1240 1241 TargetLowering::ArgListTy Args; 1242 TargetLowering::ArgListEntry Entry; 1243 1244 Entry.Ty = IntPtrTy; 1245 Entry.Node = Trmp; Args.push_back(Entry); 1246 1247 // TrampSize == (isPPC64 ? 48 : 40); 1248 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, 1249 isPPC64 ? MVT::i64 : MVT::i32); 1250 Args.push_back(Entry); 1251 1252 Entry.Node = FPtr; Args.push_back(Entry); 1253 Entry.Node = Nest; Args.push_back(Entry); 1254 1255 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) 1256 std::pair<SDValue, SDValue> CallResult = 1257 LowerCallTo(Chain, Op.getValueType().getTypeForMVT(), false, false, 1258 false, false, CallingConv::C, false, 1259 DAG.getExternalSymbol("__trampoline_setup", PtrVT), 1260 Args, DAG, dl); 1261 1262 SDValue Ops[] = 1263 { CallResult.first, CallResult.second }; 1264 1265 return DAG.getMergeValues(Ops, 2, dl); 1266} 1267 1268SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, 1269 int VarArgsFrameIndex, 1270 int VarArgsStackOffset, 1271 unsigned VarArgsNumGPR, 1272 unsigned VarArgsNumFPR, 1273 const PPCSubtarget &Subtarget) { 1274 DebugLoc dl = Op.getNode()->getDebugLoc(); 1275 1276 if (Subtarget.isMachoABI()) { 1277 // vastart just stores the address of the VarArgsFrameIndex slot into the 1278 // memory location argument. 1279 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1280 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1281 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1282 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); 1283 } 1284 1285 // For ELF 32 ABI we follow the layout of the va_list struct. 1286 // We suppose the given va_list is already allocated. 1287 // 1288 // typedef struct { 1289 // char gpr; /* index into the array of 8 GPRs 1290 // * stored in the register save area 1291 // * gpr=0 corresponds to r3, 1292 // * gpr=1 to r4, etc. 1293 // */ 1294 // char fpr; /* index into the array of 8 FPRs 1295 // * stored in the register save area 1296 // * fpr=0 corresponds to f1, 1297 // * fpr=1 to f2, etc. 1298 // */ 1299 // char *overflow_arg_area; 1300 // /* location on stack that holds 1301 // * the next overflow argument 1302 // */ 1303 // char *reg_save_area; 1304 // /* where r3:r10 and f1:f8 (if saved) 1305 // * are stored 1306 // */ 1307 // } va_list[1]; 1308 1309 1310 SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8); 1311 SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8); 1312 1313 1314 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1315 1316 SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); 1317 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1318 1319 uint64_t FrameOffset = PtrVT.getSizeInBits()/8; 1320 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1321 1322 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; 1323 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1324 1325 uint64_t FPROffset = 1; 1326 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1327 1328 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1329 1330 // Store first byte : number of int regs 1331 SDValue firstStore = DAG.getStore(Op.getOperand(0), dl, ArgGPR, 1332 Op.getOperand(1), SV, 0); 1333 uint64_t nextOffset = FPROffset; 1334 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), 1335 ConstFPROffset); 1336 1337 // Store second byte : number of float regs 1338 SDValue secondStore = 1339 DAG.getStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset); 1340 nextOffset += StackOffset; 1341 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); 1342 1343 // Store second word : arguments given on stack 1344 SDValue thirdStore = 1345 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset); 1346 nextOffset += FrameOffset; 1347 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset); 1348 1349 // Store third word : arguments given in registers 1350 return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset); 1351 1352} 1353 1354#include "PPCGenCallingConv.inc" 1355 1356/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1357/// depending on which subtarget is selected. 1358static const unsigned *GetFPR(const PPCSubtarget &Subtarget) { 1359 if (Subtarget.isMachoABI()) { 1360 static const unsigned FPR[] = { 1361 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1362 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1363 }; 1364 return FPR; 1365 } 1366 1367 1368 static const unsigned FPR[] = { 1369 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1370 PPC::F8 1371 }; 1372 return FPR; 1373} 1374 1375/// CalculateStackSlotSize - Calculates the size reserved for this argument on 1376/// the stack. 1377static unsigned CalculateStackSlotSize(SDValue Arg, ISD::ArgFlagsTy Flags, 1378 bool isVarArg, unsigned PtrByteSize) { 1379 MVT ArgVT = Arg.getValueType(); 1380 unsigned ArgSize =ArgVT.getSizeInBits()/8; 1381 if (Flags.isByVal()) 1382 ArgSize = Flags.getByValSize(); 1383 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1384 1385 return ArgSize; 1386} 1387 1388SDValue 1389PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, 1390 SelectionDAG &DAG, 1391 int &VarArgsFrameIndex, 1392 int &VarArgsStackOffset, 1393 unsigned &VarArgsNumGPR, 1394 unsigned &VarArgsNumFPR, 1395 const PPCSubtarget &Subtarget) { 1396 // TODO: add description of PPC stack frame format, or at least some docs. 1397 // 1398 MachineFunction &MF = DAG.getMachineFunction(); 1399 MachineFrameInfo *MFI = MF.getFrameInfo(); 1400 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 1401 SmallVector<SDValue, 8> ArgValues; 1402 SDValue Root = Op.getOperand(0); 1403 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0; 1404 DebugLoc dl = Op.getNode()->getDebugLoc(); 1405 1406 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1407 bool isPPC64 = PtrVT == MVT::i64; 1408 bool isMachoABI = Subtarget.isMachoABI(); 1409 bool isELF32_ABI = Subtarget.isELF32_ABI(); 1410 // Potential tail calls could cause overwriting of argument stack slots. 1411 unsigned CC = MF.getFunction()->getCallingConv(); 1412 bool isImmutable = !(PerformTailCallOpt && (CC==CallingConv::Fast)); 1413 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1414 1415 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1416 // Area that is at least reserved in caller of this function. 1417 unsigned MinReservedArea = ArgOffset; 1418 1419 static const unsigned GPR_32[] = { // 32-bit registers. 1420 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1421 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1422 }; 1423 static const unsigned GPR_64[] = { // 64-bit registers. 1424 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1425 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1426 }; 1427 1428 static const unsigned *FPR = GetFPR(Subtarget); 1429 1430 static const unsigned VR[] = { 1431 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1432 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1433 }; 1434 1435 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 1436 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8; 1437 const unsigned Num_VR_Regs = array_lengthof( VR); 1438 1439 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1440 1441 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1442 1443 // In 32-bit non-varargs functions, the stack space for vectors is after the 1444 // stack space for non-vectors. We do not use this space unless we have 1445 // too many vectors to fit in registers, something that only occurs in 1446 // constructed examples:), but we have to walk the arglist to figure 1447 // that out...for the pathological case, compute VecArgOffset as the 1448 // start of the vector parameter area. Computing VecArgOffset is the 1449 // entire point of the following loop. 1450 // Altivec is not mentioned in the ppc32 Elf Supplement, so I'm not trying 1451 // to handle Elf here. 1452 unsigned VecArgOffset = ArgOffset; 1453 if (!isVarArg && !isPPC64) { 1454 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e; 1455 ++ArgNo) { 1456 MVT ObjectVT = Op.getValue(ArgNo).getValueType(); 1457 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1458 ISD::ArgFlagsTy Flags = 1459 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags(); 1460 1461 if (Flags.isByVal()) { 1462 // ObjSize is the true size, ArgSize rounded up to multiple of regs. 1463 ObjSize = Flags.getByValSize(); 1464 unsigned ArgSize = 1465 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1466 VecArgOffset += ArgSize; 1467 continue; 1468 } 1469 1470 switch(ObjectVT.getSimpleVT()) { 1471 default: assert(0 && "Unhandled argument type!"); 1472 case MVT::i32: 1473 case MVT::f32: 1474 VecArgOffset += isPPC64 ? 8 : 4; 1475 break; 1476 case MVT::i64: // PPC64 1477 case MVT::f64: 1478 VecArgOffset += 8; 1479 break; 1480 case MVT::v4f32: 1481 case MVT::v4i32: 1482 case MVT::v8i16: 1483 case MVT::v16i8: 1484 // Nothing to do, we're only looking at Nonvector args here. 1485 break; 1486 } 1487 } 1488 } 1489 // We've found where the vector parameter area in memory is. Skip the 1490 // first 12 parameters; these don't use that memory. 1491 VecArgOffset = ((VecArgOffset+15)/16)*16; 1492 VecArgOffset += 12*16; 1493 1494 // Add DAG nodes to load the arguments or copy them out of registers. On 1495 // entry to a function on PPC, the arguments start after the linkage area, 1496 // although the first ones are often in registers. 1497 // 1498 // In the ELF 32 ABI, GPRs and stack are double word align: an argument 1499 // represented with two words (long long or double) must be copied to an 1500 // even GPR_idx value or to an even ArgOffset value. 1501 1502 SmallVector<SDValue, 8> MemOps; 1503 unsigned nAltivecParamsAtEnd = 0; 1504 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues() - 1; 1505 ArgNo != e; ++ArgNo) { 1506 SDValue ArgVal; 1507 bool needsLoad = false; 1508 MVT ObjectVT = Op.getValue(ArgNo).getValueType(); 1509 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1510 unsigned ArgSize = ObjSize; 1511 ISD::ArgFlagsTy Flags = 1512 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags(); 1513 // See if next argument requires stack alignment in ELF 1514 bool Align = Flags.isSplit(); 1515 1516 unsigned CurArgOffset = ArgOffset; 1517 1518 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 1519 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 1520 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 1521 if (isVarArg || isPPC64) { 1522 MinReservedArea = ((MinReservedArea+15)/16)*16; 1523 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo), 1524 Flags, 1525 isVarArg, 1526 PtrByteSize); 1527 } else nAltivecParamsAtEnd++; 1528 } else 1529 // Calculate min reserved area. 1530 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo), 1531 Flags, 1532 isVarArg, 1533 PtrByteSize); 1534 1535 // FIXME alignment for ELF may not be right 1536 // FIXME the codegen can be much improved in some cases. 1537 // We do not have to keep everything in memory. 1538 if (Flags.isByVal()) { 1539 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 1540 ObjSize = Flags.getByValSize(); 1541 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1542 // Double word align in ELF 1543 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2); 1544 // Objects of size 1 and 2 are right justified, everything else is 1545 // left justified. This means the memory address is adjusted forwards. 1546 if (ObjSize==1 || ObjSize==2) { 1547 CurArgOffset = CurArgOffset + (4 - ObjSize); 1548 } 1549 // The value of the object is its address. 1550 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset); 1551 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1552 ArgValues.push_back(FIN); 1553 if (ObjSize==1 || ObjSize==2) { 1554 if (GPR_idx != Num_GPR_Regs) { 1555 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1556 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1557 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT); 1558 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 1559 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 ); 1560 MemOps.push_back(Store); 1561 ++GPR_idx; 1562 if (isMachoABI) ArgOffset += PtrByteSize; 1563 } else { 1564 ArgOffset += PtrByteSize; 1565 } 1566 continue; 1567 } 1568 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 1569 // Store whatever pieces of the object are in registers 1570 // to memory. ArgVal will be address of the beginning of 1571 // the object. 1572 if (GPR_idx != Num_GPR_Regs) { 1573 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1574 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1575 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset); 1576 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1577 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT); 1578 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); 1579 MemOps.push_back(Store); 1580 ++GPR_idx; 1581 if (isMachoABI) ArgOffset += PtrByteSize; 1582 } else { 1583 ArgOffset += ArgSize - (ArgOffset-CurArgOffset); 1584 break; 1585 } 1586 } 1587 continue; 1588 } 1589 1590 switch (ObjectVT.getSimpleVT()) { 1591 default: assert(0 && "Unhandled argument type!"); 1592 case MVT::i32: 1593 if (!isPPC64) { 1594 // Double word align in ELF 1595 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2); 1596 1597 if (GPR_idx != Num_GPR_Regs) { 1598 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1599 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1600 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); 1601 ++GPR_idx; 1602 } else { 1603 needsLoad = true; 1604 ArgSize = PtrByteSize; 1605 } 1606 // Stack align in ELF 1607 if (needsLoad && Align && isELF32_ABI) 1608 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1609 // All int arguments reserve stack space in Macho ABI. 1610 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize; 1611 break; 1612 } 1613 // FALLTHROUGH 1614 case MVT::i64: // PPC64 1615 if (GPR_idx != Num_GPR_Regs) { 1616 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); 1617 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1618 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64); 1619 1620 if (ObjectVT == MVT::i32) { 1621 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 1622 // value to MVT::i64 and then truncate to the correct register size. 1623 if (Flags.isSExt()) 1624 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, 1625 DAG.getValueType(ObjectVT)); 1626 else if (Flags.isZExt()) 1627 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, 1628 DAG.getValueType(ObjectVT)); 1629 1630 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); 1631 } 1632 1633 ++GPR_idx; 1634 } else { 1635 needsLoad = true; 1636 ArgSize = PtrByteSize; 1637 } 1638 // All int arguments reserve stack space in Macho ABI. 1639 if (isMachoABI || needsLoad) ArgOffset += 8; 1640 break; 1641 1642 case MVT::f32: 1643 case MVT::f64: 1644 // Every 4 bytes of argument space consumes one of the GPRs available for 1645 // argument passing. 1646 if (GPR_idx != Num_GPR_Regs && isMachoABI) { 1647 ++GPR_idx; 1648 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 1649 ++GPR_idx; 1650 } 1651 if (FPR_idx != Num_FPR_Regs) { 1652 unsigned VReg; 1653 if (ObjectVT == MVT::f32) 1654 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass); 1655 else 1656 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); 1657 RegInfo.addLiveIn(FPR[FPR_idx], VReg); 1658 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT); 1659 ++FPR_idx; 1660 } else { 1661 needsLoad = true; 1662 } 1663 1664 // Stack align in ELF 1665 if (needsLoad && Align && isELF32_ABI) 1666 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1667 // All FP arguments reserve stack space in Macho ABI. 1668 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize; 1669 break; 1670 case MVT::v4f32: 1671 case MVT::v4i32: 1672 case MVT::v8i16: 1673 case MVT::v16i8: 1674 // Note that vector arguments in registers don't reserve stack space, 1675 // except in varargs functions. 1676 if (VR_idx != Num_VR_Regs) { 1677 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass); 1678 RegInfo.addLiveIn(VR[VR_idx], VReg); 1679 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT); 1680 if (isVarArg) { 1681 while ((ArgOffset % 16) != 0) { 1682 ArgOffset += PtrByteSize; 1683 if (GPR_idx != Num_GPR_Regs) 1684 GPR_idx++; 1685 } 1686 ArgOffset += 16; 1687 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); 1688 } 1689 ++VR_idx; 1690 } else { 1691 if (!isVarArg && !isPPC64) { 1692 // Vectors go after all the nonvectors. 1693 CurArgOffset = VecArgOffset; 1694 VecArgOffset += 16; 1695 } else { 1696 // Vectors are aligned. 1697 ArgOffset = ((ArgOffset+15)/16)*16; 1698 CurArgOffset = ArgOffset; 1699 ArgOffset += 16; 1700 } 1701 needsLoad = true; 1702 } 1703 break; 1704 } 1705 1706 // We need to load the argument to a virtual register if we determined above 1707 // that we ran out of physical registers of the appropriate type. 1708 if (needsLoad) { 1709 int FI = MFI->CreateFixedObject(ObjSize, 1710 CurArgOffset + (ArgSize - ObjSize), 1711 isImmutable); 1712 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1713 ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0); 1714 } 1715 1716 ArgValues.push_back(ArgVal); 1717 } 1718 1719 // Set the size that is at least reserved in caller of this function. Tail 1720 // call optimized function's reserved stack space needs to be aligned so that 1721 // taking the difference between two stack areas will result in an aligned 1722 // stack. 1723 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1724 // Add the Altivec parameters at the end, if needed. 1725 if (nAltivecParamsAtEnd) { 1726 MinReservedArea = ((MinReservedArea+15)/16)*16; 1727 MinReservedArea += 16*nAltivecParamsAtEnd; 1728 } 1729 MinReservedArea = 1730 std::max(MinReservedArea, 1731 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI)); 1732 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 1733 getStackAlignment(); 1734 unsigned AlignMask = TargetAlign-1; 1735 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 1736 FI->setMinReservedArea(MinReservedArea); 1737 1738 // If the function takes variable number of arguments, make a frame index for 1739 // the start of the first vararg value... for expansion of llvm.va_start. 1740 if (isVarArg) { 1741 1742 int depth; 1743 if (isELF32_ABI) { 1744 VarArgsNumGPR = GPR_idx; 1745 VarArgsNumFPR = FPR_idx; 1746 1747 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame 1748 // pointer. 1749 depth = -(Num_GPR_Regs * PtrVT.getSizeInBits()/8 + 1750 Num_FPR_Regs * MVT(MVT::f64).getSizeInBits()/8 + 1751 PtrVT.getSizeInBits()/8); 1752 1753 VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 1754 ArgOffset); 1755 1756 } 1757 else 1758 depth = ArgOffset; 1759 1760 VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 1761 depth); 1762 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1763 1764 // In ELF 32 ABI, the fixed integer arguments of a variadic function are 1765 // stored to the VarArgsFrameIndex on the stack. 1766 if (isELF32_ABI) { 1767 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) { 1768 SDValue Val = DAG.getRegister(GPR[GPR_idx], PtrVT); 1769 SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0); 1770 MemOps.push_back(Store); 1771 // Increment the address by four for the next argument to store 1772 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 1773 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1774 } 1775 } 1776 1777 // If this function is vararg, store any remaining integer argument regs 1778 // to their spots on the stack so that they may be loaded by deferencing the 1779 // result of va_next. 1780 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 1781 unsigned VReg; 1782 if (isPPC64) 1783 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); 1784 else 1785 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1786 1787 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1788 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT); 1789 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); 1790 MemOps.push_back(Store); 1791 // Increment the address by four for the next argument to store 1792 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 1793 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1794 } 1795 1796 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex 1797 // on the stack. 1798 if (isELF32_ABI) { 1799 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) { 1800 SDValue Val = DAG.getRegister(FPR[FPR_idx], MVT::f64); 1801 SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0); 1802 MemOps.push_back(Store); 1803 // Increment the address by eight for the next argument to store 1804 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, 1805 PtrVT); 1806 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1807 } 1808 1809 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) { 1810 unsigned VReg; 1811 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); 1812 1813 RegInfo.addLiveIn(FPR[FPR_idx], VReg); 1814 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::f64); 1815 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); 1816 MemOps.push_back(Store); 1817 // Increment the address by eight for the next argument to store 1818 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, 1819 PtrVT); 1820 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1821 } 1822 } 1823 } 1824 1825 if (!MemOps.empty()) 1826 Root = DAG.getNode(ISD::TokenFactor, dl, 1827 MVT::Other, &MemOps[0], MemOps.size()); 1828 1829 ArgValues.push_back(Root); 1830 1831 // Return the new list of results. 1832 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), 1833 &ArgValues[0], ArgValues.size()); 1834} 1835 1836/// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus 1837/// linkage area. 1838static unsigned 1839CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, 1840 bool isPPC64, 1841 bool isMachoABI, 1842 bool isVarArg, 1843 unsigned CC, 1844 CallSDNode *TheCall, 1845 unsigned &nAltivecParamsAtEnd) { 1846 // Count how many bytes are to be pushed on the stack, including the linkage 1847 // area, and parameter passing area. We start with 24/48 bytes, which is 1848 // prereserved space for [SP][CR][LR][3 x unused]. 1849 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1850 unsigned NumOps = TheCall->getNumArgs(); 1851 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1852 1853 // Add up all the space actually used. 1854 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually 1855 // they all go in registers, but we must reserve stack space for them for 1856 // possible use by the caller. In varargs or 64-bit calls, parameters are 1857 // assigned stack space in order, with padding so Altivec parameters are 1858 // 16-byte aligned. 1859 nAltivecParamsAtEnd = 0; 1860 for (unsigned i = 0; i != NumOps; ++i) { 1861 SDValue Arg = TheCall->getArg(i); 1862 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i); 1863 MVT ArgVT = Arg.getValueType(); 1864 // Varargs Altivec parameters are padded to a 16 byte boundary. 1865 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 1866 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { 1867 if (!isVarArg && !isPPC64) { 1868 // Non-varargs Altivec parameters go after all the non-Altivec 1869 // parameters; handle those later so we know how much padding we need. 1870 nAltivecParamsAtEnd++; 1871 continue; 1872 } 1873 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. 1874 NumBytes = ((NumBytes+15)/16)*16; 1875 } 1876 NumBytes += CalculateStackSlotSize(Arg, Flags, isVarArg, PtrByteSize); 1877 } 1878 1879 // Allow for Altivec parameters at the end, if needed. 1880 if (nAltivecParamsAtEnd) { 1881 NumBytes = ((NumBytes+15)/16)*16; 1882 NumBytes += 16*nAltivecParamsAtEnd; 1883 } 1884 1885 // The prolog code of the callee may store up to 8 GPR argument registers to 1886 // the stack, allowing va_start to index over them in memory if its varargs. 1887 // Because we cannot tell if this is needed on the caller side, we have to 1888 // conservatively assume that it is needed. As such, make sure we have at 1889 // least enough stack space for the caller to store the 8 GPRs. 1890 NumBytes = std::max(NumBytes, 1891 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI)); 1892 1893 // Tail call needs the stack to be aligned. 1894 if (CC==CallingConv::Fast && PerformTailCallOpt) { 1895 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 1896 getStackAlignment(); 1897 unsigned AlignMask = TargetAlign-1; 1898 NumBytes = (NumBytes + AlignMask) & ~AlignMask; 1899 } 1900 1901 return NumBytes; 1902} 1903 1904/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be 1905/// adjusted to accomodate the arguments for the tailcall. 1906static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall, 1907 unsigned ParamSize) { 1908 1909 if (!IsTailCall) return 0; 1910 1911 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>(); 1912 unsigned CallerMinReservedArea = FI->getMinReservedArea(); 1913 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize; 1914 // Remember only if the new adjustement is bigger. 1915 if (SPDiff < FI->getTailCallSPDelta()) 1916 FI->setTailCallSPDelta(SPDiff); 1917 1918 return SPDiff; 1919} 1920 1921/// IsEligibleForTailCallElimination - Check to see whether the next instruction 1922/// following the call is a return. A function is eligible if caller/callee 1923/// calling conventions match, currently only fastcc supports tail calls, and 1924/// the function CALL is immediatly followed by a RET. 1925bool 1926PPCTargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall, 1927 SDValue Ret, 1928 SelectionDAG& DAG) const { 1929 // Variable argument functions are not supported. 1930 if (!PerformTailCallOpt || TheCall->isVarArg()) 1931 return false; 1932 1933 if (CheckTailCallReturnConstraints(TheCall, Ret)) { 1934 MachineFunction &MF = DAG.getMachineFunction(); 1935 unsigned CallerCC = MF.getFunction()->getCallingConv(); 1936 unsigned CalleeCC = TheCall->getCallingConv(); 1937 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 1938 // Functions containing by val parameters are not supported. 1939 for (unsigned i = 0; i != TheCall->getNumArgs(); i++) { 1940 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i); 1941 if (Flags.isByVal()) return false; 1942 } 1943 1944 SDValue Callee = TheCall->getCallee(); 1945 // Non PIC/GOT tail calls are supported. 1946 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 1947 return true; 1948 1949 // At the moment we can only do local tail calls (in same module, hidden 1950 // or protected) if we are generating PIC. 1951 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1952 return G->getGlobal()->hasHiddenVisibility() 1953 || G->getGlobal()->hasProtectedVisibility(); 1954 } 1955 } 1956 1957 return false; 1958} 1959 1960/// isCallCompatibleAddress - Return the immediate to use if the specified 1961/// 32-bit value is representable in the immediate field of a BxA instruction. 1962static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { 1963 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1964 if (!C) return 0; 1965 1966 int Addr = C->getZExtValue(); 1967 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 1968 (Addr << 6 >> 6) != Addr) 1969 return 0; // Top 6 bits have to be sext of immediate. 1970 1971 return DAG.getConstant((int)C->getZExtValue() >> 2, 1972 DAG.getTargetLoweringInfo().getPointerTy()).getNode(); 1973} 1974 1975namespace { 1976 1977struct TailCallArgumentInfo { 1978 SDValue Arg; 1979 SDValue FrameIdxOp; 1980 int FrameIdx; 1981 1982 TailCallArgumentInfo() : FrameIdx(0) {} 1983}; 1984 1985} 1986 1987/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. 1988static void 1989StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, 1990 SDValue Chain, 1991 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, 1992 SmallVector<SDValue, 8> &MemOpChains, 1993 DebugLoc dl) { 1994 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { 1995 SDValue Arg = TailCallArgs[i].Arg; 1996 SDValue FIN = TailCallArgs[i].FrameIdxOp; 1997 int FI = TailCallArgs[i].FrameIdx; 1998 // Store relative to framepointer. 1999 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN, 2000 PseudoSourceValue::getFixedStack(FI), 2001 0)); 2002 } 2003} 2004 2005/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to 2006/// the appropriate stack slot for the tail call optimized function call. 2007static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, 2008 MachineFunction &MF, 2009 SDValue Chain, 2010 SDValue OldRetAddr, 2011 SDValue OldFP, 2012 int SPDiff, 2013 bool isPPC64, 2014 bool isMachoABI, 2015 DebugLoc dl) { 2016 if (SPDiff) { 2017 // Calculate the new stack slot for the return address. 2018 int SlotSize = isPPC64 ? 8 : 4; 2019 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64, 2020 isMachoABI); 2021 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, 2022 NewRetAddrLoc); 2023 int NewFPLoc = SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, 2024 isMachoABI); 2025 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc); 2026 2027 MVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2028 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); 2029 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, 2030 PseudoSourceValue::getFixedStack(NewRetAddr), 0); 2031 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); 2032 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, 2033 PseudoSourceValue::getFixedStack(NewFPIdx), 0); 2034 } 2035 return Chain; 2036} 2037 2038/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate 2039/// the position of the argument. 2040static void 2041CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, 2042 SDValue Arg, int SPDiff, unsigned ArgOffset, 2043 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 2044 int Offset = ArgOffset + SPDiff; 2045 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; 2046 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset); 2047 MVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2048 SDValue FIN = DAG.getFrameIndex(FI, VT); 2049 TailCallArgumentInfo Info; 2050 Info.Arg = Arg; 2051 Info.FrameIdxOp = FIN; 2052 Info.FrameIdx = FI; 2053 TailCallArguments.push_back(Info); 2054} 2055 2056/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address 2057/// stack slot. Returns the chain as result and the loaded frame pointers in 2058/// LROpOut/FPOpout. Used when tail calling. 2059SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 2060 int SPDiff, 2061 SDValue Chain, 2062 SDValue &LROpOut, 2063 SDValue &FPOpOut, 2064 DebugLoc dl) { 2065 if (SPDiff) { 2066 // Load the LR and FP stack slot for later adjusting. 2067 MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; 2068 LROpOut = getReturnAddrFrameIndex(DAG); 2069 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0); 2070 Chain = SDValue(LROpOut.getNode(), 1); 2071 FPOpOut = getFramePointerFrameIndex(DAG); 2072 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0); 2073 Chain = SDValue(FPOpOut.getNode(), 1); 2074 } 2075 return Chain; 2076} 2077 2078/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 2079/// by "Src" to address "Dst" of size "Size". Alignment information is 2080/// specified by the specific parameter attribute. The copy will be passed as 2081/// a byval function parameter. 2082/// Sometimes what we are copying is the end of a larger object, the part that 2083/// does not fit in registers. 2084static SDValue 2085CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 2086 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 2087 unsigned Size, DebugLoc dl) { 2088 SDValue SizeNode = DAG.getConstant(Size, MVT::i32); 2089 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 2090 false, NULL, 0, NULL, 0); 2091} 2092 2093/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of 2094/// tail calls. 2095static void 2096LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, 2097 SDValue Arg, SDValue PtrOff, int SPDiff, 2098 unsigned ArgOffset, bool isPPC64, bool isTailCall, 2099 bool isVector, SmallVector<SDValue, 8> &MemOpChains, 2100 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments, 2101 DebugLoc dl) { 2102 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2103 if (!isTailCall) { 2104 if (isVector) { 2105 SDValue StackPtr; 2106 if (isPPC64) 2107 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2108 else 2109 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2110 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 2111 DAG.getConstant(ArgOffset, PtrVT)); 2112 } 2113 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0)); 2114 // Calculate and remember argument location. 2115 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, 2116 TailCallArguments); 2117} 2118 2119SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG, 2120 const PPCSubtarget &Subtarget, 2121 TargetMachine &TM) { 2122 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode()); 2123 SDValue Chain = TheCall->getChain(); 2124 bool isVarArg = TheCall->isVarArg(); 2125 unsigned CC = TheCall->getCallingConv(); 2126 bool isTailCall = TheCall->isTailCall() 2127 && CC == CallingConv::Fast && PerformTailCallOpt; 2128 SDValue Callee = TheCall->getCallee(); 2129 unsigned NumOps = TheCall->getNumArgs(); 2130 DebugLoc dl = TheCall->getDebugLoc(); 2131 2132 bool isMachoABI = Subtarget.isMachoABI(); 2133 bool isELF32_ABI = Subtarget.isELF32_ABI(); 2134 2135 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2136 bool isPPC64 = PtrVT == MVT::i64; 2137 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2138 2139 MachineFunction &MF = DAG.getMachineFunction(); 2140 2141 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in 2142 // SelectExpr to use to put the arguments in the appropriate registers. 2143 std::vector<SDValue> args_to_use; 2144 2145 // Mark this function as potentially containing a function that contains a 2146 // tail call. As a consequence the frame pointer will be used for dynamicalloc 2147 // and restoring the callers stack pointer in this functions epilog. This is 2148 // done because by tail calling the called function might overwrite the value 2149 // in this function's (MF) stack pointer stack slot 0(SP). 2150 if (PerformTailCallOpt && CC==CallingConv::Fast) 2151 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 2152 2153 unsigned nAltivecParamsAtEnd = 0; 2154 2155 // Count how many bytes are to be pushed on the stack, including the linkage 2156 // area, and parameter passing area. We start with 24/48 bytes, which is 2157 // prereserved space for [SP][CR][LR][3 x unused]. 2158 unsigned NumBytes = 2159 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isMachoABI, isVarArg, CC, 2160 TheCall, nAltivecParamsAtEnd); 2161 2162 // Calculate by how many bytes the stack has to be adjusted in case of tail 2163 // call optimization. 2164 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 2165 2166 // Adjust the stack pointer for the new arguments... 2167 // These operations are automatically eliminated by the prolog/epilog pass 2168 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2169 SDValue CallSeqStart = Chain; 2170 2171 // Load the return address and frame pointer so it can be move somewhere else 2172 // later. 2173 SDValue LROp, FPOp; 2174 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl); 2175 2176 // Set up a copy of the stack pointer for use loading and storing any 2177 // arguments that may not fit in the registers available for argument 2178 // passing. 2179 SDValue StackPtr; 2180 if (isPPC64) 2181 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2182 else 2183 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2184 2185 // Figure out which arguments are going to go in registers, and which in 2186 // memory. Also, if this is a vararg function, floating point operations 2187 // must be stored to our stack, and loaded into integer regs as well, if 2188 // any integer regs are available for argument passing. 2189 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 2190 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 2191 2192 static const unsigned GPR_32[] = { // 32-bit registers. 2193 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 2194 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 2195 }; 2196 static const unsigned GPR_64[] = { // 64-bit registers. 2197 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 2198 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 2199 }; 2200 static const unsigned *FPR = GetFPR(Subtarget); 2201 2202 static const unsigned VR[] = { 2203 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 2204 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 2205 }; 2206 const unsigned NumGPRs = array_lengthof(GPR_32); 2207 const unsigned NumFPRs = isMachoABI ? 13 : 8; 2208 const unsigned NumVRs = array_lengthof( VR); 2209 2210 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 2211 2212 std::vector<std::pair<unsigned, SDValue> > RegsToPass; 2213 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 2214 2215 SmallVector<SDValue, 8> MemOpChains; 2216 for (unsigned i = 0; i != NumOps; ++i) { 2217 bool inMem = false; 2218 SDValue Arg = TheCall->getArg(i); 2219 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i); 2220 // See if next argument requires stack alignment in ELF 2221 bool Align = Flags.isSplit(); 2222 2223 // PtrOff will be used to store the current argument to the stack if a 2224 // register cannot be found for it. 2225 SDValue PtrOff; 2226 2227 // Stack align in ELF 32 2228 if (isELF32_ABI && Align) 2229 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize, 2230 StackPtr.getValueType()); 2231 else 2232 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 2233 2234 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 2235 2236 // On PPC64, promote integers to 64-bit values. 2237 if (isPPC64 && Arg.getValueType() == MVT::i32) { 2238 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 2239 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 2240 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 2241 } 2242 2243 // FIXME Elf untested, what are alignment rules? 2244 // FIXME memcpy is used way more than necessary. Correctness first. 2245 if (Flags.isByVal()) { 2246 unsigned Size = Flags.getByValSize(); 2247 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2); 2248 if (Size==1 || Size==2) { 2249 // Very small objects are passed right-justified. 2250 // Everything else is passed left-justified. 2251 MVT VT = (Size==1) ? MVT::i8 : MVT::i16; 2252 if (GPR_idx != NumGPRs) { 2253 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, 2254 NULL, 0, VT); 2255 MemOpChains.push_back(Load.getValue(1)); 2256 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 2257 if (isMachoABI) 2258 ArgOffset += PtrByteSize; 2259 } else { 2260 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType()); 2261 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 2262 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, 2263 CallSeqStart.getNode()->getOperand(0), 2264 Flags, DAG, Size, dl); 2265 // This must go outside the CALLSEQ_START..END. 2266 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 2267 CallSeqStart.getNode()->getOperand(1)); 2268 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 2269 NewCallSeqStart.getNode()); 2270 Chain = CallSeqStart = NewCallSeqStart; 2271 ArgOffset += PtrByteSize; 2272 } 2273 continue; 2274 } 2275 // Copy entire object into memory. There are cases where gcc-generated 2276 // code assumes it is there, even if it could be put entirely into 2277 // registers. (This is not what the doc says.) 2278 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, 2279 CallSeqStart.getNode()->getOperand(0), 2280 Flags, DAG, Size, dl); 2281 // This must go outside the CALLSEQ_START..END. 2282 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 2283 CallSeqStart.getNode()->getOperand(1)); 2284 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode()); 2285 Chain = CallSeqStart = NewCallSeqStart; 2286 // And copy the pieces of it that fit into registers. 2287 for (unsigned j=0; j<Size; j+=PtrByteSize) { 2288 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 2289 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 2290 if (GPR_idx != NumGPRs) { 2291 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, NULL, 0); 2292 MemOpChains.push_back(Load.getValue(1)); 2293 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 2294 if (isMachoABI) 2295 ArgOffset += PtrByteSize; 2296 } else { 2297 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 2298 break; 2299 } 2300 } 2301 continue; 2302 } 2303 2304 switch (Arg.getValueType().getSimpleVT()) { 2305 default: assert(0 && "Unexpected ValueType for argument!"); 2306 case MVT::i32: 2307 case MVT::i64: 2308 // Double word align in ELF 2309 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2); 2310 if (GPR_idx != NumGPRs) { 2311 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 2312 } else { 2313 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 2314 isPPC64, isTailCall, false, MemOpChains, 2315 TailCallArguments, dl); 2316 inMem = true; 2317 } 2318 if (inMem || isMachoABI) { 2319 // Stack align in ELF 2320 if (isELF32_ABI && Align) 2321 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 2322 2323 ArgOffset += PtrByteSize; 2324 } 2325 break; 2326 case MVT::f32: 2327 case MVT::f64: 2328 if (FPR_idx != NumFPRs) { 2329 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 2330 2331 if (isVarArg) { 2332 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0); 2333 MemOpChains.push_back(Store); 2334 2335 // Float varargs are always shadowed in available integer registers 2336 if (GPR_idx != NumGPRs) { 2337 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0); 2338 MemOpChains.push_back(Load.getValue(1)); 2339 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 2340 Load)); 2341 } 2342 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 2343 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 2344 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 2345 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0); 2346 MemOpChains.push_back(Load.getValue(1)); 2347 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 2348 Load)); 2349 } 2350 } else { 2351 // If we have any FPRs remaining, we may also have GPRs remaining. 2352 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 2353 // GPRs. 2354 if (isMachoABI) { 2355 if (GPR_idx != NumGPRs) 2356 ++GPR_idx; 2357 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 2358 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 2359 ++GPR_idx; 2360 } 2361 } 2362 } else { 2363 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 2364 isPPC64, isTailCall, false, MemOpChains, 2365 TailCallArguments, dl); 2366 inMem = true; 2367 } 2368 if (inMem || isMachoABI) { 2369 // Stack align in ELF 2370 if (isELF32_ABI && Align) 2371 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 2372 if (isPPC64) 2373 ArgOffset += 8; 2374 else 2375 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 2376 } 2377 break; 2378 case MVT::v4f32: 2379 case MVT::v4i32: 2380 case MVT::v8i16: 2381 case MVT::v16i8: 2382 if (isVarArg) { 2383 // These go aligned on the stack, or in the corresponding R registers 2384 // when within range. The Darwin PPC ABI doc claims they also go in 2385 // V registers; in fact gcc does this only for arguments that are 2386 // prototyped, not for those that match the ... We do it for all 2387 // arguments, seems to work. 2388 while (ArgOffset % 16 !=0) { 2389 ArgOffset += PtrByteSize; 2390 if (GPR_idx != NumGPRs) 2391 GPR_idx++; 2392 } 2393 // We could elide this store in the case where the object fits 2394 // entirely in R registers. Maybe later. 2395 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 2396 DAG.getConstant(ArgOffset, PtrVT)); 2397 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0); 2398 MemOpChains.push_back(Store); 2399 if (VR_idx != NumVRs) { 2400 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0); 2401 MemOpChains.push_back(Load.getValue(1)); 2402 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 2403 } 2404 ArgOffset += 16; 2405 for (unsigned i=0; i<16; i+=PtrByteSize) { 2406 if (GPR_idx == NumGPRs) 2407 break; 2408 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 2409 DAG.getConstant(i, PtrVT)); 2410 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, NULL, 0); 2411 MemOpChains.push_back(Load.getValue(1)); 2412 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 2413 } 2414 break; 2415 } 2416 2417 // Non-varargs Altivec params generally go in registers, but have 2418 // stack space allocated at the end. 2419 if (VR_idx != NumVRs) { 2420 // Doesn't have GPR space allocated. 2421 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 2422 } else if (nAltivecParamsAtEnd==0) { 2423 // We are emitting Altivec params in order. 2424 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 2425 isPPC64, isTailCall, true, MemOpChains, 2426 TailCallArguments, dl); 2427 ArgOffset += 16; 2428 } 2429 break; 2430 } 2431 } 2432 // If all Altivec parameters fit in registers, as they usually do, 2433 // they get stack space following the non-Altivec parameters. We 2434 // don't track this here because nobody below needs it. 2435 // If there are more Altivec parameters than fit in registers emit 2436 // the stores here. 2437 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) { 2438 unsigned j = 0; 2439 // Offset is aligned; skip 1st 12 params which go in V registers. 2440 ArgOffset = ((ArgOffset+15)/16)*16; 2441 ArgOffset += 12*16; 2442 for (unsigned i = 0; i != NumOps; ++i) { 2443 SDValue Arg = TheCall->getArg(i); 2444 MVT ArgType = Arg.getValueType(); 2445 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || 2446 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { 2447 if (++j > NumVRs) { 2448 SDValue PtrOff; 2449 // We are emitting Altivec params in order. 2450 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 2451 isPPC64, isTailCall, true, MemOpChains, 2452 TailCallArguments, dl); 2453 ArgOffset += 16; 2454 } 2455 } 2456 } 2457 } 2458 2459 if (!MemOpChains.empty()) 2460 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2461 &MemOpChains[0], MemOpChains.size()); 2462 2463 // Build a sequence of copy-to-reg nodes chained together with token chain 2464 // and flag operands which copy the outgoing args into the appropriate regs. 2465 SDValue InFlag; 2466 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2467 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2468 RegsToPass[i].second, InFlag); 2469 InFlag = Chain.getValue(1); 2470 } 2471 2472 // With the ELF 32 ABI, set CR6 to true if this is a vararg call. 2473 if (isVarArg && isELF32_ABI) { 2474 SDValue SetCR(DAG.getTargetNode(PPC::CRSET, dl, MVT::i32), 0); 2475 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag); 2476 InFlag = Chain.getValue(1); 2477 } 2478 2479 // Emit a sequence of copyto/copyfrom virtual registers for arguments that 2480 // might overwrite each other in case of tail call optimization. 2481 if (isTailCall) { 2482 SmallVector<SDValue, 8> MemOpChains2; 2483 // Do not flag preceeding copytoreg stuff together with the following stuff. 2484 InFlag = SDValue(); 2485 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, 2486 MemOpChains2, dl); 2487 if (!MemOpChains2.empty()) 2488 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2489 &MemOpChains2[0], MemOpChains2.size()); 2490 2491 // Store the return address to the appropriate stack slot. 2492 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, 2493 isPPC64, isMachoABI, dl); 2494 } 2495 2496 // Emit callseq_end just before tailcall node. 2497 if (isTailCall) { 2498 SmallVector<SDValue, 8> CallSeqOps; 2499 SDVTList CallSeqNodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 2500 CallSeqOps.push_back(Chain); 2501 CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes, true)); 2502 CallSeqOps.push_back(DAG.getIntPtrConstant(0, true)); 2503 if (InFlag.getNode()) 2504 CallSeqOps.push_back(InFlag); 2505 Chain = DAG.getNode(ISD::CALLSEQ_END, CallSeqNodeTys, &CallSeqOps[0], 2506 CallSeqOps.size()); 2507 InFlag = Chain.getValue(1); 2508 } 2509 2510 std::vector<MVT> NodeTys; 2511 NodeTys.push_back(MVT::Other); // Returns a chain 2512 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 2513 2514 SmallVector<SDValue, 8> Ops; 2515 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF; 2516 2517 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2518 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2519 // node so that legalize doesn't hack it. 2520 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2521 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); 2522 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 2523 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); 2524 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) 2525 // If this is an absolute destination address, use the munged value. 2526 Callee = SDValue(Dest, 0); 2527 else { 2528 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 2529 // to do the call, we can't use PPCISD::CALL. 2530 SDValue MTCTROps[] = {Chain, Callee, InFlag}; 2531 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps, 2532 2 + (InFlag.getNode() != 0)); 2533 InFlag = Chain.getValue(1); 2534 2535 // Copy the callee address into R12/X12 on darwin. 2536 if (isMachoABI) { 2537 unsigned Reg = Callee.getValueType() == MVT::i32 ? PPC::R12 : PPC::X12; 2538 Chain = DAG.getCopyToReg(Chain, dl, Reg, Callee, InFlag); 2539 InFlag = Chain.getValue(1); 2540 } 2541 2542 NodeTys.clear(); 2543 NodeTys.push_back(MVT::Other); 2544 NodeTys.push_back(MVT::Flag); 2545 Ops.push_back(Chain); 2546 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF; 2547 Callee.setNode(0); 2548 // Add CTR register as callee so a bctr can be emitted later. 2549 if (isTailCall) 2550 Ops.push_back(DAG.getRegister(PPC::CTR, getPointerTy())); 2551 } 2552 2553 // If this is a direct call, pass the chain and the callee. 2554 if (Callee.getNode()) { 2555 Ops.push_back(Chain); 2556 Ops.push_back(Callee); 2557 } 2558 // If this is a tail call add stack pointer delta. 2559 if (isTailCall) 2560 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); 2561 2562 // Add argument registers to the end of the list so that they are known live 2563 // into the call. 2564 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2565 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2566 RegsToPass[i].second.getValueType())); 2567 2568 // When performing tail call optimization the callee pops its arguments off 2569 // the stack. Account for this here so these bytes can be pushed back on in 2570 // PPCRegisterInfo::eliminateCallFramePseudoInstr. 2571 int BytesCalleePops = 2572 (CC==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0; 2573 2574 if (InFlag.getNode()) 2575 Ops.push_back(InFlag); 2576 2577 // Emit tail call. 2578 if (isTailCall) { 2579 assert(InFlag.getNode() && 2580 "Flag must be set. Depend on flag being set in LowerRET"); 2581 Chain = DAG.getNode(PPCISD::TAILCALL, dl, 2582 TheCall->getVTList(), &Ops[0], Ops.size()); 2583 return SDValue(Chain.getNode(), Op.getResNo()); 2584 } 2585 2586 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 2587 InFlag = Chain.getValue(1); 2588 2589 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2590 DAG.getIntPtrConstant(BytesCalleePops, true), 2591 InFlag); 2592 if (TheCall->getValueType(0) != MVT::Other) 2593 InFlag = Chain.getValue(1); 2594 2595 SmallVector<SDValue, 16> ResultVals; 2596 SmallVector<CCValAssign, 16> RVLocs; 2597 unsigned CallerCC = DAG.getMachineFunction().getFunction()->getCallingConv(); 2598 CCState CCInfo(CallerCC, isVarArg, TM, RVLocs); 2599 CCInfo.AnalyzeCallResult(TheCall, RetCC_PPC); 2600 2601 // Copy all of the result registers out of their specified physreg. 2602 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2603 CCValAssign &VA = RVLocs[i]; 2604 MVT VT = VA.getValVT(); 2605 assert(VA.isRegLoc() && "Can only return in registers!"); 2606 Chain = DAG.getCopyFromReg(Chain, dl, 2607 VA.getLocReg(), VT, InFlag).getValue(1); 2608 ResultVals.push_back(Chain.getValue(0)); 2609 InFlag = Chain.getValue(2); 2610 } 2611 2612 // If the function returns void, just return the chain. 2613 if (RVLocs.empty()) 2614 return Chain; 2615 2616 // Otherwise, merge everything together with a MERGE_VALUES node. 2617 ResultVals.push_back(Chain); 2618 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(), 2619 &ResultVals[0], ResultVals.size()); 2620 return Res.getValue(Op.getResNo()); 2621} 2622 2623SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG, 2624 TargetMachine &TM) { 2625 SmallVector<CCValAssign, 16> RVLocs; 2626 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 2627 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 2628 DebugLoc dl = Op.getDebugLoc(); 2629 CCState CCInfo(CC, isVarArg, TM, RVLocs); 2630 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_PPC); 2631 2632 // If this is the first return lowered for this function, add the regs to the 2633 // liveout set for the function. 2634 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2635 for (unsigned i = 0; i != RVLocs.size(); ++i) 2636 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2637 } 2638 2639 SDValue Chain = Op.getOperand(0); 2640 2641 Chain = GetPossiblePreceedingTailCall(Chain, PPCISD::TAILCALL); 2642 if (Chain.getOpcode() == PPCISD::TAILCALL) { 2643 SDValue TailCall = Chain; 2644 SDValue TargetAddress = TailCall.getOperand(1); 2645 SDValue StackAdjustment = TailCall.getOperand(2); 2646 2647 assert(((TargetAddress.getOpcode() == ISD::Register && 2648 cast<RegisterSDNode>(TargetAddress)->getReg() == PPC::CTR) || 2649 TargetAddress.getOpcode() == ISD::TargetExternalSymbol || 2650 TargetAddress.getOpcode() == ISD::TargetGlobalAddress || 2651 isa<ConstantSDNode>(TargetAddress)) && 2652 "Expecting an global address, external symbol, absolute value or register"); 2653 2654 assert(StackAdjustment.getOpcode() == ISD::Constant && 2655 "Expecting a const value"); 2656 2657 SmallVector<SDValue,8> Operands; 2658 Operands.push_back(Chain.getOperand(0)); 2659 Operands.push_back(TargetAddress); 2660 Operands.push_back(StackAdjustment); 2661 // Copy registers used by the call. Last operand is a flag so it is not 2662 // copied. 2663 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) { 2664 Operands.push_back(Chain.getOperand(i)); 2665 } 2666 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Operands[0], 2667 Operands.size()); 2668 } 2669 2670 SDValue Flag; 2671 2672 // Copy the result values into the output registers. 2673 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2674 CCValAssign &VA = RVLocs[i]; 2675 assert(VA.isRegLoc() && "Can only return in registers!"); 2676 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 2677 Op.getOperand(i*2+1), Flag); 2678 Flag = Chain.getValue(1); 2679 } 2680 2681 if (Flag.getNode()) 2682 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 2683 else 2684 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain); 2685} 2686 2687SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 2688 const PPCSubtarget &Subtarget) { 2689 // When we pop the dynamic allocation we need to restore the SP link. 2690 DebugLoc dl = Op.getNode()->getDebugLoc(); 2691 2692 // Get the corect type for pointers. 2693 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2694 2695 // Construct the stack pointer operand. 2696 bool IsPPC64 = Subtarget.isPPC64(); 2697 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1; 2698 SDValue StackPtr = DAG.getRegister(SP, PtrVT); 2699 2700 // Get the operands for the STACKRESTORE. 2701 SDValue Chain = Op.getOperand(0); 2702 SDValue SaveSP = Op.getOperand(1); 2703 2704 // Load the old link SP. 2705 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0); 2706 2707 // Restore the stack pointer. 2708 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); 2709 2710 // Store the old link SP. 2711 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0); 2712} 2713 2714 2715 2716SDValue 2717PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { 2718 MachineFunction &MF = DAG.getMachineFunction(); 2719 bool IsPPC64 = PPCSubTarget.isPPC64(); 2720 bool isMachoABI = PPCSubTarget.isMachoABI(); 2721 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2722 2723 // Get current frame pointer save index. The users of this index will be 2724 // primarily DYNALLOC instructions. 2725 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2726 int RASI = FI->getReturnAddrSaveIndex(); 2727 2728 // If the frame pointer save index hasn't been defined yet. 2729 if (!RASI) { 2730 // Find out what the fix offset of the frame pointer save area. 2731 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isMachoABI); 2732 // Allocate the frame index for frame pointer save area. 2733 RASI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, LROffset); 2734 // Save the result. 2735 FI->setReturnAddrSaveIndex(RASI); 2736 } 2737 return DAG.getFrameIndex(RASI, PtrVT); 2738} 2739 2740SDValue 2741PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { 2742 MachineFunction &MF = DAG.getMachineFunction(); 2743 bool IsPPC64 = PPCSubTarget.isPPC64(); 2744 bool isMachoABI = PPCSubTarget.isMachoABI(); 2745 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2746 2747 // Get current frame pointer save index. The users of this index will be 2748 // primarily DYNALLOC instructions. 2749 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2750 int FPSI = FI->getFramePointerSaveIndex(); 2751 2752 // If the frame pointer save index hasn't been defined yet. 2753 if (!FPSI) { 2754 // Find out what the fix offset of the frame pointer save area. 2755 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI); 2756 2757 // Allocate the frame index for frame pointer save area. 2758 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 2759 // Save the result. 2760 FI->setFramePointerSaveIndex(FPSI); 2761 } 2762 return DAG.getFrameIndex(FPSI, PtrVT); 2763} 2764 2765SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 2766 SelectionDAG &DAG, 2767 const PPCSubtarget &Subtarget) { 2768 // Get the inputs. 2769 SDValue Chain = Op.getOperand(0); 2770 SDValue Size = Op.getOperand(1); 2771 2772 // Get the corect type for pointers. 2773 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2774 // Negate the size. 2775 SDValue NegSize = DAG.getNode(ISD::SUB, PtrVT, 2776 DAG.getConstant(0, PtrVT), Size); 2777 // Construct a node for the frame pointer save index. 2778 SDValue FPSIdx = getFramePointerFrameIndex(DAG); 2779 // Build a DYNALLOC node. 2780 SDValue Ops[3] = { Chain, NegSize, FPSIdx }; 2781 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 2782 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3); 2783} 2784 2785/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 2786/// possible. 2787SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 2788 // Not FP? Not a fsel. 2789 if (!Op.getOperand(0).getValueType().isFloatingPoint() || 2790 !Op.getOperand(2).getValueType().isFloatingPoint()) 2791 return SDValue(); 2792 2793 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2794 2795 // Cannot handle SETEQ/SETNE. 2796 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDValue(); 2797 2798 MVT ResVT = Op.getValueType(); 2799 MVT CmpVT = Op.getOperand(0).getValueType(); 2800 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2801 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); 2802 2803 // If the RHS of the comparison is a 0.0, we don't need to do the 2804 // subtraction at all. 2805 if (isFloatingPointZero(RHS)) 2806 switch (CC) { 2807 default: break; // SETUO etc aren't handled by fsel. 2808 case ISD::SETULT: 2809 case ISD::SETLT: 2810 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 2811 case ISD::SETOGE: 2812 case ISD::SETGE: 2813 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 2814 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 2815 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 2816 case ISD::SETUGT: 2817 case ISD::SETGT: 2818 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 2819 case ISD::SETOLE: 2820 case ISD::SETLE: 2821 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 2822 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 2823 return DAG.getNode(PPCISD::FSEL, ResVT, 2824 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 2825 } 2826 2827 SDValue Cmp; 2828 switch (CC) { 2829 default: break; // SETUO etc aren't handled by fsel. 2830 case ISD::SETULT: 2831 case ISD::SETLT: 2832 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2833 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2834 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2835 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2836 case ISD::SETOGE: 2837 case ISD::SETGE: 2838 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2839 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2840 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2841 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2842 case ISD::SETUGT: 2843 case ISD::SETGT: 2844 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2845 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2846 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2847 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2848 case ISD::SETOLE: 2849 case ISD::SETLE: 2850 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2851 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2852 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2853 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2854 } 2855 return SDValue(); 2856} 2857 2858// FIXME: Split this code up when LegalizeDAGTypes lands. 2859SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, 2860 DebugLoc dl) { 2861 assert(Op.getOperand(0).getValueType().isFloatingPoint()); 2862 SDValue Src = Op.getOperand(0); 2863 if (Src.getValueType() == MVT::f32) 2864 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); 2865 2866 SDValue Tmp; 2867 switch (Op.getValueType().getSimpleVT()) { 2868 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 2869 case MVT::i32: 2870 Tmp = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Src); 2871 break; 2872 case MVT::i64: 2873 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src); 2874 break; 2875 } 2876 2877 // Convert the FP value to an int value through memory. 2878 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); 2879 2880 // Emit a store to the stack slot. 2881 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0); 2882 2883 // Result is a load from the stack slot. If loading 4 bytes, make sure to 2884 // add in a bias. 2885 if (Op.getValueType() == MVT::i32) 2886 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, 2887 DAG.getConstant(4, FIPtr.getValueType())); 2888 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0); 2889} 2890 2891SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 2892 DebugLoc dl = Op.getNode()->getDebugLoc(); 2893 // Don't handle ppc_fp128 here; let it be lowered to a libcall. 2894 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) 2895 return SDValue(); 2896 2897 if (Op.getOperand(0).getValueType() == MVT::i64) { 2898 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl, 2899 MVT::f64, Op.getOperand(0)); 2900 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); 2901 if (Op.getValueType() == MVT::f32) 2902 FP = DAG.getNode(ISD::FP_ROUND, dl, 2903 MVT::f32, FP, DAG.getIntPtrConstant(0)); 2904 return FP; 2905 } 2906 2907 assert(Op.getOperand(0).getValueType() == MVT::i32 && 2908 "Unhandled SINT_TO_FP type in custom expander!"); 2909 // Since we only generate this in 64-bit mode, we can take advantage of 2910 // 64-bit registers. In particular, sign extend the input value into the 2911 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 2912 // then lfd it and fcfid it. 2913 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2914 int FrameIdx = FrameInfo->CreateStackObject(8, 8); 2915 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2916 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2917 2918 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32, 2919 Op.getOperand(0)); 2920 2921 // STD the extended value into the stack slot. 2922 MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx), 2923 MachineMemOperand::MOStore, 0, 8, 8); 2924 SDValue Store = DAG.getNode(PPCISD::STD_32, dl, MVT::Other, 2925 DAG.getEntryNode(), Ext64, FIdx, 2926 DAG.getMemOperand(MO)); 2927 // Load the value as a double. 2928 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0); 2929 2930 // FCFID it and return it. 2931 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); 2932 if (Op.getValueType() == MVT::f32) 2933 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); 2934 return FP; 2935} 2936 2937SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { 2938 DebugLoc dl = Op.getNode()->getDebugLoc(); 2939 /* 2940 The rounding mode is in bits 30:31 of FPSR, and has the following 2941 settings: 2942 00 Round to nearest 2943 01 Round to 0 2944 10 Round to +inf 2945 11 Round to -inf 2946 2947 FLT_ROUNDS, on the other hand, expects the following: 2948 -1 Undefined 2949 0 Round to 0 2950 1 Round to nearest 2951 2 Round to +inf 2952 3 Round to -inf 2953 2954 To perform the conversion, we do: 2955 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 2956 */ 2957 2958 MachineFunction &MF = DAG.getMachineFunction(); 2959 MVT VT = Op.getValueType(); 2960 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2961 std::vector<MVT> NodeTys; 2962 SDValue MFFSreg, InFlag; 2963 2964 // Save FP Control Word to register 2965 NodeTys.push_back(MVT::f64); // return register 2966 NodeTys.push_back(MVT::Flag); // unused in this context 2967 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 2968 2969 // Save FP register to stack slot 2970 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 2971 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 2972 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, 2973 StackSlot, NULL, 0); 2974 2975 // Load FP Control Word from low 32 bits of stack slot. 2976 SDValue Four = DAG.getConstant(4, PtrVT); 2977 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); 2978 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0); 2979 2980 // Transform as necessary 2981 SDValue CWD1 = 2982 DAG.getNode(ISD::AND, dl, MVT::i32, 2983 CWD, DAG.getConstant(3, MVT::i32)); 2984 SDValue CWD2 = 2985 DAG.getNode(ISD::SRL, dl, MVT::i32, 2986 DAG.getNode(ISD::AND, dl, MVT::i32, 2987 DAG.getNode(ISD::XOR, dl, MVT::i32, 2988 CWD, DAG.getConstant(3, MVT::i32)), 2989 DAG.getConstant(3, MVT::i32)), 2990 DAG.getConstant(1, MVT::i32)); 2991 2992 SDValue RetVal = 2993 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); 2994 2995 return DAG.getNode((VT.getSizeInBits() < 16 ? 2996 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 2997} 2998 2999SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) { 3000 MVT VT = Op.getValueType(); 3001 unsigned BitWidth = VT.getSizeInBits(); 3002 DebugLoc dl = Op.getDebugLoc(); 3003 assert(Op.getNumOperands() == 3 && 3004 VT == Op.getOperand(1).getValueType() && 3005 "Unexpected SHL!"); 3006 3007 // Expand into a bunch of logical ops. Note that these ops 3008 // depend on the PPC behavior for oversized shift amounts. 3009 SDValue Lo = Op.getOperand(0); 3010 SDValue Hi = Op.getOperand(1); 3011 SDValue Amt = Op.getOperand(2); 3012 MVT AmtVT = Amt.getValueType(); 3013 3014 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3015 DAG.getConstant(BitWidth, AmtVT), Amt); 3016 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); 3017 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); 3018 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); 3019 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3020 DAG.getConstant(-BitWidth, AmtVT)); 3021 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); 3022 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 3023 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); 3024 SDValue OutOps[] = { OutLo, OutHi }; 3025 return DAG.getMergeValues(OutOps, 2, dl); 3026} 3027 3028SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) { 3029 MVT VT = Op.getValueType(); 3030 DebugLoc dl = Op.getDebugLoc(); 3031 unsigned BitWidth = VT.getSizeInBits(); 3032 assert(Op.getNumOperands() == 3 && 3033 VT == Op.getOperand(1).getValueType() && 3034 "Unexpected SRL!"); 3035 3036 // Expand into a bunch of logical ops. Note that these ops 3037 // depend on the PPC behavior for oversized shift amounts. 3038 SDValue Lo = Op.getOperand(0); 3039 SDValue Hi = Op.getOperand(1); 3040 SDValue Amt = Op.getOperand(2); 3041 MVT AmtVT = Amt.getValueType(); 3042 3043 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3044 DAG.getConstant(BitWidth, AmtVT), Amt); 3045 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3046 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 3047 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 3048 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3049 DAG.getConstant(-BitWidth, AmtVT)); 3050 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); 3051 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 3052 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); 3053 SDValue OutOps[] = { OutLo, OutHi }; 3054 return DAG.getMergeValues(OutOps, 2, dl); 3055} 3056 3057SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) { 3058 DebugLoc dl = Op.getNode()->getDebugLoc(); 3059 MVT VT = Op.getValueType(); 3060 unsigned BitWidth = VT.getSizeInBits(); 3061 assert(Op.getNumOperands() == 3 && 3062 VT == Op.getOperand(1).getValueType() && 3063 "Unexpected SRA!"); 3064 3065 // Expand into a bunch of logical ops, followed by a select_cc. 3066 SDValue Lo = Op.getOperand(0); 3067 SDValue Hi = Op.getOperand(1); 3068 SDValue Amt = Op.getOperand(2); 3069 MVT AmtVT = Amt.getValueType(); 3070 3071 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3072 DAG.getConstant(BitWidth, AmtVT), Amt); 3073 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3074 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 3075 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 3076 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3077 DAG.getConstant(-BitWidth, AmtVT)); 3078 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); 3079 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); 3080 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), 3081 Tmp4, Tmp6, ISD::SETLE); 3082 SDValue OutOps[] = { OutLo, OutHi }; 3083 return DAG.getMergeValues(OutOps, 2, dl); 3084} 3085 3086//===----------------------------------------------------------------------===// 3087// Vector related lowering. 3088// 3089 3090// If this is a vector of constants or undefs, get the bits. A bit in 3091// UndefBits is set if the corresponding element of the vector is an 3092// ISD::UNDEF value. For undefs, the corresponding VectorBits values are 3093// zero. Return true if this is not an array of constants, false if it is. 3094// 3095static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], 3096 uint64_t UndefBits[2]) { 3097 // Start with zero'd results. 3098 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; 3099 3100 unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits(); 3101 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3102 SDValue OpVal = BV->getOperand(i); 3103 3104 unsigned PartNo = i >= e/2; // In the upper 128 bits? 3105 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. 3106 3107 uint64_t EltBits = 0; 3108 if (OpVal.getOpcode() == ISD::UNDEF) { 3109 uint64_t EltUndefBits = ~0U >> (32-EltBitSize); 3110 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); 3111 continue; 3112 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 3113 EltBits = CN->getZExtValue() & (~0U >> (32-EltBitSize)); 3114 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 3115 assert(CN->getValueType(0) == MVT::f32 && 3116 "Only one legal FP vector type!"); 3117 EltBits = FloatToBits(CN->getValueAPF().convertToFloat()); 3118 } else { 3119 // Nonconstant element. 3120 return true; 3121 } 3122 3123 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); 3124 } 3125 3126 //printf("%llx %llx %llx %llx\n", 3127 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); 3128 return false; 3129} 3130 3131// If this is a splat (repetition) of a value across the whole vector, return 3132// the smallest size that splats it. For example, "0x01010101010101..." is a 3133// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 3134// SplatSize = 1 byte. 3135static bool isConstantSplat(const uint64_t Bits128[2], 3136 const uint64_t Undef128[2], 3137 unsigned &SplatBits, unsigned &SplatUndef, 3138 unsigned &SplatSize) { 3139 3140 // Don't let undefs prevent splats from matching. See if the top 64-bits are 3141 // the same as the lower 64-bits, ignoring undefs. 3142 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0])) 3143 return false; // Can't be a splat if two pieces don't match. 3144 3145 uint64_t Bits64 = Bits128[0] | Bits128[1]; 3146 uint64_t Undef64 = Undef128[0] & Undef128[1]; 3147 3148 // Check that the top 32-bits are the same as the lower 32-bits, ignoring 3149 // undefs. 3150 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64)) 3151 return false; // Can't be a splat if two pieces don't match. 3152 3153 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32); 3154 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32); 3155 3156 // If the top 16-bits are different than the lower 16-bits, ignoring 3157 // undefs, we have an i32 splat. 3158 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) { 3159 SplatBits = Bits32; 3160 SplatUndef = Undef32; 3161 SplatSize = 4; 3162 return true; 3163 } 3164 3165 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16); 3166 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16); 3167 3168 // If the top 8-bits are different than the lower 8-bits, ignoring 3169 // undefs, we have an i16 splat. 3170 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) { 3171 SplatBits = Bits16; 3172 SplatUndef = Undef16; 3173 SplatSize = 2; 3174 return true; 3175 } 3176 3177 // Otherwise, we have an 8-bit splat. 3178 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); 3179 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); 3180 SplatSize = 1; 3181 return true; 3182} 3183 3184/// BuildSplatI - Build a canonical splati of Val with an element size of 3185/// SplatSize. Cast the result to VT. 3186static SDValue BuildSplatI(int Val, unsigned SplatSize, MVT VT, 3187 SelectionDAG &DAG, DebugLoc dl) { 3188 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 3189 3190 static const MVT VTys[] = { // canonical VT to use for each size. 3191 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 3192 }; 3193 3194 MVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 3195 3196 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 3197 if (Val == -1) 3198 SplatSize = 1; 3199 3200 MVT CanonicalVT = VTys[SplatSize-1]; 3201 3202 // Build a canonical splat for this value. 3203 SDValue Elt = DAG.getConstant(Val, CanonicalVT.getVectorElementType()); 3204 SmallVector<SDValue, 8> Ops; 3205 Ops.assign(CanonicalVT.getVectorNumElements(), Elt); 3206 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, 3207 &Ops[0], Ops.size()); 3208 return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res); 3209} 3210 3211/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 3212/// specified intrinsic ID. 3213static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, 3214 SelectionDAG &DAG, DebugLoc dl, 3215 MVT DestVT = MVT::Other) { 3216 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 3217 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 3218 DAG.getConstant(IID, MVT::i32), LHS, RHS); 3219} 3220 3221/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 3222/// specified intrinsic ID. 3223static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, 3224 SDValue Op2, SelectionDAG &DAG, 3225 DebugLoc dl, MVT DestVT = MVT::Other) { 3226 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 3227 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 3228 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 3229} 3230 3231 3232/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 3233/// amount. The result has the specified value type. 3234static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, 3235 MVT VT, SelectionDAG &DAG, DebugLoc dl) { 3236 // Force LHS/RHS to be the right type. 3237 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS); 3238 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS); 3239 3240 SDValue Ops[16]; 3241 for (unsigned i = 0; i != 16; ++i) 3242 Ops[i] = DAG.getConstant(i+Amt, MVT::i8); 3243 SDValue T = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v16i8, LHS, RHS, 3244 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops,16)); 3245 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T); 3246} 3247 3248// If this is a case we can't handle, return null and let the default 3249// expansion code take care of it. If we CAN select this case, and if it 3250// selects to a single instruction, return Op. Otherwise, if we can codegen 3251// this case more efficiently than a constant pool load, lower it to the 3252// sequence of ops that should be used. 3253SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, 3254 SelectionDAG &DAG) { 3255 // If this is a vector of constants or undefs, get the bits. A bit in 3256 // UndefBits is set if the corresponding element of the vector is an 3257 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are 3258 // zero. 3259 uint64_t VectorBits[2]; 3260 uint64_t UndefBits[2]; 3261 DebugLoc dl = Op.getDebugLoc(); 3262 if (GetConstantBuildVectorBits(Op.getNode(), VectorBits, UndefBits)) 3263 return SDValue(); // Not a constant vector. 3264 3265 // If this is a splat (repetition) of a value across the whole vector, return 3266 // the smallest size that splats it. For example, "0x01010101010101..." is a 3267 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 3268 // SplatSize = 1 byte. 3269 unsigned SplatBits, SplatUndef, SplatSize; 3270 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){ 3271 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0; 3272 3273 // First, handle single instruction cases. 3274 3275 // All zeros? 3276 if (SplatBits == 0) { 3277 // Canonicalize all zero vectors to be v4i32. 3278 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 3279 SDValue Z = DAG.getConstant(0, MVT::i32); 3280 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); 3281 Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z); 3282 } 3283 return Op; 3284 } 3285 3286 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 3287 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); 3288 if (SextVal >= -16 && SextVal <= 15) 3289 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl); 3290 3291 3292 // Two instruction sequences. 3293 3294 // If this value is in the range [-32,30] and is even, use: 3295 // tmp = VSPLTI[bhw], result = add tmp, tmp 3296 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 3297 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl); 3298 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res); 3299 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3300 } 3301 3302 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 3303 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 3304 // for fneg/fabs. 3305 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 3306 // Make -1 and vspltisw -1: 3307 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); 3308 3309 // Make the VSLW intrinsic, computing 0x8000_0000. 3310 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 3311 OnesV, DAG, dl); 3312 3313 // xor by OnesV to invert it. 3314 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); 3315 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3316 } 3317 3318 // Check to see if this is a wide variety of vsplti*, binop self cases. 3319 unsigned SplatBitSize = SplatSize*8; 3320 static const signed char SplatCsts[] = { 3321 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 3322 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 3323 }; 3324 3325 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 3326 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 3327 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 3328 int i = SplatCsts[idx]; 3329 3330 // Figure out what shift amount will be used by altivec if shifted by i in 3331 // this splat size. 3332 unsigned TypeShiftAmt = i & (SplatBitSize-1); 3333 3334 // vsplti + shl self. 3335 if (SextVal == (i << (int)TypeShiftAmt)) { 3336 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3337 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3338 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 3339 Intrinsic::ppc_altivec_vslw 3340 }; 3341 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3342 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3343 } 3344 3345 // vsplti + srl self. 3346 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 3347 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3348 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3349 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 3350 Intrinsic::ppc_altivec_vsrw 3351 }; 3352 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3353 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3354 } 3355 3356 // vsplti + sra self. 3357 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 3358 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3359 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3360 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 3361 Intrinsic::ppc_altivec_vsraw 3362 }; 3363 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3364 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3365 } 3366 3367 // vsplti + rol self. 3368 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 3369 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 3370 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3371 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3372 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 3373 Intrinsic::ppc_altivec_vrlw 3374 }; 3375 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3376 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3377 } 3378 3379 // t = vsplti c, result = vsldoi t, t, 1 3380 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { 3381 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3382 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); 3383 } 3384 // t = vsplti c, result = vsldoi t, t, 2 3385 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { 3386 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3387 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); 3388 } 3389 // t = vsplti c, result = vsldoi t, t, 3 3390 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { 3391 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3392 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); 3393 } 3394 } 3395 3396 // Three instruction sequences. 3397 3398 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 3399 if (SextVal >= 0 && SextVal <= 31) { 3400 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl); 3401 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 3402 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS); 3403 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS); 3404 } 3405 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 3406 if (SextVal >= -31 && SextVal <= 0) { 3407 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl); 3408 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 3409 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS); 3410 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS); 3411 } 3412 } 3413 3414 return SDValue(); 3415} 3416 3417/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 3418/// the specified operations to build the shuffle. 3419static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 3420 SDValue RHS, SelectionDAG &DAG, 3421 DebugLoc dl) { 3422 unsigned OpNum = (PFEntry >> 26) & 0x0F; 3423 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 3424 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 3425 3426 enum { 3427 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 3428 OP_VMRGHW, 3429 OP_VMRGLW, 3430 OP_VSPLTISW0, 3431 OP_VSPLTISW1, 3432 OP_VSPLTISW2, 3433 OP_VSPLTISW3, 3434 OP_VSLDOI4, 3435 OP_VSLDOI8, 3436 OP_VSLDOI12 3437 }; 3438 3439 if (OpNum == OP_COPY) { 3440 if (LHSID == (1*9+2)*9+3) return LHS; 3441 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 3442 return RHS; 3443 } 3444 3445 SDValue OpLHS, OpRHS; 3446 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 3447 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 3448 3449 unsigned ShufIdxs[16]; 3450 switch (OpNum) { 3451 default: assert(0 && "Unknown i32 permute!"); 3452 case OP_VMRGHW: 3453 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 3454 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 3455 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 3456 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 3457 break; 3458 case OP_VMRGLW: 3459 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 3460 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 3461 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 3462 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 3463 break; 3464 case OP_VSPLTISW0: 3465 for (unsigned i = 0; i != 16; ++i) 3466 ShufIdxs[i] = (i&3)+0; 3467 break; 3468 case OP_VSPLTISW1: 3469 for (unsigned i = 0; i != 16; ++i) 3470 ShufIdxs[i] = (i&3)+4; 3471 break; 3472 case OP_VSPLTISW2: 3473 for (unsigned i = 0; i != 16; ++i) 3474 ShufIdxs[i] = (i&3)+8; 3475 break; 3476 case OP_VSPLTISW3: 3477 for (unsigned i = 0; i != 16; ++i) 3478 ShufIdxs[i] = (i&3)+12; 3479 break; 3480 case OP_VSLDOI4: 3481 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl); 3482 case OP_VSLDOI8: 3483 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl); 3484 case OP_VSLDOI12: 3485 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl); 3486 } 3487 SDValue Ops[16]; 3488 for (unsigned i = 0; i != 16; ++i) 3489 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i8); 3490 3491 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, OpLHS.getValueType(), 3492 OpLHS, OpRHS, 3493 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops, 16)); 3494} 3495 3496/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 3497/// is a shuffle we can handle in a single instruction, return it. Otherwise, 3498/// return the code it can be lowered into. Worst case, it can always be 3499/// lowered into a vperm. 3500SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 3501 SelectionDAG &DAG) { 3502 DebugLoc dl = Op.getDebugLoc(); 3503 SDValue V1 = Op.getOperand(0); 3504 SDValue V2 = Op.getOperand(1); 3505 SDValue PermMask = Op.getOperand(2); 3506 3507 // Cases that are handled by instructions that take permute immediates 3508 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 3509 // selected by the instruction selector. 3510 if (V2.getOpcode() == ISD::UNDEF) { 3511 if (PPC::isSplatShuffleMask(PermMask.getNode(), 1) || 3512 PPC::isSplatShuffleMask(PermMask.getNode(), 2) || 3513 PPC::isSplatShuffleMask(PermMask.getNode(), 4) || 3514 PPC::isVPKUWUMShuffleMask(PermMask.getNode(), true) || 3515 PPC::isVPKUHUMShuffleMask(PermMask.getNode(), true) || 3516 PPC::isVSLDOIShuffleMask(PermMask.getNode(), true) != -1 || 3517 PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, true) || 3518 PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, true) || 3519 PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, true) || 3520 PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, true) || 3521 PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, true) || 3522 PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, true)) { 3523 return Op; 3524 } 3525 } 3526 3527 // Altivec has a variety of "shuffle immediates" that take two vector inputs 3528 // and produce a fixed permutation. If any of these match, do not lower to 3529 // VPERM. 3530 if (PPC::isVPKUWUMShuffleMask(PermMask.getNode(), false) || 3531 PPC::isVPKUHUMShuffleMask(PermMask.getNode(), false) || 3532 PPC::isVSLDOIShuffleMask(PermMask.getNode(), false) != -1 || 3533 PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, false) || 3534 PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, false) || 3535 PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, false) || 3536 PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, false) || 3537 PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, false) || 3538 PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, false)) 3539 return Op; 3540 3541 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 3542 // perfect shuffle table to emit an optimal matching sequence. 3543 unsigned PFIndexes[4]; 3544 bool isFourElementShuffle = true; 3545 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 3546 unsigned EltNo = 8; // Start out undef. 3547 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 3548 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF) 3549 continue; // Undef, ignore it. 3550 3551 unsigned ByteSource = 3552 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getZExtValue(); 3553 if ((ByteSource & 3) != j) { 3554 isFourElementShuffle = false; 3555 break; 3556 } 3557 3558 if (EltNo == 8) { 3559 EltNo = ByteSource/4; 3560 } else if (EltNo != ByteSource/4) { 3561 isFourElementShuffle = false; 3562 break; 3563 } 3564 } 3565 PFIndexes[i] = EltNo; 3566 } 3567 3568 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 3569 // perfect shuffle vector to determine if it is cost effective to do this as 3570 // discrete instructions, or whether we should use a vperm. 3571 if (isFourElementShuffle) { 3572 // Compute the index in the perfect shuffle table. 3573 unsigned PFTableIndex = 3574 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 3575 3576 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 3577 unsigned Cost = (PFEntry >> 30); 3578 3579 // Determining when to avoid vperm is tricky. Many things affect the cost 3580 // of vperm, particularly how many times the perm mask needs to be computed. 3581 // For example, if the perm mask can be hoisted out of a loop or is already 3582 // used (perhaps because there are multiple permutes with the same shuffle 3583 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 3584 // the loop requires an extra register. 3585 // 3586 // As a compromise, we only emit discrete instructions if the shuffle can be 3587 // generated in 3 or fewer operations. When we have loop information 3588 // available, if this block is within a loop, we should avoid using vperm 3589 // for 3-operation perms and use a constant pool load instead. 3590 if (Cost < 3) 3591 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 3592 } 3593 3594 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 3595 // vector that will get spilled to the constant pool. 3596 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 3597 3598 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 3599 // that it is in input element units, not in bytes. Convert now. 3600 MVT EltVT = V1.getValueType().getVectorElementType(); 3601 unsigned BytesPerElement = EltVT.getSizeInBits()/8; 3602 3603 SmallVector<SDValue, 16> ResultMask; 3604 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { 3605 unsigned SrcElt; 3606 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) 3607 SrcElt = 0; 3608 else 3609 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getZExtValue(); 3610 3611 for (unsigned j = 0; j != BytesPerElement; ++j) 3612 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 3613 MVT::i8)); 3614 } 3615 3616 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, 3617 &ResultMask[0], ResultMask.size()); 3618 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); 3619} 3620 3621/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 3622/// altivec comparison. If it is, return true and fill in Opc/isDot with 3623/// information about the intrinsic. 3624static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, 3625 bool &isDot) { 3626 unsigned IntrinsicID = 3627 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue(); 3628 CompareOpc = -1; 3629 isDot = false; 3630 switch (IntrinsicID) { 3631 default: return false; 3632 // Comparison predicates. 3633 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 3634 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 3635 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 3636 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 3637 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 3638 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 3639 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 3640 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 3641 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 3642 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 3643 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 3644 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 3645 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 3646 3647 // Normal Comparisons. 3648 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 3649 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 3650 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 3651 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 3652 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 3653 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 3654 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 3655 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 3656 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 3657 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 3658 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 3659 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 3660 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 3661 } 3662 return true; 3663} 3664 3665/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 3666/// lower, do it, otherwise return null. 3667SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 3668 SelectionDAG &DAG) { 3669 // If this is a lowered altivec predicate compare, CompareOpc is set to the 3670 // opcode number of the comparison. 3671 DebugLoc dl = Op.getDebugLoc(); 3672 int CompareOpc; 3673 bool isDot; 3674 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 3675 return SDValue(); // Don't custom lower most intrinsics. 3676 3677 // If this is a non-dot comparison, make the VCMP node and we are done. 3678 if (!isDot) { 3679 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), 3680 Op.getOperand(1), Op.getOperand(2), 3681 DAG.getConstant(CompareOpc, MVT::i32)); 3682 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp); 3683 } 3684 3685 // Create the PPCISD altivec 'dot' comparison node. 3686 SDValue Ops[] = { 3687 Op.getOperand(2), // LHS 3688 Op.getOperand(3), // RHS 3689 DAG.getConstant(CompareOpc, MVT::i32) 3690 }; 3691 std::vector<MVT> VTs; 3692 VTs.push_back(Op.getOperand(2).getValueType()); 3693 VTs.push_back(MVT::Flag); 3694 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 3695 3696 // Now that we have the comparison, emit a copy from the CR to a GPR. 3697 // This is flagged to the above dot comparison. 3698 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32, 3699 DAG.getRegister(PPC::CR6, MVT::i32), 3700 CompNode.getValue(1)); 3701 3702 // Unpack the result based on how the target uses it. 3703 unsigned BitNo; // Bit # of CR6. 3704 bool InvertBit; // Invert result? 3705 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) { 3706 default: // Can't happen, don't crash on invalid number though. 3707 case 0: // Return the value of the EQ bit of CR6. 3708 BitNo = 0; InvertBit = false; 3709 break; 3710 case 1: // Return the inverted value of the EQ bit of CR6. 3711 BitNo = 0; InvertBit = true; 3712 break; 3713 case 2: // Return the value of the LT bit of CR6. 3714 BitNo = 2; InvertBit = false; 3715 break; 3716 case 3: // Return the inverted value of the LT bit of CR6. 3717 BitNo = 2; InvertBit = true; 3718 break; 3719 } 3720 3721 // Shift the bit into the low position. 3722 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, 3723 DAG.getConstant(8-(3-BitNo), MVT::i32)); 3724 // Isolate the bit. 3725 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, 3726 DAG.getConstant(1, MVT::i32)); 3727 3728 // If we are supposed to, toggle the bit. 3729 if (InvertBit) 3730 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, 3731 DAG.getConstant(1, MVT::i32)); 3732 return Flags; 3733} 3734 3735SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, 3736 SelectionDAG &DAG) { 3737 DebugLoc dl = Op.getNode()->getDebugLoc(); 3738 // Create a stack slot that is 16-byte aligned. 3739 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 3740 int FrameIdx = FrameInfo->CreateStackObject(16, 16); 3741 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3742 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 3743 3744 // Store the input value into Value#0 of the stack slot. 3745 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 3746 Op.getOperand(0), FIdx, NULL, 0); 3747 // Load it out. 3748 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0); 3749} 3750 3751SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { 3752 DebugLoc dl = Op.getDebugLoc(); 3753 if (Op.getValueType() == MVT::v4i32) { 3754 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3755 3756 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); 3757 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. 3758 3759 SDValue RHSSwap = // = vrlw RHS, 16 3760 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); 3761 3762 // Shrinkify inputs to v8i16. 3763 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS); 3764 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS); 3765 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap); 3766 3767 // Low parts multiplied together, generating 32-bit results (we ignore the 3768 // top parts). 3769 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 3770 LHS, RHS, DAG, dl, MVT::v4i32); 3771 3772 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 3773 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); 3774 // Shift the high parts up 16 bits. 3775 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, 3776 Neg16, DAG, dl); 3777 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); 3778 } else if (Op.getValueType() == MVT::v8i16) { 3779 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3780 3781 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); 3782 3783 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 3784 LHS, RHS, Zero, DAG, dl); 3785 } else if (Op.getValueType() == MVT::v16i8) { 3786 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3787 3788 // Multiply the even 8-bit parts, producing 16-bit sums. 3789 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 3790 LHS, RHS, DAG, dl, MVT::v8i16); 3791 EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts); 3792 3793 // Multiply the odd 8-bit parts, producing 16-bit sums. 3794 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 3795 LHS, RHS, DAG, dl, MVT::v8i16); 3796 OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts); 3797 3798 // Merge the results together. 3799 SDValue Ops[16]; 3800 for (unsigned i = 0; i != 8; ++i) { 3801 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); 3802 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); 3803 } 3804 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v16i8, EvenParts, OddParts, 3805 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops, 16)); 3806 } else { 3807 assert(0 && "Unknown mul to lower!"); 3808 abort(); 3809 } 3810} 3811 3812/// LowerOperation - Provide custom lowering hooks for some operations. 3813/// 3814SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 3815 switch (Op.getOpcode()) { 3816 default: assert(0 && "Wasn't expecting to be able to lower this!"); 3817 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 3818 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 3819 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 3820 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 3821 case ISD::SETCC: return LowerSETCC(Op, DAG); 3822 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 3823 case ISD::VASTART: 3824 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 3825 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 3826 3827 case ISD::VAARG: 3828 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 3829 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 3830 3831 case ISD::FORMAL_ARGUMENTS: 3832 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex, 3833 VarArgsStackOffset, VarArgsNumGPR, 3834 VarArgsNumFPR, PPCSubTarget); 3835 3836 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget, 3837 getTargetMachine()); 3838 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine()); 3839 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 3840 case ISD::DYNAMIC_STACKALLOC: 3841 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 3842 3843 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 3844 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, 3845 Op.getDebugLoc()); 3846 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 3847 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 3848 3849 // Lower 64-bit shifts. 3850 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 3851 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 3852 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 3853 3854 // Vector-related lowering. 3855 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 3856 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 3857 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 3858 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 3859 case ISD::MUL: return LowerMUL(Op, DAG); 3860 3861 // Frame & Return address. 3862 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 3863 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 3864 } 3865 return SDValue(); 3866} 3867 3868void PPCTargetLowering::ReplaceNodeResults(SDNode *N, 3869 SmallVectorImpl<SDValue>&Results, 3870 SelectionDAG &DAG) { 3871 DebugLoc dl = N->getDebugLoc(); 3872 switch (N->getOpcode()) { 3873 default: 3874 assert(false && "Do not know how to custom type legalize this operation!"); 3875 return; 3876 case ISD::FP_ROUND_INREG: { 3877 assert(N->getValueType(0) == MVT::ppcf128); 3878 assert(N->getOperand(0).getValueType() == MVT::ppcf128); 3879 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 3880 MVT::f64, N->getOperand(0), 3881 DAG.getIntPtrConstant(0)); 3882 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 3883 MVT::f64, N->getOperand(0), 3884 DAG.getIntPtrConstant(1)); 3885 3886 // This sequence changes FPSCR to do round-to-zero, adds the two halves 3887 // of the long double, and puts FPSCR back the way it was. We do not 3888 // actually model FPSCR. 3889 std::vector<MVT> NodeTys; 3890 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg; 3891 3892 NodeTys.push_back(MVT::f64); // Return register 3893 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns 3894 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 3895 MFFSreg = Result.getValue(0); 3896 InFlag = Result.getValue(1); 3897 3898 NodeTys.clear(); 3899 NodeTys.push_back(MVT::Flag); // Returns a flag 3900 Ops[0] = DAG.getConstant(31, MVT::i32); 3901 Ops[1] = InFlag; 3902 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2); 3903 InFlag = Result.getValue(0); 3904 3905 NodeTys.clear(); 3906 NodeTys.push_back(MVT::Flag); // Returns a flag 3907 Ops[0] = DAG.getConstant(30, MVT::i32); 3908 Ops[1] = InFlag; 3909 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2); 3910 InFlag = Result.getValue(0); 3911 3912 NodeTys.clear(); 3913 NodeTys.push_back(MVT::f64); // result of add 3914 NodeTys.push_back(MVT::Flag); // Returns a flag 3915 Ops[0] = Lo; 3916 Ops[1] = Hi; 3917 Ops[2] = InFlag; 3918 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3); 3919 FPreg = Result.getValue(0); 3920 InFlag = Result.getValue(1); 3921 3922 NodeTys.clear(); 3923 NodeTys.push_back(MVT::f64); 3924 Ops[0] = DAG.getConstant(1, MVT::i32); 3925 Ops[1] = MFFSreg; 3926 Ops[2] = FPreg; 3927 Ops[3] = InFlag; 3928 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4); 3929 FPreg = Result.getValue(0); 3930 3931 // We know the low half is about to be thrown away, so just use something 3932 // convenient. 3933 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, 3934 FPreg, FPreg)); 3935 return; 3936 } 3937 case ISD::FP_TO_SINT: 3938 Results.push_back(LowerFP_TO_SINT(SDValue(N, 0), DAG, dl)); 3939 return; 3940 } 3941} 3942 3943 3944//===----------------------------------------------------------------------===// 3945// Other Lowering Code 3946//===----------------------------------------------------------------------===// 3947 3948MachineBasicBlock * 3949PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 3950 bool is64bit, unsigned BinOpcode) { 3951 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 3952 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 3953 3954 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3955 MachineFunction *F = BB->getParent(); 3956 MachineFunction::iterator It = BB; 3957 ++It; 3958 3959 unsigned dest = MI->getOperand(0).getReg(); 3960 unsigned ptrA = MI->getOperand(1).getReg(); 3961 unsigned ptrB = MI->getOperand(2).getReg(); 3962 unsigned incr = MI->getOperand(3).getReg(); 3963 3964 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 3965 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 3966 F->insert(It, loopMBB); 3967 F->insert(It, exitMBB); 3968 exitMBB->transferSuccessors(BB); 3969 3970 MachineRegisterInfo &RegInfo = F->getRegInfo(); 3971 unsigned TmpReg = (!BinOpcode) ? incr : 3972 RegInfo.createVirtualRegister( 3973 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 3974 (const TargetRegisterClass *) &PPC::GPRCRegClass); 3975 3976 // thisMBB: 3977 // ... 3978 // fallthrough --> loopMBB 3979 BB->addSuccessor(loopMBB); 3980 3981 // loopMBB: 3982 // l[wd]arx dest, ptr 3983 // add r0, dest, incr 3984 // st[wd]cx. r0, ptr 3985 // bne- loopMBB 3986 // fallthrough --> exitMBB 3987 BB = loopMBB; 3988 BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 3989 .addReg(ptrA).addReg(ptrB); 3990 if (BinOpcode) 3991 BuildMI(BB, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); 3992 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 3993 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); 3994 BuildMI(BB, TII->get(PPC::BCC)) 3995 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 3996 BB->addSuccessor(loopMBB); 3997 BB->addSuccessor(exitMBB); 3998 3999 // exitMBB: 4000 // ... 4001 BB = exitMBB; 4002 return BB; 4003} 4004 4005MachineBasicBlock * 4006PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, 4007 MachineBasicBlock *BB, 4008 bool is8bit, // operation 4009 unsigned BinOpcode) { 4010 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4011 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4012 // In 64 bit mode we have to use 64 bits for addresses, even though the 4013 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address 4014 // registers without caring whether they're 32 or 64, but here we're 4015 // doing actual arithmetic on the addresses. 4016 bool is64bit = PPCSubTarget.isPPC64(); 4017 4018 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4019 MachineFunction *F = BB->getParent(); 4020 MachineFunction::iterator It = BB; 4021 ++It; 4022 4023 unsigned dest = MI->getOperand(0).getReg(); 4024 unsigned ptrA = MI->getOperand(1).getReg(); 4025 unsigned ptrB = MI->getOperand(2).getReg(); 4026 unsigned incr = MI->getOperand(3).getReg(); 4027 4028 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4029 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4030 F->insert(It, loopMBB); 4031 F->insert(It, exitMBB); 4032 exitMBB->transferSuccessors(BB); 4033 4034 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4035 const TargetRegisterClass *RC = 4036 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4037 (const TargetRegisterClass *) &PPC::GPRCRegClass; 4038 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 4039 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 4040 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 4041 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC); 4042 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 4043 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4044 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4045 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4046 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC); 4047 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4048 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4049 unsigned Ptr1Reg; 4050 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); 4051 4052 // thisMBB: 4053 // ... 4054 // fallthrough --> loopMBB 4055 BB->addSuccessor(loopMBB); 4056 4057 // The 4-byte load must be aligned, while a char or short may be 4058 // anywhere in the word. Hence all this nasty bookkeeping code. 4059 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4060 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4061 // xori shift, shift1, 24 [16] 4062 // rlwinm ptr, ptr1, 0, 0, 29 4063 // slw incr2, incr, shift 4064 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 4065 // slw mask, mask2, shift 4066 // loopMBB: 4067 // lwarx tmpDest, ptr 4068 // add tmp, tmpDest, incr2 4069 // andc tmp2, tmpDest, mask 4070 // and tmp3, tmp, mask 4071 // or tmp4, tmp3, tmp2 4072 // stwcx. tmp4, ptr 4073 // bne- loopMBB 4074 // fallthrough --> exitMBB 4075 // srw dest, tmpDest, shift 4076 4077 if (ptrA!=PPC::R0) { 4078 Ptr1Reg = RegInfo.createVirtualRegister(RC); 4079 BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 4080 .addReg(ptrA).addReg(ptrB); 4081 } else { 4082 Ptr1Reg = ptrB; 4083 } 4084 BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 4085 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 4086 BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 4087 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 4088 if (is64bit) 4089 BuildMI(BB, TII->get(PPC::RLDICR), PtrReg) 4090 .addReg(Ptr1Reg).addImm(0).addImm(61); 4091 else 4092 BuildMI(BB, TII->get(PPC::RLWINM), PtrReg) 4093 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 4094 BuildMI(BB, TII->get(PPC::SLW), Incr2Reg) 4095 .addReg(incr).addReg(ShiftReg); 4096 if (is8bit) 4097 BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255); 4098 else { 4099 BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0); 4100 BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535); 4101 } 4102 BuildMI(BB, TII->get(PPC::SLW), MaskReg) 4103 .addReg(Mask2Reg).addReg(ShiftReg); 4104 4105 BB = loopMBB; 4106 BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg) 4107 .addReg(PPC::R0).addReg(PtrReg); 4108 if (BinOpcode) 4109 BuildMI(BB, TII->get(BinOpcode), TmpReg) 4110 .addReg(Incr2Reg).addReg(TmpDestReg); 4111 BuildMI(BB, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) 4112 .addReg(TmpDestReg).addReg(MaskReg); 4113 BuildMI(BB, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) 4114 .addReg(TmpReg).addReg(MaskReg); 4115 BuildMI(BB, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) 4116 .addReg(Tmp3Reg).addReg(Tmp2Reg); 4117 BuildMI(BB, TII->get(PPC::STWCX)) 4118 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg); 4119 BuildMI(BB, TII->get(PPC::BCC)) 4120 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4121 BB->addSuccessor(loopMBB); 4122 BB->addSuccessor(exitMBB); 4123 4124 // exitMBB: 4125 // ... 4126 BB = exitMBB; 4127 BuildMI(BB, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg); 4128 return BB; 4129} 4130 4131MachineBasicBlock * 4132PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 4133 MachineBasicBlock *BB) { 4134 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4135 4136 // To "insert" these instructions we actually have to insert their 4137 // control-flow patterns. 4138 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4139 MachineFunction::iterator It = BB; 4140 ++It; 4141 4142 MachineFunction *F = BB->getParent(); 4143 4144 if (MI->getOpcode() == PPC::SELECT_CC_I4 || 4145 MI->getOpcode() == PPC::SELECT_CC_I8 || 4146 MI->getOpcode() == PPC::SELECT_CC_F4 || 4147 MI->getOpcode() == PPC::SELECT_CC_F8 || 4148 MI->getOpcode() == PPC::SELECT_CC_VRRC) { 4149 4150 // The incoming instruction knows the destination vreg to set, the 4151 // condition code register to branch on, the true/false values to 4152 // select between, and a branch opcode to use. 4153 4154 // thisMBB: 4155 // ... 4156 // TrueVal = ... 4157 // cmpTY ccX, r1, r2 4158 // bCC copy1MBB 4159 // fallthrough --> copy0MBB 4160 MachineBasicBlock *thisMBB = BB; 4161 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4162 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4163 unsigned SelectPred = MI->getOperand(4).getImm(); 4164 BuildMI(BB, TII->get(PPC::BCC)) 4165 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 4166 F->insert(It, copy0MBB); 4167 F->insert(It, sinkMBB); 4168 // Update machine-CFG edges by transferring all successors of the current 4169 // block to the new block which will contain the Phi node for the select. 4170 sinkMBB->transferSuccessors(BB); 4171 // Next, add the true and fallthrough blocks as its successors. 4172 BB->addSuccessor(copy0MBB); 4173 BB->addSuccessor(sinkMBB); 4174 4175 // copy0MBB: 4176 // %FalseValue = ... 4177 // # fallthrough to sinkMBB 4178 BB = copy0MBB; 4179 4180 // Update machine-CFG edges 4181 BB->addSuccessor(sinkMBB); 4182 4183 // sinkMBB: 4184 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 4185 // ... 4186 BB = sinkMBB; 4187 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg()) 4188 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 4189 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 4190 } 4191 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) 4192 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); 4193 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) 4194 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); 4195 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) 4196 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4); 4197 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) 4198 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8); 4199 4200 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8) 4201 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); 4202 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16) 4203 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); 4204 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32) 4205 BB = EmitAtomicBinary(MI, BB, false, PPC::AND); 4206 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64) 4207 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8); 4208 4209 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8) 4210 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); 4211 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16) 4212 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); 4213 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32) 4214 BB = EmitAtomicBinary(MI, BB, false, PPC::OR); 4215 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64) 4216 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8); 4217 4218 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) 4219 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); 4220 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) 4221 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); 4222 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) 4223 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR); 4224 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) 4225 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8); 4226 4227 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) 4228 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC); 4229 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) 4230 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC); 4231 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) 4232 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC); 4233 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) 4234 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8); 4235 4236 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) 4237 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); 4238 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) 4239 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); 4240 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) 4241 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF); 4242 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) 4243 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8); 4244 4245 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8) 4246 BB = EmitPartwordAtomicBinary(MI, BB, true, 0); 4247 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16) 4248 BB = EmitPartwordAtomicBinary(MI, BB, false, 0); 4249 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32) 4250 BB = EmitAtomicBinary(MI, BB, false, 0); 4251 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64) 4252 BB = EmitAtomicBinary(MI, BB, true, 0); 4253 4254 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || 4255 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) { 4256 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; 4257 4258 unsigned dest = MI->getOperand(0).getReg(); 4259 unsigned ptrA = MI->getOperand(1).getReg(); 4260 unsigned ptrB = MI->getOperand(2).getReg(); 4261 unsigned oldval = MI->getOperand(3).getReg(); 4262 unsigned newval = MI->getOperand(4).getReg(); 4263 4264 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 4265 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 4266 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 4267 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4268 F->insert(It, loop1MBB); 4269 F->insert(It, loop2MBB); 4270 F->insert(It, midMBB); 4271 F->insert(It, exitMBB); 4272 exitMBB->transferSuccessors(BB); 4273 4274 // thisMBB: 4275 // ... 4276 // fallthrough --> loopMBB 4277 BB->addSuccessor(loop1MBB); 4278 4279 // loop1MBB: 4280 // l[wd]arx dest, ptr 4281 // cmp[wd] dest, oldval 4282 // bne- midMBB 4283 // loop2MBB: 4284 // st[wd]cx. newval, ptr 4285 // bne- loopMBB 4286 // b exitBB 4287 // midMBB: 4288 // st[wd]cx. dest, ptr 4289 // exitBB: 4290 BB = loop1MBB; 4291 BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4292 .addReg(ptrA).addReg(ptrB); 4293 BuildMI(BB, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) 4294 .addReg(oldval).addReg(dest); 4295 BuildMI(BB, TII->get(PPC::BCC)) 4296 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 4297 BB->addSuccessor(loop2MBB); 4298 BB->addSuccessor(midMBB); 4299 4300 BB = loop2MBB; 4301 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4302 .addReg(newval).addReg(ptrA).addReg(ptrB); 4303 BuildMI(BB, TII->get(PPC::BCC)) 4304 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 4305 BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB); 4306 BB->addSuccessor(loop1MBB); 4307 BB->addSuccessor(exitMBB); 4308 4309 BB = midMBB; 4310 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4311 .addReg(dest).addReg(ptrA).addReg(ptrB); 4312 BB->addSuccessor(exitMBB); 4313 4314 // exitMBB: 4315 // ... 4316 BB = exitMBB; 4317 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || 4318 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { 4319 // We must use 64-bit registers for addresses when targeting 64-bit, 4320 // since we're actually doing arithmetic on them. Other registers 4321 // can be 32-bit. 4322 bool is64bit = PPCSubTarget.isPPC64(); 4323 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; 4324 4325 unsigned dest = MI->getOperand(0).getReg(); 4326 unsigned ptrA = MI->getOperand(1).getReg(); 4327 unsigned ptrB = MI->getOperand(2).getReg(); 4328 unsigned oldval = MI->getOperand(3).getReg(); 4329 unsigned newval = MI->getOperand(4).getReg(); 4330 4331 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 4332 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 4333 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 4334 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4335 F->insert(It, loop1MBB); 4336 F->insert(It, loop2MBB); 4337 F->insert(It, midMBB); 4338 F->insert(It, exitMBB); 4339 exitMBB->transferSuccessors(BB); 4340 4341 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4342 const TargetRegisterClass *RC = 4343 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4344 (const TargetRegisterClass *) &PPC::GPRCRegClass; 4345 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 4346 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 4347 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 4348 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC); 4349 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC); 4350 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC); 4351 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC); 4352 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 4353 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4354 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4355 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4356 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4357 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4358 unsigned Ptr1Reg; 4359 unsigned TmpReg = RegInfo.createVirtualRegister(RC); 4360 // thisMBB: 4361 // ... 4362 // fallthrough --> loopMBB 4363 BB->addSuccessor(loop1MBB); 4364 4365 // The 4-byte load must be aligned, while a char or short may be 4366 // anywhere in the word. Hence all this nasty bookkeeping code. 4367 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4368 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4369 // xori shift, shift1, 24 [16] 4370 // rlwinm ptr, ptr1, 0, 0, 29 4371 // slw newval2, newval, shift 4372 // slw oldval2, oldval,shift 4373 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 4374 // slw mask, mask2, shift 4375 // and newval3, newval2, mask 4376 // and oldval3, oldval2, mask 4377 // loop1MBB: 4378 // lwarx tmpDest, ptr 4379 // and tmp, tmpDest, mask 4380 // cmpw tmp, oldval3 4381 // bne- midMBB 4382 // loop2MBB: 4383 // andc tmp2, tmpDest, mask 4384 // or tmp4, tmp2, newval3 4385 // stwcx. tmp4, ptr 4386 // bne- loop1MBB 4387 // b exitBB 4388 // midMBB: 4389 // stwcx. tmpDest, ptr 4390 // exitBB: 4391 // srw dest, tmpDest, shift 4392 if (ptrA!=PPC::R0) { 4393 Ptr1Reg = RegInfo.createVirtualRegister(RC); 4394 BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 4395 .addReg(ptrA).addReg(ptrB); 4396 } else { 4397 Ptr1Reg = ptrB; 4398 } 4399 BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 4400 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 4401 BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 4402 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 4403 if (is64bit) 4404 BuildMI(BB, TII->get(PPC::RLDICR), PtrReg) 4405 .addReg(Ptr1Reg).addImm(0).addImm(61); 4406 else 4407 BuildMI(BB, TII->get(PPC::RLWINM), PtrReg) 4408 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 4409 BuildMI(BB, TII->get(PPC::SLW), NewVal2Reg) 4410 .addReg(newval).addReg(ShiftReg); 4411 BuildMI(BB, TII->get(PPC::SLW), OldVal2Reg) 4412 .addReg(oldval).addReg(ShiftReg); 4413 if (is8bit) 4414 BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255); 4415 else { 4416 BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0); 4417 BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535); 4418 } 4419 BuildMI(BB, TII->get(PPC::SLW), MaskReg) 4420 .addReg(Mask2Reg).addReg(ShiftReg); 4421 BuildMI(BB, TII->get(PPC::AND), NewVal3Reg) 4422 .addReg(NewVal2Reg).addReg(MaskReg); 4423 BuildMI(BB, TII->get(PPC::AND), OldVal3Reg) 4424 .addReg(OldVal2Reg).addReg(MaskReg); 4425 4426 BB = loop1MBB; 4427 BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg) 4428 .addReg(PPC::R0).addReg(PtrReg); 4429 BuildMI(BB, TII->get(PPC::AND),TmpReg).addReg(TmpDestReg).addReg(MaskReg); 4430 BuildMI(BB, TII->get(PPC::CMPW), PPC::CR0) 4431 .addReg(TmpReg).addReg(OldVal3Reg); 4432 BuildMI(BB, TII->get(PPC::BCC)) 4433 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 4434 BB->addSuccessor(loop2MBB); 4435 BB->addSuccessor(midMBB); 4436 4437 BB = loop2MBB; 4438 BuildMI(BB, TII->get(PPC::ANDC),Tmp2Reg).addReg(TmpDestReg).addReg(MaskReg); 4439 BuildMI(BB, TII->get(PPC::OR),Tmp4Reg).addReg(Tmp2Reg).addReg(NewVal3Reg); 4440 BuildMI(BB, TII->get(PPC::STWCX)).addReg(Tmp4Reg) 4441 .addReg(PPC::R0).addReg(PtrReg); 4442 BuildMI(BB, TII->get(PPC::BCC)) 4443 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 4444 BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB); 4445 BB->addSuccessor(loop1MBB); 4446 BB->addSuccessor(exitMBB); 4447 4448 BB = midMBB; 4449 BuildMI(BB, TII->get(PPC::STWCX)).addReg(TmpDestReg) 4450 .addReg(PPC::R0).addReg(PtrReg); 4451 BB->addSuccessor(exitMBB); 4452 4453 // exitMBB: 4454 // ... 4455 BB = exitMBB; 4456 BuildMI(BB, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg); 4457 } else { 4458 assert(0 && "Unexpected instr type to insert"); 4459 } 4460 4461 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 4462 return BB; 4463} 4464 4465//===----------------------------------------------------------------------===// 4466// Target Optimization Hooks 4467//===----------------------------------------------------------------------===// 4468 4469SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, 4470 DAGCombinerInfo &DCI) const { 4471 TargetMachine &TM = getTargetMachine(); 4472 SelectionDAG &DAG = DCI.DAG; 4473 DebugLoc dl = N->getDebugLoc(); 4474 switch (N->getOpcode()) { 4475 default: break; 4476 case PPCISD::SHL: 4477 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 4478 if (C->getZExtValue() == 0) // 0 << V -> 0. 4479 return N->getOperand(0); 4480 } 4481 break; 4482 case PPCISD::SRL: 4483 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 4484 if (C->getZExtValue() == 0) // 0 >>u V -> 0. 4485 return N->getOperand(0); 4486 } 4487 break; 4488 case PPCISD::SRA: 4489 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 4490 if (C->getZExtValue() == 0 || // 0 >>s V -> 0. 4491 C->isAllOnesValue()) // -1 >>s V -> -1. 4492 return N->getOperand(0); 4493 } 4494 break; 4495 4496 case ISD::SINT_TO_FP: 4497 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 4498 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 4499 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 4500 // We allow the src/dst to be either f32/f64, but the intermediate 4501 // type must be i64. 4502 if (N->getOperand(0).getValueType() == MVT::i64 && 4503 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 4504 SDValue Val = N->getOperand(0).getOperand(0); 4505 if (Val.getValueType() == MVT::f32) { 4506 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 4507 DCI.AddToWorklist(Val.getNode()); 4508 } 4509 4510 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val); 4511 DCI.AddToWorklist(Val.getNode()); 4512 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val); 4513 DCI.AddToWorklist(Val.getNode()); 4514 if (N->getValueType(0) == MVT::f32) { 4515 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val, 4516 DAG.getIntPtrConstant(0)); 4517 DCI.AddToWorklist(Val.getNode()); 4518 } 4519 return Val; 4520 } else if (N->getOperand(0).getValueType() == MVT::i32) { 4521 // If the intermediate type is i32, we can avoid the load/store here 4522 // too. 4523 } 4524 } 4525 } 4526 break; 4527 case ISD::STORE: 4528 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 4529 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 4530 !cast<StoreSDNode>(N)->isTruncatingStore() && 4531 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 4532 N->getOperand(1).getValueType() == MVT::i32 && 4533 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 4534 SDValue Val = N->getOperand(1).getOperand(0); 4535 if (Val.getValueType() == MVT::f32) { 4536 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 4537 DCI.AddToWorklist(Val.getNode()); 4538 } 4539 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); 4540 DCI.AddToWorklist(Val.getNode()); 4541 4542 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val, 4543 N->getOperand(2), N->getOperand(3)); 4544 DCI.AddToWorklist(Val.getNode()); 4545 return Val; 4546 } 4547 4548 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 4549 if (N->getOperand(1).getOpcode() == ISD::BSWAP && 4550 N->getOperand(1).getNode()->hasOneUse() && 4551 (N->getOperand(1).getValueType() == MVT::i32 || 4552 N->getOperand(1).getValueType() == MVT::i16)) { 4553 SDValue BSwapOp = N->getOperand(1).getOperand(0); 4554 // Do an any-extend to 32-bits if this is a half-word input. 4555 if (BSwapOp.getValueType() == MVT::i16) 4556 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); 4557 4558 return DAG.getNode(PPCISD::STBRX, dl, MVT::Other, N->getOperand(0), 4559 BSwapOp, N->getOperand(2), N->getOperand(3), 4560 DAG.getValueType(N->getOperand(1).getValueType())); 4561 } 4562 break; 4563 case ISD::BSWAP: 4564 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 4565 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) && 4566 N->getOperand(0).hasOneUse() && 4567 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 4568 SDValue Load = N->getOperand(0); 4569 LoadSDNode *LD = cast<LoadSDNode>(Load); 4570 // Create the byte-swapping load. 4571 std::vector<MVT> VTs; 4572 VTs.push_back(MVT::i32); 4573 VTs.push_back(MVT::Other); 4574 SDValue MO = DAG.getMemOperand(LD->getMemOperand()); 4575 SDValue Ops[] = { 4576 LD->getChain(), // Chain 4577 LD->getBasePtr(), // Ptr 4578 MO, // MemOperand 4579 DAG.getValueType(N->getValueType(0)) // VT 4580 }; 4581 SDValue BSLoad = DAG.getNode(PPCISD::LBRX, dl, VTs, Ops, 4); 4582 4583 // If this is an i16 load, insert the truncate. 4584 SDValue ResVal = BSLoad; 4585 if (N->getValueType(0) == MVT::i16) 4586 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); 4587 4588 // First, combine the bswap away. This makes the value produced by the 4589 // load dead. 4590 DCI.CombineTo(N, ResVal); 4591 4592 // Next, combine the load away, we give it a bogus result value but a real 4593 // chain result. The result value is dead because the bswap is dead. 4594 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1)); 4595 4596 // Return N so it doesn't get rechecked! 4597 return SDValue(N, 0); 4598 } 4599 4600 break; 4601 case PPCISD::VCMP: { 4602 // If a VCMPo node already exists with exactly the same operands as this 4603 // node, use its result instead of this node (VCMPo computes both a CR6 and 4604 // a normal output). 4605 // 4606 if (!N->getOperand(0).hasOneUse() && 4607 !N->getOperand(1).hasOneUse() && 4608 !N->getOperand(2).hasOneUse()) { 4609 4610 // Scan all of the users of the LHS, looking for VCMPo's that match. 4611 SDNode *VCMPoNode = 0; 4612 4613 SDNode *LHSN = N->getOperand(0).getNode(); 4614 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 4615 UI != E; ++UI) 4616 if (UI->getOpcode() == PPCISD::VCMPo && 4617 UI->getOperand(1) == N->getOperand(1) && 4618 UI->getOperand(2) == N->getOperand(2) && 4619 UI->getOperand(0) == N->getOperand(0)) { 4620 VCMPoNode = *UI; 4621 break; 4622 } 4623 4624 // If there is no VCMPo node, or if the flag value has a single use, don't 4625 // transform this. 4626 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 4627 break; 4628 4629 // Look at the (necessarily single) use of the flag value. If it has a 4630 // chain, this transformation is more complex. Note that multiple things 4631 // could use the value result, which we should ignore. 4632 SDNode *FlagUser = 0; 4633 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 4634 FlagUser == 0; ++UI) { 4635 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 4636 SDNode *User = *UI; 4637 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 4638 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) { 4639 FlagUser = User; 4640 break; 4641 } 4642 } 4643 } 4644 4645 // If the user is a MFCR instruction, we know this is safe. Otherwise we 4646 // give up for right now. 4647 if (FlagUser->getOpcode() == PPCISD::MFCR) 4648 return SDValue(VCMPoNode, 0); 4649 } 4650 break; 4651 } 4652 case ISD::BR_CC: { 4653 // If this is a branch on an altivec predicate comparison, lower this so 4654 // that we don't have to do a MFCR: instead, branch directly on CR6. This 4655 // lowering is done pre-legalize, because the legalizer lowers the predicate 4656 // compare down to code that is difficult to reassemble. 4657 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 4658 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 4659 int CompareOpc; 4660 bool isDot; 4661 4662 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 4663 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 4664 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 4665 assert(isDot && "Can't compare against a vector result!"); 4666 4667 // If this is a comparison against something other than 0/1, then we know 4668 // that the condition is never/always true. 4669 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue(); 4670 if (Val != 0 && Val != 1) { 4671 if (CC == ISD::SETEQ) // Cond never true, remove branch. 4672 return N->getOperand(0); 4673 // Always !=, turn it into an unconditional branch. 4674 return DAG.getNode(ISD::BR, dl, MVT::Other, 4675 N->getOperand(0), N->getOperand(4)); 4676 } 4677 4678 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 4679 4680 // Create the PPCISD altivec 'dot' comparison node. 4681 std::vector<MVT> VTs; 4682 SDValue Ops[] = { 4683 LHS.getOperand(2), // LHS of compare 4684 LHS.getOperand(3), // RHS of compare 4685 DAG.getConstant(CompareOpc, MVT::i32) 4686 }; 4687 VTs.push_back(LHS.getOperand(2).getValueType()); 4688 VTs.push_back(MVT::Flag); 4689 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 4690 4691 // Unpack the result based on how the target uses it. 4692 PPC::Predicate CompOpc; 4693 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) { 4694 default: // Can't happen, don't crash on invalid number though. 4695 case 0: // Branch on the value of the EQ bit of CR6. 4696 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 4697 break; 4698 case 1: // Branch on the inverted value of the EQ bit of CR6. 4699 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 4700 break; 4701 case 2: // Branch on the value of the LT bit of CR6. 4702 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 4703 break; 4704 case 3: // Branch on the inverted value of the LT bit of CR6. 4705 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 4706 break; 4707 } 4708 4709 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), 4710 DAG.getConstant(CompOpc, MVT::i32), 4711 DAG.getRegister(PPC::CR6, MVT::i32), 4712 N->getOperand(4), CompNode.getValue(1)); 4713 } 4714 break; 4715 } 4716 } 4717 4718 return SDValue(); 4719} 4720 4721//===----------------------------------------------------------------------===// 4722// Inline Assembly Support 4723//===----------------------------------------------------------------------===// 4724 4725void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 4726 const APInt &Mask, 4727 APInt &KnownZero, 4728 APInt &KnownOne, 4729 const SelectionDAG &DAG, 4730 unsigned Depth) const { 4731 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 4732 switch (Op.getOpcode()) { 4733 default: break; 4734 case PPCISD::LBRX: { 4735 // lhbrx is known to have the top bits cleared out. 4736 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16) 4737 KnownZero = 0xFFFF0000; 4738 break; 4739 } 4740 case ISD::INTRINSIC_WO_CHAIN: { 4741 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) { 4742 default: break; 4743 case Intrinsic::ppc_altivec_vcmpbfp_p: 4744 case Intrinsic::ppc_altivec_vcmpeqfp_p: 4745 case Intrinsic::ppc_altivec_vcmpequb_p: 4746 case Intrinsic::ppc_altivec_vcmpequh_p: 4747 case Intrinsic::ppc_altivec_vcmpequw_p: 4748 case Intrinsic::ppc_altivec_vcmpgefp_p: 4749 case Intrinsic::ppc_altivec_vcmpgtfp_p: 4750 case Intrinsic::ppc_altivec_vcmpgtsb_p: 4751 case Intrinsic::ppc_altivec_vcmpgtsh_p: 4752 case Intrinsic::ppc_altivec_vcmpgtsw_p: 4753 case Intrinsic::ppc_altivec_vcmpgtub_p: 4754 case Intrinsic::ppc_altivec_vcmpgtuh_p: 4755 case Intrinsic::ppc_altivec_vcmpgtuw_p: 4756 KnownZero = ~1U; // All bits but the low one are known to be zero. 4757 break; 4758 } 4759 } 4760 } 4761} 4762 4763 4764/// getConstraintType - Given a constraint, return the type of 4765/// constraint it is for this target. 4766PPCTargetLowering::ConstraintType 4767PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 4768 if (Constraint.size() == 1) { 4769 switch (Constraint[0]) { 4770 default: break; 4771 case 'b': 4772 case 'r': 4773 case 'f': 4774 case 'v': 4775 case 'y': 4776 return C_RegisterClass; 4777 } 4778 } 4779 return TargetLowering::getConstraintType(Constraint); 4780} 4781 4782std::pair<unsigned, const TargetRegisterClass*> 4783PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 4784 MVT VT) const { 4785 if (Constraint.size() == 1) { 4786 // GCC RS6000 Constraint Letters 4787 switch (Constraint[0]) { 4788 case 'b': // R1-R31 4789 case 'r': // R0-R31 4790 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 4791 return std::make_pair(0U, PPC::G8RCRegisterClass); 4792 return std::make_pair(0U, PPC::GPRCRegisterClass); 4793 case 'f': 4794 if (VT == MVT::f32) 4795 return std::make_pair(0U, PPC::F4RCRegisterClass); 4796 else if (VT == MVT::f64) 4797 return std::make_pair(0U, PPC::F8RCRegisterClass); 4798 break; 4799 case 'v': 4800 return std::make_pair(0U, PPC::VRRCRegisterClass); 4801 case 'y': // crrc 4802 return std::make_pair(0U, PPC::CRRCRegisterClass); 4803 } 4804 } 4805 4806 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 4807} 4808 4809 4810/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 4811/// vector. If it is invalid, don't add anything to Ops. If hasMemory is true 4812/// it means one of the asm constraint of the inline asm instruction being 4813/// processed is 'm'. 4814void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter, 4815 bool hasMemory, 4816 std::vector<SDValue>&Ops, 4817 SelectionDAG &DAG) const { 4818 SDValue Result(0,0); 4819 switch (Letter) { 4820 default: break; 4821 case 'I': 4822 case 'J': 4823 case 'K': 4824 case 'L': 4825 case 'M': 4826 case 'N': 4827 case 'O': 4828 case 'P': { 4829 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 4830 if (!CST) return; // Must be an immediate to match. 4831 unsigned Value = CST->getZExtValue(); 4832 switch (Letter) { 4833 default: assert(0 && "Unknown constraint letter!"); 4834 case 'I': // "I" is a signed 16-bit constant. 4835 if ((short)Value == (int)Value) 4836 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4837 break; 4838 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 4839 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 4840 if ((short)Value == 0) 4841 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4842 break; 4843 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 4844 if ((Value >> 16) == 0) 4845 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4846 break; 4847 case 'M': // "M" is a constant that is greater than 31. 4848 if (Value > 31) 4849 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4850 break; 4851 case 'N': // "N" is a positive constant that is an exact power of two. 4852 if ((int)Value > 0 && isPowerOf2_32(Value)) 4853 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4854 break; 4855 case 'O': // "O" is the constant zero. 4856 if (Value == 0) 4857 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4858 break; 4859 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 4860 if ((short)-Value == (int)-Value) 4861 Result = DAG.getTargetConstant(Value, Op.getValueType()); 4862 break; 4863 } 4864 break; 4865 } 4866 } 4867 4868 if (Result.getNode()) { 4869 Ops.push_back(Result); 4870 return; 4871 } 4872 4873 // Handle standard constraint letters. 4874 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, hasMemory, Ops, DAG); 4875} 4876 4877// isLegalAddressingMode - Return true if the addressing mode represented 4878// by AM is legal for this target, for a load/store of the specified type. 4879bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 4880 const Type *Ty) const { 4881 // FIXME: PPC does not allow r+i addressing modes for vectors! 4882 4883 // PPC allows a sign-extended 16-bit immediate field. 4884 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 4885 return false; 4886 4887 // No global is ever allowed as a base. 4888 if (AM.BaseGV) 4889 return false; 4890 4891 // PPC only support r+r, 4892 switch (AM.Scale) { 4893 case 0: // "r+i" or just "i", depending on HasBaseReg. 4894 break; 4895 case 1: 4896 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 4897 return false; 4898 // Otherwise we have r+r or r+i. 4899 break; 4900 case 2: 4901 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 4902 return false; 4903 // Allow 2*r as r+r. 4904 break; 4905 default: 4906 // No other scales are supported. 4907 return false; 4908 } 4909 4910 return true; 4911} 4912 4913/// isLegalAddressImmediate - Return true if the integer value can be used 4914/// as the offset of the target addressing mode for load / store of the 4915/// given type. 4916bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{ 4917 // PPC allows a sign-extended 16-bit immediate field. 4918 return (V > -(1 << 16) && V < (1 << 16)-1); 4919} 4920 4921bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 4922 return false; 4923} 4924 4925SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 4926 DebugLoc dl = Op.getNode()->getDebugLoc(); 4927 // Depths > 0 not supported yet! 4928 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) 4929 return SDValue(); 4930 4931 MachineFunction &MF = DAG.getMachineFunction(); 4932 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 4933 4934 // Just load the return address off the stack. 4935 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); 4936 4937 // Make sure the function really does not optimize away the store of the RA 4938 // to the stack. 4939 FuncInfo->setLRStoreRequired(); 4940 return DAG.getLoad(getPointerTy(), dl, 4941 DAG.getEntryNode(), RetAddrFI, NULL, 0); 4942} 4943 4944SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 4945 DebugLoc dl = Op.getDebugLoc(); 4946 // Depths > 0 not supported yet! 4947 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) 4948 return SDValue(); 4949 4950 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4951 bool isPPC64 = PtrVT == MVT::i64; 4952 4953 MachineFunction &MF = DAG.getMachineFunction(); 4954 MachineFrameInfo *MFI = MF.getFrameInfo(); 4955 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects()) 4956 && MFI->getStackSize(); 4957 4958 if (isPPC64) 4959 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1, 4960 MVT::i64); 4961 else 4962 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1, 4963 MVT::i32); 4964} 4965 4966bool 4967PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 4968 // The PowerPC target isn't yet aware of offsets. 4969 return false; 4970} 4971