PPCISelLowering.cpp revision ee625573b5b39b91441fc6ea23f3ba415abdc71f
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCTargetMachine.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineInstrBuilder.h" 19#include "llvm/CodeGen/SelectionDAG.h" 20#include "llvm/CodeGen/SSARegMap.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23using namespace llvm; 24 25PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) 26 : TargetLowering(TM) { 27 28 // Fold away setcc operations if possible. 29 setSetCCIsExpensive(); 30 setPow2DivIsCheap(); 31 32 // Use _setjmp/_longjmp instead of setjmp/longjmp. 33 setUseUnderscoreSetJmpLongJmp(true); 34 35 // Set up the register classes. 36 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 37 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 38 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 39 40 // PowerPC has no intrinsics for these particular operations 41 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 42 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 43 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 44 45 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 46 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand); 47 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand); 48 49 // PowerPC has no SREM/UREM instructions 50 setOperationAction(ISD::SREM, MVT::i32, Expand); 51 setOperationAction(ISD::UREM, MVT::i32, Expand); 52 53 // We don't support sin/cos/sqrt/fmod 54 setOperationAction(ISD::FSIN , MVT::f64, Expand); 55 setOperationAction(ISD::FCOS , MVT::f64, Expand); 56 setOperationAction(ISD::FREM , MVT::f64, Expand); 57 setOperationAction(ISD::FSIN , MVT::f32, Expand); 58 setOperationAction(ISD::FCOS , MVT::f32, Expand); 59 setOperationAction(ISD::FREM , MVT::f32, Expand); 60 61 // If we're enabling GP optimizations, use hardware square root 62 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 63 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 64 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 65 } 66 67 // PowerPC does not have BSWAP, CTPOP or CTTZ 68 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 69 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 70 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 71 72 // PowerPC does not have ROTR 73 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 74 75 // PowerPC does not have Select 76 setOperationAction(ISD::SELECT, MVT::i32, Expand); 77 setOperationAction(ISD::SELECT, MVT::f32, Expand); 78 setOperationAction(ISD::SELECT, MVT::f64, Expand); 79 80 // PowerPC wants to turn select_cc of FP into fsel when possible. 81 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 82 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 83 84 // PowerPC does not have BRCOND* which requires SetCC 85 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 86 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 87 88 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 89 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 90 91 // PowerPC does not have [U|S]INT_TO_FP 92 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 93 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 94 95 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 96 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 97 98 // PowerPC does not have truncstore for i1. 99 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote); 100 101 // Support label based line numbers. 102 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 103 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 104 // FIXME - use subtarget debug flags 105 if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) 106 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 107 108 // We want to legalize GlobalAddress and ConstantPool nodes into the 109 // appropriate instructions to materialize the address. 110 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 111 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 112 113 // RET must be custom lowered, to meet ABI requirements 114 setOperationAction(ISD::RET , MVT::Other, Custom); 115 116 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 117 setOperationAction(ISD::VASTART , MVT::Other, Custom); 118 119 // Use the default implementation. 120 setOperationAction(ISD::VAARG , MVT::Other, Expand); 121 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 122 setOperationAction(ISD::VAEND , MVT::Other, Expand); 123 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 124 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 125 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 126 127 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) { 128 // They also have instructions for converting between i64 and fp. 129 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 130 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 131 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 132 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 133 } else { 134 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 135 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 136 } 137 138 if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) { 139 // 64 bit PowerPC implementations can support i64 types directly 140 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 141 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 142 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 143 } else { 144 // 32 bit PowerPC wants to expand i64 shifts itself. 145 setOperationAction(ISD::SHL, MVT::i64, Custom); 146 setOperationAction(ISD::SRL, MVT::i64, Custom); 147 setOperationAction(ISD::SRA, MVT::i64, Custom); 148 } 149 150 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 151 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 152 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 153 } 154 155 setSetCCResultContents(ZeroOrOneSetCCResult); 156 setStackPointerRegisterToSaveRestore(PPC::R1); 157 158 computeRegisterProperties(); 159} 160 161const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 162 switch (Opcode) { 163 default: return 0; 164 case PPCISD::FSEL: return "PPCISD::FSEL"; 165 case PPCISD::FCFID: return "PPCISD::FCFID"; 166 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 167 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 168 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 169 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 170 case PPCISD::Hi: return "PPCISD::Hi"; 171 case PPCISD::Lo: return "PPCISD::Lo"; 172 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 173 case PPCISD::SRL: return "PPCISD::SRL"; 174 case PPCISD::SRA: return "PPCISD::SRA"; 175 case PPCISD::SHL: return "PPCISD::SHL"; 176 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 177 } 178} 179 180/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 181static bool isFloatingPointZero(SDOperand Op) { 182 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 183 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 184 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) { 185 // Maybe this has already been legalized into the constant pool? 186 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 187 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get())) 188 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 189 } 190 return false; 191} 192 193/// LowerOperation - Provide custom lowering hooks for some operations. 194/// 195SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 196 switch (Op.getOpcode()) { 197 default: assert(0 && "Wasn't expecting to be able to lower this!"); 198 case ISD::FP_TO_SINT: { 199 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 200 SDOperand Src = Op.getOperand(0); 201 if (Src.getValueType() == MVT::f32) 202 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 203 204 SDOperand Tmp; 205 switch (Op.getValueType()) { 206 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 207 case MVT::i32: 208 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 209 break; 210 case MVT::i64: 211 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 212 break; 213 } 214 215 // Convert the FP value to an int value through memory. 216 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp); 217 if (Op.getValueType() == MVT::i32) 218 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits); 219 return Bits; 220 } 221 case ISD::SINT_TO_FP: { 222 assert(MVT::i64 == Op.getOperand(0).getValueType() && 223 "Unhandled SINT_TO_FP type in custom expander!"); 224 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 225 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 226 if (MVT::f32 == Op.getValueType()) 227 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 228 return FP; 229 } 230 case ISD::SELECT_CC: { 231 // Turn FP only select_cc's into fsel instructions. 232 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 233 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 234 break; 235 236 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 237 238 // Cannot handle SETEQ/SETNE. 239 if (CC == ISD::SETEQ || CC == ISD::SETNE) break; 240 241 MVT::ValueType ResVT = Op.getValueType(); 242 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 243 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 244 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 245 246 // If the RHS of the comparison is a 0.0, we don't need to do the 247 // subtraction at all. 248 if (isFloatingPointZero(RHS)) 249 switch (CC) { 250 default: break; // SETUO etc aren't handled by fsel. 251 case ISD::SETULT: 252 case ISD::SETLT: 253 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 254 case ISD::SETUGE: 255 case ISD::SETGE: 256 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 257 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 258 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 259 case ISD::SETUGT: 260 case ISD::SETGT: 261 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 262 case ISD::SETULE: 263 case ISD::SETLE: 264 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 265 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 266 return DAG.getNode(PPCISD::FSEL, ResVT, 267 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 268 } 269 270 SDOperand Cmp; 271 switch (CC) { 272 default: break; // SETUO etc aren't handled by fsel. 273 case ISD::SETULT: 274 case ISD::SETLT: 275 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 276 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 277 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 278 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 279 case ISD::SETUGE: 280 case ISD::SETGE: 281 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 282 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 283 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 284 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 285 case ISD::SETUGT: 286 case ISD::SETGT: 287 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 288 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 289 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 290 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 291 case ISD::SETULE: 292 case ISD::SETLE: 293 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 294 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 295 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 296 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 297 } 298 break; 299 } 300 case ISD::SHL: { 301 assert(Op.getValueType() == MVT::i64 && 302 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 303 // The generic code does a fine job expanding shift by a constant. 304 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 305 306 // Otherwise, expand into a bunch of logical ops. Note that these ops 307 // depend on the PPC behavior for oversized shift amounts. 308 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 309 DAG.getConstant(0, MVT::i32)); 310 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 311 DAG.getConstant(1, MVT::i32)); 312 SDOperand Amt = Op.getOperand(1); 313 314 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 315 DAG.getConstant(32, MVT::i32), Amt); 316 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); 317 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); 318 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 319 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 320 DAG.getConstant(-32U, MVT::i32)); 321 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); 322 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 323 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); 324 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 325 } 326 case ISD::SRL: { 327 assert(Op.getValueType() == MVT::i64 && 328 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 329 // The generic code does a fine job expanding shift by a constant. 330 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 331 332 // Otherwise, expand into a bunch of logical ops. Note that these ops 333 // depend on the PPC behavior for oversized shift amounts. 334 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 335 DAG.getConstant(0, MVT::i32)); 336 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 337 DAG.getConstant(1, MVT::i32)); 338 SDOperand Amt = Op.getOperand(1); 339 340 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 341 DAG.getConstant(32, MVT::i32), Amt); 342 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 343 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 344 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 345 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 346 DAG.getConstant(-32U, MVT::i32)); 347 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); 348 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 349 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); 350 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 351 } 352 case ISD::SRA: { 353 assert(Op.getValueType() == MVT::i64 && 354 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 355 // The generic code does a fine job expanding shift by a constant. 356 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 357 358 // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 359 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 360 DAG.getConstant(0, MVT::i32)); 361 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 362 DAG.getConstant(1, MVT::i32)); 363 SDOperand Amt = Op.getOperand(1); 364 365 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 366 DAG.getConstant(32, MVT::i32), Amt); 367 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 368 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 369 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 370 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 371 DAG.getConstant(-32U, MVT::i32)); 372 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); 373 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); 374 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 375 Tmp4, Tmp6, ISD::SETLE); 376 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 377 } 378 case ISD::ConstantPool: { 379 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 380 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32); 381 SDOperand Zero = DAG.getConstant(0, MVT::i32); 382 383 if (PPCGenerateStaticCode) { 384 // Generate non-pic code that has direct accesses to the constant pool. 385 // The address of the global is just (hi(&g)+lo(&g)). 386 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); 387 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); 388 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 389 } 390 391 // Only lower ConstantPool on Darwin. 392 if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break; 393 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); 394 if (PICEnabled) { 395 // With PIC, the first instruction is actually "GR+hi(&G)". 396 Hi = DAG.getNode(ISD::ADD, MVT::i32, 397 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); 398 } 399 400 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); 401 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 402 return Lo; 403 } 404 case ISD::GlobalAddress: { 405 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 406 GlobalValue *GV = GSDN->getGlobal(); 407 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset()); 408 SDOperand Zero = DAG.getConstant(0, MVT::i32); 409 410 if (PPCGenerateStaticCode) { 411 // Generate non-pic code that has direct accesses to globals. 412 // The address of the global is just (hi(&g)+lo(&g)). 413 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); 414 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); 415 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 416 } 417 418 // Only lower GlobalAddress on Darwin. 419 if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break; 420 421 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); 422 if (PICEnabled) { 423 // With PIC, the first instruction is actually "GR+hi(&G)". 424 Hi = DAG.getNode(ISD::ADD, MVT::i32, 425 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); 426 } 427 428 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); 429 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 430 431 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() && !GV->isExternal()) 432 return Lo; 433 434 // If the global is weak or external, we have to go through the lazy 435 // resolution stub. 436 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0)); 437 } 438 case ISD::VASTART: { 439 // vastart just stores the address of the VarArgsFrameIndex slot into the 440 // memory location argument. 441 // FIXME: Replace MVT::i32 with PointerTy 442 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 443 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR, 444 Op.getOperand(1), Op.getOperand(2)); 445 } 446 case ISD::RET: { 447 SDOperand Copy; 448 449 switch(Op.getNumOperands()) { 450 default: 451 assert(0 && "Do not know how to return this many arguments!"); 452 abort(); 453 case 1: 454 return SDOperand(); // ret void is legal 455 case 2: { 456 MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); 457 unsigned ArgReg = MVT::isInteger(ArgVT) ? PPC::R3 : PPC::F1; 458 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 459 SDOperand()); 460 break; 461 } 462 case 3: 463 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2), 464 SDOperand()); 465 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1)); 466 break; 467 } 468 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 469 } 470 } 471 return SDOperand(); 472} 473 474std::vector<SDOperand> 475PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 476 // 477 // add beautiful description of PPC stack frame format, or at least some docs 478 // 479 MachineFunction &MF = DAG.getMachineFunction(); 480 MachineFrameInfo *MFI = MF.getFrameInfo(); 481 MachineBasicBlock& BB = MF.front(); 482 SSARegMap *RegMap = MF.getSSARegMap(); 483 std::vector<SDOperand> ArgValues; 484 485 unsigned ArgOffset = 24; 486 unsigned GPR_remaining = 8; 487 unsigned FPR_remaining = 13; 488 unsigned GPR_idx = 0, FPR_idx = 0; 489 static const unsigned GPR[] = { 490 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 491 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 492 }; 493 static const unsigned FPR[] = { 494 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 495 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 496 }; 497 498 // Add DAG nodes to load the arguments... On entry to a function on PPC, 499 // the arguments start at offset 24, although they are likely to be passed 500 // in registers. 501 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 502 SDOperand newroot, argt; 503 unsigned ObjSize; 504 bool needsLoad = false; 505 bool ArgLive = !I->use_empty(); 506 MVT::ValueType ObjectVT = getValueType(I->getType()); 507 508 switch (ObjectVT) { 509 default: assert(0 && "Unhandled argument type!"); 510 case MVT::i1: 511 case MVT::i8: 512 case MVT::i16: 513 case MVT::i32: 514 ObjSize = 4; 515 if (!ArgLive) break; 516 if (GPR_remaining > 0) { 517 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 518 MF.addLiveIn(GPR[GPR_idx], VReg); 519 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 520 if (ObjectVT != MVT::i32) { 521 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 522 : ISD::AssertZext; 523 argt = DAG.getNode(AssertOp, MVT::i32, argt, 524 DAG.getValueType(ObjectVT)); 525 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt); 526 } 527 } else { 528 needsLoad = true; 529 } 530 break; 531 case MVT::i64: 532 ObjSize = 8; 533 if (!ArgLive) break; 534 if (GPR_remaining > 0) { 535 SDOperand argHi, argLo; 536 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 537 MF.addLiveIn(GPR[GPR_idx], VReg); 538 argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 539 // If we have two or more remaining argument registers, then both halves 540 // of the i64 can be sourced from there. Otherwise, the lower half will 541 // have to come off the stack. This can happen when an i64 is preceded 542 // by 28 bytes of arguments. 543 if (GPR_remaining > 1) { 544 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 545 MF.addLiveIn(GPR[GPR_idx+1], VReg); 546 argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32); 547 } else { 548 int FI = MFI->CreateFixedObject(4, ArgOffset+4); 549 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 550 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, 551 DAG.getSrcValue(NULL)); 552 } 553 // Build the outgoing arg thingy 554 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi); 555 newroot = argLo; 556 } else { 557 needsLoad = true; 558 } 559 break; 560 case MVT::f32: 561 case MVT::f64: 562 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4; 563 if (!ArgLive) { 564 if (FPR_remaining > 0) { 565 --FPR_remaining; 566 ++FPR_idx; 567 } 568 break; 569 } 570 if (FPR_remaining > 0) { 571 unsigned VReg; 572 if (ObjectVT == MVT::f32) 573 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); 574 else 575 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 576 MF.addLiveIn(FPR[FPR_idx], VReg); 577 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT); 578 --FPR_remaining; 579 ++FPR_idx; 580 } else { 581 needsLoad = true; 582 } 583 break; 584 } 585 586 // We need to load the argument to a virtual register if we determined above 587 // that we ran out of physical registers of the appropriate type 588 if (needsLoad) { 589 unsigned SubregOffset = 0; 590 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3; 591 if (ObjectVT == MVT::i16) SubregOffset = 2; 592 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 593 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 594 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, 595 DAG.getConstant(SubregOffset, MVT::i32)); 596 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, 597 DAG.getSrcValue(NULL)); 598 } 599 600 // Every 4 bytes of argument space consumes one of the GPRs available for 601 // argument passing. 602 if (GPR_remaining > 0) { 603 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1; 604 GPR_remaining -= delta; 605 GPR_idx += delta; 606 } 607 ArgOffset += ObjSize; 608 if (newroot.Val) 609 DAG.setRoot(newroot.getValue(1)); 610 611 ArgValues.push_back(argt); 612 } 613 614 // If the function takes variable number of arguments, make a frame index for 615 // the start of the first vararg value... for expansion of llvm.va_start. 616 if (F.isVarArg()) { 617 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 618 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 619 // If this function is vararg, store any remaining integer argument regs 620 // to their spots on the stack so that they may be loaded by deferencing the 621 // result of va_next. 622 std::vector<SDOperand> MemOps; 623 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) { 624 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 625 MF.addLiveIn(GPR[GPR_idx], VReg); 626 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 627 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), 628 Val, FIN, DAG.getSrcValue(NULL)); 629 MemOps.push_back(Store); 630 // Increment the address by four for the next argument to store 631 SDOperand PtrOff = DAG.getConstant(4, getPointerTy()); 632 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff); 633 } 634 if (!MemOps.empty()) { 635 MemOps.push_back(DAG.getRoot()); 636 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps)); 637 } 638 } 639 640 // Finally, inform the code generator which regs we return values in. 641 switch (getValueType(F.getReturnType())) { 642 default: assert(0 && "Unknown type!"); 643 case MVT::isVoid: break; 644 case MVT::i1: 645 case MVT::i8: 646 case MVT::i16: 647 case MVT::i32: 648 MF.addLiveOut(PPC::R3); 649 break; 650 case MVT::i64: 651 MF.addLiveOut(PPC::R3); 652 MF.addLiveOut(PPC::R4); 653 break; 654 case MVT::f32: 655 case MVT::f64: 656 MF.addLiveOut(PPC::F1); 657 break; 658 } 659 660 return ArgValues; 661} 662 663std::pair<SDOperand, SDOperand> 664PPCTargetLowering::LowerCallTo(SDOperand Chain, 665 const Type *RetTy, bool isVarArg, 666 unsigned CallingConv, bool isTailCall, 667 SDOperand Callee, ArgListTy &Args, 668 SelectionDAG &DAG) { 669 // args_to_use will accumulate outgoing args for the ISD::CALL case in 670 // SelectExpr to use to put the arguments in the appropriate registers. 671 std::vector<SDOperand> args_to_use; 672 673 // Count how many bytes are to be pushed on the stack, including the linkage 674 // area, and parameter passing area. 675 unsigned NumBytes = 24; 676 677 if (Args.empty()) { 678 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 679 DAG.getConstant(NumBytes, getPointerTy())); 680 } else { 681 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 682 switch (getValueType(Args[i].second)) { 683 default: assert(0 && "Unknown value type!"); 684 case MVT::i1: 685 case MVT::i8: 686 case MVT::i16: 687 case MVT::i32: 688 case MVT::f32: 689 NumBytes += 4; 690 break; 691 case MVT::i64: 692 case MVT::f64: 693 NumBytes += 8; 694 break; 695 } 696 } 697 698 // Just to be safe, we'll always reserve the full 24 bytes of linkage area 699 // plus 32 bytes of argument space in case any called code gets funky on us. 700 // (Required by ABI to support var arg) 701 if (NumBytes < 56) NumBytes = 56; 702 703 // Adjust the stack pointer for the new arguments... 704 // These operations are automatically eliminated by the prolog/epilog pass 705 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 706 DAG.getConstant(NumBytes, getPointerTy())); 707 708 // Set up a copy of the stack pointer for use loading and storing any 709 // arguments that may not fit in the registers available for argument 710 // passing. 711 SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 712 713 // Figure out which arguments are going to go in registers, and which in 714 // memory. Also, if this is a vararg function, floating point operations 715 // must be stored to our stack, and loaded into integer regs as well, if 716 // any integer regs are available for argument passing. 717 unsigned ArgOffset = 24; 718 unsigned GPR_remaining = 8; 719 unsigned FPR_remaining = 13; 720 721 std::vector<SDOperand> MemOps; 722 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 723 // PtrOff will be used to store the current argument to the stack if a 724 // register cannot be found for it. 725 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 726 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 727 MVT::ValueType ArgVT = getValueType(Args[i].second); 728 729 switch (ArgVT) { 730 default: assert(0 && "Unexpected ValueType for argument!"); 731 case MVT::i1: 732 case MVT::i8: 733 case MVT::i16: 734 // Promote the integer to 32 bits. If the input type is signed use a 735 // sign extend, otherwise use a zero extend. 736 if (Args[i].second->isSigned()) 737 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first); 738 else 739 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first); 740 // FALL THROUGH 741 case MVT::i32: 742 if (GPR_remaining > 0) { 743 args_to_use.push_back(Args[i].first); 744 --GPR_remaining; 745 } else { 746 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 747 Args[i].first, PtrOff, 748 DAG.getSrcValue(NULL))); 749 } 750 ArgOffset += 4; 751 break; 752 case MVT::i64: 753 // If we have one free GPR left, we can place the upper half of the i64 754 // in it, and store the other half to the stack. If we have two or more 755 // free GPRs, then we can pass both halves of the i64 in registers. 756 if (GPR_remaining > 0) { 757 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 758 Args[i].first, DAG.getConstant(1, MVT::i32)); 759 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 760 Args[i].first, DAG.getConstant(0, MVT::i32)); 761 args_to_use.push_back(Hi); 762 --GPR_remaining; 763 if (GPR_remaining > 0) { 764 args_to_use.push_back(Lo); 765 --GPR_remaining; 766 } else { 767 SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); 768 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); 769 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 770 Lo, PtrOff, DAG.getSrcValue(NULL))); 771 } 772 } else { 773 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 774 Args[i].first, PtrOff, 775 DAG.getSrcValue(NULL))); 776 } 777 ArgOffset += 8; 778 break; 779 case MVT::f32: 780 case MVT::f64: 781 if (FPR_remaining > 0) { 782 args_to_use.push_back(Args[i].first); 783 --FPR_remaining; 784 if (isVarArg) { 785 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 786 Args[i].first, PtrOff, 787 DAG.getSrcValue(NULL)); 788 MemOps.push_back(Store); 789 // Float varargs are always shadowed in available integer registers 790 if (GPR_remaining > 0) { 791 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, 792 DAG.getSrcValue(NULL)); 793 MemOps.push_back(Load.getValue(1)); 794 args_to_use.push_back(Load); 795 --GPR_remaining; 796 } 797 if (GPR_remaining > 0 && MVT::f64 == ArgVT) { 798 SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); 799 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); 800 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, 801 DAG.getSrcValue(NULL)); 802 MemOps.push_back(Load.getValue(1)); 803 args_to_use.push_back(Load); 804 --GPR_remaining; 805 } 806 } else { 807 // If we have any FPRs remaining, we may also have GPRs remaining. 808 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 809 // GPRs. 810 if (GPR_remaining > 0) { 811 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 812 --GPR_remaining; 813 } 814 if (GPR_remaining > 0 && MVT::f64 == ArgVT) { 815 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 816 --GPR_remaining; 817 } 818 } 819 } else { 820 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 821 Args[i].first, PtrOff, 822 DAG.getSrcValue(NULL))); 823 } 824 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8; 825 break; 826 } 827 } 828 if (!MemOps.empty()) 829 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps); 830 } 831 832 std::vector<MVT::ValueType> RetVals; 833 MVT::ValueType RetTyVT = getValueType(RetTy); 834 MVT::ValueType ActualRetTyVT = RetTyVT; 835 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16) 836 ActualRetTyVT = MVT::i32; // Promote result to i32. 837 838 if (RetTyVT != MVT::isVoid) 839 RetVals.push_back(ActualRetTyVT); 840 RetVals.push_back(MVT::Other); 841 842 // If the callee is a GlobalAddress node (quite common, every direct call is) 843 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 844 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 845 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 846 847 SDOperand TheCall = SDOperand(DAG.getCall(RetVals, 848 Chain, Callee, args_to_use), 0); 849 Chain = TheCall.getValue(RetTyVT != MVT::isVoid); 850 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 851 DAG.getConstant(NumBytes, getPointerTy())); 852 SDOperand RetVal = TheCall; 853 854 // If the result is a small value, add a note so that we keep track of the 855 // information about whether it is sign or zero extended. 856 if (RetTyVT != ActualRetTyVT) { 857 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext, 858 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 859 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 860 } 861 862 return std::make_pair(RetVal, Chain); 863} 864 865std::pair<SDOperand, SDOperand> PPCTargetLowering:: 866LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth, 867 SelectionDAG &DAG) { 868 assert(0 && "LowerFrameReturnAddress unimplemented"); 869 abort(); 870} 871 872MachineBasicBlock * 873PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 874 MachineBasicBlock *BB) { 875 assert((MI->getOpcode() == PPC::SELECT_CC_Int || 876 MI->getOpcode() == PPC::SELECT_CC_F4 || 877 MI->getOpcode() == PPC::SELECT_CC_F8) && 878 "Unexpected instr type to insert"); 879 880 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 881 // control-flow pattern. The incoming instruction knows the destination vreg 882 // to set, the condition code register to branch on, the true/false values to 883 // select between, and a branch opcode to use. 884 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 885 ilist<MachineBasicBlock>::iterator It = BB; 886 ++It; 887 888 // thisMBB: 889 // ... 890 // TrueVal = ... 891 // cmpTY ccX, r1, r2 892 // bCC copy1MBB 893 // fallthrough --> copy0MBB 894 MachineBasicBlock *thisMBB = BB; 895 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 896 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 897 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2) 898 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 899 MachineFunction *F = BB->getParent(); 900 F->getBasicBlockList().insert(It, copy0MBB); 901 F->getBasicBlockList().insert(It, sinkMBB); 902 // Update machine-CFG edges 903 BB->addSuccessor(copy0MBB); 904 BB->addSuccessor(sinkMBB); 905 906 // copy0MBB: 907 // %FalseValue = ... 908 // # fallthrough to sinkMBB 909 BB = copy0MBB; 910 911 // Update machine-CFG edges 912 BB->addSuccessor(sinkMBB); 913 914 // sinkMBB: 915 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 916 // ... 917 BB = sinkMBB; 918 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg()) 919 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 920 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 921 922 delete MI; // The pseudo instruction is gone now. 923 return BB; 924} 925 926