PPCISelLowering.cpp revision f1b4708950cb0dc2a0cafb572d5a56d99b8140c0
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCTargetMachine.h" 16#include "llvm/ADT/VectorExtras.h" 17#include "llvm/Analysis/ScalarEvolutionExpressions.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/CodeGen/SSARegMap.h" 23#include "llvm/Constants.h" 24#include "llvm/Function.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/Support/MathExtras.h" 27#include "llvm/Target/TargetOptions.h" 28using namespace llvm; 29 30PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) 31 : TargetLowering(TM) { 32 33 // Fold away setcc operations if possible. 34 setSetCCIsExpensive(); 35 setPow2DivIsCheap(); 36 37 // Use _setjmp/_longjmp instead of setjmp/longjmp. 38 setUseUnderscoreSetJmpLongJmp(true); 39 40 // Set up the register classes. 41 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 42 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 43 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 44 45 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 46 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 47 48 // PowerPC has no intrinsics for these particular operations 49 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 50 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 51 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 52 53 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 54 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand); 55 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand); 56 57 // PowerPC has no SREM/UREM instructions 58 setOperationAction(ISD::SREM, MVT::i32, Expand); 59 setOperationAction(ISD::UREM, MVT::i32, Expand); 60 61 // We don't support sin/cos/sqrt/fmod 62 setOperationAction(ISD::FSIN , MVT::f64, Expand); 63 setOperationAction(ISD::FCOS , MVT::f64, Expand); 64 setOperationAction(ISD::FREM , MVT::f64, Expand); 65 setOperationAction(ISD::FSIN , MVT::f32, Expand); 66 setOperationAction(ISD::FCOS , MVT::f32, Expand); 67 setOperationAction(ISD::FREM , MVT::f32, Expand); 68 69 // If we're enabling GP optimizations, use hardware square root 70 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 71 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 72 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 73 } 74 75 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 76 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 77 78 // PowerPC does not have BSWAP, CTPOP or CTTZ 79 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 80 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 81 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 82 83 // PowerPC does not have ROTR 84 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 85 86 // PowerPC does not have Select 87 setOperationAction(ISD::SELECT, MVT::i32, Expand); 88 setOperationAction(ISD::SELECT, MVT::f32, Expand); 89 setOperationAction(ISD::SELECT, MVT::f64, Expand); 90 setOperationAction(ISD::SELECT, MVT::v4f32, Expand); 91 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 92 setOperationAction(ISD::SELECT, MVT::v8i16, Expand); 93 setOperationAction(ISD::SELECT, MVT::v16i8, Expand); 94 95 // PowerPC wants to turn select_cc of FP into fsel when possible. 96 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 97 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 98 99 // PowerPC wants to optimize integer setcc a bit 100 setOperationAction(ISD::SETCC, MVT::i32, Custom); 101 102 // PowerPC does not have BRCOND which requires SetCC 103 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 104 105 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 106 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 107 108 // PowerPC does not have [U|S]INT_TO_FP 109 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 110 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 111 112 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 113 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 114 115 // PowerPC does not have truncstore for i1. 116 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote); 117 118 // Support label based line numbers. 119 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 120 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 121 // FIXME - use subtarget debug flags 122 if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) 123 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 124 125 // We want to legalize GlobalAddress and ConstantPool nodes into the 126 // appropriate instructions to materialize the address. 127 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 128 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 129 130 // RET must be custom lowered, to meet ABI requirements 131 setOperationAction(ISD::RET , MVT::Other, Custom); 132 133 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 134 setOperationAction(ISD::VASTART , MVT::Other, Custom); 135 136 // Use the default implementation. 137 setOperationAction(ISD::VAARG , MVT::Other, Expand); 138 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 139 setOperationAction(ISD::VAEND , MVT::Other, Expand); 140 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 141 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 142 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 143 144 // We want to custom lower some of our intrinsics. 145 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 146 147 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) { 148 // They also have instructions for converting between i64 and fp. 149 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 150 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 151 152 // FIXME: disable this lowered code. This generates 64-bit register values, 153 // and we don't model the fact that the top part is clobbered by calls. We 154 // need to flag these together so that the value isn't live across a call. 155 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 156 157 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 158 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 159 } else { 160 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 161 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 162 } 163 164 if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) { 165 // 64 bit PowerPC implementations can support i64 types directly 166 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 167 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 168 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 169 } else { 170 // 32 bit PowerPC wants to expand i64 shifts itself. 171 setOperationAction(ISD::SHL, MVT::i64, Custom); 172 setOperationAction(ISD::SRL, MVT::i64, Custom); 173 setOperationAction(ISD::SRA, MVT::i64, Custom); 174 } 175 176 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 177 // First set operation action for all vector types to expand. Then we 178 // will selectively turn on ones that can be effectively codegen'd. 179 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 180 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 181 // add/sub/and/or/xor are legal for all supported vector VT's. 182 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); 183 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); 184 setOperationAction(ISD::AND , (MVT::ValueType)VT, Legal); 185 setOperationAction(ISD::OR , (MVT::ValueType)VT, Legal); 186 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal); 187 188 // We promote all shuffles to v16i8. 189 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); 190 AddPromotedToType(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); 191 192 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); 193 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); 194 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); 195 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); 196 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); 197 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 198 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 199 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); 200 201 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); 202 } 203 204 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 205 // with merges, splats, etc. 206 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 207 208 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 209 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 210 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 211 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 212 213 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 214 215 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 216 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 217 218 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 219 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 220 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 221 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 222 } 223 224 setSetCCResultContents(ZeroOrOneSetCCResult); 225 setStackPointerRegisterToSaveRestore(PPC::R1); 226 227 // We have target-specific dag combine patterns for the following nodes: 228 setTargetDAGCombine(ISD::SINT_TO_FP); 229 setTargetDAGCombine(ISD::STORE); 230 231 computeRegisterProperties(); 232} 233 234const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 235 switch (Opcode) { 236 default: return 0; 237 case PPCISD::FSEL: return "PPCISD::FSEL"; 238 case PPCISD::FCFID: return "PPCISD::FCFID"; 239 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 240 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 241 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 242 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 243 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 244 case PPCISD::VPERM: return "PPCISD::VPERM"; 245 case PPCISD::Hi: return "PPCISD::Hi"; 246 case PPCISD::Lo: return "PPCISD::Lo"; 247 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 248 case PPCISD::SRL: return "PPCISD::SRL"; 249 case PPCISD::SRA: return "PPCISD::SRA"; 250 case PPCISD::SHL: return "PPCISD::SHL"; 251 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 252 case PPCISD::STD_32: return "PPCISD::STD_32"; 253 case PPCISD::CALL: return "PPCISD::CALL"; 254 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 255 case PPCISD::MFCR: return "PPCISD::MFCR"; 256 case PPCISD::VCMP: return "PPCISD::VCMP"; 257 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 258 } 259} 260 261/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 262static bool isFloatingPointZero(SDOperand Op) { 263 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 264 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 265 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) { 266 // Maybe this has already been legalized into the constant pool? 267 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 268 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get())) 269 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 270 } 271 return false; 272} 273 274/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 275/// true if Op is undef or if it matches the specified value. 276static bool isConstantOrUndef(SDOperand Op, unsigned Val) { 277 return Op.getOpcode() == ISD::UNDEF || 278 cast<ConstantSDNode>(Op)->getValue() == Val; 279} 280 281/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 282/// VPKUHUM instruction. 283bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { 284 if (!isUnary) { 285 for (unsigned i = 0; i != 16; ++i) 286 if (!isConstantOrUndef(N->getOperand(i), i*2+1)) 287 return false; 288 } else { 289 for (unsigned i = 0; i != 8; ++i) 290 if (!isConstantOrUndef(N->getOperand(i), i*2+1) || 291 !isConstantOrUndef(N->getOperand(i+8), i*2+1)) 292 return false; 293 } 294 return true; 295} 296 297/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 298/// VPKUWUM instruction. 299bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { 300 if (!isUnary) { 301 for (unsigned i = 0; i != 16; i += 2) 302 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 303 !isConstantOrUndef(N->getOperand(i+1), i*2+3)) 304 return false; 305 } else { 306 for (unsigned i = 0; i != 8; i += 2) 307 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 308 !isConstantOrUndef(N->getOperand(i+1), i*2+3) || 309 !isConstantOrUndef(N->getOperand(i+8), i*2+2) || 310 !isConstantOrUndef(N->getOperand(i+9), i*2+3)) 311 return false; 312 } 313 return true; 314} 315 316/// isVMerge - Common function, used to match vmrg* shuffles. 317/// 318static bool isVMerge(SDNode *N, unsigned UnitSize, 319 unsigned LHSStart, unsigned RHSStart) { 320 assert(N->getOpcode() == ISD::BUILD_VECTOR && 321 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 322 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 323 "Unsupported merge size!"); 324 325 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 326 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 327 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), 328 LHSStart+j+i*UnitSize) || 329 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), 330 RHSStart+j+i*UnitSize)) 331 return false; 332 } 333 return true; 334} 335 336/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 337/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 338bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 339 if (!isUnary) 340 return isVMerge(N, UnitSize, 8, 24); 341 return isVMerge(N, UnitSize, 8, 8); 342} 343 344/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 345/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 346bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 347 if (!isUnary) 348 return isVMerge(N, UnitSize, 0, 16); 349 return isVMerge(N, UnitSize, 0, 0); 350} 351 352 353/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 354/// amount, otherwise return -1. 355int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 356 assert(N->getOpcode() == ISD::BUILD_VECTOR && 357 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 358 // Find the first non-undef value in the shuffle mask. 359 unsigned i; 360 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) 361 /*search*/; 362 363 if (i == 16) return -1; // all undef. 364 365 // Otherwise, check to see if the rest of the elements are consequtively 366 // numbered from this value. 367 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue(); 368 if (ShiftAmt < i) return -1; 369 ShiftAmt -= i; 370 371 if (!isUnary) { 372 // Check the rest of the elements to see if they are consequtive. 373 for (++i; i != 16; ++i) 374 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) 375 return -1; 376 } else { 377 // Check the rest of the elements to see if they are consequtive. 378 for (++i; i != 16; ++i) 379 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) 380 return -1; 381 } 382 383 return ShiftAmt; 384} 385 386/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 387/// specifies a splat of a single element that is suitable for input to 388/// VSPLTB/VSPLTH/VSPLTW. 389bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { 390 assert(N->getOpcode() == ISD::BUILD_VECTOR && 391 N->getNumOperands() == 16 && 392 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 393 394 // This is a splat operation if each element of the permute is the same, and 395 // if the value doesn't reference the second vector. 396 unsigned ElementBase = 0; 397 SDOperand Elt = N->getOperand(0); 398 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) 399 ElementBase = EltV->getValue(); 400 else 401 return false; // FIXME: Handle UNDEF elements too! 402 403 if (cast<ConstantSDNode>(Elt)->getValue() >= 16) 404 return false; 405 406 // Check that they are consequtive. 407 for (unsigned i = 1; i != EltSize; ++i) { 408 if (!isa<ConstantSDNode>(N->getOperand(i)) || 409 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase) 410 return false; 411 } 412 413 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); 414 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 415 assert(isa<ConstantSDNode>(N->getOperand(i)) && 416 "Invalid VECTOR_SHUFFLE mask!"); 417 for (unsigned j = 0; j != EltSize; ++j) 418 if (N->getOperand(i+j) != N->getOperand(j)) 419 return false; 420 } 421 422 return true; 423} 424 425/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 426/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 427unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 428 assert(isSplatShuffleMask(N, EltSize)); 429 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize; 430} 431 432/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 433/// by using a vspltis[bhw] instruction of the specified element size, return 434/// the constant being splatted. The ByteSize field indicates the number of 435/// bytes of each element [124] -> [bhw]. 436SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 437 SDOperand OpVal(0, 0); 438 439 // If ByteSize of the splat is bigger than the element size of the 440 // build_vector, then we have a case where we are checking for a splat where 441 // multiple elements of the buildvector are folded together into a single 442 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 443 unsigned EltSize = 16/N->getNumOperands(); 444 if (EltSize < ByteSize) { 445 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 446 SDOperand UniquedVals[4]; 447 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 448 449 // See if all of the elements in the buildvector agree across. 450 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 451 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 452 // If the element isn't a constant, bail fully out. 453 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand(); 454 455 456 if (UniquedVals[i&(Multiple-1)].Val == 0) 457 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 458 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 459 return SDOperand(); // no match. 460 } 461 462 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 463 // either constant or undef values that are identical for each chunk. See 464 // if these chunks can form into a larger vspltis*. 465 466 // Check to see if all of the leading entries are either 0 or -1. If 467 // neither, then this won't fit into the immediate field. 468 bool LeadingZero = true; 469 bool LeadingOnes = true; 470 for (unsigned i = 0; i != Multiple-1; ++i) { 471 if (UniquedVals[i].Val == 0) continue; // Must have been undefs. 472 473 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 474 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 475 } 476 // Finally, check the least significant entry. 477 if (LeadingZero) { 478 if (UniquedVals[Multiple-1].Val == 0) 479 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 480 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue(); 481 if (Val < 16) 482 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 483 } 484 if (LeadingOnes) { 485 if (UniquedVals[Multiple-1].Val == 0) 486 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 487 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended(); 488 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 489 return DAG.getTargetConstant(Val, MVT::i32); 490 } 491 492 return SDOperand(); 493 } 494 495 // Check to see if this buildvec has a single non-undef value in its elements. 496 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 497 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 498 if (OpVal.Val == 0) 499 OpVal = N->getOperand(i); 500 else if (OpVal != N->getOperand(i)) 501 return SDOperand(); 502 } 503 504 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def. 505 506 unsigned ValSizeInBytes = 0; 507 uint64_t Value = 0; 508 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 509 Value = CN->getValue(); 510 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8; 511 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 512 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 513 Value = FloatToBits(CN->getValue()); 514 ValSizeInBytes = 4; 515 } 516 517 // If the splat value is larger than the element value, then we can never do 518 // this splat. The only case that we could fit the replicated bits into our 519 // immediate field for would be zero, and we prefer to use vxor for it. 520 if (ValSizeInBytes < ByteSize) return SDOperand(); 521 522 // If the element value is larger than the splat value, cut it in half and 523 // check to see if the two halves are equal. Continue doing this until we 524 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 525 while (ValSizeInBytes > ByteSize) { 526 ValSizeInBytes >>= 1; 527 528 // If the top half equals the bottom half, we're still ok. 529 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 530 (Value & ((1 << (8*ValSizeInBytes))-1))) 531 return SDOperand(); 532 } 533 534 // Properly sign extend the value. 535 int ShAmt = (4-ByteSize)*8; 536 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 537 538 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 539 if (MaskVal == 0) return SDOperand(); 540 541 // Finally, if this value fits in a 5 bit sext field, return it 542 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 543 return DAG.getTargetConstant(MaskVal, MVT::i32); 544 return SDOperand(); 545} 546 547// If this is a vector of constants or undefs, get the bits. A bit in 548// UndefBits is set if the corresponding element of the vector is an 549// ISD::UNDEF value. For undefs, the corresponding VectorBits values are 550// zero. Return true if this is not an array of constants, false if it is. 551// 552// Note that VectorBits/UndefBits are returned in 'little endian' form, so 553// elements 0,1 go in VectorBits[0] and 2,3 go in VectorBits[1] for a v4i32. 554static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], 555 uint64_t UndefBits[2]) { 556 // Start with zero'd results. 557 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; 558 559 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType()); 560 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 561 SDOperand OpVal = BV->getOperand(i); 562 563 unsigned PartNo = i >= e/2; // In the upper 128 bits? 564 unsigned SlotNo = i & (e/2-1); // Which subpiece of the uint64_t it is. 565 566 uint64_t EltBits = 0; 567 if (OpVal.getOpcode() == ISD::UNDEF) { 568 uint64_t EltUndefBits = ~0U >> (32-EltBitSize); 569 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); 570 continue; 571 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 572 EltBits = CN->getValue() & (~0U >> (32-EltBitSize)); 573 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 574 assert(CN->getValueType(0) == MVT::f32 && 575 "Only one legal FP vector type!"); 576 EltBits = FloatToBits(CN->getValue()); 577 } else { 578 // Nonconstant element. 579 return true; 580 } 581 582 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); 583 } 584 585 //printf("%llx %llx %llx %llx\n", 586 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); 587 return false; 588} 589 590// If this is a case we can't handle, return null and let the default 591// expansion code take care of it. If we CAN select this case, and if it 592// selects to a single instruction, return Op. Otherwise, if we can codegen 593// this case more efficiently than a constant pool load, lower it to the 594// sequence of ops that should be used. 595static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { 596 // If this is a vector of constants or undefs, get the bits. A bit in 597 // UndefBits is set if the corresponding element of the vector is an 598 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are 599 // zero. 600 uint64_t VectorBits[2]; 601 uint64_t UndefBits[2]; 602 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) 603 return SDOperand(); // Not a constant vector. 604 605 // See if this is all zeros. 606 if ((VectorBits[0] | VectorBits[1]) == 0) { 607 // Canonicalize all zero vectors to be v4i32. 608 if (Op.getValueType() != MVT::v4i32) { 609 SDOperand Z = DAG.getConstant(0, MVT::i32); 610 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); 611 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); 612 } 613 return Op; 614 } 615 616 // Check to see if this is something we can use VSPLTI* to form. 617 MVT::ValueType CanonicalVT = MVT::Other; 618 SDNode *CST = 0; 619 620 if ((CST = PPC::get_VSPLTI_elt(Op.Val, 4, DAG).Val)) // vspltisw 621 CanonicalVT = MVT::v4i32; 622 else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 2, DAG).Val)) // vspltish 623 CanonicalVT = MVT::v8i16; 624 else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 1, DAG).Val)) // vspltisb 625 CanonicalVT = MVT::v16i8; 626 627 // If this matches one of the vsplti* patterns, force it to the canonical 628 // type for the pattern. 629 if (CST) { 630 if (Op.getValueType() != CanonicalVT) { 631 // Convert the splatted element to the right element type. 632 SDOperand Elt = DAG.getNode(ISD::TRUNCATE, 633 MVT::getVectorBaseType(CanonicalVT), 634 SDOperand(CST, 0)); 635 std::vector<SDOperand> Ops(MVT::getVectorNumElements(CanonicalVT), Elt); 636 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops); 637 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 638 } 639 return Op; 640 } 641 642 // If this is some other splat of 4-byte elements, see if we can handle it 643 // in another way. 644 // FIXME: Make this more undef happy and work with other widths (1,2 bytes). 645 if (VectorBits[0] == VectorBits[1] && 646 unsigned(VectorBits[0]) == unsigned(VectorBits[0] >> 32)) { 647 unsigned Bits = unsigned(VectorBits[0]); 648 649 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 650 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). These are important 651 // for fneg/fabs. 652 if (Bits == 0x80000000 || Bits == 0x7FFFFFFF) { 653 // Make -1 and vspltisw -1: 654 SDOperand OnesI = DAG.getConstant(~0U, MVT::i32); 655 SDOperand OnesV = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, 656 OnesI, OnesI, OnesI, OnesI); 657 658 // Make the VSLW intrinsic, computing 0x8000_0000. 659 SDOperand Res 660 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, MVT::v4i32, 661 DAG.getConstant(Intrinsic::ppc_altivec_vslw, MVT::i32), 662 OnesV, OnesV); 663 664 // If this is 0x7FFF_FFFF, xor by OnesV to invert it. 665 if (Bits == 0x7FFFFFFF) 666 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); 667 668 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 669 } 670 } 671 672 return SDOperand(); 673} 674 675/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 676/// is a shuffle we can handle in a single instruction, return it. Otherwise, 677/// return the code it can be lowered into. Worst case, it can always be 678/// lowered into a vperm. 679static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { 680 SDOperand V1 = Op.getOperand(0); 681 SDOperand V2 = Op.getOperand(1); 682 SDOperand PermMask = Op.getOperand(2); 683 684 // Cases that are handled by instructions that take permute immediates 685 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 686 // selected by the instruction selector. 687 if (V2.getOpcode() == ISD::UNDEF) { 688 if (PPC::isSplatShuffleMask(PermMask.Val, 1) || 689 PPC::isSplatShuffleMask(PermMask.Val, 2) || 690 PPC::isSplatShuffleMask(PermMask.Val, 4) || 691 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || 692 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || 693 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || 694 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || 695 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || 696 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || 697 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || 698 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || 699 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { 700 return Op; 701 } 702 } 703 704 // Altivec has a variety of "shuffle immediates" that take two vector inputs 705 // and produce a fixed permutation. If any of these match, do not lower to 706 // VPERM. 707 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || 708 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || 709 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || 710 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || 711 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || 712 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || 713 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || 714 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || 715 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) 716 return Op; 717 718 // TODO: Handle more cases, and also handle cases that are cheaper to do as 719 // multiple such instructions than as a constant pool load/vperm pair. 720 721 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 722 // vector that will get spilled to the constant pool. 723 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 724 725 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 726 // that it is in input element units, not in bytes. Convert now. 727 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType()); 728 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; 729 730 std::vector<SDOperand> ResultMask; 731 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { 732 unsigned SrcElt =cast<ConstantSDNode>(PermMask.getOperand(i))->getValue(); 733 734 for (unsigned j = 0; j != BytesPerElement; ++j) 735 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 736 MVT::i8)); 737 } 738 739 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask); 740 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); 741} 742 743/// LowerOperation - Provide custom lowering hooks for some operations. 744/// 745SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 746 switch (Op.getOpcode()) { 747 default: assert(0 && "Wasn't expecting to be able to lower this!"); 748 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 749 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 750 case ISD::FP_TO_SINT: { 751 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 752 SDOperand Src = Op.getOperand(0); 753 if (Src.getValueType() == MVT::f32) 754 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 755 756 SDOperand Tmp; 757 switch (Op.getValueType()) { 758 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 759 case MVT::i32: 760 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 761 break; 762 case MVT::i64: 763 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 764 break; 765 } 766 767 // Convert the FP value to an int value through memory. 768 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp); 769 if (Op.getValueType() == MVT::i32) 770 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits); 771 return Bits; 772 } 773 case ISD::SINT_TO_FP: 774 if (Op.getOperand(0).getValueType() == MVT::i64) { 775 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 776 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 777 if (Op.getValueType() == MVT::f32) 778 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 779 return FP; 780 } else { 781 assert(Op.getOperand(0).getValueType() == MVT::i32 && 782 "Unhandled SINT_TO_FP type in custom expander!"); 783 // Since we only generate this in 64-bit mode, we can take advantage of 784 // 64-bit registers. In particular, sign extend the input value into the 785 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 786 // then lfd it and fcfid it. 787 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 788 int FrameIdx = FrameInfo->CreateStackObject(8, 8); 789 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32); 790 791 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, 792 Op.getOperand(0)); 793 794 // STD the extended value into the stack slot. 795 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, 796 DAG.getEntryNode(), Ext64, FIdx, 797 DAG.getSrcValue(NULL)); 798 // Load the value as a double. 799 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL)); 800 801 // FCFID it and return it. 802 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); 803 if (Op.getValueType() == MVT::f32) 804 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 805 return FP; 806 } 807 break; 808 809 case ISD::SELECT_CC: { 810 // Turn FP only select_cc's into fsel instructions. 811 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 812 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 813 break; 814 815 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 816 817 // Cannot handle SETEQ/SETNE. 818 if (CC == ISD::SETEQ || CC == ISD::SETNE) break; 819 820 MVT::ValueType ResVT = Op.getValueType(); 821 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 822 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 823 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 824 825 // If the RHS of the comparison is a 0.0, we don't need to do the 826 // subtraction at all. 827 if (isFloatingPointZero(RHS)) 828 switch (CC) { 829 default: break; // SETUO etc aren't handled by fsel. 830 case ISD::SETULT: 831 case ISD::SETLT: 832 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 833 case ISD::SETUGE: 834 case ISD::SETGE: 835 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 836 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 837 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 838 case ISD::SETUGT: 839 case ISD::SETGT: 840 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 841 case ISD::SETULE: 842 case ISD::SETLE: 843 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 844 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 845 return DAG.getNode(PPCISD::FSEL, ResVT, 846 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 847 } 848 849 SDOperand Cmp; 850 switch (CC) { 851 default: break; // SETUO etc aren't handled by fsel. 852 case ISD::SETULT: 853 case ISD::SETLT: 854 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 855 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 856 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 857 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 858 case ISD::SETUGE: 859 case ISD::SETGE: 860 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 861 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 862 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 863 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 864 case ISD::SETUGT: 865 case ISD::SETGT: 866 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 867 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 868 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 869 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 870 case ISD::SETULE: 871 case ISD::SETLE: 872 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 873 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 874 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 875 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 876 } 877 break; 878 } 879 case ISD::SHL: { 880 assert(Op.getValueType() == MVT::i64 && 881 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 882 // The generic code does a fine job expanding shift by a constant. 883 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 884 885 // Otherwise, expand into a bunch of logical ops. Note that these ops 886 // depend on the PPC behavior for oversized shift amounts. 887 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 888 DAG.getConstant(0, MVT::i32)); 889 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 890 DAG.getConstant(1, MVT::i32)); 891 SDOperand Amt = Op.getOperand(1); 892 893 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 894 DAG.getConstant(32, MVT::i32), Amt); 895 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); 896 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); 897 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 898 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 899 DAG.getConstant(-32U, MVT::i32)); 900 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); 901 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 902 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); 903 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 904 } 905 case ISD::SRL: { 906 assert(Op.getValueType() == MVT::i64 && 907 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 908 // The generic code does a fine job expanding shift by a constant. 909 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 910 911 // Otherwise, expand into a bunch of logical ops. Note that these ops 912 // depend on the PPC behavior for oversized shift amounts. 913 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 914 DAG.getConstant(0, MVT::i32)); 915 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 916 DAG.getConstant(1, MVT::i32)); 917 SDOperand Amt = Op.getOperand(1); 918 919 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 920 DAG.getConstant(32, MVT::i32), Amt); 921 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 922 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 923 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 924 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 925 DAG.getConstant(-32U, MVT::i32)); 926 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); 927 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 928 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); 929 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 930 } 931 case ISD::SRA: { 932 assert(Op.getValueType() == MVT::i64 && 933 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 934 // The generic code does a fine job expanding shift by a constant. 935 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 936 937 // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 938 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 939 DAG.getConstant(0, MVT::i32)); 940 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 941 DAG.getConstant(1, MVT::i32)); 942 SDOperand Amt = Op.getOperand(1); 943 944 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 945 DAG.getConstant(32, MVT::i32), Amt); 946 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 947 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 948 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 949 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 950 DAG.getConstant(-32U, MVT::i32)); 951 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); 952 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); 953 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 954 Tmp4, Tmp6, ISD::SETLE); 955 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 956 } 957 case ISD::ConstantPool: { 958 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 959 Constant *C = CP->get(); 960 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32, CP->getAlignment()); 961 SDOperand Zero = DAG.getConstant(0, MVT::i32); 962 963 // If this is a non-darwin platform, we don't support non-static relo models 964 // yet. 965 if (getTargetMachine().getRelocationModel() == Reloc::Static || 966 !getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) { 967 // Generate non-pic code that has direct accesses to the constant pool. 968 // The address of the global is just (hi(&g)+lo(&g)). 969 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); 970 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); 971 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 972 } 973 974 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); 975 if (getTargetMachine().getRelocationModel() == Reloc::PIC) { 976 // With PIC, the first instruction is actually "GR+hi(&G)". 977 Hi = DAG.getNode(ISD::ADD, MVT::i32, 978 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); 979 } 980 981 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); 982 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 983 return Lo; 984 } 985 case ISD::GlobalAddress: { 986 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 987 GlobalValue *GV = GSDN->getGlobal(); 988 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset()); 989 SDOperand Zero = DAG.getConstant(0, MVT::i32); 990 991 // If this is a non-darwin platform, we don't support non-static relo models 992 // yet. 993 if (getTargetMachine().getRelocationModel() == Reloc::Static || 994 !getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) { 995 // Generate non-pic code that has direct accesses to globals. 996 // The address of the global is just (hi(&g)+lo(&g)). 997 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); 998 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); 999 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 1000 } 1001 1002 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); 1003 if (getTargetMachine().getRelocationModel() == Reloc::PIC) { 1004 // With PIC, the first instruction is actually "GR+hi(&G)". 1005 Hi = DAG.getNode(ISD::ADD, MVT::i32, 1006 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); 1007 } 1008 1009 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); 1010 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 1011 1012 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() && 1013 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode())) 1014 return Lo; 1015 1016 // If the global is weak or external, we have to go through the lazy 1017 // resolution stub. 1018 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0)); 1019 } 1020 case ISD::SETCC: { 1021 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1022 1023 // If we're comparing for equality to zero, expose the fact that this is 1024 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1025 // fold the new nodes. 1026 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1027 if (C->isNullValue() && CC == ISD::SETEQ) { 1028 MVT::ValueType VT = Op.getOperand(0).getValueType(); 1029 SDOperand Zext = Op.getOperand(0); 1030 if (VT < MVT::i32) { 1031 VT = MVT::i32; 1032 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); 1033 } 1034 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); 1035 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); 1036 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, 1037 DAG.getConstant(Log2b, getShiftAmountTy())); 1038 return DAG.getNode(ISD::TRUNCATE, getSetCCResultTy(), Scc); 1039 } 1040 // Leave comparisons against 0 and -1 alone for now, since they're usually 1041 // optimized. FIXME: revisit this when we can custom lower all setcc 1042 // optimizations. 1043 if (C->isAllOnesValue() || C->isNullValue()) 1044 break; 1045 } 1046 1047 // If we have an integer seteq/setne, turn it into a compare against zero 1048 // by subtracting the rhs from the lhs, which is faster than setting a 1049 // condition register, reading it back out, and masking the correct bit. 1050 MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); 1051 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1052 MVT::ValueType VT = Op.getValueType(); 1053 SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0), 1054 Op.getOperand(1)); 1055 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); 1056 } 1057 break; 1058 } 1059 case ISD::VASTART: { 1060 // vastart just stores the address of the VarArgsFrameIndex slot into the 1061 // memory location argument. 1062 // FIXME: Replace MVT::i32 with PointerTy 1063 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 1064 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR, 1065 Op.getOperand(1), Op.getOperand(2)); 1066 } 1067 case ISD::RET: { 1068 SDOperand Copy; 1069 1070 switch(Op.getNumOperands()) { 1071 default: 1072 assert(0 && "Do not know how to return this many arguments!"); 1073 abort(); 1074 case 1: 1075 return SDOperand(); // ret void is legal 1076 case 2: { 1077 MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); 1078 unsigned ArgReg; 1079 if (MVT::isVector(ArgVT)) 1080 ArgReg = PPC::V2; 1081 else if (MVT::isInteger(ArgVT)) 1082 ArgReg = PPC::R3; 1083 else { 1084 assert(MVT::isFloatingPoint(ArgVT)); 1085 ArgReg = PPC::F1; 1086 } 1087 1088 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 1089 SDOperand()); 1090 1091 // If we haven't noted the R3/F1 are live out, do so now. 1092 if (DAG.getMachineFunction().liveout_empty()) 1093 DAG.getMachineFunction().addLiveOut(ArgReg); 1094 break; 1095 } 1096 case 3: 1097 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2), 1098 SDOperand()); 1099 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1)); 1100 // If we haven't noted the R3+R4 are live out, do so now. 1101 if (DAG.getMachineFunction().liveout_empty()) { 1102 DAG.getMachineFunction().addLiveOut(PPC::R3); 1103 DAG.getMachineFunction().addLiveOut(PPC::R4); 1104 } 1105 break; 1106 } 1107 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 1108 } 1109 case ISD::SCALAR_TO_VECTOR: { 1110 // Create a stack slot that is 16-byte aligned. 1111 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 1112 int FrameIdx = FrameInfo->CreateStackObject(16, 16); 1113 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32); 1114 1115 // Store the input value into Value#0 of the stack slot. 1116 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 1117 Op.getOperand(0), FIdx,DAG.getSrcValue(NULL)); 1118 // Load it out. 1119 return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL)); 1120 } 1121 case ISD::INTRINSIC_WO_CHAIN: { 1122 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue(); 1123 1124 // If this is a lowered altivec predicate compare, CompareOpc is set to the 1125 // opcode number of the comparison. 1126 int CompareOpc = -1; 1127 bool isDot = false; 1128 switch (IntNo) { 1129 default: return SDOperand(); // Don't custom lower most intrinsics. 1130 // Comparison predicates. 1131 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 1132 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 1133 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 1134 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 1135 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 1136 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 1137 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 1138 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 1139 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 1140 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 1141 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 1142 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 1143 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 1144 1145 // Normal Comparisons. 1146 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 1147 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 1148 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 1149 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 1150 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 1151 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 1152 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 1153 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 1154 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 1155 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 1156 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 1157 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 1158 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 1159 } 1160 1161 assert(CompareOpc>0 && "We only lower altivec predicate compares so far!"); 1162 1163 // If this is a non-dot comparison, make the VCMP node. 1164 if (!isDot) { 1165 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), 1166 Op.getOperand(1), Op.getOperand(2), 1167 DAG.getConstant(CompareOpc, MVT::i32)); 1168 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); 1169 } 1170 1171 // Create the PPCISD altivec 'dot' comparison node. 1172 std::vector<SDOperand> Ops; 1173 std::vector<MVT::ValueType> VTs; 1174 Ops.push_back(Op.getOperand(2)); // LHS 1175 Ops.push_back(Op.getOperand(3)); // RHS 1176 Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32)); 1177 VTs.push_back(Op.getOperand(2).getValueType()); 1178 VTs.push_back(MVT::Flag); 1179 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops); 1180 1181 // Now that we have the comparison, emit a copy from the CR to a GPR. 1182 // This is flagged to the above dot comparison. 1183 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, 1184 DAG.getRegister(PPC::CR6, MVT::i32), 1185 CompNode.getValue(1)); 1186 1187 // Unpack the result based on how the target uses it. 1188 unsigned BitNo; // Bit # of CR6. 1189 bool InvertBit; // Invert result? 1190 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { 1191 default: // Can't happen, don't crash on invalid number though. 1192 case 0: // Return the value of the EQ bit of CR6. 1193 BitNo = 0; InvertBit = false; 1194 break; 1195 case 1: // Return the inverted value of the EQ bit of CR6. 1196 BitNo = 0; InvertBit = true; 1197 break; 1198 case 2: // Return the value of the LT bit of CR6. 1199 BitNo = 2; InvertBit = false; 1200 break; 1201 case 3: // Return the inverted value of the LT bit of CR6. 1202 BitNo = 2; InvertBit = true; 1203 break; 1204 } 1205 1206 // Shift the bit into the low position. 1207 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, 1208 DAG.getConstant(8-(3-BitNo), MVT::i32)); 1209 // Isolate the bit. 1210 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, 1211 DAG.getConstant(1, MVT::i32)); 1212 1213 // If we are supposed to, toggle the bit. 1214 if (InvertBit) 1215 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, 1216 DAG.getConstant(1, MVT::i32)); 1217 return Flags; 1218 } 1219 } 1220 return SDOperand(); 1221} 1222 1223std::vector<SDOperand> 1224PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 1225 // 1226 // add beautiful description of PPC stack frame format, or at least some docs 1227 // 1228 MachineFunction &MF = DAG.getMachineFunction(); 1229 MachineFrameInfo *MFI = MF.getFrameInfo(); 1230 MachineBasicBlock& BB = MF.front(); 1231 SSARegMap *RegMap = MF.getSSARegMap(); 1232 std::vector<SDOperand> ArgValues; 1233 1234 unsigned ArgOffset = 24; 1235 unsigned GPR_remaining = 8; 1236 unsigned FPR_remaining = 13; 1237 unsigned GPR_idx = 0, FPR_idx = 0; 1238 static const unsigned GPR[] = { 1239 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1240 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1241 }; 1242 static const unsigned FPR[] = { 1243 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1244 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1245 }; 1246 1247 // Add DAG nodes to load the arguments... On entry to a function on PPC, 1248 // the arguments start at offset 24, although they are likely to be passed 1249 // in registers. 1250 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 1251 SDOperand newroot, argt; 1252 unsigned ObjSize; 1253 bool needsLoad = false; 1254 bool ArgLive = !I->use_empty(); 1255 MVT::ValueType ObjectVT = getValueType(I->getType()); 1256 1257 switch (ObjectVT) { 1258 default: assert(0 && "Unhandled argument type!"); 1259 case MVT::i1: 1260 case MVT::i8: 1261 case MVT::i16: 1262 case MVT::i32: 1263 ObjSize = 4; 1264 if (!ArgLive) break; 1265 if (GPR_remaining > 0) { 1266 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1267 MF.addLiveIn(GPR[GPR_idx], VReg); 1268 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 1269 if (ObjectVT != MVT::i32) { 1270 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 1271 : ISD::AssertZext; 1272 argt = DAG.getNode(AssertOp, MVT::i32, argt, 1273 DAG.getValueType(ObjectVT)); 1274 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt); 1275 } 1276 } else { 1277 needsLoad = true; 1278 } 1279 break; 1280 case MVT::i64: 1281 ObjSize = 8; 1282 if (!ArgLive) break; 1283 if (GPR_remaining > 0) { 1284 SDOperand argHi, argLo; 1285 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1286 MF.addLiveIn(GPR[GPR_idx], VReg); 1287 argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 1288 // If we have two or more remaining argument registers, then both halves 1289 // of the i64 can be sourced from there. Otherwise, the lower half will 1290 // have to come off the stack. This can happen when an i64 is preceded 1291 // by 28 bytes of arguments. 1292 if (GPR_remaining > 1) { 1293 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1294 MF.addLiveIn(GPR[GPR_idx+1], VReg); 1295 argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32); 1296 } else { 1297 int FI = MFI->CreateFixedObject(4, ArgOffset+4); 1298 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 1299 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, 1300 DAG.getSrcValue(NULL)); 1301 } 1302 // Build the outgoing arg thingy 1303 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi); 1304 newroot = argLo; 1305 } else { 1306 needsLoad = true; 1307 } 1308 break; 1309 case MVT::f32: 1310 case MVT::f64: 1311 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4; 1312 if (!ArgLive) { 1313 if (FPR_remaining > 0) { 1314 --FPR_remaining; 1315 ++FPR_idx; 1316 } 1317 break; 1318 } 1319 if (FPR_remaining > 0) { 1320 unsigned VReg; 1321 if (ObjectVT == MVT::f32) 1322 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); 1323 else 1324 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 1325 MF.addLiveIn(FPR[FPR_idx], VReg); 1326 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT); 1327 --FPR_remaining; 1328 ++FPR_idx; 1329 } else { 1330 needsLoad = true; 1331 } 1332 break; 1333 } 1334 1335 // We need to load the argument to a virtual register if we determined above 1336 // that we ran out of physical registers of the appropriate type 1337 if (needsLoad) { 1338 unsigned SubregOffset = 0; 1339 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3; 1340 if (ObjectVT == MVT::i16) SubregOffset = 2; 1341 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 1342 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 1343 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, 1344 DAG.getConstant(SubregOffset, MVT::i32)); 1345 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, 1346 DAG.getSrcValue(NULL)); 1347 } 1348 1349 // Every 4 bytes of argument space consumes one of the GPRs available for 1350 // argument passing. 1351 if (GPR_remaining > 0) { 1352 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1; 1353 GPR_remaining -= delta; 1354 GPR_idx += delta; 1355 } 1356 ArgOffset += ObjSize; 1357 if (newroot.Val) 1358 DAG.setRoot(newroot.getValue(1)); 1359 1360 ArgValues.push_back(argt); 1361 } 1362 1363 // If the function takes variable number of arguments, make a frame index for 1364 // the start of the first vararg value... for expansion of llvm.va_start. 1365 if (F.isVarArg()) { 1366 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 1367 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 1368 // If this function is vararg, store any remaining integer argument regs 1369 // to their spots on the stack so that they may be loaded by deferencing the 1370 // result of va_next. 1371 std::vector<SDOperand> MemOps; 1372 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) { 1373 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1374 MF.addLiveIn(GPR[GPR_idx], VReg); 1375 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 1376 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), 1377 Val, FIN, DAG.getSrcValue(NULL)); 1378 MemOps.push_back(Store); 1379 // Increment the address by four for the next argument to store 1380 SDOperand PtrOff = DAG.getConstant(4, getPointerTy()); 1381 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff); 1382 } 1383 if (!MemOps.empty()) { 1384 MemOps.push_back(DAG.getRoot()); 1385 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps)); 1386 } 1387 } 1388 1389 return ArgValues; 1390} 1391 1392std::pair<SDOperand, SDOperand> 1393PPCTargetLowering::LowerCallTo(SDOperand Chain, 1394 const Type *RetTy, bool isVarArg, 1395 unsigned CallingConv, bool isTailCall, 1396 SDOperand Callee, ArgListTy &Args, 1397 SelectionDAG &DAG) { 1398 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in 1399 // SelectExpr to use to put the arguments in the appropriate registers. 1400 std::vector<SDOperand> args_to_use; 1401 1402 // Count how many bytes are to be pushed on the stack, including the linkage 1403 // area, and parameter passing area. 1404 unsigned NumBytes = 24; 1405 1406 if (Args.empty()) { 1407 Chain = DAG.getCALLSEQ_START(Chain, 1408 DAG.getConstant(NumBytes, getPointerTy())); 1409 } else { 1410 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 1411 switch (getValueType(Args[i].second)) { 1412 default: assert(0 && "Unknown value type!"); 1413 case MVT::i1: 1414 case MVT::i8: 1415 case MVT::i16: 1416 case MVT::i32: 1417 case MVT::f32: 1418 NumBytes += 4; 1419 break; 1420 case MVT::i64: 1421 case MVT::f64: 1422 NumBytes += 8; 1423 break; 1424 } 1425 } 1426 1427 // Just to be safe, we'll always reserve the full 24 bytes of linkage area 1428 // plus 32 bytes of argument space in case any called code gets funky on us. 1429 // (Required by ABI to support var arg) 1430 if (NumBytes < 56) NumBytes = 56; 1431 1432 // Adjust the stack pointer for the new arguments... 1433 // These operations are automatically eliminated by the prolog/epilog pass 1434 Chain = DAG.getCALLSEQ_START(Chain, 1435 DAG.getConstant(NumBytes, getPointerTy())); 1436 1437 // Set up a copy of the stack pointer for use loading and storing any 1438 // arguments that may not fit in the registers available for argument 1439 // passing. 1440 SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 1441 1442 // Figure out which arguments are going to go in registers, and which in 1443 // memory. Also, if this is a vararg function, floating point operations 1444 // must be stored to our stack, and loaded into integer regs as well, if 1445 // any integer regs are available for argument passing. 1446 unsigned ArgOffset = 24; 1447 unsigned GPR_remaining = 8; 1448 unsigned FPR_remaining = 13; 1449 1450 std::vector<SDOperand> MemOps; 1451 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 1452 // PtrOff will be used to store the current argument to the stack if a 1453 // register cannot be found for it. 1454 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 1455 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 1456 MVT::ValueType ArgVT = getValueType(Args[i].second); 1457 1458 switch (ArgVT) { 1459 default: assert(0 && "Unexpected ValueType for argument!"); 1460 case MVT::i1: 1461 case MVT::i8: 1462 case MVT::i16: 1463 // Promote the integer to 32 bits. If the input type is signed use a 1464 // sign extend, otherwise use a zero extend. 1465 if (Args[i].second->isSigned()) 1466 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first); 1467 else 1468 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first); 1469 // FALL THROUGH 1470 case MVT::i32: 1471 if (GPR_remaining > 0) { 1472 args_to_use.push_back(Args[i].first); 1473 --GPR_remaining; 1474 } else { 1475 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 1476 Args[i].first, PtrOff, 1477 DAG.getSrcValue(NULL))); 1478 } 1479 ArgOffset += 4; 1480 break; 1481 case MVT::i64: 1482 // If we have one free GPR left, we can place the upper half of the i64 1483 // in it, and store the other half to the stack. If we have two or more 1484 // free GPRs, then we can pass both halves of the i64 in registers. 1485 if (GPR_remaining > 0) { 1486 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 1487 Args[i].first, DAG.getConstant(1, MVT::i32)); 1488 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 1489 Args[i].first, DAG.getConstant(0, MVT::i32)); 1490 args_to_use.push_back(Hi); 1491 --GPR_remaining; 1492 if (GPR_remaining > 0) { 1493 args_to_use.push_back(Lo); 1494 --GPR_remaining; 1495 } else { 1496 SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); 1497 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); 1498 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 1499 Lo, PtrOff, DAG.getSrcValue(NULL))); 1500 } 1501 } else { 1502 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 1503 Args[i].first, PtrOff, 1504 DAG.getSrcValue(NULL))); 1505 } 1506 ArgOffset += 8; 1507 break; 1508 case MVT::f32: 1509 case MVT::f64: 1510 if (FPR_remaining > 0) { 1511 args_to_use.push_back(Args[i].first); 1512 --FPR_remaining; 1513 if (isVarArg) { 1514 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 1515 Args[i].first, PtrOff, 1516 DAG.getSrcValue(NULL)); 1517 MemOps.push_back(Store); 1518 // Float varargs are always shadowed in available integer registers 1519 if (GPR_remaining > 0) { 1520 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, 1521 DAG.getSrcValue(NULL)); 1522 MemOps.push_back(Load.getValue(1)); 1523 args_to_use.push_back(Load); 1524 --GPR_remaining; 1525 } 1526 if (GPR_remaining > 0 && MVT::f64 == ArgVT) { 1527 SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); 1528 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); 1529 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, 1530 DAG.getSrcValue(NULL)); 1531 MemOps.push_back(Load.getValue(1)); 1532 args_to_use.push_back(Load); 1533 --GPR_remaining; 1534 } 1535 } else { 1536 // If we have any FPRs remaining, we may also have GPRs remaining. 1537 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 1538 // GPRs. 1539 if (GPR_remaining > 0) { 1540 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 1541 --GPR_remaining; 1542 } 1543 if (GPR_remaining > 0 && MVT::f64 == ArgVT) { 1544 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 1545 --GPR_remaining; 1546 } 1547 } 1548 } else { 1549 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 1550 Args[i].first, PtrOff, 1551 DAG.getSrcValue(NULL))); 1552 } 1553 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8; 1554 break; 1555 } 1556 } 1557 if (!MemOps.empty()) 1558 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps); 1559 } 1560 1561 std::vector<MVT::ValueType> RetVals; 1562 MVT::ValueType RetTyVT = getValueType(RetTy); 1563 MVT::ValueType ActualRetTyVT = RetTyVT; 1564 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16) 1565 ActualRetTyVT = MVT::i32; // Promote result to i32. 1566 1567 if (RetTyVT == MVT::i64) { 1568 RetVals.push_back(MVT::i32); 1569 RetVals.push_back(MVT::i32); 1570 } else if (RetTyVT != MVT::isVoid) { 1571 RetVals.push_back(ActualRetTyVT); 1572 } 1573 RetVals.push_back(MVT::Other); 1574 1575 // If the callee is a GlobalAddress node (quite common, every direct call is) 1576 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1577 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1578 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 1579 1580 std::vector<SDOperand> Ops; 1581 Ops.push_back(Chain); 1582 Ops.push_back(Callee); 1583 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end()); 1584 SDOperand TheCall = DAG.getNode(PPCISD::CALL, RetVals, Ops); 1585 Chain = TheCall.getValue(TheCall.Val->getNumValues()-1); 1586 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 1587 DAG.getConstant(NumBytes, getPointerTy())); 1588 SDOperand RetVal = TheCall; 1589 1590 // If the result is a small value, add a note so that we keep track of the 1591 // information about whether it is sign or zero extended. 1592 if (RetTyVT != ActualRetTyVT) { 1593 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext, 1594 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 1595 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 1596 } else if (RetTyVT == MVT::i64) { 1597 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, RetVal, RetVal.getValue(1)); 1598 } 1599 1600 return std::make_pair(RetVal, Chain); 1601} 1602 1603MachineBasicBlock * 1604PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 1605 MachineBasicBlock *BB) { 1606 assert((MI->getOpcode() == PPC::SELECT_CC_Int || 1607 MI->getOpcode() == PPC::SELECT_CC_F4 || 1608 MI->getOpcode() == PPC::SELECT_CC_F8 || 1609 MI->getOpcode() == PPC::SELECT_CC_VRRC) && 1610 "Unexpected instr type to insert"); 1611 1612 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 1613 // control-flow pattern. The incoming instruction knows the destination vreg 1614 // to set, the condition code register to branch on, the true/false values to 1615 // select between, and a branch opcode to use. 1616 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1617 ilist<MachineBasicBlock>::iterator It = BB; 1618 ++It; 1619 1620 // thisMBB: 1621 // ... 1622 // TrueVal = ... 1623 // cmpTY ccX, r1, r2 1624 // bCC copy1MBB 1625 // fallthrough --> copy0MBB 1626 MachineBasicBlock *thisMBB = BB; 1627 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 1628 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 1629 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2) 1630 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 1631 MachineFunction *F = BB->getParent(); 1632 F->getBasicBlockList().insert(It, copy0MBB); 1633 F->getBasicBlockList().insert(It, sinkMBB); 1634 // Update machine-CFG edges by first adding all successors of the current 1635 // block to the new block which will contain the Phi node for the select. 1636 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 1637 e = BB->succ_end(); i != e; ++i) 1638 sinkMBB->addSuccessor(*i); 1639 // Next, remove all successors of the current block, and add the true 1640 // and fallthrough blocks as its successors. 1641 while(!BB->succ_empty()) 1642 BB->removeSuccessor(BB->succ_begin()); 1643 BB->addSuccessor(copy0MBB); 1644 BB->addSuccessor(sinkMBB); 1645 1646 // copy0MBB: 1647 // %FalseValue = ... 1648 // # fallthrough to sinkMBB 1649 BB = copy0MBB; 1650 1651 // Update machine-CFG edges 1652 BB->addSuccessor(sinkMBB); 1653 1654 // sinkMBB: 1655 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1656 // ... 1657 BB = sinkMBB; 1658 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg()) 1659 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 1660 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 1661 1662 delete MI; // The pseudo instruction is gone now. 1663 return BB; 1664} 1665 1666SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, 1667 DAGCombinerInfo &DCI) const { 1668 TargetMachine &TM = getTargetMachine(); 1669 SelectionDAG &DAG = DCI.DAG; 1670 switch (N->getOpcode()) { 1671 default: break; 1672 case ISD::SINT_TO_FP: 1673 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) { 1674 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 1675 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 1676 // We allow the src/dst to be either f32/f64, but the intermediate 1677 // type must be i64. 1678 if (N->getOperand(0).getValueType() == MVT::i64) { 1679 SDOperand Val = N->getOperand(0).getOperand(0); 1680 if (Val.getValueType() == MVT::f32) { 1681 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 1682 DCI.AddToWorklist(Val.Val); 1683 } 1684 1685 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); 1686 DCI.AddToWorklist(Val.Val); 1687 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); 1688 DCI.AddToWorklist(Val.Val); 1689 if (N->getValueType(0) == MVT::f32) { 1690 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val); 1691 DCI.AddToWorklist(Val.Val); 1692 } 1693 return Val; 1694 } else if (N->getOperand(0).getValueType() == MVT::i32) { 1695 // If the intermediate type is i32, we can avoid the load/store here 1696 // too. 1697 } 1698 } 1699 } 1700 break; 1701 case ISD::STORE: 1702 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 1703 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 1704 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 1705 N->getOperand(1).getValueType() == MVT::i32) { 1706 SDOperand Val = N->getOperand(1).getOperand(0); 1707 if (Val.getValueType() == MVT::f32) { 1708 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 1709 DCI.AddToWorklist(Val.Val); 1710 } 1711 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); 1712 DCI.AddToWorklist(Val.Val); 1713 1714 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, 1715 N->getOperand(2), N->getOperand(3)); 1716 DCI.AddToWorklist(Val.Val); 1717 return Val; 1718 } 1719 break; 1720 case PPCISD::VCMP: { 1721 // If a VCMPo node already exists with exactly the same operands as this 1722 // node, use its result instead of this node (VCMPo computes both a CR6 and 1723 // a normal output). 1724 // 1725 if (!N->getOperand(0).hasOneUse() && 1726 !N->getOperand(1).hasOneUse() && 1727 !N->getOperand(2).hasOneUse()) { 1728 1729 // Scan all of the users of the LHS, looking for VCMPo's that match. 1730 SDNode *VCMPoNode = 0; 1731 1732 SDNode *LHSN = N->getOperand(0).Val; 1733 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 1734 UI != E; ++UI) 1735 if ((*UI)->getOpcode() == PPCISD::VCMPo && 1736 (*UI)->getOperand(1) == N->getOperand(1) && 1737 (*UI)->getOperand(2) == N->getOperand(2) && 1738 (*UI)->getOperand(0) == N->getOperand(0)) { 1739 VCMPoNode = *UI; 1740 break; 1741 } 1742 1743 // If there are non-zero uses of the flag value, use the VCMPo node! 1744 if (VCMPoNode && !VCMPoNode->hasNUsesOfValue(0, 1)) 1745 return SDOperand(VCMPoNode, 0); 1746 } 1747 break; 1748 } 1749 } 1750 1751 return SDOperand(); 1752} 1753 1754void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 1755 uint64_t Mask, 1756 uint64_t &KnownZero, 1757 uint64_t &KnownOne, 1758 unsigned Depth) const { 1759 KnownZero = 0; 1760 KnownOne = 0; 1761 switch (Op.getOpcode()) { 1762 default: break; 1763 case ISD::INTRINSIC_WO_CHAIN: { 1764 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) { 1765 default: break; 1766 case Intrinsic::ppc_altivec_vcmpbfp_p: 1767 case Intrinsic::ppc_altivec_vcmpeqfp_p: 1768 case Intrinsic::ppc_altivec_vcmpequb_p: 1769 case Intrinsic::ppc_altivec_vcmpequh_p: 1770 case Intrinsic::ppc_altivec_vcmpequw_p: 1771 case Intrinsic::ppc_altivec_vcmpgefp_p: 1772 case Intrinsic::ppc_altivec_vcmpgtfp_p: 1773 case Intrinsic::ppc_altivec_vcmpgtsb_p: 1774 case Intrinsic::ppc_altivec_vcmpgtsh_p: 1775 case Intrinsic::ppc_altivec_vcmpgtsw_p: 1776 case Intrinsic::ppc_altivec_vcmpgtub_p: 1777 case Intrinsic::ppc_altivec_vcmpgtuh_p: 1778 case Intrinsic::ppc_altivec_vcmpgtuw_p: 1779 KnownZero = ~1U; // All bits but the low one are known to be zero. 1780 break; 1781 } 1782 } 1783 } 1784} 1785 1786 1787/// getConstraintType - Given a constraint letter, return the type of 1788/// constraint it is for this target. 1789PPCTargetLowering::ConstraintType 1790PPCTargetLowering::getConstraintType(char ConstraintLetter) const { 1791 switch (ConstraintLetter) { 1792 default: break; 1793 case 'b': 1794 case 'r': 1795 case 'f': 1796 case 'v': 1797 case 'y': 1798 return C_RegisterClass; 1799 } 1800 return TargetLowering::getConstraintType(ConstraintLetter); 1801} 1802 1803 1804std::vector<unsigned> PPCTargetLowering:: 1805getRegClassForInlineAsmConstraint(const std::string &Constraint, 1806 MVT::ValueType VT) const { 1807 if (Constraint.size() == 1) { 1808 switch (Constraint[0]) { // GCC RS6000 Constraint Letters 1809 default: break; // Unknown constriant letter 1810 case 'b': 1811 return make_vector<unsigned>(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 , 1812 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 , 1813 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11, 1814 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 1815 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 1816 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 1817 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 1818 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 1819 0); 1820 case 'r': 1821 return make_vector<unsigned>(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 , 1822 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 , 1823 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11, 1824 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 1825 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 1826 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 1827 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 1828 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 1829 0); 1830 case 'f': 1831 return make_vector<unsigned>(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 , 1832 PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 , 1833 PPC::F8 , PPC::F9 , PPC::F10, PPC::F11, 1834 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 1835 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 1836 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 1837 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 1838 PPC::F28, PPC::F29, PPC::F30, PPC::F31, 1839 0); 1840 case 'v': 1841 return make_vector<unsigned>(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , 1842 PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 1843 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, 1844 PPC::V12, PPC::V13, PPC::V14, PPC::V15, 1845 PPC::V16, PPC::V17, PPC::V18, PPC::V19, 1846 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 1847 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 1848 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 1849 0); 1850 case 'y': 1851 return make_vector<unsigned>(PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, 1852 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 1853 0); 1854 } 1855 } 1856 1857 return std::vector<unsigned>(); 1858} 1859 1860// isOperandValidForConstraint 1861bool PPCTargetLowering:: 1862isOperandValidForConstraint(SDOperand Op, char Letter) { 1863 switch (Letter) { 1864 default: break; 1865 case 'I': 1866 case 'J': 1867 case 'K': 1868 case 'L': 1869 case 'M': 1870 case 'N': 1871 case 'O': 1872 case 'P': { 1873 if (!isa<ConstantSDNode>(Op)) return false; // Must be an immediate. 1874 unsigned Value = cast<ConstantSDNode>(Op)->getValue(); 1875 switch (Letter) { 1876 default: assert(0 && "Unknown constraint letter!"); 1877 case 'I': // "I" is a signed 16-bit constant. 1878 return (short)Value == (int)Value; 1879 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 1880 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 1881 return (short)Value == 0; 1882 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 1883 return (Value >> 16) == 0; 1884 case 'M': // "M" is a constant that is greater than 31. 1885 return Value > 31; 1886 case 'N': // "N" is a positive constant that is an exact power of two. 1887 return (int)Value > 0 && isPowerOf2_32(Value); 1888 case 'O': // "O" is the constant zero. 1889 return Value == 0; 1890 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 1891 return (short)-Value == (int)-Value; 1892 } 1893 break; 1894 } 1895 } 1896 1897 // Handle standard constraint letters. 1898 return TargetLowering::isOperandValidForConstraint(Op, Letter); 1899} 1900 1901/// isLegalAddressImmediate - Return true if the integer value can be used 1902/// as the offset of the target addressing mode. 1903bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const { 1904 // PPC allows a sign-extended 16-bit immediate field. 1905 return (V > -(1 << 16) && V < (1 << 16)-1); 1906} 1907