PPCISelLowering.h revision 1f873003266fbdec7c2c48a965c60f4e2e35a158
149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski// 349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski// The LLVM Compiler Infrastructure 449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski// 549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski// This file was developed by Chris Lattner and is distributed under 649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski// the University of Illinois Open Source License. See LICENSE.TXT for details. 749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski// 849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski//===----------------------------------------------------------------------===// 949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski// 1049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski// This file defines the interfaces that PPC uses to lower LLVM code into a 1149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski// selection DAG. 1249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski// 1349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski//===----------------------------------------------------------------------===// 1449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 1549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 160b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 170b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth 18d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/Target/TargetLowering.h" 1949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski#include "llvm/CodeGen/SelectionDAG.h" 2049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski#include "PPC.h" 21d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "PPCSubtarget.h" 2249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 2349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinskinamespace llvm { 2449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski namespace PPCISD { 2549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski enum NodeType { 2649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski // Start the numbering where the builtin ops and target ops leave off. 2749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END, 2849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 2949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// FSEL - Traditional three-operand fsel node. 3049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// 3149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski FSEL, 3249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 3349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// FCFID - The FCFID instruction, taking an f64 operand and producing 3449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// and f64 value containing the FP representation of the integer that 3549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// was temporarily in the f64 operand. 3649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski FCFID, 3749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 3849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 3949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// operand, producing an f64 value containing the integer representation 4049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// of that FP value. 4149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski FCTIDZ, FCTIWZ, 4249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 4349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// STFIWX - The STFIWX instruction. The first operand is an input token 4449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// chain, then an f64 value to store, then an address to store it to, 4549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// then a SRCVALUE for the address. 4649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski STFIWX, 4749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 4849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 4949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski // three v4f32 operands and producing a v4f32 result. 5049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski VMADDFP, VNMSUBFP, 5149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 5249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// VPERM - The PPC VPERM Instruction. 5349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// 5449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski VPERM, 5549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 5649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// Hi/Lo - These represent the high and low 16-bit parts of a global 5749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// address respectively. These nodes have two operands, the first of 5849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// which must be a TargetGlobalAddress, and the second of which must be a 5949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 6049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// though these are usually folded into other nodes. 6149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski Hi, Lo, 6249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 6349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 6449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 6549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// compute an allocation on the stack. 6649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski DYNALLOC, 6749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 6849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 6949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// at function entry, used for PIC code. 7049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski GlobalBaseReg, 7149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 7249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 7349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// shift amounts. These nodes are generated by the multi-precision shift 7449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// code. 7549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski SRL, SRA, SHL, 7649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 7749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit" 7849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// registers. 7949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski EXTSW_32, 8049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 81af878315192a9fa5b534364e327c24aeb8d73b5aBenjamin Kramer /// STD_32 - This is the STD instruction for use with "32-bit" registers. 82af878315192a9fa5b534364e327c24aeb8d73b5aBenjamin Kramer STD_32, 8349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 8449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// CALL - A direct function call. 8549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski CALL_Macho, CALL_ELF, 8649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 8749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 8849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// MTCTR instruction. 8949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski MTCTR, 9049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 9149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 9249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// BCTRL instruction. 9349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski BCTRL_Macho, BCTRL_ELF, 9449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 9549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// Return with a flag operand, matched by 'blr' 9649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski RET_FLAG, 9749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 9849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions. 9949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// This copies the bits corresponding to the specified CRREG into the 10049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// resultant GPR. Bits corresponding to other CR regs are undefined. 10149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski MFCR, 10249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 10349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 10449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// instructions. For lack of better number, we use the opcode number 10549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// encoding for the OPC field to identify the compare. For example, 838 10649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// is VCMPGTSH. 10749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski VCMP, 10849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 10949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 11049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// altivec VCMP*o instructions. For lack of better number, we use the 11149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// opcode number encoding for the OPC field to identify the compare. For 11249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// example, 838 is VCMPGTSH. 11349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski VCMPo, 11449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 11549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 11649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 11749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// condition register to branch on, OPC is the branch opcode to use (e.g. 11849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 11949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// an optional input flag argument. 12049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski COND_BRANCH, 12149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 12249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// CHAIN = STBRX CHAIN, GPRC, Ptr, SRCVALUE, Type - This is a 12349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 12449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// the GPRC input, then stores it through Ptr. Type can be either i16 or 12549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// i32. 12649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski STBRX, 12749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 12849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// GPRC, CHAIN = LBRX CHAIN, Ptr, SRCVALUE, Type - This is a 12949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 13049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 13149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// or i32. 13249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski LBRX, 13349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 13449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski // The following 5 instructions are used only as part of the 13549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski // long double-to-int conversion sequence. 13649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 13749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the 13849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// register. 13949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski MFFS, 14049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 14149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR. 14249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski MTFSB0, 14349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 14449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR. 14549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski MTFSB1, 14649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 14749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with 14849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// rounding towards zero. It has flags added so it won't move past the 14949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// FPSCR-setting instructions. 15049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski FADDRTZ, 15149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 15249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR. 15349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski MTFSF 15449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski }; 15549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski } 15649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 15749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// Define some predicates that are used for node matching. 15849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski namespace PPC { 15949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 16049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// VPKUHUM instruction. 16149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski bool isVPKUHUMShuffleMask(SDNode *N, bool isUnary); 16249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 16349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 16449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// VPKUWUM instruction. 16549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski bool isVPKUWUMShuffleMask(SDNode *N, bool isUnary); 16649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 16749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 16849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 16949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary); 17049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 17149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 17249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 17349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary); 17449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 17549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 17649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// amount, otherwise return -1. 17749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski int isVSLDOIShuffleMask(SDNode *N, bool isUnary); 17849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 17949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 18049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// specifies a splat of a single element that is suitable for input to 18149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// VSPLTB/VSPLTH/VSPLTW. 18249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski bool isSplatShuffleMask(SDNode *N, unsigned EltSize); 18349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 18449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// isAllNegativeZeroVector - Returns true if all elements of build_vector 18549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// are -0.0. 18649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski bool isAllNegativeZeroVector(SDNode *N); 18749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 18849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 18949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 19049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize); 19149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 19249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// get_VSPLTI_elt - If this is a build_vector of constants which can be 19349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// formed by using a vspltis[bhw] instruction of the specified element 19449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// size, return the constant being splatted. The ByteSize field indicates 19549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// the number of bytes of each element [124] -> [bhw]. 19649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski SDOperand get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 19749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski } 19849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 19949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski class PPCTargetLowering : public TargetLowering { 20049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski int VarArgsFrameIndex; // FrameIndex for start of varargs area. 20149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski int VarArgsStackOffset; // StackOffset for start of stack 20249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski // arguments. 20349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski unsigned VarArgsNumGPR; // Index of the first unused integer 20449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski // register for parameter passing. 20549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski unsigned VarArgsNumFPR; // Index of the first unused double 20649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski // register for parameter passing. 20749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski int ReturnAddrIndex; // FrameIndex for return slot. 20849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski const PPCSubtarget &PPCSubTarget; 20949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski public: 21049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski explicit PPCTargetLowering(PPCTargetMachine &TM); 21149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 21249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// getTargetNodeName() - This method returns the name of a target specific 21349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// DAG node. 21449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski virtual const char *getTargetNodeName(unsigned Opcode) const; 21549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 21649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// getPreIndexedAddressParts - returns true by value, base pointer and 21749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// offset pointer and addressing mode by reference if the node's address 21849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// can be legally represented as pre-indexed load / store address. 21949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 22049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski SDOperand &Offset, 22149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski ISD::MemIndexedMode &AM, 22249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski SelectionDAG &DAG); 22349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 22449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// SelectAddressRegReg - Given the specified addressed, check to see if it 22549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// can be represented as an indexed [r+r] operation. Returns false if it 22649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// can be more efficiently represented with [r+imm]. 22749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski bool SelectAddressRegReg(SDOperand N, SDOperand &Base, SDOperand &Index, 22849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski SelectionDAG &DAG); 22949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 23049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// SelectAddressRegImm - Returns true if the address N can be represented 23149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// by a base register plus a signed 16-bit displacement [r+imm], and if it 23249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// is not better represented as reg+reg. 23349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski bool SelectAddressRegImm(SDOperand N, SDOperand &Disp, SDOperand &Base, 23449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski SelectionDAG &DAG); 23549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 23649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 23749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// represented as an indexed [r+r] operation. 23849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski bool SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, SDOperand &Index, 23949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski SelectionDAG &DAG); 24049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 24149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// SelectAddressRegImmShift - Returns true if the address N can be 24249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// represented by a base register plus a signed 14-bit displacement 24349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// [r+imm*4]. Suitable for use by STD and friends. 24449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski bool SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base, 24549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski SelectionDAG &DAG); 24649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 24749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 24849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// LowerOperation - Provide custom lowering hooks for some operations. 24949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// 25049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 25149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 25249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG); 25349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 25449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 25549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 25649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 25749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski uint64_t Mask, 25849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski uint64_t &KnownZero, 25949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski uint64_t &KnownOne, 26049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski const SelectionDAG &DAG, 26149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski unsigned Depth = 0) const; 26249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 26349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 26449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski MachineBasicBlock *MBB); 26549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 26649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski ConstraintType getConstraintType(const std::string &Constraint) const; 26749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski std::pair<unsigned, const TargetRegisterClass*> 26849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski getRegForInlineAsmConstraint(const std::string &Constraint, 26949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski MVT::ValueType VT) const; 27049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 27149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 27249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// vector. If it is invalid, don't add anything to Ops. 27349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski virtual void LowerAsmOperandForConstraint(SDOperand Op, 27449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski char ConstraintLetter, 27549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski std::vector<SDOperand> &Ops, 27649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski SelectionDAG &DAG); 27749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 27849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// isLegalAddressingMode - Return true if the addressing mode represented 27949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// by AM is legal for this target, for a load/store of the specified type. 28049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 28149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 28249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// isLegalAddressImmediate - Return true if the integer value can be used 28349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// as the offset of the target addressing mode for load / store of the 28449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// given type. 28549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const; 28649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 28749683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// isLegalAddressImmediate - Return true if the GlobalValue can be used as 28849683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski /// the offset of the target addressing mode. 28949683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski virtual bool isLegalAddressImmediate(GlobalValue *GV) const; 29049683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 29149683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG); 29249683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski }; 29349683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski} 29449683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski 29549683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 29649683f3c961379fbc088871a5d6304950f1f1cbcJustin Holewinski