PPCISelLowering.h revision 61e729e2e9517ab2d8887bab86fb377900fa1081
130d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 230d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun// 330d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun// The LLVM Compiler Infrastructure 430d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun// 530d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun// This file was developed by Chris Lattner and is distributed under 630d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun// the University of Illinois Open Source License. See LICENSE.TXT for details. 730d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun// 830d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun//===----------------------------------------------------------------------===// 930d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun// 1030d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun// This file defines the interfaces that PPC uses to lower LLVM code into a 1130d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun// selection DAG. 1230d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun// 1330d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun//===----------------------------------------------------------------------===// 1430d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun 1530d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 1630d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 1730d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun 1830d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun#include "llvm/Target/TargetLowering.h" 1930d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun#include "llvm/CodeGen/SelectionDAG.h" 2030d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun#include "PPC.h" 2130d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun#include "PPCSubtarget.h" 2230d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun 2330d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurunnamespace llvm { 2430d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun namespace PPCISD { 2530d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun enum NodeType { 2630d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun // Start the numbering where the builtin ops and target ops leave off. 2730d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END, 2830d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun 2930d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// FSEL - Traditional three-operand fsel node. 3030d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// 3130d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun FSEL, 3230d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun 3330d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// FCFID - The FCFID instruction, taking an f64 operand and producing 3430d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// and f64 value containing the FP representation of the integer that 3530d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// was temporarily in the f64 operand. 3630d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun FCFID, 3730d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun 3830d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 3930d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// operand, producing an f64 value containing the integer representation 4030d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// of that FP value. 4130d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun FCTIDZ, FCTIWZ, 4230d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun 4330d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// STFIWX - The STFIWX instruction. The first operand is an input token 4430d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// chain, then an f64 value to store, then an address to store it to, 4530d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// then a SRCVALUE for the address. 4630d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun STFIWX, 4730d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun 4830d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 4930d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun // three v4f32 operands and producing a v4f32 result. 5030d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun VMADDFP, VNMSUBFP, 5130d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun 5230d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// VPERM - The PPC VPERM Instruction. 5330d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// 5430d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun VPERM, 5530d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun 5630d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// Hi/Lo - These represent the high and low 16-bit parts of a global 5730d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// address respectively. These nodes have two operands, the first of 5830d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// which must be a TargetGlobalAddress, and the second of which must be a 5930d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 6030d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// though these are usually folded into other nodes. 6130d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun Hi, Lo, 6230d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun 6330d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 6430d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 6530d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// compute an allocation on the stack. 6630d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun DYNALLOC, 6730d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun 6830d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 6930d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun /// at function entry, used for PIC code. 7030d4e1f3d81ad9f7a1aa14ce6d2ceb5df56c15cdSelim Gurun GlobalBaseReg, 71 72 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 73 /// shift amounts. These nodes are generated by the multi-precision shift 74 /// code. 75 SRL, SRA, SHL, 76 77 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit" 78 /// registers. 79 EXTSW_32, 80 81 /// STD_32 - This is the STD instruction for use with "32-bit" registers. 82 STD_32, 83 84 /// CALL - A direct function call. 85 CALL_Macho, CALL_ELF, 86 87 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 88 /// MTCTR instruction. 89 MTCTR, 90 91 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 92 /// BCTRL instruction. 93 BCTRL_Macho, BCTRL_ELF, 94 95 /// Return with a flag operand, matched by 'blr' 96 RET_FLAG, 97 98 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions. 99 /// This copies the bits corresponding to the specified CRREG into the 100 /// resultant GPR. Bits corresponding to other CR regs are undefined. 101 MFCR, 102 103 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 104 /// instructions. For lack of better number, we use the opcode number 105 /// encoding for the OPC field to identify the compare. For example, 838 106 /// is VCMPGTSH. 107 VCMP, 108 109 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 110 /// altivec VCMP*o instructions. For lack of better number, we use the 111 /// opcode number encoding for the OPC field to identify the compare. For 112 /// example, 838 is VCMPGTSH. 113 VCMPo, 114 115 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 116 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 117 /// condition register to branch on, OPC is the branch opcode to use (e.g. 118 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 119 /// an optional input flag argument. 120 COND_BRANCH, 121 122 /// CHAIN = STBRX CHAIN, GPRC, Ptr, SRCVALUE, Type - This is a 123 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 124 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 125 /// i32. 126 STBRX, 127 128 /// GPRC, CHAIN = LBRX CHAIN, Ptr, SRCVALUE, Type - This is a 129 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 130 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 131 /// or i32. 132 LBRX 133 }; 134 } 135 136 /// Define some predicates that are used for node matching. 137 namespace PPC { 138 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 139 /// VPKUHUM instruction. 140 bool isVPKUHUMShuffleMask(SDNode *N, bool isUnary); 141 142 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 143 /// VPKUWUM instruction. 144 bool isVPKUWUMShuffleMask(SDNode *N, bool isUnary); 145 146 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 147 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 148 bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary); 149 150 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 151 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 152 bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary); 153 154 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 155 /// amount, otherwise return -1. 156 int isVSLDOIShuffleMask(SDNode *N, bool isUnary); 157 158 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 159 /// specifies a splat of a single element that is suitable for input to 160 /// VSPLTB/VSPLTH/VSPLTW. 161 bool isSplatShuffleMask(SDNode *N, unsigned EltSize); 162 163 /// isAllNegativeZeroVector - Returns true if all elements of build_vector 164 /// are -0.0. 165 bool isAllNegativeZeroVector(SDNode *N); 166 167 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 168 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 169 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize); 170 171 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 172 /// formed by using a vspltis[bhw] instruction of the specified element 173 /// size, return the constant being splatted. The ByteSize field indicates 174 /// the number of bytes of each element [124] -> [bhw]. 175 SDOperand get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 176 } 177 178 class PPCTargetLowering : public TargetLowering { 179 int VarArgsFrameIndex; // FrameIndex for start of varargs area. 180 int VarArgsStackOffset; // StackOffset for start of stack 181 // arguments. 182 unsigned VarArgsNumGPR; // Index of the first unused integer 183 // register for parameter passing. 184 unsigned VarArgsNumFPR; // Index of the first unused double 185 // register for parameter passing. 186 int ReturnAddrIndex; // FrameIndex for return slot. 187 const PPCSubtarget &PPCSubTarget; 188 public: 189 explicit PPCTargetLowering(PPCTargetMachine &TM); 190 191 /// getTargetNodeName() - This method returns the name of a target specific 192 /// DAG node. 193 virtual const char *getTargetNodeName(unsigned Opcode) const; 194 195 /// getPreIndexedAddressParts - returns true by value, base pointer and 196 /// offset pointer and addressing mode by reference if the node's address 197 /// can be legally represented as pre-indexed load / store address. 198 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 199 SDOperand &Offset, 200 ISD::MemIndexedMode &AM, 201 SelectionDAG &DAG); 202 203 /// SelectAddressRegReg - Given the specified addressed, check to see if it 204 /// can be represented as an indexed [r+r] operation. Returns false if it 205 /// can be more efficiently represented with [r+imm]. 206 bool SelectAddressRegReg(SDOperand N, SDOperand &Base, SDOperand &Index, 207 SelectionDAG &DAG); 208 209 /// SelectAddressRegImm - Returns true if the address N can be represented 210 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 211 /// is not better represented as reg+reg. 212 bool SelectAddressRegImm(SDOperand N, SDOperand &Disp, SDOperand &Base, 213 SelectionDAG &DAG); 214 215 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 216 /// represented as an indexed [r+r] operation. 217 bool SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, SDOperand &Index, 218 SelectionDAG &DAG); 219 220 /// SelectAddressRegImmShift - Returns true if the address N can be 221 /// represented by a base register plus a signed 14-bit displacement 222 /// [r+imm*4]. Suitable for use by STD and friends. 223 bool SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base, 224 SelectionDAG &DAG); 225 226 227 /// LowerOperation - Provide custom lowering hooks for some operations. 228 /// 229 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 230 231 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 232 233 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 234 uint64_t Mask, 235 uint64_t &KnownZero, 236 uint64_t &KnownOne, 237 const SelectionDAG &DAG, 238 unsigned Depth = 0) const; 239 240 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 241 MachineBasicBlock *MBB); 242 243 ConstraintType getConstraintType(const std::string &Constraint) const; 244 std::pair<unsigned, const TargetRegisterClass*> 245 getRegForInlineAsmConstraint(const std::string &Constraint, 246 MVT::ValueType VT) const; 247 SDOperand isOperandValidForConstraint(SDOperand Op, char ConstraintLetter, 248 SelectionDAG &DAG); 249 250 /// isLegalAddressingMode - Return true if the addressing mode represented 251 /// by AM is legal for this target, for a load/store of the specified type. 252 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 253 254 /// isLegalAddressImmediate - Return true if the integer value can be used 255 /// as the offset of the target addressing mode for load / store of the 256 /// given type. 257 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const; 258 259 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as 260 /// the offset of the target addressing mode. 261 virtual bool isLegalAddressImmediate(GlobalValue *GV) const; 262 263 SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG); 264 }; 265} 266 267#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 268