PPCInstrInfo.cpp revision c909950c384e8234a7b3c5a76b7f79e3f7012ceb
131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===// 2b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 3f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// The LLVM Compiler Infrastructure 4f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 8f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 9f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 10f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// This file contains the PowerPC implementation of the TargetInstrInfo class. 11f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 12f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 13f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 1416e71f2f70811c69c56052dd146324fe20e31db5Chris Lattner#include "PPCInstrInfo.h" 1559ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng#include "PPC.h" 16f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson#include "PPCInstrBuilder.h" 177194aaf738a1b89441635340403f1c5b06ae18efBill Wendling#include "PPCMachineFunctionInfo.h" 18b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner#include "PPCTargetMachine.h" 192da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick#include "PPCHazardRecognizers.h" 2094b9550a32d189704a8eae55505edf62662c0534Evan Cheng#include "MCTargetDesc/PPCPredicates.h" 217a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen#include "llvm/CodeGen/MachineFrameInfo.h" 22f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#include "llvm/CodeGen/MachineInstrBuilder.h" 237a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen#include "llvm/CodeGen/MachineMemOperand.h" 24243296690ec78fc918762bd73896b09e26537f47Jakob Stoklund Olesen#include "llvm/CodeGen/MachineRegisterInfo.h" 254d989ac93ce608057fb6b13a4068264ab037ecd5Hal Finkel#include "llvm/CodeGen/PseudoSourceValue.h" 2659ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng#include "llvm/MC/MCAsmInfo.h" 27880d0f6018b6928bdcad291be60c801238619955Bill Wendling#include "llvm/Support/CommandLine.h" 28dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/ErrorHandling.h" 293e74d6fdd248e20a280f1dff3da9a6c689c2c4c3Evan Cheng#include "llvm/Support/TargetRegistry.h" 30dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/raw_ostream.h" 3159ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng#include "llvm/ADT/STLExtras.h" 32f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 334db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng#define GET_INSTRINFO_CTOR 3422fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng#include "PPCGenInstrInfo.inc" 3522fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 3682bcd236937b378e56e46bdde9c17a3ea3377068Dan Gohmannamespace llvm { 373fd0018af1b692cabfa5a002bf41f1e756aa9ddeHal Finkelextern cl::opt<bool> DisablePPC32RS; 383fd0018af1b692cabfa5a002bf41f1e756aa9ddeHal Finkelextern cl::opt<bool> DisablePPC64RS; 3982bcd236937b378e56e46bdde9c17a3ea3377068Dan Gohman} 4082bcd236937b378e56e46bdde9c17a3ea3377068Dan Gohman 4182bcd236937b378e56e46bdde9c17a3ea3377068Dan Gohmanusing namespace llvm; 42880d0f6018b6928bdcad291be60c801238619955Bill Wendling 43b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris LattnerPPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) 444db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 45d5b03f252c0db6b49a242abab63d7c5a260fceaeEvan Cheng TM(tm), RI(*TM.getSubtargetImpl(), *this) {} 46b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner 472da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for 482da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick/// this target when scheduling the DAG. 492da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer( 502da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const TargetMachine *TM, 512da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 52c6d08f10bf797cc78068ef30bd0e8812a5bdc9a2Hal Finkel unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective(); 534d989ac93ce608057fb6b13a4068264ab037ecd5Hal Finkel if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2) { 54768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel const InstrItineraryData *II = TM->getInstrItineraryData(); 555b00ceaeeabff8c25abb09926343c3fcb06053d8Hal Finkel return new PPCScoreboardHazardRecognizer(II, DAG); 56c6d08f10bf797cc78068ef30bd0e8812a5bdc9a2Hal Finkel } 5764c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel 5864c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG); 592da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick} 602da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 6164c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel/// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer 6264c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel/// to use for this target when scheduling the DAG. 6364c34e253563a8ba6b41fbce2bb020632cf65961Hal FinkelScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer( 6464c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel const InstrItineraryData *II, 6564c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel const ScheduleDAG *DAG) const { 6664c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective(); 6764c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel 6864c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel // Most subtargets use a PPC970 recognizer. 694d989ac93ce608057fb6b13a4068264ab037ecd5Hal Finkel if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2) { 7064c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel const TargetInstrInfo *TII = TM.getInstrInfo(); 7164c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel assert(TII && "No InstrInfo?"); 7264c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel 7364c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel return new PPCHazardRecognizer970(*TII); 7464c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel } 7564c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel 764d989ac93ce608057fb6b13a4068264ab037ecd5Hal Finkel return new PPCScoreboardHazardRecognizer(II, DAG); 7764c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel} 786e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trickunsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 799c09c9ec9dab61450800b42cbf746164aa076b88Chris Lattner int &FrameIndex) const { 80408396014742a05cad1c91949d2226169e3f9d80Chris Lattner switch (MI->getOpcode()) { 81408396014742a05cad1c91949d2226169e3f9d80Chris Lattner default: break; 82408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LD: 83408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LWZ: 84408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LFS: 85408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LFD: 86d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 87d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(2).isFI()) { 888aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FrameIndex = MI->getOperand(2).getIndex(); 89408396014742a05cad1c91949d2226169e3f9d80Chris Lattner return MI->getOperand(0).getReg(); 90408396014742a05cad1c91949d2226169e3f9d80Chris Lattner } 91408396014742a05cad1c91949d2226169e3f9d80Chris Lattner break; 92408396014742a05cad1c91949d2226169e3f9d80Chris Lattner } 93408396014742a05cad1c91949d2226169e3f9d80Chris Lattner return 0; 946524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner} 95408396014742a05cad1c91949d2226169e3f9d80Chris Lattner 966e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trickunsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 976524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner int &FrameIndex) const { 986524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner switch (MI->getOpcode()) { 996524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner default: break; 1003b478b31e297208ef2c9f74750a8a603eb3726fbNate Begeman case PPC::STD: 1016524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner case PPC::STW: 1026524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner case PPC::STFS: 1036524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner case PPC::STFD: 104d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 105d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(2).isFI()) { 1068aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FrameIndex = MI->getOperand(2).getIndex(); 1076524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner return MI->getOperand(0).getReg(); 1086524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner } 1096524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner break; 1106524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner } 1116524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner return 0; 1126524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner} 113408396014742a05cad1c91949d2226169e3f9d80Chris Lattner 114043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner// commuteInstruction - We can commute rlwimi instructions, but only if the 115043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner// rotate amt is zero. We also have to munge the immediates a bit. 11658dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan ChengMachineInstr * 11758dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan ChengPPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1188e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineFunction &MF = *MI->getParent()->getParent(); 1198e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman 120043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Normal instructions can be commuted the obvious way. 121043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner if (MI->getOpcode() != PPC::RLWIMI) 12258dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1236e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 124043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Cannot commute if it has a non-zero rotate count. 1259a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner if (MI->getOperand(3).getImm() != 0) 126043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner return 0; 1276e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 128043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // If we have a zero rotate count, we have: 129043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // M = mask(MB,ME) 130043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Op0 = (Op1 & ~M) | (Op2 & M) 131043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Change this to: 132043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // M = mask((ME+1)&31, (MB-1)&31) 133043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Op0 = (Op2 & ~M) | (Op1 & M) 134043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner 135043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Swap op1/op2 136a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng unsigned Reg0 = MI->getOperand(0).getReg(); 137043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner unsigned Reg1 = MI->getOperand(1).getReg(); 138043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner unsigned Reg2 = MI->getOperand(2).getReg(); 1396ce7dc2a97260eea5fba414332796464912b9359Evan Cheng bool Reg1IsKill = MI->getOperand(1).isKill(); 1406ce7dc2a97260eea5fba414332796464912b9359Evan Cheng bool Reg2IsKill = MI->getOperand(2).isKill(); 14158dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool ChangeReg0 = false; 142a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng // If machine instrs are no longer in two-address forms, update 143a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng // destination register as well. 144a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng if (Reg0 == Reg1) { 145a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng // Must be two address instruction! 146e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) && 147a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng "Expecting a two-address instruction!"); 148a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng Reg2IsKill = false; 14958dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng ChangeReg0 = true; 15058dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng } 15158dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 15258dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng // Masks. 15358dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng unsigned MB = MI->getOperand(4).getImm(); 15458dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng unsigned ME = MI->getOperand(5).getImm(); 15558dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 15658dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng if (NewMI) { 15758dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng // Create a new instruction. 15858dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); 15958dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool Reg0IsDead = MI->getOperand(0).isDead(); 160d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 161587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 162587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(Reg2, getKillRegState(Reg2IsKill)) 163587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(Reg1, getKillRegState(Reg1IsKill)) 16458dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng .addImm((ME+1) & 31) 16558dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng .addImm((MB-1) & 31); 166a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng } 16758dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 16858dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng if (ChangeReg0) 16958dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng MI->getOperand(0).setReg(Reg2); 170e53f4a055f74bded20d6129b4724ddd17fd199f6Chris Lattner MI->getOperand(2).setReg(Reg1); 171e53f4a055f74bded20d6129b4724ddd17fd199f6Chris Lattner MI->getOperand(1).setReg(Reg2); 172f73823000e2d5d6e1cf65bdf5a107297e18d35fbChris Lattner MI->getOperand(2).setIsKill(Reg1IsKill); 173f73823000e2d5d6e1cf65bdf5a107297e18d35fbChris Lattner MI->getOperand(1).setIsKill(Reg2IsKill); 1746e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 175043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Swap the mask around. 1769a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner MI->getOperand(4).setImm((ME+1) & 31); 1779a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner MI->getOperand(5).setImm((MB-1) & 31); 178043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner return MI; 179043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner} 180bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner 1816e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trickvoid PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 182bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner MachineBasicBlock::iterator MI) const { 183c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 184d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, MI, DL, get(PPC::NOP)); 185bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner} 186c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 187c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 188c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner// Branch analysis. 189c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattnerbool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 190c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineBasicBlock *&FBB, 191dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng SmallVectorImpl<MachineOperand> &Cond, 192dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng bool AllowModify) const { 193c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // If the block has no terminators, it just falls into the block after it. 194c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineBasicBlock::iterator I = MBB.end(); 19593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 19693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 19793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 19893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 19993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 20093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 20193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 20293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 20393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (!isUnpredicatedTerminator(I)) 204c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return false; 205c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 206c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Get the last instruction in the block. 207c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineInstr *LastInst = I; 2086e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 209c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // If there is only one terminator instruction, process it. 210bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 211c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner if (LastInst->getOpcode() == PPC::B) { 21282ae933e55839713ea039e7c6353483b14dc5724Evan Cheng if (!LastInst->getOperand(0).isMBB()) 21382ae933e55839713ea039e7c6353483b14dc5724Evan Cheng return true; 2148aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = LastInst->getOperand(0).getMBB(); 215c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return false; 216289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner } else if (LastInst->getOpcode() == PPC::BCC) { 21782ae933e55839713ea039e7c6353483b14dc5724Evan Cheng if (!LastInst->getOperand(2).isMBB()) 21882ae933e55839713ea039e7c6353483b14dc5724Evan Cheng return true; 219c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Block ends with fall-through condbranch. 2208aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = LastInst->getOperand(2).getMBB(); 221c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(LastInst->getOperand(0)); 222c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(LastInst->getOperand(1)); 2237c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner return false; 224c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner } 225c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Otherwise, don't know what this is. 226c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return true; 227c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner } 2286e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 229c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Get the instruction before it if it's a terminator. 230c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineInstr *SecondLastInst = I; 231c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 232c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // If there are three terminators, we don't know what sort of block this is. 233c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner if (SecondLastInst && I != MBB.begin() && 234bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng isUnpredicatedTerminator(--I)) 235c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return true; 2366e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 237289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner // If the block ends with PPC::B and PPC:BCC, handle it. 2386e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick if (SecondLastInst->getOpcode() == PPC::BCC && 239c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner LastInst->getOpcode() == PPC::B) { 24082ae933e55839713ea039e7c6353483b14dc5724Evan Cheng if (!SecondLastInst->getOperand(2).isMBB() || 24182ae933e55839713ea039e7c6353483b14dc5724Evan Cheng !LastInst->getOperand(0).isMBB()) 24282ae933e55839713ea039e7c6353483b14dc5724Evan Cheng return true; 2438aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = SecondLastInst->getOperand(2).getMBB(); 244c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(SecondLastInst->getOperand(0)); 245c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(SecondLastInst->getOperand(1)); 2468aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FBB = LastInst->getOperand(0).getMBB(); 247c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return false; 248c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner } 2496e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 25013e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen // If the block ends with two PPC:Bs, handle it. The second one is not 25113e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen // executed, so remove it. 2526e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick if (SecondLastInst->getOpcode() == PPC::B && 25313e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen LastInst->getOpcode() == PPC::B) { 25482ae933e55839713ea039e7c6353483b14dc5724Evan Cheng if (!SecondLastInst->getOperand(0).isMBB()) 25582ae933e55839713ea039e7c6353483b14dc5724Evan Cheng return true; 2568aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = SecondLastInst->getOperand(0).getMBB(); 25713e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen I = LastInst; 258dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng if (AllowModify) 259dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng I->eraseFromParent(); 26013e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen return false; 26113e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen } 26213e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen 263c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Otherwise, can't handle this. 264c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return true; 265c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 266c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 267b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Chengunsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 268c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineBasicBlock::iterator I = MBB.end(); 269b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng if (I == MBB.begin()) return 0; 270c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner --I; 27193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 27293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 27393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 27493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 27593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 276289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC) 277b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 2786e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 279c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Remove the branch. 280c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner I->eraseFromParent(); 2816e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 282c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner I = MBB.end(); 283c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 284b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng if (I == MBB.begin()) return 1; 285c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner --I; 286289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner if (I->getOpcode() != PPC::BCC) 287b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 1; 2886e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 289c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Remove the branch. 290c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner I->eraseFromParent(); 291b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 2; 292c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 293c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 294b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Chengunsigned 295b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan ChengPPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 296b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng MachineBasicBlock *FBB, 2973bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 2983bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 2992dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner // Shouldn't be a fall through. 3002dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 3016e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick assert((Cond.size() == 2 || Cond.size() == 0) && 30254108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner "PPC branch conditions have two components!"); 3036e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 30454108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner // One-way branch. 3052dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner if (FBB == 0) { 30654108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner if (Cond.empty()) // Unconditional branch 3073bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); 30854108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner else // Conditional branch 3093bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(PPC::BCC)) 31018258c640466274c26e89016e361ec411ff78520Chris Lattner .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 311b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 1; 3122dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner } 3136e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 314879d09cf130f3760a08865913c04d9ff328fad5fChris Lattner // Two-way Conditional Branch. 3153bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(PPC::BCC)) 31618258c640466274c26e89016e361ec411ff78520Chris Lattner .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 3173bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); 318b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 2; 319c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 320c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 32127689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesenvoid PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 32227689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 32327689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 32427689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen bool KillSrc) const { 32527689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen unsigned Opc; 32627689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) 32727689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen Opc = PPC::OR; 32827689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) 32927689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen Opc = PPC::OR8; 33027689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) 33127689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen Opc = PPC::FMR; 33227689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) 33327689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen Opc = PPC::MCRF; 33427689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) 33527689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen Opc = PPC::VOR; 33627689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) 33727689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen Opc = PPC::CROR; 33827689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen else 33927689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen llvm_unreachable("Impossible reg-to-reg copy"); 340d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 341e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = get(Opc); 342e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (MCID.getNumOperands() == 3) 343e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng BuildMI(MBB, I, DL, MCID, DestReg) 34427689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); 34527689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen else 346e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); 347d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson} 348d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 3493fd0018af1b692cabfa5a002bf41f1e756aa9ddeHal Finkel// This function returns true if a CR spill is necessary and false otherwise. 3504a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendlingbool 3518e5f2c6f65841542e2a7092553fe42a00048e4c7Dan GohmanPPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, 3528e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman unsigned SrcReg, bool isKill, 3534a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling int FrameIdx, 3544a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling const TargetRegisterClass *RC, 3554a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling SmallVectorImpl<MachineInstr*> &NewMIs) const{ 356c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 357c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper if (PPC::GPRCRegClass.hasSubClassEq(RC)) { 358f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (SrcReg != PPC::LR) { 35921b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 360587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SrcReg, 361587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling getKillRegState(isKill)), 3624a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling FrameIdx)); 363f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 364f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: this spills LR immediately to memory in one step. To do this, 365f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // we use R11, which we know cannot be used in the prolog/epilog. This is 366f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // a hack. 36721b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); 36821b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 369587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(PPC::R11, 370587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling getKillRegState(isKill)), 3714a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling FrameIdx)); 372f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 373c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) { 374f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (SrcReg != PPC::LR8) { 37521b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 376587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SrcReg, 377587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling getKillRegState(isKill)), 378587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling FrameIdx)); 379f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 380f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: this spills LR immediately to memory in one step. To do this, 3817ad6b7d35978e1bb89de90aa732cf2f57377d69dHal Finkel // we use X11, which we know cannot be used in the prolog/epilog. This is 382f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // a hack. 38321b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11)); 38421b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 385587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(PPC::X11, 386587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling getKillRegState(isKill)), 387587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling FrameIdx)); 388f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 389c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { 39021b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) 391587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SrcReg, 392587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling getKillRegState(isKill)), 393587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling FrameIdx)); 394c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { 39521b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) 396587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SrcReg, 397587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling getKillRegState(isKill)), 398587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling FrameIdx)); 399c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { 4003fd0018af1b692cabfa5a002bf41f1e756aa9ddeHal Finkel if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || 4013fd0018af1b692cabfa5a002bf41f1e756aa9ddeHal Finkel (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { 40221b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) 403587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SrcReg, 404587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling getKillRegState(isKill)), 40571a2cb25ebc818383dd0f80475bc166f834e8d99Chris Lattner FrameIdx)); 4067194aaf738a1b89441635340403f1c5b06ae18efBill Wendling return true; 4077194aaf738a1b89441635340403f1c5b06ae18efBill Wendling } else { 408c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // FIXME: We need a scatch reg here. The trouble with using R0 is that 409c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // it's possible for the stack frame to be so big the save location is 410c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // out of range of immediate offsets, necessitating another register. 411c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // We hack this on Darwin by reserving R2. It's probably broken on Linux 412c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // at the moment. 413c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen 414234bb38d6c421ea22229087a9835afe99e531276Hal Finkel bool is64Bit = TM.getSubtargetImpl()->isPPC64(); 415c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // We need to store the CR in the low 4-bits of the saved value. First, 416c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // issue a MFCR to save all of the CRBits. 4176e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? 418234bb38d6c421ea22229087a9835afe99e531276Hal Finkel (is64Bit ? PPC::X2 : PPC::R2) : 419234bb38d6c421ea22229087a9835afe99e531276Hal Finkel (is64Bit ? PPC::X0 : PPC::R0); 420234bb38d6c421ea22229087a9835afe99e531276Hal Finkel NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::MFCR8pseud : 421234bb38d6c421ea22229087a9835afe99e531276Hal Finkel PPC::MFCRpseud), ScratchReg) 4225f07d5224ddc32f405d7e19de8e58e91ab2816bcDale Johannesen .addReg(SrcReg, getKillRegState(isKill))); 4236e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 4247194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // If the saved register wasn't CR0, shift the bits left so that they are 4257194aaf738a1b89441635340403f1c5b06ae18efBill Wendling // in CR0's slot. 4267194aaf738a1b89441635340403f1c5b06ae18efBill Wendling if (SrcReg != PPC::CR0) { 427966aeb5788c242cfaca35c56c0ddc0ff778d4376Evan Cheng unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4; 428c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen // rlwinm scratch, scratch, ShiftBits, 0, 31. 429234bb38d6c421ea22229087a9835afe99e531276Hal Finkel NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::RLWINM8 : 430234bb38d6c421ea22229087a9835afe99e531276Hal Finkel PPC::RLWINM), ScratchReg) 431c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen .addReg(ScratchReg).addImm(ShiftBits) 432c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen .addImm(0).addImm(31)); 4337194aaf738a1b89441635340403f1c5b06ae18efBill Wendling } 4346e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 435234bb38d6c421ea22229087a9835afe99e531276Hal Finkel NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(is64Bit ? 436234bb38d6c421ea22229087a9835afe99e531276Hal Finkel PPC::STW8 : PPC::STW)) 437c12da8d30a1394847ee4608fcd54daa24b889b37Dale Johannesen .addReg(ScratchReg, 438587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling getKillRegState(isKill)), 4397194aaf738a1b89441635340403f1c5b06ae18efBill Wendling FrameIdx)); 4407194aaf738a1b89441635340403f1c5b06ae18efBill Wendling } 441c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { 4420404cd97e4f6ebfe4f8057d4e21119d77654dff2Nicolas Geoffray // FIXME: We use CRi here because there is no mtcrf on a bit. Since the 4430404cd97e4f6ebfe4f8057d4e21119d77654dff2Nicolas Geoffray // backend currently only uses CR1EQ as an individual bit, this should 4440404cd97e4f6ebfe4f8057d4e21119d77654dff2Nicolas Geoffray // not cause any bug. If we need other uses of CR bits, the following 4450404cd97e4f6ebfe4f8057d4e21119d77654dff2Nicolas Geoffray // code may be invalid. 4469348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray unsigned Reg = 0; 4476a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 4486a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 4499348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR0; 4506a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 4516a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 4529348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR1; 4536a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 4546a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 4559348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR2; 4566a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 4576a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 4589348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR3; 4596a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 4606a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 4619348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR4; 4626a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 4636a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 4649348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR5; 4656a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 4666a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 4679348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR6; 4686a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 4696a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 4709348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR7; 4719348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray 4726e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx, 473c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper &PPC::CRRCRegClass, NewMIs); 4749348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray 475c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { 476f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // We don't have indexed addressing for vector loads. Emit: 477f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // R0 = ADDI FI# 478f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // STVX VAL, 0, R0 4796e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick // 480f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: We use R0 here, because it isn't available for RA. 48121b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 482f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx, 0, 0)); 48321b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX)) 484587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SrcReg, getKillRegState(isKill)) 485587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(PPC::R0) 486587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(PPC::R0)); 487f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 488c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown regclass!"); 489f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 4907194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 4917194aaf738a1b89441635340403f1c5b06ae18efBill Wendling return false; 492f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 493f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 494f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid 495f6372aa1cc568df19da7c5023e83c75aa9404a07Owen AndersonPPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 4967194aaf738a1b89441635340403f1c5b06ae18efBill Wendling MachineBasicBlock::iterator MI, 4977194aaf738a1b89441635340403f1c5b06ae18efBill Wendling unsigned SrcReg, bool isKill, int FrameIdx, 498746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 499746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 5008e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineFunction &MF = *MBB.getParent(); 501f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVector<MachineInstr*, 4> NewMIs; 5027194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 5038e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) { 5048e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 5057194aaf738a1b89441635340403f1c5b06ae18efBill Wendling FuncInfo->setSpillsCR(); 5067194aaf738a1b89441635340403f1c5b06ae18efBill Wendling } 5077194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 508f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 509f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MBB.insert(MI, NewMIs[i]); 5107a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen 5117a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen const MachineFrameInfo &MFI = *MF.getFrameInfo(); 5127a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen MachineMemOperand *MMO = 513978e0dfe46e481bfb1281e683aa308329e879e95Jay Foad MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 51459db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOStore, 5157a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen MFI.getObjectSize(FrameIdx), 5167a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen MFI.getObjectAlignment(FrameIdx)); 5177a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen NewMIs.back()->addMemOperand(MF, MMO); 518f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 519f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 520d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkelbool 521d1c321a89ab999b9bb602b0f398ecd4c2022262cBill WendlingPPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 5228e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman unsigned DestReg, int FrameIdx, 5234a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling const TargetRegisterClass *RC, 5244a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling SmallVectorImpl<MachineInstr*> &NewMIs)const{ 525c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper if (PPC::GPRCRegClass.hasSubClassEq(RC)) { 526f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (DestReg != PPC::LR) { 527d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 528d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling DestReg), FrameIdx)); 529f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 530d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 531d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling PPC::R11), FrameIdx)); 532d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11)); 533f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 534c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) { 535f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (DestReg != PPC::LR8) { 536d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg), 537f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 538f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 539d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), 5407ad6b7d35978e1bb89de90aa732cf2f57377d69dHal Finkel PPC::X11), FrameIdx)); 5417ad6b7d35978e1bb89de90aa732cf2f57377d69dHal Finkel NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::X11)); 542f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 543c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { 544d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg), 545f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 546c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { 547d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg), 548f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 549c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { 550d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || 551d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { 552d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel NewMIs.push_back(addFrameReference(BuildMI(MF, DL, 553d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel get(PPC::RESTORE_CR), DestReg) 554d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel , FrameIdx)); 555d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel return true; 556d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel } else { 557d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // FIXME: We need a scatch reg here. The trouble with using R0 is that 558d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // it's possible for the stack frame to be so big the save location is 559d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // out of range of immediate offsets, necessitating another register. 560d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // We hack this on Darwin by reserving R2. It's probably broken on Linux 561d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // at the moment. 562d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? 563d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel PPC::R2 : PPC::R0; 564d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 565d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel ScratchReg), FrameIdx)); 566d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel 567d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // If the reloaded register isn't CR0, shift the bits right so that they are 568d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // in the right CR's slot. 569d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel if (DestReg != PPC::CR0) { 570d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; 571d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel // rlwinm r11, r11, 32-ShiftBits, 0, 31. 572d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) 573d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0) 574d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel .addImm(31)); 575d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel } 576d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel 577234bb38d6c421ea22229087a9835afe99e531276Hal Finkel NewMIs.push_back(BuildMI(MF, DL, get(TM.getSubtargetImpl()->isPPC64() ? 578234bb38d6c421ea22229087a9835afe99e531276Hal Finkel PPC::MTCRF8 : PPC::MTCRF), DestReg) 579d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel .addReg(ScratchReg)); 580f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 581c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { 5826e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 5839348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray unsigned Reg = 0; 5846a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT || 5856a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN) 5869348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR0; 5876a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT || 5886a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN) 5899348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR1; 5906a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT || 5916a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN) 5929348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR2; 5936a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT || 5946a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN) 5959348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR3; 5966a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT || 5976a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN) 5989348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR4; 5996a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT || 6006a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN) 6019348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR5; 6026a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT || 6036a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN) 6049348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR6; 6056a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT || 6066a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN) 6079348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR7; 6089348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray 6096e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx, 610c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper &PPC::CRRCRegClass, NewMIs); 6119348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray 612c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { 613f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // We don't have indexed addressing for vector loads. Emit: 614f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // R0 = ADDI FI# 615f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // Dest = LVX 0, R0 6166e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick // 617f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // FIXME: We use R0 here, because it isn't available for RA. 618d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 619f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx, 0, 0)); 620d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0) 621f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(PPC::R0)); 622f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 623c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown regclass!"); 624f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 625d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel 626d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel return false; 627f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 628f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 629f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid 630f6372aa1cc568df19da7c5023e83c75aa9404a07Owen AndersonPPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 6317194aaf738a1b89441635340403f1c5b06ae18efBill Wendling MachineBasicBlock::iterator MI, 6327194aaf738a1b89441635340403f1c5b06ae18efBill Wendling unsigned DestReg, int FrameIdx, 633746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 634746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 6358e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineFunction &MF = *MBB.getParent(); 636f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVector<MachineInstr*, 4> NewMIs; 637c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 638d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling if (MI != MBB.end()) DL = MI->getDebugLoc(); 639d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs)) { 640d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 641d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel FuncInfo->setSpillsCR(); 642d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel } 643f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 644f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MBB.insert(MI, NewMIs[i]); 6457a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen 6467a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen const MachineFrameInfo &MFI = *MF.getFrameInfo(); 6477a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen MachineMemOperand *MMO = 648978e0dfe46e481bfb1281e683aa308329e879e95Jay Foad MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 64959db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOLoad, 6507a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen MFI.getObjectSize(FrameIdx), 6517a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen MFI.getObjectAlignment(FrameIdx)); 6527a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen NewMIs.back()->addMemOperand(MF, MMO); 653f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 654f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 6550965217e74fe07f1451350a80114ab566ced5de0Evan ChengMachineInstr* 6560965217e74fe07f1451350a80114ab566ced5de0Evan ChengPPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 6578601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 6580965217e74fe07f1451350a80114ab566ced5de0Evan Cheng const MDNode *MDPtr, 6590965217e74fe07f1451350a80114ab566ced5de0Evan Cheng DebugLoc DL) const { 6600965217e74fe07f1451350a80114ab566ced5de0Evan Cheng MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE)); 6610965217e74fe07f1451350a80114ab566ced5de0Evan Cheng addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr); 6620965217e74fe07f1451350a80114ab566ced5de0Evan Cheng return &*MIB; 6630965217e74fe07f1451350a80114ab566ced5de0Evan Cheng} 6640965217e74fe07f1451350a80114ab566ced5de0Evan Cheng 665c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattnerbool PPCInstrInfo:: 66644eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen AndersonReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 6677c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); 6687c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner // Leave the CR# the same, but invert the condition. 66918258c640466274c26e89016e361ec411ff78520Chris Lattner Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); 6707c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner return false; 671c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 67252e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray 67352e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray/// GetInstSize - Return the number of bytes of code the specified 67452e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray/// instruction may be. This returns the maximum number of bytes. 67552e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray/// 67652e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffrayunsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 67752e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray switch (MI->getOpcode()) { 67852e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray case PPC::INLINEASM: { // Inline Asm: Variable size. 67952e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray const MachineFunction *MF = MI->getParent()->getParent(); 68052e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray const char *AsmStr = MI->getOperand(0).getSymbolName(); 681af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); 68252e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray } 6837431beaba2a01c3fe299c861b2ec85cbf1dc81c4Bill Wendling case PPC::PROLOG_LABEL: 6844406604047423576e36657c7ede266ca42e79642Dan Gohman case PPC::EH_LABEL: 6854406604047423576e36657c7ede266ca42e79642Dan Gohman case PPC::GC_LABEL: 686375be7730a6f3dee7a6dc319ee6c355a11ac99adDale Johannesen case PPC::DBG_VALUE: 68752e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray return 0; 6885b00ceaeeabff8c25abb09926343c3fcb06053d8Hal Finkel case PPC::BL8_NOP_ELF: 6895b00ceaeeabff8c25abb09926343c3fcb06053d8Hal Finkel case PPC::BLA8_NOP_ELF: 6905b00ceaeeabff8c25abb09926343c3fcb06053d8Hal Finkel return 8; 69152e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray default: 69252e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray return 4; // PowerPC instructions are all 4 bytes 69352e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray } 69452e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray} 695