PPCInstrInfo.cpp revision d10fd9791c20fd8368fa0ce94b626b769c6c8ba0 
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPCPredicates.h"
16#include "PPCGenInstrInfo.inc"
17#include "PPCTargetMachine.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20using namespace llvm;
21
22PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
23  : TargetInstrInfo(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
24    RI(*TM.getSubtargetImpl(), *this) {}
25
26/// getPointerRegClass - Return the register class to use to hold pointers.
27/// This is used for addressing modes.
28const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
29  if (TM.getSubtargetImpl()->isPPC64())
30    return &PPC::G8RCRegClass;
31  else
32    return &PPC::GPRCRegClass;
33}
34
35
36bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
37                               unsigned& sourceReg,
38                               unsigned& destReg) const {
39  MachineOpCode oc = MI.getOpcode();
40  if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
41      oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
42    assert(MI.getNumOperands() >= 3 &&
43           MI.getOperand(0).isRegister() &&
44           MI.getOperand(1).isRegister() &&
45           MI.getOperand(2).isRegister() &&
46           "invalid PPC OR instruction!");
47    if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
48      sourceReg = MI.getOperand(1).getReg();
49      destReg = MI.getOperand(0).getReg();
50      return true;
51    }
52  } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
53    assert(MI.getNumOperands() >= 3 &&
54           MI.getOperand(0).isRegister() &&
55           MI.getOperand(2).isImmediate() &&
56           "invalid PPC ADDI instruction!");
57    if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImm() == 0) {
58      sourceReg = MI.getOperand(1).getReg();
59      destReg = MI.getOperand(0).getReg();
60      return true;
61    }
62  } else if (oc == PPC::ORI) {             // ori r1, r2, 0
63    assert(MI.getNumOperands() >= 3 &&
64           MI.getOperand(0).isRegister() &&
65           MI.getOperand(1).isRegister() &&
66           MI.getOperand(2).isImmediate() &&
67           "invalid PPC ORI instruction!");
68    if (MI.getOperand(2).getImm() == 0) {
69      sourceReg = MI.getOperand(1).getReg();
70      destReg = MI.getOperand(0).getReg();
71      return true;
72    }
73  } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
74             oc == PPC::FMRSD) {      // fmr r1, r2
75    assert(MI.getNumOperands() >= 2 &&
76           MI.getOperand(0).isRegister() &&
77           MI.getOperand(1).isRegister() &&
78           "invalid PPC FMR instruction");
79    sourceReg = MI.getOperand(1).getReg();
80    destReg = MI.getOperand(0).getReg();
81    return true;
82  } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
83    assert(MI.getNumOperands() >= 2 &&
84           MI.getOperand(0).isRegister() &&
85           MI.getOperand(1).isRegister() &&
86           "invalid PPC MCRF instruction");
87    sourceReg = MI.getOperand(1).getReg();
88    destReg = MI.getOperand(0).getReg();
89    return true;
90  }
91  return false;
92}
93
94unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
95                                           int &FrameIndex) const {
96  switch (MI->getOpcode()) {
97  default: break;
98  case PPC::LD:
99  case PPC::LWZ:
100  case PPC::LFS:
101  case PPC::LFD:
102    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
103        MI->getOperand(2).isFI()) {
104      FrameIndex = MI->getOperand(2).getIndex();
105      return MI->getOperand(0).getReg();
106    }
107    break;
108  }
109  return 0;
110}
111
112unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
113                                          int &FrameIndex) const {
114  switch (MI->getOpcode()) {
115  default: break;
116  case PPC::STD:
117  case PPC::STW:
118  case PPC::STFS:
119  case PPC::STFD:
120    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
121        MI->getOperand(2).isFI()) {
122      FrameIndex = MI->getOperand(2).getIndex();
123      return MI->getOperand(0).getReg();
124    }
125    break;
126  }
127  return 0;
128}
129
130// commuteInstruction - We can commute rlwimi instructions, but only if the
131// rotate amt is zero.  We also have to munge the immediates a bit.
132MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
133  // Normal instructions can be commuted the obvious way.
134  if (MI->getOpcode() != PPC::RLWIMI)
135    return TargetInstrInfo::commuteInstruction(MI);
136
137  // Cannot commute if it has a non-zero rotate count.
138  if (MI->getOperand(3).getImm() != 0)
139    return 0;
140
141  // If we have a zero rotate count, we have:
142  //   M = mask(MB,ME)
143  //   Op0 = (Op1 & ~M) | (Op2 & M)
144  // Change this to:
145  //   M = mask((ME+1)&31, (MB-1)&31)
146  //   Op0 = (Op2 & ~M) | (Op1 & M)
147
148  // Swap op1/op2
149  unsigned Reg1 = MI->getOperand(1).getReg();
150  unsigned Reg2 = MI->getOperand(2).getReg();
151  bool Reg1IsKill = MI->getOperand(1).isKill();
152  bool Reg2IsKill = MI->getOperand(2).isKill();
153  MI->getOperand(2).setReg(Reg1);
154  MI->getOperand(1).setReg(Reg2);
155  MI->getOperand(2).setIsKill(Reg1IsKill);
156  MI->getOperand(1).setIsKill(Reg2IsKill);
157
158  // Swap the mask around.
159  unsigned MB = MI->getOperand(4).getImm();
160  unsigned ME = MI->getOperand(5).getImm();
161  MI->getOperand(4).setImm((ME+1) & 31);
162  MI->getOperand(5).setImm((MB-1) & 31);
163  return MI;
164}
165
166void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
167                              MachineBasicBlock::iterator MI) const {
168  BuildMI(MBB, MI, get(PPC::NOP));
169}
170
171
172// Branch analysis.
173bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
174                                 MachineBasicBlock *&FBB,
175                                 std::vector<MachineOperand> &Cond) const {
176  // If the block has no terminators, it just falls into the block after it.
177  MachineBasicBlock::iterator I = MBB.end();
178  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
179    return false;
180
181  // Get the last instruction in the block.
182  MachineInstr *LastInst = I;
183
184  // If there is only one terminator instruction, process it.
185  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
186    if (LastInst->getOpcode() == PPC::B) {
187      TBB = LastInst->getOperand(0).getMBB();
188      return false;
189    } else if (LastInst->getOpcode() == PPC::BCC) {
190      // Block ends with fall-through condbranch.
191      TBB = LastInst->getOperand(2).getMBB();
192      Cond.push_back(LastInst->getOperand(0));
193      Cond.push_back(LastInst->getOperand(1));
194      return false;
195    }
196    // Otherwise, don't know what this is.
197    return true;
198  }
199
200  // Get the instruction before it if it's a terminator.
201  MachineInstr *SecondLastInst = I;
202
203  // If there are three terminators, we don't know what sort of block this is.
204  if (SecondLastInst && I != MBB.begin() &&
205      isUnpredicatedTerminator(--I))
206    return true;
207
208  // If the block ends with PPC::B and PPC:BCC, handle it.
209  if (SecondLastInst->getOpcode() == PPC::BCC &&
210      LastInst->getOpcode() == PPC::B) {
211    TBB =  SecondLastInst->getOperand(2).getMBB();
212    Cond.push_back(SecondLastInst->getOperand(0));
213    Cond.push_back(SecondLastInst->getOperand(1));
214    FBB = LastInst->getOperand(0).getMBB();
215    return false;
216  }
217
218  // If the block ends with two PPC:Bs, handle it.  The second one is not
219  // executed, so remove it.
220  if (SecondLastInst->getOpcode() == PPC::B &&
221      LastInst->getOpcode() == PPC::B) {
222    TBB = SecondLastInst->getOperand(0).getMBB();
223    I = LastInst;
224    I->eraseFromParent();
225    return false;
226  }
227
228  // Otherwise, can't handle this.
229  return true;
230}
231
232unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
233  MachineBasicBlock::iterator I = MBB.end();
234  if (I == MBB.begin()) return 0;
235  --I;
236  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
237    return 0;
238
239  // Remove the branch.
240  I->eraseFromParent();
241
242  I = MBB.end();
243
244  if (I == MBB.begin()) return 1;
245  --I;
246  if (I->getOpcode() != PPC::BCC)
247    return 1;
248
249  // Remove the branch.
250  I->eraseFromParent();
251  return 2;
252}
253
254unsigned
255PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
256                           MachineBasicBlock *FBB,
257                           const std::vector<MachineOperand> &Cond) const {
258  // Shouldn't be a fall through.
259  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
260  assert((Cond.size() == 2 || Cond.size() == 0) &&
261         "PPC branch conditions have two components!");
262
263  // One-way branch.
264  if (FBB == 0) {
265    if (Cond.empty())   // Unconditional branch
266      BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
267    else                // Conditional branch
268      BuildMI(&MBB, get(PPC::BCC))
269        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
270    return 1;
271  }
272
273  // Two-way Conditional Branch.
274  BuildMI(&MBB, get(PPC::BCC))
275    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
276  BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
277  return 2;
278}
279
280void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
281                                   MachineBasicBlock::iterator MI,
282                                   unsigned DestReg, unsigned SrcReg,
283                                   const TargetRegisterClass *DestRC,
284                                   const TargetRegisterClass *SrcRC) const {
285  if (DestRC != SrcRC) {
286    cerr << "Not yet supported!";
287    abort();
288  }
289
290  if (DestRC == PPC::GPRCRegisterClass) {
291    BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
292  } else if (DestRC == PPC::G8RCRegisterClass) {
293    BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
294  } else if (DestRC == PPC::F4RCRegisterClass) {
295    BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg);
296  } else if (DestRC == PPC::F8RCRegisterClass) {
297    BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg);
298  } else if (DestRC == PPC::CRRCRegisterClass) {
299    BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg);
300  } else if (DestRC == PPC::VRRCRegisterClass) {
301    BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
302  } else {
303    cerr << "Attempt to copy register that is not GPR or FPR";
304    abort();
305  }
306}
307
308bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
309  if (MBB.empty()) return false;
310
311  switch (MBB.back().getOpcode()) {
312  case PPC::BLR:   // Return.
313  case PPC::B:     // Uncond branch.
314  case PPC::BCTR:  // Indirect branch.
315    return true;
316  default: return false;
317  }
318}
319
320bool PPCInstrInfo::
321ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
322  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
323  // Leave the CR# the same, but invert the condition.
324  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
325  return false;
326}
327