PPCInstrInfo.cpp revision da47e17a6f58bb4dae22d3e79c69fcb1d254ba44
131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===// 2b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 3f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// The LLVM Compiler Infrastructure 4f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 8f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 9f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 10f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// This file contains the PowerPC implementation of the TargetInstrInfo class. 11f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman// 12f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman//===----------------------------------------------------------------------===// 13f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 1416e71f2f70811c69c56052dd146324fe20e31db5Chris Lattner#include "PPCInstrInfo.h" 15d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "MCTargetDesc/PPCPredicates.h" 1659ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng#include "PPC.h" 17d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "PPCHazardRecognizers.h" 18f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson#include "PPCInstrBuilder.h" 197194aaf738a1b89441635340403f1c5b06ae18efBill Wendling#include "PPCMachineFunctionInfo.h" 20b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner#include "PPCTargetMachine.h" 215ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel#include "llvm/ADT/Statistic.h" 22d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/ADT/STLExtras.h" 237a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen#include "llvm/CodeGen/MachineFrameInfo.h" 245ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel#include "llvm/CodeGen/MachineFunctionPass.h" 25f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman#include "llvm/CodeGen/MachineInstrBuilder.h" 267a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen#include "llvm/CodeGen/MachineMemOperand.h" 27243296690ec78fc918762bd73896b09e26537f47Jakob Stoklund Olesen#include "llvm/CodeGen/MachineRegisterInfo.h" 284d989ac93ce608057fb6b13a4068264ab037ecd5Hal Finkel#include "llvm/CodeGen/PseudoSourceValue.h" 2959ee62d2418df8db499eca1ae17f5900dc2dcbbaEvan Cheng#include "llvm/MC/MCAsmInfo.h" 30880d0f6018b6928bdcad291be60c801238619955Bill Wendling#include "llvm/Support/CommandLine.h" 31dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/ErrorHandling.h" 323e74d6fdd248e20a280f1dff3da9a6c689c2c4c3Evan Cheng#include "llvm/Support/TargetRegistry.h" 33dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/raw_ostream.h" 34f2ccb77ee9d8ab35866dae111fa36929689c7511Misha Brukman 354db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng#define GET_INSTRINFO_CTOR 3622fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng#include "PPCGenInstrInfo.inc" 3722fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 3882bcd236937b378e56e46bdde9c17a3ea3377068Dan Gohmanusing namespace llvm; 39880d0f6018b6928bdcad291be60c801238619955Bill Wendling 4009fdc7baae1b6905fe18df48e2278e74d4e39ccdHal Finkelstatic cl:: 417255d2a8084cb6aa96ea0e5f30acfff76df04ee8Hal Finkelopt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, 427255d2a8084cb6aa96ea0e5f30acfff76df04ee8Hal Finkel cl::desc("Disable analysis for CTR loops")); 4309fdc7baae1b6905fe18df48e2278e74d4e39ccdHal Finkel 44b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris LattnerPPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) 454db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 46d5b03f252c0db6b49a242abab63d7c5a260fceaeEvan Cheng TM(tm), RI(*TM.getSubtargetImpl(), *this) {} 47b1d26f66658cff3ceb7d44a72fbc8c8e975532f9Chris Lattner 482da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for 492da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick/// this target when scheduling the DAG. 502da8bc8a5f7705ac131184cd247f48500da0d74eAndrew TrickScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer( 512da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const TargetMachine *TM, 522da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const { 53c6d08f10bf797cc78068ef30bd0e8812a5bdc9a2Hal Finkel unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective(); 54621b77ade2ff46d1d8594bddee6931b2f4a14706Hal Finkel if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 || 55621b77ade2ff46d1d8594bddee6931b2f4a14706Hal Finkel Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) { 56768c65f677af3f05c2e94982043f90a1bfaceda5Hal Finkel const InstrItineraryData *II = TM->getInstrItineraryData(); 575b00ceaeeabff8c25abb09926343c3fcb06053d8Hal Finkel return new PPCScoreboardHazardRecognizer(II, DAG); 58c6d08f10bf797cc78068ef30bd0e8812a5bdc9a2Hal Finkel } 5964c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel 60a9fa4fd9736f7d1066223f32fa54efbe86c0fcebJakob Stoklund Olesen return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG); 612da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick} 622da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 6364c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel/// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer 6464c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel/// to use for this target when scheduling the DAG. 6564c34e253563a8ba6b41fbce2bb020632cf65961Hal FinkelScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer( 6664c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel const InstrItineraryData *II, 6764c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel const ScheduleDAG *DAG) const { 6864c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective(); 6964c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel 7064c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel // Most subtargets use a PPC970 recognizer. 71621b77ade2ff46d1d8594bddee6931b2f4a14706Hal Finkel if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 && 72621b77ade2ff46d1d8594bddee6931b2f4a14706Hal Finkel Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) { 7364c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel const TargetInstrInfo *TII = TM.getInstrInfo(); 7464c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel assert(TII && "No InstrInfo?"); 7564c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel 7664c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel return new PPCHazardRecognizer970(*TII); 7764c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel } 7864c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel 794d989ac93ce608057fb6b13a4068264ab037ecd5Hal Finkel return new PPCScoreboardHazardRecognizer(II, DAG); 8064c34e253563a8ba6b41fbce2bb020632cf65961Hal Finkel} 817164288c3eb52e20454fc757440f867f04eb13a4Jakob Stoklund Olesen 827164288c3eb52e20454fc757440f867f04eb13a4Jakob Stoklund Olesen// Detect 32 -> 64-bit extensions where we may reuse the low sub-register. 837164288c3eb52e20454fc757440f867f04eb13a4Jakob Stoklund Olesenbool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 847164288c3eb52e20454fc757440f867f04eb13a4Jakob Stoklund Olesen unsigned &SrcReg, unsigned &DstReg, 857164288c3eb52e20454fc757440f867f04eb13a4Jakob Stoklund Olesen unsigned &SubIdx) const { 867164288c3eb52e20454fc757440f867f04eb13a4Jakob Stoklund Olesen switch (MI.getOpcode()) { 877164288c3eb52e20454fc757440f867f04eb13a4Jakob Stoklund Olesen default: return false; 887164288c3eb52e20454fc757440f867f04eb13a4Jakob Stoklund Olesen case PPC::EXTSW: 897164288c3eb52e20454fc757440f867f04eb13a4Jakob Stoklund Olesen case PPC::EXTSW_32_64: 907164288c3eb52e20454fc757440f867f04eb13a4Jakob Stoklund Olesen SrcReg = MI.getOperand(1).getReg(); 917164288c3eb52e20454fc757440f867f04eb13a4Jakob Stoklund Olesen DstReg = MI.getOperand(0).getReg(); 927164288c3eb52e20454fc757440f867f04eb13a4Jakob Stoklund Olesen SubIdx = PPC::sub_32; 937164288c3eb52e20454fc757440f867f04eb13a4Jakob Stoklund Olesen return true; 947164288c3eb52e20454fc757440f867f04eb13a4Jakob Stoklund Olesen } 957164288c3eb52e20454fc757440f867f04eb13a4Jakob Stoklund Olesen} 967164288c3eb52e20454fc757440f867f04eb13a4Jakob Stoklund Olesen 976e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trickunsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 989c09c9ec9dab61450800b42cbf746164aa076b88Chris Lattner int &FrameIndex) const { 99f25f93b685a6cb91d8370ae5dc1436a863a670d2Hal Finkel // Note: This list must be kept consistent with LoadRegFromStackSlot. 100408396014742a05cad1c91949d2226169e3f9d80Chris Lattner switch (MI->getOpcode()) { 101408396014742a05cad1c91949d2226169e3f9d80Chris Lattner default: break; 102408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LD: 103408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LWZ: 104408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LFS: 105408396014742a05cad1c91949d2226169e3f9d80Chris Lattner case PPC::LFD: 106f25f93b685a6cb91d8370ae5dc1436a863a670d2Hal Finkel case PPC::RESTORE_CR: 107f25f93b685a6cb91d8370ae5dc1436a863a670d2Hal Finkel case PPC::LVX: 108f25f93b685a6cb91d8370ae5dc1436a863a670d2Hal Finkel case PPC::RESTORE_VRSAVE: 109f25f93b685a6cb91d8370ae5dc1436a863a670d2Hal Finkel // Check for the operands added by addFrameReference (the immediate is the 110f25f93b685a6cb91d8370ae5dc1436a863a670d2Hal Finkel // offset which defaults to 0). 111d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 112d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(2).isFI()) { 1138aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FrameIndex = MI->getOperand(2).getIndex(); 114408396014742a05cad1c91949d2226169e3f9d80Chris Lattner return MI->getOperand(0).getReg(); 115408396014742a05cad1c91949d2226169e3f9d80Chris Lattner } 116408396014742a05cad1c91949d2226169e3f9d80Chris Lattner break; 117408396014742a05cad1c91949d2226169e3f9d80Chris Lattner } 118408396014742a05cad1c91949d2226169e3f9d80Chris Lattner return 0; 1196524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner} 120408396014742a05cad1c91949d2226169e3f9d80Chris Lattner 1216e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trickunsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 1226524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner int &FrameIndex) const { 123f25f93b685a6cb91d8370ae5dc1436a863a670d2Hal Finkel // Note: This list must be kept consistent with StoreRegToStackSlot. 1246524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner switch (MI->getOpcode()) { 1256524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner default: break; 1263b478b31e297208ef2c9f74750a8a603eb3726fbNate Begeman case PPC::STD: 1276524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner case PPC::STW: 1286524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner case PPC::STFS: 1296524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner case PPC::STFD: 130f25f93b685a6cb91d8370ae5dc1436a863a670d2Hal Finkel case PPC::SPILL_CR: 131f25f93b685a6cb91d8370ae5dc1436a863a670d2Hal Finkel case PPC::STVX: 132f25f93b685a6cb91d8370ae5dc1436a863a670d2Hal Finkel case PPC::SPILL_VRSAVE: 133f25f93b685a6cb91d8370ae5dc1436a863a670d2Hal Finkel // Check for the operands added by addFrameReference (the immediate is the 134f25f93b685a6cb91d8370ae5dc1436a863a670d2Hal Finkel // offset which defaults to 0). 135d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 136d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(2).isFI()) { 1378aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FrameIndex = MI->getOperand(2).getIndex(); 1386524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner return MI->getOperand(0).getReg(); 1396524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner } 1406524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner break; 1416524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner } 1426524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner return 0; 1436524287c53cf727a8ef33517403fcb1bbd7adff9Chris Lattner} 144408396014742a05cad1c91949d2226169e3f9d80Chris Lattner 145043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner// commuteInstruction - We can commute rlwimi instructions, but only if the 146043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner// rotate amt is zero. We also have to munge the immediates a bit. 14758dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan ChengMachineInstr * 14858dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan ChengPPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1498e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineFunction &MF = *MI->getParent()->getParent(); 1508e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman 151043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Normal instructions can be commuted the obvious way. 152043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner if (MI->getOpcode() != PPC::RLWIMI) 153a9fa4fd9736f7d1066223f32fa54efbe86c0fcebJakob Stoklund Olesen return TargetInstrInfo::commuteInstruction(MI, NewMI); 1546e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 155043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Cannot commute if it has a non-zero rotate count. 1569a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner if (MI->getOperand(3).getImm() != 0) 157043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner return 0; 1586e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 159043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // If we have a zero rotate count, we have: 160043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // M = mask(MB,ME) 161043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Op0 = (Op1 & ~M) | (Op2 & M) 162043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Change this to: 163043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // M = mask((ME+1)&31, (MB-1)&31) 164043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Op0 = (Op2 & ~M) | (Op1 & M) 165043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner 166043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Swap op1/op2 167a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng unsigned Reg0 = MI->getOperand(0).getReg(); 168043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner unsigned Reg1 = MI->getOperand(1).getReg(); 169043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner unsigned Reg2 = MI->getOperand(2).getReg(); 1706ce7dc2a97260eea5fba414332796464912b9359Evan Cheng bool Reg1IsKill = MI->getOperand(1).isKill(); 1716ce7dc2a97260eea5fba414332796464912b9359Evan Cheng bool Reg2IsKill = MI->getOperand(2).isKill(); 17258dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool ChangeReg0 = false; 173a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng // If machine instrs are no longer in two-address forms, update 174a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng // destination register as well. 175a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng if (Reg0 == Reg1) { 176a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng // Must be two address instruction! 177e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) && 178a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng "Expecting a two-address instruction!"); 179a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng Reg2IsKill = false; 18058dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng ChangeReg0 = true; 18158dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng } 18258dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 18358dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng // Masks. 18458dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng unsigned MB = MI->getOperand(4).getImm(); 18558dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng unsigned ME = MI->getOperand(5).getImm(); 18658dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 18758dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng if (NewMI) { 18858dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng // Create a new instruction. 18958dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); 19058dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool Reg0IsDead = MI->getOperand(0).isDead(); 191d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 192587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 193587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(Reg2, getKillRegState(Reg2IsKill)) 194587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(Reg1, getKillRegState(Reg1IsKill)) 19558dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng .addImm((ME+1) & 31) 19658dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng .addImm((MB-1) & 31); 197a4d16a1f0dcdd1ab2862737105f900e2c577532dEvan Cheng } 19858dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng 19958dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng if (ChangeReg0) 20058dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng MI->getOperand(0).setReg(Reg2); 201e53f4a055f74bded20d6129b4724ddd17fd199f6Chris Lattner MI->getOperand(2).setReg(Reg1); 202e53f4a055f74bded20d6129b4724ddd17fd199f6Chris Lattner MI->getOperand(1).setReg(Reg2); 203f73823000e2d5d6e1cf65bdf5a107297e18d35fbChris Lattner MI->getOperand(2).setIsKill(Reg1IsKill); 204f73823000e2d5d6e1cf65bdf5a107297e18d35fbChris Lattner MI->getOperand(1).setIsKill(Reg2IsKill); 2056e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 206043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner // Swap the mask around. 2079a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner MI->getOperand(4).setImm((ME+1) & 31); 2089a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner MI->getOperand(5).setImm((MB-1) & 31); 209043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner return MI; 210043870dd85ea41e8972c304b122070a417c8a4bcChris Lattner} 211bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner 2126e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trickvoid PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 213bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner MachineBasicBlock::iterator MI) const { 214c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 215d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, MI, DL, get(PPC::NOP)); 216bbf1c72d51a77bf54c9c684b90a78e59f0b70b2fChris Lattner} 217c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 218c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 219c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner// Branch analysis. 22099f823f94374917174f96a7689955b8463db6816Hal Finkel// Note: If the condition register is set to CTR or CTR8 then this is a 22199f823f94374917174f96a7689955b8463db6816Hal Finkel// BDNZ (imm == 1) or BDZ (imm == 0) branch. 222c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattnerbool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 223c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineBasicBlock *&FBB, 224dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng SmallVectorImpl<MachineOperand> &Cond, 225dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng bool AllowModify) const { 22699f823f94374917174f96a7689955b8463db6816Hal Finkel bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); 22799f823f94374917174f96a7689955b8463db6816Hal Finkel 228c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // If the block has no terminators, it just falls into the block after it. 229c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineBasicBlock::iterator I = MBB.end(); 23093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 23193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 23293d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 23393d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 23493d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 23593d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return false; 23693d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 23793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 23893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (!isUnpredicatedTerminator(I)) 239c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return false; 240c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 241c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Get the last instruction in the block. 242c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineInstr *LastInst = I; 2436e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 244c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // If there is only one terminator instruction, process it. 245bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 246c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner if (LastInst->getOpcode() == PPC::B) { 24782ae933e55839713ea039e7c6353483b14dc5724Evan Cheng if (!LastInst->getOperand(0).isMBB()) 24882ae933e55839713ea039e7c6353483b14dc5724Evan Cheng return true; 2498aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = LastInst->getOperand(0).getMBB(); 250c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return false; 251289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner } else if (LastInst->getOpcode() == PPC::BCC) { 25282ae933e55839713ea039e7c6353483b14dc5724Evan Cheng if (!LastInst->getOperand(2).isMBB()) 25382ae933e55839713ea039e7c6353483b14dc5724Evan Cheng return true; 254c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Block ends with fall-through condbranch. 2558aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = LastInst->getOperand(2).getMBB(); 256c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(LastInst->getOperand(0)); 257c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(LastInst->getOperand(1)); 2587c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner return false; 25999f823f94374917174f96a7689955b8463db6816Hal Finkel } else if (LastInst->getOpcode() == PPC::BDNZ8 || 26099f823f94374917174f96a7689955b8463db6816Hal Finkel LastInst->getOpcode() == PPC::BDNZ) { 26199f823f94374917174f96a7689955b8463db6816Hal Finkel if (!LastInst->getOperand(0).isMBB()) 26299f823f94374917174f96a7689955b8463db6816Hal Finkel return true; 2637255d2a8084cb6aa96ea0e5f30acfff76df04ee8Hal Finkel if (DisableCTRLoopAnal) 26409fdc7baae1b6905fe18df48e2278e74d4e39ccdHal Finkel return true; 26599f823f94374917174f96a7689955b8463db6816Hal Finkel TBB = LastInst->getOperand(0).getMBB(); 26699f823f94374917174f96a7689955b8463db6816Hal Finkel Cond.push_back(MachineOperand::CreateImm(1)); 26799f823f94374917174f96a7689955b8463db6816Hal Finkel Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 26899f823f94374917174f96a7689955b8463db6816Hal Finkel true)); 26999f823f94374917174f96a7689955b8463db6816Hal Finkel return false; 27099f823f94374917174f96a7689955b8463db6816Hal Finkel } else if (LastInst->getOpcode() == PPC::BDZ8 || 27199f823f94374917174f96a7689955b8463db6816Hal Finkel LastInst->getOpcode() == PPC::BDZ) { 27299f823f94374917174f96a7689955b8463db6816Hal Finkel if (!LastInst->getOperand(0).isMBB()) 27399f823f94374917174f96a7689955b8463db6816Hal Finkel return true; 2747255d2a8084cb6aa96ea0e5f30acfff76df04ee8Hal Finkel if (DisableCTRLoopAnal) 27509fdc7baae1b6905fe18df48e2278e74d4e39ccdHal Finkel return true; 27699f823f94374917174f96a7689955b8463db6816Hal Finkel TBB = LastInst->getOperand(0).getMBB(); 27799f823f94374917174f96a7689955b8463db6816Hal Finkel Cond.push_back(MachineOperand::CreateImm(0)); 27899f823f94374917174f96a7689955b8463db6816Hal Finkel Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 27999f823f94374917174f96a7689955b8463db6816Hal Finkel true)); 28099f823f94374917174f96a7689955b8463db6816Hal Finkel return false; 281c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner } 28299f823f94374917174f96a7689955b8463db6816Hal Finkel 283c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Otherwise, don't know what this is. 284c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return true; 285c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner } 2866e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 287c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Get the instruction before it if it's a terminator. 288c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineInstr *SecondLastInst = I; 289c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 290c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // If there are three terminators, we don't know what sort of block this is. 291c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner if (SecondLastInst && I != MBB.begin() && 292bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng isUnpredicatedTerminator(--I)) 293c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return true; 2946e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 295289c2d5f4566d8d7722e3934f4763d3df92886f3Chris Lattner // If the block ends with PPC::B and PPC:BCC, handle it. 2966e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick if (SecondLastInst->getOpcode() == PPC::BCC && 297c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner LastInst->getOpcode() == PPC::B) { 29882ae933e55839713ea039e7c6353483b14dc5724Evan Cheng if (!SecondLastInst->getOperand(2).isMBB() || 29982ae933e55839713ea039e7c6353483b14dc5724Evan Cheng !LastInst->getOperand(0).isMBB()) 30082ae933e55839713ea039e7c6353483b14dc5724Evan Cheng return true; 3018aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = SecondLastInst->getOperand(2).getMBB(); 302c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(SecondLastInst->getOperand(0)); 303c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner Cond.push_back(SecondLastInst->getOperand(1)); 3048aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FBB = LastInst->getOperand(0).getMBB(); 305c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return false; 30699f823f94374917174f96a7689955b8463db6816Hal Finkel } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 || 30799f823f94374917174f96a7689955b8463db6816Hal Finkel SecondLastInst->getOpcode() == PPC::BDNZ) && 30899f823f94374917174f96a7689955b8463db6816Hal Finkel LastInst->getOpcode() == PPC::B) { 30999f823f94374917174f96a7689955b8463db6816Hal Finkel if (!SecondLastInst->getOperand(0).isMBB() || 31099f823f94374917174f96a7689955b8463db6816Hal Finkel !LastInst->getOperand(0).isMBB()) 31199f823f94374917174f96a7689955b8463db6816Hal Finkel return true; 3127255d2a8084cb6aa96ea0e5f30acfff76df04ee8Hal Finkel if (DisableCTRLoopAnal) 31309fdc7baae1b6905fe18df48e2278e74d4e39ccdHal Finkel return true; 31499f823f94374917174f96a7689955b8463db6816Hal Finkel TBB = SecondLastInst->getOperand(0).getMBB(); 31599f823f94374917174f96a7689955b8463db6816Hal Finkel Cond.push_back(MachineOperand::CreateImm(1)); 31699f823f94374917174f96a7689955b8463db6816Hal Finkel Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 31799f823f94374917174f96a7689955b8463db6816Hal Finkel true)); 31899f823f94374917174f96a7689955b8463db6816Hal Finkel FBB = LastInst->getOperand(0).getMBB(); 31999f823f94374917174f96a7689955b8463db6816Hal Finkel return false; 32099f823f94374917174f96a7689955b8463db6816Hal Finkel } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 || 32199f823f94374917174f96a7689955b8463db6816Hal Finkel SecondLastInst->getOpcode() == PPC::BDZ) && 32299f823f94374917174f96a7689955b8463db6816Hal Finkel LastInst->getOpcode() == PPC::B) { 32399f823f94374917174f96a7689955b8463db6816Hal Finkel if (!SecondLastInst->getOperand(0).isMBB() || 32499f823f94374917174f96a7689955b8463db6816Hal Finkel !LastInst->getOperand(0).isMBB()) 32599f823f94374917174f96a7689955b8463db6816Hal Finkel return true; 3267255d2a8084cb6aa96ea0e5f30acfff76df04ee8Hal Finkel if (DisableCTRLoopAnal) 32709fdc7baae1b6905fe18df48e2278e74d4e39ccdHal Finkel return true; 32899f823f94374917174f96a7689955b8463db6816Hal Finkel TBB = SecondLastInst->getOperand(0).getMBB(); 32999f823f94374917174f96a7689955b8463db6816Hal Finkel Cond.push_back(MachineOperand::CreateImm(0)); 33099f823f94374917174f96a7689955b8463db6816Hal Finkel Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 33199f823f94374917174f96a7689955b8463db6816Hal Finkel true)); 33299f823f94374917174f96a7689955b8463db6816Hal Finkel FBB = LastInst->getOperand(0).getMBB(); 33399f823f94374917174f96a7689955b8463db6816Hal Finkel return false; 334c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner } 3356e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 33613e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen // If the block ends with two PPC:Bs, handle it. The second one is not 33713e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen // executed, so remove it. 3386e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick if (SecondLastInst->getOpcode() == PPC::B && 33913e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen LastInst->getOpcode() == PPC::B) { 34082ae933e55839713ea039e7c6353483b14dc5724Evan Cheng if (!SecondLastInst->getOperand(0).isMBB()) 34182ae933e55839713ea039e7c6353483b14dc5724Evan Cheng return true; 3428aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner TBB = SecondLastInst->getOperand(0).getMBB(); 34313e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen I = LastInst; 344dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng if (AllowModify) 345dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng I->eraseFromParent(); 34613e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen return false; 34713e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen } 34813e8b51e3ec014c5d7ae83afdf3b8fd29c3a461dDale Johannesen 349c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Otherwise, can't handle this. 350c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner return true; 351c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 352c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 353b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Chengunsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 354c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner MachineBasicBlock::iterator I = MBB.end(); 355b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng if (I == MBB.begin()) return 0; 356c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner --I; 35793d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen while (I->isDebugValue()) { 35893d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen if (I == MBB.begin()) 35993d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen return 0; 36093d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen --I; 36193d6a7e9c21204c52d6efec6c672163e7de79660Dale Johannesen } 36299f823f94374917174f96a7689955b8463db6816Hal Finkel if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC && 36399f823f94374917174f96a7689955b8463db6816Hal Finkel I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && 36499f823f94374917174f96a7689955b8463db6816Hal Finkel I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) 365b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 3666e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 367c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Remove the branch. 368c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner I->eraseFromParent(); 3696e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 370c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner I = MBB.end(); 371c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 372b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng if (I == MBB.begin()) return 1; 373c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner --I; 37499f823f94374917174f96a7689955b8463db6816Hal Finkel if (I->getOpcode() != PPC::BCC && 37599f823f94374917174f96a7689955b8463db6816Hal Finkel I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && 37699f823f94374917174f96a7689955b8463db6816Hal Finkel I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) 377b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 1; 3786e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 379c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner // Remove the branch. 380c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner I->eraseFromParent(); 381b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 2; 382c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 383c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 384b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Chengunsigned 385b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan ChengPPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 386b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng MachineBasicBlock *FBB, 3873bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 3883bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 3892dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner // Shouldn't be a fall through. 3902dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 3916e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick assert((Cond.size() == 2 || Cond.size() == 0) && 39254108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner "PPC branch conditions have two components!"); 3936e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 39499f823f94374917174f96a7689955b8463db6816Hal Finkel bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); 39599f823f94374917174f96a7689955b8463db6816Hal Finkel 39654108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner // One-way branch. 3972dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner if (FBB == 0) { 39854108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner if (Cond.empty()) // Unconditional branch 3993bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); 40099f823f94374917174f96a7689955b8463db6816Hal Finkel else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) 40199f823f94374917174f96a7689955b8463db6816Hal Finkel BuildMI(&MBB, DL, get(Cond[0].getImm() ? 40299f823f94374917174f96a7689955b8463db6816Hal Finkel (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : 40399f823f94374917174f96a7689955b8463db6816Hal Finkel (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); 40454108068b71a7dbc48f4ebf1b2d7d87ca541070aChris Lattner else // Conditional branch 4053bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(PPC::BCC)) 40618258c640466274c26e89016e361ec411ff78520Chris Lattner .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 407b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 1; 4082dc7723474c54efcbcac6265dad0a7271902f1a5Chris Lattner } 4096e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 410879d09cf130f3760a08865913c04d9ff328fad5fChris Lattner // Two-way Conditional Branch. 41199f823f94374917174f96a7689955b8463db6816Hal Finkel if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) 41299f823f94374917174f96a7689955b8463db6816Hal Finkel BuildMI(&MBB, DL, get(Cond[0].getImm() ? 41399f823f94374917174f96a7689955b8463db6816Hal Finkel (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : 41499f823f94374917174f96a7689955b8463db6816Hal Finkel (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); 41599f823f94374917174f96a7689955b8463db6816Hal Finkel else 41699f823f94374917174f96a7689955b8463db6816Hal Finkel BuildMI(&MBB, DL, get(PPC::BCC)) 41799f823f94374917174f96a7689955b8463db6816Hal Finkel .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 4183bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); 419b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 2; 420c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 421c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner 422ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel// Select analysis. 423ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkelbool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB, 424ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel const SmallVectorImpl<MachineOperand> &Cond, 425ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel unsigned TrueReg, unsigned FalseReg, 426ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel int &CondCycles, int &TrueCycles, int &FalseCycles) const { 427ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel if (!TM.getSubtargetImpl()->hasISEL()) 428ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel return false; 429ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel 430ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel if (Cond.size() != 2) 431ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel return false; 432ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel 433ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel // If this is really a bdnz-like condition, then it cannot be turned into a 434ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel // select. 435ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) 436ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel return false; 437ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel 438ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel // Check register classes. 439ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 440ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel const TargetRegisterClass *RC = 441ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 442ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel if (!RC) 443ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel return false; 444ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel 445ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel // isel is for regular integer GPRs only. 446ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel if (!PPC::GPRCRegClass.hasSubClassEq(RC) && 447ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel !PPC::G8RCRegClass.hasSubClassEq(RC)) 448ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel return false; 449ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel 450ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel // FIXME: These numbers are for the A2, how well they work for other cores is 451ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel // an open question. On the A2, the isel instruction has a 2-cycle latency 452ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel // but single-cycle throughput. These numbers are used in combination with 453ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel // the MispredictPenalty setting from the active SchedMachineModel. 454ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel CondCycles = 1; 455ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel TrueCycles = 1; 456ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel FalseCycles = 1; 457ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel 458ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel return true; 459ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel} 460ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel 461ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkelvoid PPCInstrInfo::insertSelect(MachineBasicBlock &MBB, 462ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel MachineBasicBlock::iterator MI, DebugLoc dl, 463ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel unsigned DestReg, 464ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel const SmallVectorImpl<MachineOperand> &Cond, 465ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel unsigned TrueReg, unsigned FalseReg) const { 466ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel assert(Cond.size() == 2 && 467ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel "PPC branch conditions have two components!"); 468ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel 469ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel assert(TM.getSubtargetImpl()->hasISEL() && 470ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel "Cannot insert select on target without ISEL support"); 471ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel 472ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel // Get the register classes. 473ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 474ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel const TargetRegisterClass *RC = 475ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 476ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel assert(RC && "TrueReg and FalseReg must have overlapping register classes"); 477ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel assert((PPC::GPRCRegClass.hasSubClassEq(RC) || 478ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel PPC::G8RCRegClass.hasSubClassEq(RC)) && 479ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel "isel is for regular integer GPRs only"); 480ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel 481ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel unsigned OpCode = 482ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel PPC::GPRCRegClass.hasSubClassEq(RC) ? PPC::ISEL : PPC::ISEL8; 483ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel unsigned SelectPred = Cond[0].getImm(); 484ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel 485ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel unsigned SubIdx; 486ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel bool SwapOps; 487ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel switch (SelectPred) { 488ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel default: llvm_unreachable("invalid predicate for isel"); 489ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break; 490ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break; 491ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break; 492ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break; 493ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break; 494ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break; 495ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break; 496ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break; 497ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel } 498ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel 499ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel unsigned FirstReg = SwapOps ? FalseReg : TrueReg, 500ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel SecondReg = SwapOps ? TrueReg : FalseReg; 501ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel 502ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel // The first input register of isel cannot be r0. If it is a member 503ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel // of a register class that can be r0, then copy it first (the 504ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel // register allocator should eliminate the copy). 505ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || 506ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel MRI.getRegClass(FirstReg)->contains(PPC::X0)) { 507ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel const TargetRegisterClass *FirstRC = 508ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel MRI.getRegClass(FirstReg)->contains(PPC::X0) ? 509ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass; 510ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel unsigned OldFirstReg = FirstReg; 511ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel FirstReg = MRI.createVirtualRegister(FirstRC); 512ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg) 513ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel .addReg(OldFirstReg); 514ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel } 515ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel 516ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel BuildMI(MBB, MI, dl, get(OpCode), DestReg) 517ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel .addReg(FirstReg).addReg(SecondReg) 518ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel .addReg(Cond[1].getReg(), 0, SubIdx); 519ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel} 520ff56d1a2011f239e114267c13302ea26db4f8046Hal Finkel 52127689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesenvoid PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 52227689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 52327689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 52427689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen bool KillSrc) const { 52527689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen unsigned Opc; 52627689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) 52727689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen Opc = PPC::OR; 52827689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) 52927689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen Opc = PPC::OR8; 53027689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) 53127689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen Opc = PPC::FMR; 53227689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) 53327689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen Opc = PPC::MCRF; 53427689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) 53527689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen Opc = PPC::VOR; 53627689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) 53727689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen Opc = PPC::CROR; 53827689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen else 53927689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen llvm_unreachable("Impossible reg-to-reg copy"); 540d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 541e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = get(Opc); 542e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng if (MCID.getNumOperands() == 3) 543e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng BuildMI(MBB, I, DL, MCID, DestReg) 54427689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); 54527689b0affee8fb1bfbef11dcc84287b7757cfe8Jakob Stoklund Olesen else 546e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); 547d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson} 548d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 5493fd0018af1b692cabfa5a002bf41f1e756aa9ddeHal Finkel// This function returns true if a CR spill is necessary and false otherwise. 5504a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendlingbool 5518e5f2c6f65841542e2a7092553fe42a00048e4c7Dan GohmanPPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, 5528e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman unsigned SrcReg, bool isKill, 5534a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling int FrameIdx, 5544a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling const TargetRegisterClass *RC, 555324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel SmallVectorImpl<MachineInstr*> &NewMIs, 5563f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel bool &NonRI, bool &SpillsVRS) const{ 557f25f93b685a6cb91d8370ae5dc1436a863a670d2Hal Finkel // Note: If additional store instructions are added here, 558f25f93b685a6cb91d8370ae5dc1436a863a670d2Hal Finkel // update isStoreToStackSlot. 559f25f93b685a6cb91d8370ae5dc1436a863a670d2Hal Finkel 560c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 561c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper if (PPC::GPRCRegClass.hasSubClassEq(RC)) { 5627257fda1b3b047f6fd46df8a9999580fcfafbfaeHal Finkel NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 5637257fda1b3b047f6fd46df8a9999580fcfafbfaeHal Finkel .addReg(SrcReg, 5647257fda1b3b047f6fd46df8a9999580fcfafbfaeHal Finkel getKillRegState(isKill)), 5657257fda1b3b047f6fd46df8a9999580fcfafbfaeHal Finkel FrameIdx)); 566c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) { 5677257fda1b3b047f6fd46df8a9999580fcfafbfaeHal Finkel NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 5687257fda1b3b047f6fd46df8a9999580fcfafbfaeHal Finkel .addReg(SrcReg, 5697257fda1b3b047f6fd46df8a9999580fcfafbfaeHal Finkel getKillRegState(isKill)), 5707257fda1b3b047f6fd46df8a9999580fcfafbfaeHal Finkel FrameIdx)); 571c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { 57221b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) 573587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SrcReg, 574587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling getKillRegState(isKill)), 575587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling FrameIdx)); 576c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { 57721b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) 578587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SrcReg, 579587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling getKillRegState(isKill)), 580587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling FrameIdx)); 581c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { 5827285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) 5837285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel .addReg(SrcReg, 5847285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel getKillRegState(isKill)), 5857285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel FrameIdx)); 5867285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel return true; 587c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { 5880404cd97e4f6ebfe4f8057d4e21119d77654dff2Nicolas Geoffray // FIXME: We use CRi here because there is no mtcrf on a bit. Since the 5890404cd97e4f6ebfe4f8057d4e21119d77654dff2Nicolas Geoffray // backend currently only uses CR1EQ as an individual bit, this should 5900404cd97e4f6ebfe4f8057d4e21119d77654dff2Nicolas Geoffray // not cause any bug. If we need other uses of CR bits, the following 5910404cd97e4f6ebfe4f8057d4e21119d77654dff2Nicolas Geoffray // code may be invalid. 5929348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray unsigned Reg = 0; 5936a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 5946a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 5959348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR0; 5966a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 5976a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 5989348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR1; 5996a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 6006a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 6019348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR2; 6026a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 6036a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 6049348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR3; 6056a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 6066a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 6079348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR4; 6086a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 6096a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 6109348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR5; 6116a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 6126a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 6139348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR6; 6146a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 6156a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 6169348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR7; 6179348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray 6186e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx, 6193f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS); 6209348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray 621c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { 622324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX)) 623324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel .addReg(SrcReg, 624324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel getKillRegState(isKill)), 625324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel FrameIdx)); 626324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel NonRI = true; 62710f7f2a222d0e83dc0c33ad506a7686190c2f7a2Hal Finkel } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) { 628b7e11e400dabced046e7ec53a66926716563bb36Hal Finkel assert(TM.getSubtargetImpl()->isDarwin() && 629b7e11e400dabced046e7ec53a66926716563bb36Hal Finkel "VRSAVE only needs spill/restore on Darwin"); 63010f7f2a222d0e83dc0c33ad506a7686190c2f7a2Hal Finkel NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE)) 63110f7f2a222d0e83dc0c33ad506a7686190c2f7a2Hal Finkel .addReg(SrcReg, 63210f7f2a222d0e83dc0c33ad506a7686190c2f7a2Hal Finkel getKillRegState(isKill)), 63310f7f2a222d0e83dc0c33ad506a7686190c2f7a2Hal Finkel FrameIdx)); 6343f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel SpillsVRS = true; 635f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 636c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown regclass!"); 637f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 6387194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 6397194aaf738a1b89441635340403f1c5b06ae18efBill Wendling return false; 640f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 641f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 642f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid 643f6372aa1cc568df19da7c5023e83c75aa9404a07Owen AndersonPPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 6447194aaf738a1b89441635340403f1c5b06ae18efBill Wendling MachineBasicBlock::iterator MI, 6457194aaf738a1b89441635340403f1c5b06ae18efBill Wendling unsigned SrcReg, bool isKill, int FrameIdx, 646746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 647746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 6488e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineFunction &MF = *MBB.getParent(); 649f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVector<MachineInstr*, 4> NewMIs; 6507194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 6510cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 6520cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel FuncInfo->setHasSpills(); 6530cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel 6543f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel bool NonRI = false, SpillsVRS = false; 6553f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs, 6563f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel NonRI, SpillsVRS)) 6577194aaf738a1b89441635340403f1c5b06ae18efBill Wendling FuncInfo->setSpillsCR(); 6587194aaf738a1b89441635340403f1c5b06ae18efBill Wendling 6593f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel if (SpillsVRS) 6603f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel FuncInfo->setSpillsVRSAVE(); 6613f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel 662324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel if (NonRI) 663324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel FuncInfo->setHasNonRISpills(); 664324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel 665f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 666f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MBB.insert(MI, NewMIs[i]); 6677a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen 6687a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen const MachineFrameInfo &MFI = *MF.getFrameInfo(); 6697a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen MachineMemOperand *MMO = 670978e0dfe46e481bfb1281e683aa308329e879e95Jay Foad MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 67159db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOStore, 6727a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen MFI.getObjectSize(FrameIdx), 6737a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen MFI.getObjectAlignment(FrameIdx)); 6747a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen NewMIs.back()->addMemOperand(MF, MMO); 675f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 676f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 677d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkelbool 678d1c321a89ab999b9bb602b0f398ecd4c2022262cBill WendlingPPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 6798e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman unsigned DestReg, int FrameIdx, 6804a66e9a57e679b4f3243bf2061daf53c70102030Bill Wendling const TargetRegisterClass *RC, 681324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel SmallVectorImpl<MachineInstr*> &NewMIs, 6823f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel bool &NonRI, bool &SpillsVRS) const{ 683f25f93b685a6cb91d8370ae5dc1436a863a670d2Hal Finkel // Note: If additional load instructions are added here, 684f25f93b685a6cb91d8370ae5dc1436a863a670d2Hal Finkel // update isLoadFromStackSlot. 685f25f93b685a6cb91d8370ae5dc1436a863a670d2Hal Finkel 686c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper if (PPC::GPRCRegClass.hasSubClassEq(RC)) { 687fc8058696820332cfd3d382f6534edc96420a0b1Hal Finkel NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 688fc8058696820332cfd3d382f6534edc96420a0b1Hal Finkel DestReg), FrameIdx)); 689c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) { 690fc8058696820332cfd3d382f6534edc96420a0b1Hal Finkel NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg), 691fc8058696820332cfd3d382f6534edc96420a0b1Hal Finkel FrameIdx)); 692c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { 693d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg), 694f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 695c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { 696d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg), 697f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson FrameIdx)); 698c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { 6997285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel NewMIs.push_back(addFrameReference(BuildMI(MF, DL, 7007285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel get(PPC::RESTORE_CR), DestReg), 7017285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel FrameIdx)); 7027285e8d98c9a44b7efe792462188cfe713dd9641Hal Finkel return true; 703c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { 7046e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 7059348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray unsigned Reg = 0; 7066a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT || 7076a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN) 7089348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR0; 7096a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT || 7106a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN) 7119348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR1; 7126a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT || 7136a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN) 7149348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR2; 7156a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT || 7166a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN) 7179348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR3; 7186a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT || 7196a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN) 7209348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR4; 7216a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT || 7226a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN) 7239348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR5; 7246a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT || 7256a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN) 7269348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR6; 7276a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT || 7286a3a1ba97e996bfdc061f9a51bd4cf4915962913Tilmann Scheller DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN) 7299348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray Reg = PPC::CR7; 7309348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray 7316e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx, 7323f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS); 7339348c69dcfe1aa1e7f92752a18222dcfbcd96214Nicolas Geoffray 734c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { 735324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg), 736324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel FrameIdx)); 737324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel NonRI = true; 73810f7f2a222d0e83dc0c33ad506a7686190c2f7a2Hal Finkel } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) { 739b7e11e400dabced046e7ec53a66926716563bb36Hal Finkel assert(TM.getSubtargetImpl()->isDarwin() && 740b7e11e400dabced046e7ec53a66926716563bb36Hal Finkel "VRSAVE only needs spill/restore on Darwin"); 74110f7f2a222d0e83dc0c33ad506a7686190c2f7a2Hal Finkel NewMIs.push_back(addFrameReference(BuildMI(MF, DL, 74210f7f2a222d0e83dc0c33ad506a7686190c2f7a2Hal Finkel get(PPC::RESTORE_VRSAVE), 74310f7f2a222d0e83dc0c33ad506a7686190c2f7a2Hal Finkel DestReg), 74410f7f2a222d0e83dc0c33ad506a7686190c2f7a2Hal Finkel FrameIdx)); 7453f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel SpillsVRS = true; 746f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } else { 747c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown regclass!"); 748f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 749d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel 750d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel return false; 751f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 752f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 753f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid 754f6372aa1cc568df19da7c5023e83c75aa9404a07Owen AndersonPPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 7557194aaf738a1b89441635340403f1c5b06ae18efBill Wendling MachineBasicBlock::iterator MI, 7567194aaf738a1b89441635340403f1c5b06ae18efBill Wendling unsigned DestReg, int FrameIdx, 757746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 758746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 7598e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineFunction &MF = *MBB.getParent(); 760f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVector<MachineInstr*, 4> NewMIs; 761c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 762d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling if (MI != MBB.end()) DL = MI->getDebugLoc(); 763324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel 764324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 765324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel FuncInfo->setHasSpills(); 766324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel 7673f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel bool NonRI = false, SpillsVRS = false; 7683f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs, 7693f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel NonRI, SpillsVRS)) 770d21e930eac3d99dd77ee33ea5826700b4bc97ae8Hal Finkel FuncInfo->setSpillsCR(); 771324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel 7723f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel if (SpillsVRS) 7733f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel FuncInfo->setSpillsVRSAVE(); 7743f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel 775324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel if (NonRI) 776324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel FuncInfo->setHasNonRISpills(); 777324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel 778f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 779f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MBB.insert(MI, NewMIs[i]); 7807a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen 7817a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen const MachineFrameInfo &MFI = *MF.getFrameInfo(); 7827a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen MachineMemOperand *MMO = 783978e0dfe46e481bfb1281e683aa308329e879e95Jay Foad MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 78459db5496f4fc2ef6111569e542f8b65480ef14c1Chris Lattner MachineMemOperand::MOLoad, 7857a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen MFI.getObjectSize(FrameIdx), 7867a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen MFI.getObjectAlignment(FrameIdx)); 7877a79fcb55b83b8b98b9853c390cc5bf8ce382dd3Jakob Stoklund Olesen NewMIs.back()->addMemOperand(MF, MMO); 788f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 789f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 7900965217e74fe07f1451350a80114ab566ced5de0Evan ChengMachineInstr* 7910965217e74fe07f1451350a80114ab566ced5de0Evan ChengPPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 7928601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, uint64_t Offset, 7930965217e74fe07f1451350a80114ab566ced5de0Evan Cheng const MDNode *MDPtr, 7940965217e74fe07f1451350a80114ab566ced5de0Evan Cheng DebugLoc DL) const { 7950965217e74fe07f1451350a80114ab566ced5de0Evan Cheng MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE)); 7960965217e74fe07f1451350a80114ab566ced5de0Evan Cheng addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr); 7970965217e74fe07f1451350a80114ab566ced5de0Evan Cheng return &*MIB; 7980965217e74fe07f1451350a80114ab566ced5de0Evan Cheng} 7990965217e74fe07f1451350a80114ab566ced5de0Evan Cheng 800c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattnerbool PPCInstrInfo:: 80144eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen AndersonReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 8027c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); 80399f823f94374917174f96a7689955b8463db6816Hal Finkel if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR) 80499f823f94374917174f96a7689955b8463db6816Hal Finkel Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0); 80599f823f94374917174f96a7689955b8463db6816Hal Finkel else 80699f823f94374917174f96a7689955b8463db6816Hal Finkel // Leave the CR# the same, but invert the condition. 80799f823f94374917174f96a7689955b8463db6816Hal Finkel Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); 8087c4fe259f8bfeae542cfef25c1f1e9b1ff25a39bChris Lattner return false; 809c50e2bcdf7bff1f9681ab80e52691f274950fab5Chris Lattner} 81052e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray 811839b9096538f790a2bb060547df24703807cb83bHal Finkelbool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 812839b9096538f790a2bb060547df24703807cb83bHal Finkel unsigned Reg, MachineRegisterInfo *MRI) const { 813839b9096538f790a2bb060547df24703807cb83bHal Finkel // For some instructions, it is legal to fold ZERO into the RA register field. 814839b9096538f790a2bb060547df24703807cb83bHal Finkel // A zero immediate should always be loaded with a single li. 815839b9096538f790a2bb060547df24703807cb83bHal Finkel unsigned DefOpc = DefMI->getOpcode(); 816839b9096538f790a2bb060547df24703807cb83bHal Finkel if (DefOpc != PPC::LI && DefOpc != PPC::LI8) 817839b9096538f790a2bb060547df24703807cb83bHal Finkel return false; 818839b9096538f790a2bb060547df24703807cb83bHal Finkel if (!DefMI->getOperand(1).isImm()) 819839b9096538f790a2bb060547df24703807cb83bHal Finkel return false; 820839b9096538f790a2bb060547df24703807cb83bHal Finkel if (DefMI->getOperand(1).getImm() != 0) 821839b9096538f790a2bb060547df24703807cb83bHal Finkel return false; 822839b9096538f790a2bb060547df24703807cb83bHal Finkel 823839b9096538f790a2bb060547df24703807cb83bHal Finkel // Note that we cannot here invert the arguments of an isel in order to fold 824839b9096538f790a2bb060547df24703807cb83bHal Finkel // a ZERO into what is presented as the second argument. All we have here 825839b9096538f790a2bb060547df24703807cb83bHal Finkel // is the condition bit, and that might come from a CR-logical bit operation. 826839b9096538f790a2bb060547df24703807cb83bHal Finkel 827839b9096538f790a2bb060547df24703807cb83bHal Finkel const MCInstrDesc &UseMCID = UseMI->getDesc(); 828839b9096538f790a2bb060547df24703807cb83bHal Finkel 829839b9096538f790a2bb060547df24703807cb83bHal Finkel // Only fold into real machine instructions. 830839b9096538f790a2bb060547df24703807cb83bHal Finkel if (UseMCID.isPseudo()) 831839b9096538f790a2bb060547df24703807cb83bHal Finkel return false; 832839b9096538f790a2bb060547df24703807cb83bHal Finkel 833839b9096538f790a2bb060547df24703807cb83bHal Finkel unsigned UseIdx; 834839b9096538f790a2bb060547df24703807cb83bHal Finkel for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx) 835839b9096538f790a2bb060547df24703807cb83bHal Finkel if (UseMI->getOperand(UseIdx).isReg() && 836839b9096538f790a2bb060547df24703807cb83bHal Finkel UseMI->getOperand(UseIdx).getReg() == Reg) 837839b9096538f790a2bb060547df24703807cb83bHal Finkel break; 838839b9096538f790a2bb060547df24703807cb83bHal Finkel 839839b9096538f790a2bb060547df24703807cb83bHal Finkel assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI"); 840839b9096538f790a2bb060547df24703807cb83bHal Finkel assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg"); 841839b9096538f790a2bb060547df24703807cb83bHal Finkel 842839b9096538f790a2bb060547df24703807cb83bHal Finkel const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx]; 843839b9096538f790a2bb060547df24703807cb83bHal Finkel 844839b9096538f790a2bb060547df24703807cb83bHal Finkel // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0 845839b9096538f790a2bb060547df24703807cb83bHal Finkel // register (which might also be specified as a pointer class kind). 846839b9096538f790a2bb060547df24703807cb83bHal Finkel if (UseInfo->isLookupPtrRegClass()) { 847839b9096538f790a2bb060547df24703807cb83bHal Finkel if (UseInfo->RegClass /* Kind */ != 1) 848839b9096538f790a2bb060547df24703807cb83bHal Finkel return false; 849839b9096538f790a2bb060547df24703807cb83bHal Finkel } else { 850839b9096538f790a2bb060547df24703807cb83bHal Finkel if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID && 851839b9096538f790a2bb060547df24703807cb83bHal Finkel UseInfo->RegClass != PPC::G8RC_NOX0RegClassID) 852839b9096538f790a2bb060547df24703807cb83bHal Finkel return false; 853839b9096538f790a2bb060547df24703807cb83bHal Finkel } 854839b9096538f790a2bb060547df24703807cb83bHal Finkel 855839b9096538f790a2bb060547df24703807cb83bHal Finkel // Make sure this is not tied to an output register (or otherwise 856839b9096538f790a2bb060547df24703807cb83bHal Finkel // constrained). This is true for ST?UX registers, for example, which 857839b9096538f790a2bb060547df24703807cb83bHal Finkel // are tied to their output registers. 858839b9096538f790a2bb060547df24703807cb83bHal Finkel if (UseInfo->Constraints != 0) 859839b9096538f790a2bb060547df24703807cb83bHal Finkel return false; 860839b9096538f790a2bb060547df24703807cb83bHal Finkel 861839b9096538f790a2bb060547df24703807cb83bHal Finkel unsigned ZeroReg; 862839b9096538f790a2bb060547df24703807cb83bHal Finkel if (UseInfo->isLookupPtrRegClass()) { 863839b9096538f790a2bb060547df24703807cb83bHal Finkel bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); 864839b9096538f790a2bb060547df24703807cb83bHal Finkel ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; 865839b9096538f790a2bb060547df24703807cb83bHal Finkel } else { 866839b9096538f790a2bb060547df24703807cb83bHal Finkel ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? 867839b9096538f790a2bb060547df24703807cb83bHal Finkel PPC::ZERO8 : PPC::ZERO; 868839b9096538f790a2bb060547df24703807cb83bHal Finkel } 869839b9096538f790a2bb060547df24703807cb83bHal Finkel 870839b9096538f790a2bb060547df24703807cb83bHal Finkel bool DeleteDef = MRI->hasOneNonDBGUse(Reg); 871839b9096538f790a2bb060547df24703807cb83bHal Finkel UseMI->getOperand(UseIdx).setReg(ZeroReg); 872839b9096538f790a2bb060547df24703807cb83bHal Finkel 873839b9096538f790a2bb060547df24703807cb83bHal Finkel if (DeleteDef) 874839b9096538f790a2bb060547df24703807cb83bHal Finkel DefMI->eraseFromParent(); 875839b9096538f790a2bb060547df24703807cb83bHal Finkel 876839b9096538f790a2bb060547df24703807cb83bHal Finkel return true; 877839b9096538f790a2bb060547df24703807cb83bHal Finkel} 878839b9096538f790a2bb060547df24703807cb83bHal Finkel 879da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkelstatic bool MBBDefinesCTR(MachineBasicBlock &MBB) { 880da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end(); 881da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel I != IE; ++I) 882da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8)) 883da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel return true; 884da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel return false; 885da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel} 886da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel 887da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel// We should make sure that, if we're going to predicate both sides of a 888da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel// condition (a diamond), that both sides don't define the counter register. We 889da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel// can predicate counter-decrement-based branches, but while that predicates 890da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel// the branching, it does not predicate the counter decrement. If we tried to 891da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel// merge the triangle into one predicated block, we'd decrement the counter 892da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel// twice. 893da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkelbool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB, 894da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel unsigned NumT, unsigned ExtraT, 895da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel MachineBasicBlock &FMBB, 896da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel unsigned NumF, unsigned ExtraF, 897da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel const BranchProbability &Probability) const { 898da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB)); 899da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel} 900da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel 901da47e17a6f58bb4dae22d3e79c69fcb1d254ba44Hal Finkel 9027eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkelbool PPCInstrInfo::isPredicated(const MachineInstr *MI) const { 9037eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel unsigned OpC = MI->getOpcode(); 9047eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel switch (OpC) { 9057eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel default: 9067eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel return false; 9077eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel case PPC::BCC: 90890dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel case PPC::BCCTR: 90990dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel case PPC::BCCTR8: 91090dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel case PPC::BCCTRL: 91190dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel case PPC::BCCTRL8: 9127eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel case PPC::BCLR: 9137eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel case PPC::BDZLR: 9147eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel case PPC::BDZLR8: 9157eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel case PPC::BDNZLR: 9167eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel case PPC::BDNZLR8: 9177eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel return true; 9187eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel } 9197eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel} 9207eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 9217eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkelbool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 9227eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel if (!MI->isTerminator()) 9237eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel return false; 9247eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 9257eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel // Conditional branch is a special case. 9267eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel if (MI->isBranch() && !MI->isBarrier()) 9277eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel return true; 9287eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 9297eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel return !isPredicated(MI); 9307eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel} 9317eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 9327eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkelbool PPCInstrInfo::PredicateInstruction( 9337eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel MachineInstr *MI, 9347eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel const SmallVectorImpl<MachineOperand> &Pred) const { 9357eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel unsigned OpC = MI->getOpcode(); 9367eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel if (OpC == PPC::BLR) { 9377eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { 9387eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); 9397eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel MI->setDesc(get(Pred[0].getImm() ? 9407eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) : 9417eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR))); 9427eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel } else { 9437eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel MI->setDesc(get(PPC::BCLR)); 9447eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel MachineInstrBuilder(*MI->getParent()->getParent(), MI) 9457eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel .addImm(Pred[0].getImm()) 9467eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel .addReg(Pred[1].getReg()); 9477eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel } 9487eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 9497eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel return true; 9507eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel } else if (OpC == PPC::B) { 9517eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { 9527eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); 9537eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel MI->setDesc(get(Pred[0].getImm() ? 9547eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : 9557eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel (isPPC64 ? PPC::BDZ8 : PPC::BDZ))); 9567eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel } else { 9577eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel MachineBasicBlock *MBB = MI->getOperand(0).getMBB(); 9587eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel MI->RemoveOperand(0); 9597eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 9607eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel MI->setDesc(get(PPC::BCC)); 9617eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel MachineInstrBuilder(*MI->getParent()->getParent(), MI) 9627eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel .addImm(Pred[0].getImm()) 9637eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel .addReg(Pred[1].getReg()) 9647eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel .addMBB(MBB); 9657eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel } 9667eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 9677eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel return true; 96890dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || 96990dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel OpC == PPC::BCTRL || OpC == PPC::BCTRL8) { 97090dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) 97190dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel llvm_unreachable("Cannot predicate bctr[l] on the ctr register"); 97290dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel 97390dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8; 97490dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); 97590dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) : 97690dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel (setLR ? PPC::BCCTRL : PPC::BCCTR))); 97790dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel MachineInstrBuilder(*MI->getParent()->getParent(), MI) 97890dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel .addImm(Pred[0].getImm()) 97990dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel .addReg(Pred[1].getReg()); 98090dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel return true; 9817eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel } 9827eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 9837eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel return false; 9847eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel} 9857eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 9867eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkelbool PPCInstrInfo::SubsumesPredicate( 9877eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel const SmallVectorImpl<MachineOperand> &Pred1, 9887eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel const SmallVectorImpl<MachineOperand> &Pred2) const { 9897eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel assert(Pred1.size() == 2 && "Invalid PPC first predicate"); 9907eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel assert(Pred2.size() == 2 && "Invalid PPC second predicate"); 9917eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 9927eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR) 9937eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel return false; 9947eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR) 9957eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel return false; 9967eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 9977eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm(); 9987eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm(); 9997eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 10007eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel if (P1 == P2) 10017eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel return true; 10027eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 10037eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel // Does P1 subsume P2, e.g. GE subsumes GT. 10047eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel if (P1 == PPC::PRED_LE && 10057eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ)) 10067eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel return true; 10077eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel if (P1 == PPC::PRED_GE && 10087eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ)) 10097eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel return true; 10107eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 10117eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel return false; 10127eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel} 10137eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 10147eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkelbool PPCInstrInfo::DefinesPredicate(MachineInstr *MI, 10157eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel std::vector<MachineOperand> &Pred) const { 10167eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel // Note: At the present time, the contents of Pred from this function is 10177eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel // unused by IfConversion. This implementation follows ARM by pushing the 10187eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of 10197eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel // predicate, instructions defining CTR or CTR8 are also included as 10207eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel // predicate-defining instructions. 10217eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 10227eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel const TargetRegisterClass *RCs[] = 10237eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass, 10247eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass }; 10257eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 10267eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel bool Found = false; 10277eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 10287eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel const MachineOperand &MO = MI->getOperand(i); 10294e3172867d0c1acfda9d2cc88dfad23634e649ebHal Finkel for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) { 10307eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel const TargetRegisterClass *RC = RCs[c]; 10314e3172867d0c1acfda9d2cc88dfad23634e649ebHal Finkel if (MO.isReg()) { 10324e3172867d0c1acfda9d2cc88dfad23634e649ebHal Finkel if (MO.isDef() && RC->contains(MO.getReg())) { 10337eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel Pred.push_back(MO); 10347eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel Found = true; 10357eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel } 10364e3172867d0c1acfda9d2cc88dfad23634e649ebHal Finkel } else if (MO.isRegMask()) { 10374e3172867d0c1acfda9d2cc88dfad23634e649ebHal Finkel for (TargetRegisterClass::iterator I = RC->begin(), 10384e3172867d0c1acfda9d2cc88dfad23634e649ebHal Finkel IE = RC->end(); I != IE; ++I) 10394e3172867d0c1acfda9d2cc88dfad23634e649ebHal Finkel if (MO.clobbersPhysReg(*I)) { 10404e3172867d0c1acfda9d2cc88dfad23634e649ebHal Finkel Pred.push_back(MO); 10414e3172867d0c1acfda9d2cc88dfad23634e649ebHal Finkel Found = true; 10424e3172867d0c1acfda9d2cc88dfad23634e649ebHal Finkel } 10437eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel } 10447eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel } 10457eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel } 10467eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 10477eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel return Found; 10487eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel} 10497eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 10507eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkelbool PPCInstrInfo::isPredicable(MachineInstr *MI) const { 10517eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel unsigned OpC = MI->getOpcode(); 10527eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel switch (OpC) { 10537eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel default: 10547eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel return false; 10557eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel case PPC::B: 10567eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel case PPC::BLR: 105790dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel case PPC::BCTR: 105890dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel case PPC::BCTR8: 105990dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel case PPC::BCTRL: 106090dd7fd167b6d09e4a7f37e35dcbfdc492546a79Hal Finkel case PPC::BCTRL8: 10617eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel return true; 10627eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel } 10637eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel} 10647eb0d8148e1210d9e31ab471477de47b53bab117Hal Finkel 106552e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray/// GetInstSize - Return the number of bytes of code the specified 106652e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray/// instruction may be. This returns the maximum number of bytes. 106752e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray/// 106852e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffrayunsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 106952e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray switch (MI->getOpcode()) { 107052e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray case PPC::INLINEASM: { // Inline Asm: Variable size. 107152e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray const MachineFunction *MF = MI->getParent()->getParent(); 107252e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray const char *AsmStr = MI->getOperand(0).getSymbolName(); 1073af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattner return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); 107452e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray } 10757431beaba2a01c3fe299c861b2ec85cbf1dc81c4Bill Wendling case PPC::PROLOG_LABEL: 10764406604047423576e36657c7ede266ca42e79642Dan Gohman case PPC::EH_LABEL: 10774406604047423576e36657c7ede266ca42e79642Dan Gohman case PPC::GC_LABEL: 1078375be7730a6f3dee7a6dc319ee6c355a11ac99adDale Johannesen case PPC::DBG_VALUE: 107952e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray return 0; 108086765fbe170198e7bb40fd8499d1354f4c786f60Ulrich Weigand case PPC::BL8_NOP: 108186765fbe170198e7bb40fd8499d1354f4c786f60Ulrich Weigand case PPC::BLA8_NOP: 10825b00ceaeeabff8c25abb09926343c3fcb06053d8Hal Finkel return 8; 108352e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray default: 108452e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray return 4; // PowerPC instructions are all 4 bytes 108552e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray } 108652e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray} 10875ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 10885ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel#undef DEBUG_TYPE 10895ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel#define DEBUG_TYPE "ppc-early-ret" 10905ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal FinkelSTATISTIC(NumBCLR, "Number of early conditional returns"); 10915ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal FinkelSTATISTIC(NumBLR, "Number of early returns"); 10925ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 10935ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkelnamespace llvm { 10945ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel void initializePPCEarlyReturnPass(PassRegistry&); 10955ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel} 10965ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 10975ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkelnamespace { 10985ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel // PPCEarlyReturn pass - For simple functions without epilogue code, move 10995ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel // returns up, and create conditional returns, to avoid unnecessary 11005ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel // branch-to-blr sequences. 11015ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel struct PPCEarlyReturn : public MachineFunctionPass { 11025ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel static char ID; 11035ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel PPCEarlyReturn() : MachineFunctionPass(ID) { 11045ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel initializePPCEarlyReturnPass(*PassRegistry::getPassRegistry()); 11055ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel } 11065ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 11075ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel const PPCTargetMachine *TM; 11085ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel const PPCInstrInfo *TII; 11095ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 11105ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkelprotected: 111113049aef8ad86795e94006dea0e097a8add85665Hal Finkel bool processBlock(MachineBasicBlock &ReturnMBB) { 11125ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel bool Changed = false; 11135ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 111413049aef8ad86795e94006dea0e097a8add85665Hal Finkel MachineBasicBlock::iterator I = ReturnMBB.begin(); 111513049aef8ad86795e94006dea0e097a8add85665Hal Finkel I = ReturnMBB.SkipPHIsAndLabels(I); 11165ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 11175ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel // The block must be essentially empty except for the blr. 111813049aef8ad86795e94006dea0e097a8add85665Hal Finkel if (I == ReturnMBB.end() || I->getOpcode() != PPC::BLR || 111913049aef8ad86795e94006dea0e097a8add85665Hal Finkel I != ReturnMBB.getLastNonDebugInstr()) 11205ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel return Changed; 11215ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 11225ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel SmallVector<MachineBasicBlock*, 8> PredToRemove; 112313049aef8ad86795e94006dea0e097a8add85665Hal Finkel for (MachineBasicBlock::pred_iterator PI = ReturnMBB.pred_begin(), 112413049aef8ad86795e94006dea0e097a8add85665Hal Finkel PIE = ReturnMBB.pred_end(); PI != PIE; ++PI) { 11255ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel bool OtherReference = false, BlockChanged = false; 112613049aef8ad86795e94006dea0e097a8add85665Hal Finkel for (MachineBasicBlock::iterator J = (*PI)->getLastNonDebugInstr();;) { 11275ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel if (J->getOpcode() == PPC::B) { 112813049aef8ad86795e94006dea0e097a8add85665Hal Finkel if (J->getOperand(0).getMBB() == &ReturnMBB) { 11295ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel // This is an unconditional branch to the return. Replace the 11305ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel // branch with a blr. 11315ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BLR)); 113213049aef8ad86795e94006dea0e097a8add85665Hal Finkel MachineBasicBlock::iterator K = J--; 11335ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel K->eraseFromParent(); 11345ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel BlockChanged = true; 11355ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel ++NumBLR; 11365ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel continue; 11375ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel } 11385ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel } else if (J->getOpcode() == PPC::BCC) { 113913049aef8ad86795e94006dea0e097a8add85665Hal Finkel if (J->getOperand(2).getMBB() == &ReturnMBB) { 11405ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel // This is a conditional branch to the return. Replace the branch 11415ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel // with a bclr. 11425ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCLR)) 11435ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel .addImm(J->getOperand(0).getImm()) 11445ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel .addReg(J->getOperand(1).getReg()); 114513049aef8ad86795e94006dea0e097a8add85665Hal Finkel MachineBasicBlock::iterator K = J--; 11465ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel K->eraseFromParent(); 11475ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel BlockChanged = true; 11485ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel ++NumBCLR; 11495ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel continue; 11505ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel } 11515ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel } else if (J->isBranch()) { 11525ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel if (J->isIndirectBranch()) { 115313049aef8ad86795e94006dea0e097a8add85665Hal Finkel if (ReturnMBB.hasAddressTaken()) 11545ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel OtherReference = true; 11555ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel } else 11565ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel for (unsigned i = 0; i < J->getNumOperands(); ++i) 11575ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel if (J->getOperand(i).isMBB() && 115813049aef8ad86795e94006dea0e097a8add85665Hal Finkel J->getOperand(i).getMBB() == &ReturnMBB) 11595ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel OtherReference = true; 116013049aef8ad86795e94006dea0e097a8add85665Hal Finkel } else if (!J->isTerminator() && !J->isDebugValue()) 116113049aef8ad86795e94006dea0e097a8add85665Hal Finkel break; 11625ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 116313049aef8ad86795e94006dea0e097a8add85665Hal Finkel if (J == (*PI)->begin()) 116413049aef8ad86795e94006dea0e097a8add85665Hal Finkel break; 116513049aef8ad86795e94006dea0e097a8add85665Hal Finkel 116613049aef8ad86795e94006dea0e097a8add85665Hal Finkel --J; 11675ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel } 11685ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 116913049aef8ad86795e94006dea0e097a8add85665Hal Finkel if ((*PI)->canFallThrough() && (*PI)->isLayoutSuccessor(&ReturnMBB)) 11705ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel OtherReference = true; 11715ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 11725ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel // Predecessors are stored in a vector and can't be removed here. 11735ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel if (!OtherReference && BlockChanged) { 11745ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel PredToRemove.push_back(*PI); 11755ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel } 11765ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 11775ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel if (BlockChanged) 11785ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel Changed = true; 11795ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel } 11805ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 11815ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel for (unsigned i = 0, ie = PredToRemove.size(); i != ie; ++i) 118213049aef8ad86795e94006dea0e097a8add85665Hal Finkel PredToRemove[i]->removeSuccessor(&ReturnMBB); 11835ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 118413049aef8ad86795e94006dea0e097a8add85665Hal Finkel if (Changed && !ReturnMBB.hasAddressTaken()) { 11855ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel // We now might be able to merge this blr-only block into its 11865ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel // by-layout predecessor. 118713049aef8ad86795e94006dea0e097a8add85665Hal Finkel if (ReturnMBB.pred_size() == 1 && 118813049aef8ad86795e94006dea0e097a8add85665Hal Finkel (*ReturnMBB.pred_begin())->isLayoutSuccessor(&ReturnMBB)) { 11895ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel // Move the blr into the preceding block. 119013049aef8ad86795e94006dea0e097a8add85665Hal Finkel MachineBasicBlock &PrevMBB = **ReturnMBB.pred_begin(); 119113049aef8ad86795e94006dea0e097a8add85665Hal Finkel PrevMBB.splice(PrevMBB.end(), &ReturnMBB, I); 119213049aef8ad86795e94006dea0e097a8add85665Hal Finkel PrevMBB.removeSuccessor(&ReturnMBB); 11935ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel } 11945ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 119513049aef8ad86795e94006dea0e097a8add85665Hal Finkel if (ReturnMBB.pred_empty()) 119613049aef8ad86795e94006dea0e097a8add85665Hal Finkel ReturnMBB.eraseFromParent(); 11975ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel } 11985ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 11995ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel return Changed; 12005ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel } 12015ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 12025ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkelpublic: 12035ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel virtual bool runOnMachineFunction(MachineFunction &MF) { 12045ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel TM = static_cast<const PPCTargetMachine *>(&MF.getTarget()); 12055ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel TII = TM->getInstrInfo(); 12065ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 12075ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel bool Changed = false; 12085ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 120913049aef8ad86795e94006dea0e097a8add85665Hal Finkel // If the function does not have at least two blocks, then there is 12105ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel // nothing to do. 12115ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel if (MF.size() < 2) 12125ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel return Changed; 12135ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 12145ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel for (MachineFunction::iterator I = MF.begin(); I != MF.end();) { 12155ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel MachineBasicBlock &B = *I++; 12165ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel if (processBlock(B)) 12175ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel Changed = true; 12185ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel } 12195ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 12205ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel return Changed; 12215ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel } 12225ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 12235ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel virtual void getAnalysisUsage(AnalysisUsage &AU) const { 12245ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel MachineFunctionPass::getAnalysisUsage(AU); 12255ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel } 12265ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel }; 12275ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel} 12285ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 12295ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal FinkelINITIALIZE_PASS(PPCEarlyReturn, DEBUG_TYPE, 12305ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel "PowerPC Early-Return Creation", false, false) 12315ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 12325ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkelchar PPCEarlyReturn::ID = 0; 12335ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal FinkelFunctionPass* 12345ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkelllvm::createPPCEarlyReturnPass() { return new PPCEarlyReturn(); } 12355ee67e8e76dfcaffa5e776ef3d5eeb80807a627bHal Finkel 1236