PPCInstrInfo.h revision f2ccb77ee9d8ab35866dae111fa36929689c7511 
1//===- PPC32InstrInfo.h - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef POWERPC32_INSTRUCTIONINFO_H
15#define POWERPC32_INSTRUCTIONINFO_H
16
17#include "PowerPCInstrInfo.h"
18#include "PPC32RegisterInfo.h"
19
20namespace llvm {
21
22class PPC32InstrInfo : public TargetInstrInfo {
23  const PPC32RegisterInfo RI;
24public:
25  PPC32InstrInfo();
26
27  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
28  /// such, whenever a client has an instance of instruction info, it should
29  /// always be able to get register info as well (through this method).
30  ///
31  virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
32
33  //
34  // Return true if the instruction is a register to register move and
35  // leave the source and dest operands in the passed parameters.
36  //
37  virtual bool isMoveInstr(const MachineInstr& MI,
38                           unsigned& sourceReg,
39                           unsigned& destReg) const;
40
41  static unsigned invertPPCBranchOpcode(unsigned Opcode) {
42    switch (Opcode) {
43    default: assert(0 && "Unknown PPC branch opcode!");
44    case PPC::BEQ: return PPC::BNE;
45    case PPC::BNE: return PPC::BEQ;
46    case PPC::BLT: return PPC::BGE;
47    case PPC::BGE: return PPC::BLT;
48    case PPC::BGT: return PPC::BLE;
49    case PPC::BLE: return PPC::BGT;
50    }
51  }
52};
53
54}
55
56#endif
57