SparcISelLowering.h revision fcb25e60f514e4dbceecef73ac229c61d6202ed2
1//===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Sparc uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef SPARC_ISELLOWERING_H 16#define SPARC_ISELLOWERING_H 17 18#include "Sparc.h" 19#include "llvm/Target/TargetLowering.h" 20 21namespace llvm { 22 class SparcSubtarget; 23 24 namespace SPISD { 25 enum { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 CMPICC, // Compare two GPR operands, set icc. 28 CMPFCC, // Compare two FP operands, set fcc. 29 BRICC, // Branch to dest on icc condition 30 BRFCC, // Branch to dest on fcc condition 31 SELECT_ICC, // Select between two values using the current ICC flags. 32 SELECT_FCC, // Select between two values using the current FCC flags. 33 34 Hi, Lo, // Hi/Lo operations, typically on a global address. 35 36 FTOI, // FP to Int within a FP register. 37 ITOF, // Int to FP within a FP register. 38 39 CALL, // A call instruction. 40 RET_FLAG, // Return with a flag operand. 41 GLOBAL_BASE_REG, // Global base reg for PIC 42 FLUSHW // FLUSH register windows to stack 43 }; 44 } 45 46 class SparcTargetLowering : public TargetLowering { 47 const SparcSubtarget *Subtarget; 48 public: 49 SparcTargetLowering(TargetMachine &TM); 50 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 51 52 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 53 /// in Mask are known to be either zero or one and return them in the 54 /// KnownZero/KnownOne bitsets. 55 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 56 APInt &KnownZero, 57 APInt &KnownOne, 58 const SelectionDAG &DAG, 59 unsigned Depth = 0) const; 60 61 virtual MachineBasicBlock * 62 EmitInstrWithCustomInserter(MachineInstr *MI, 63 MachineBasicBlock *MBB) const; 64 65 virtual const char *getTargetNodeName(unsigned Opcode) const; 66 67 ConstraintType getConstraintType(const std::string &Constraint) const; 68 std::pair<unsigned, const TargetRegisterClass*> 69 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; 70 71 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 72 73 virtual SDValue 74 LowerFormalArguments(SDValue Chain, 75 CallingConv::ID CallConv, 76 bool isVarArg, 77 const SmallVectorImpl<ISD::InputArg> &Ins, 78 DebugLoc dl, SelectionDAG &DAG, 79 SmallVectorImpl<SDValue> &InVals) const; 80 81 virtual SDValue 82 LowerCall(TargetLowering::CallLoweringInfo &CLI, 83 SmallVectorImpl<SDValue> &InVals) const; 84 85 virtual SDValue 86 LowerReturn(SDValue Chain, 87 CallingConv::ID CallConv, bool isVarArg, 88 const SmallVectorImpl<ISD::OutputArg> &Outs, 89 const SmallVectorImpl<SDValue> &OutVals, 90 DebugLoc dl, SelectionDAG &DAG) const; 91 92 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 93 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 94 95 unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const; 96 }; 97} // end namespace llvm 98 99#endif // SPARC_ISELLOWERING_H 100