CodeEmitterGen.cpp revision f37dd02f7743ebd2424480361f5a7db510495c4f 
1//===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// CodeEmitterGen uses the descriptions of instructions and their fields to
11// construct an automated code emitter: a function that, given a MachineInstr,
12// returns the (currently, 32-bit unsigned) value of the instruction.
13//
14//===----------------------------------------------------------------------===//
15
16#include "CodeEmitterGen.h"
17#include "CodeGenTarget.h"
18#include "Record.h"
19#include "llvm/ADT/StringExtras.h"
20#include "llvm/Support/CommandLine.h"
21#include "llvm/Support/Debug.h"
22#include <map>
23using namespace llvm;
24
25// FIXME: Somewhat hackish to use a command line option for this. There should
26// be a CodeEmitter class in the Target.td that controls this sort of thing
27// instead.
28static cl::opt<bool>
29MCEmitter("mc-emitter",
30          cl::desc("Generate CodeEmitter for use with the MC library."),
31          cl::init(false));
32
33void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
34  for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
35       I != E; ++I) {
36    Record *R = *I;
37    if (R->getValueAsString("Namespace") == "TargetOpcode" ||
38        R->getValueAsBit("isPseudo"))
39      continue;
40
41    const BitsInit *BI = R->getValueAsBitsInit("Inst");
42
43    unsigned numBits = BI->getNumBits();
44
45    SmallVector<const Init *, 16> NewBits(numBits);
46
47    for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
48      unsigned bitSwapIdx = numBits - bit - 1;
49      const Init *OrigBit = BI->getBit(bit);
50      const Init *BitSwap = BI->getBit(bitSwapIdx);
51      NewBits[bit]        = BitSwap;
52      NewBits[bitSwapIdx] = OrigBit;
53    }
54    if (numBits % 2) {
55      unsigned middle = (numBits + 1) / 2;
56      NewBits[middle] = BI->getBit(middle);
57    }
58
59    BitsInit *NewBI = new BitsInit(ArrayRef<const Init *>(NewBits));
60
61    // Update the bits in reversed order so that emitInstrOpBits will get the
62    // correct endianness.
63    R->getValue("Inst")->setValue(NewBI);
64  }
65}
66
67// If the VarBitInit at position 'bit' matches the specified variable then
68// return the variable bit position.  Otherwise return -1.
69int CodeEmitterGen::getVariableBit(const std::string &VarName,
70                                   const BitsInit *BI, int bit) {
71  if (const VarBitInit *VBI = dynamic_cast<const VarBitInit*>(BI->getBit(bit))) {
72    if (const VarInit *VI = dynamic_cast<const VarInit*>(VBI->getVariable()))
73      if (VI->getName() == VarName)
74        return VBI->getBitNum();
75  } else if (const VarInit *VI = dynamic_cast<const VarInit*>(BI->getBit(bit))) {
76    if (VI->getName() == VarName)
77      return 0;
78  }
79
80  return -1;
81}
82
83void CodeEmitterGen::
84AddCodeToMergeInOperand(Record *R, const BitsInit *BI, const std::string &VarName,
85                        unsigned &NumberedOp,
86                        std::string &Case, CodeGenTarget &Target) {
87  CodeGenInstruction &CGI = Target.getInstruction(R);
88
89  // Determine if VarName actually contributes to the Inst encoding.
90  int bit = BI->getNumBits()-1;
91
92  // Scan for a bit that this contributed to.
93  for (; bit >= 0; ) {
94    if (getVariableBit(VarName, BI, bit) != -1)
95      break;
96
97    --bit;
98  }
99
100  // If we found no bits, ignore this value, otherwise emit the call to get the
101  // operand encoding.
102  if (bit < 0) return;
103
104  // If the operand matches by name, reference according to that
105  // operand number. Non-matching operands are assumed to be in
106  // order.
107  unsigned OpIdx;
108  if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
109    // Get the machine operand number for the indicated operand.
110    OpIdx = CGI.Operands[OpIdx].MIOperandNo;
111    assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
112           "Explicitly used operand also marked as not emitted!");
113  } else {
114    /// If this operand is not supposed to be emitted by the
115    /// generated emitter, skip it.
116    while (CGI.Operands.isFlatOperandNotEmitted(NumberedOp))
117      ++NumberedOp;
118    OpIdx = NumberedOp++;
119  }
120
121  std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
122  std::string &EncoderMethodName = CGI.Operands[SO.first].EncoderMethodName;
123
124  // If the source operand has a custom encoder, use it. This will
125  // get the encoding for all of the suboperands.
126  if (!EncoderMethodName.empty()) {
127    // A custom encoder has all of the information for the
128    // sub-operands, if there are more than one, so only
129    // query the encoder once per source operand.
130    if (SO.second == 0) {
131      Case += "      // op: " + VarName + "\n" +
132              "      op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
133      if (MCEmitter)
134        Case += ", Fixups";
135      Case += ");\n";
136    }
137  } else {
138    Case += "      // op: " + VarName + "\n" +
139      "      op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
140    if (MCEmitter)
141      Case += ", Fixups";
142    Case += ");\n";
143  }
144
145  for (; bit >= 0; ) {
146    int varBit = getVariableBit(VarName, BI, bit);
147
148    // If this bit isn't from a variable, skip it.
149    if (varBit == -1) {
150      --bit;
151      continue;
152    }
153
154    // Figure out the consecutive range of bits covered by this operand, in
155    // order to generate better encoding code.
156    int beginInstBit = bit;
157    int beginVarBit = varBit;
158    int N = 1;
159    for (--bit; bit >= 0;) {
160      varBit = getVariableBit(VarName, BI, bit);
161      if (varBit == -1 || varBit != (beginVarBit - N)) break;
162      ++N;
163      --bit;
164    }
165
166    unsigned opMask = ~0U >> (32-N);
167    int opShift = beginVarBit - N + 1;
168    opMask <<= opShift;
169    opShift = beginInstBit - beginVarBit;
170
171    if (opShift > 0) {
172      Case += "      Value |= (op & " + utostr(opMask) + "U) << " +
173              itostr(opShift) + ";\n";
174    } else if (opShift < 0) {
175      Case += "      Value |= (op & " + utostr(opMask) + "U) >> " +
176              itostr(-opShift) + ";\n";
177    } else {
178      Case += "      Value |= op & " + utostr(opMask) + "U;\n";
179    }
180  }
181}
182
183
184std::string CodeEmitterGen::getInstructionCase(Record *R,
185                                               CodeGenTarget &Target) {
186  std::string Case;
187
188  const BitsInit *BI = R->getValueAsBitsInit("Inst");
189  const std::vector<RecordVal> &Vals = R->getValues();
190  unsigned NumberedOp = 0;
191
192  // Loop over all of the fields in the instruction, determining which are the
193  // operands to the instruction.
194  for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
195    // Ignore fixed fields in the record, we're looking for values like:
196    //    bits<5> RST = { ?, ?, ?, ?, ? };
197    if (Vals[i].getPrefix() || Vals[i].getValue()->isComplete())
198      continue;
199
200    AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp, Case, Target);
201  }
202
203  std::string PostEmitter = R->getValueAsString("PostEncoderMethod");
204  if (!PostEmitter.empty())
205    Case += "      Value = " + PostEmitter + "(MI, Value);\n";
206
207  return Case;
208}
209
210void CodeEmitterGen::run(raw_ostream &o) {
211  CodeGenTarget Target(Records);
212  std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
213
214  // For little-endian instruction bit encodings, reverse the bit order
215  if (Target.isLittleEndianEncoding()) reverseBits(Insts);
216
217  EmitSourceFileHeader("Machine Code Emitter", o);
218
219  const std::vector<const CodeGenInstruction*> &NumberedInstructions =
220    Target.getInstructionsByEnumValue();
221
222  // Emit function declaration
223  o << "unsigned " << Target.getName();
224  if (MCEmitter)
225    o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
226      << "    SmallVectorImpl<MCFixup> &Fixups) const {\n";
227  else
228    o << "CodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const {\n";
229
230  // Emit instruction base values
231  o << "  static const unsigned InstBits[] = {\n";
232  for (std::vector<const CodeGenInstruction*>::const_iterator
233          IN = NumberedInstructions.begin(),
234          EN = NumberedInstructions.end();
235       IN != EN; ++IN) {
236    const CodeGenInstruction *CGI = *IN;
237    Record *R = CGI->TheDef;
238
239    if (R->getValueAsString("Namespace") == "TargetOpcode" ||
240        R->getValueAsBit("isPseudo")) {
241      o << "    0U,\n";
242      continue;
243    }
244
245    const BitsInit *BI = R->getValueAsBitsInit("Inst");
246
247    // Start by filling in fixed values.
248    unsigned Value = 0;
249    for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
250      if (const BitInit *B = dynamic_cast<const BitInit*>(BI->getBit(e-i-1)))
251        Value |= B->getValue() << (e-i-1);
252    }
253    o << "    " << Value << "U," << '\t' << "// " << R->getName() << "\n";
254  }
255  o << "    0U\n  };\n";
256
257  // Map to accumulate all the cases.
258  std::map<std::string, std::vector<std::string> > CaseMap;
259
260  // Construct all cases statement for each opcode
261  for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
262        IC != EC; ++IC) {
263    Record *R = *IC;
264    if (R->getValueAsString("Namespace") == "TargetOpcode" ||
265        R->getValueAsBit("isPseudo"))
266      continue;
267    const std::string &InstName = R->getValueAsString("Namespace") + "::"
268      + R->getName();
269    std::string Case = getInstructionCase(R, Target);
270
271    CaseMap[Case].push_back(InstName);
272  }
273
274  // Emit initial function code
275  o << "  const unsigned opcode = MI.getOpcode();\n"
276    << "  unsigned Value = InstBits[opcode];\n"
277    << "  unsigned op = 0;\n"
278    << "  (void)op;  // suppress warning\n"
279    << "  switch (opcode) {\n";
280
281  // Emit each case statement
282  std::map<std::string, std::vector<std::string> >::iterator IE, EE;
283  for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
284    const std::string &Case = IE->first;
285    std::vector<std::string> &InstList = IE->second;
286
287    for (int i = 0, N = InstList.size(); i < N; i++) {
288      if (i) o << "\n";
289      o << "    case " << InstList[i]  << ":";
290    }
291    o << " {\n";
292    o << Case;
293    o << "      break;\n"
294      << "    }\n";
295  }
296
297  // Default case: unhandled opcode
298  o << "  default:\n"
299    << "    std::string msg;\n"
300    << "    raw_string_ostream Msg(msg);\n"
301    << "    Msg << \"Not supported instr: \" << MI;\n"
302    << "    report_fatal_error(Msg.str());\n"
303    << "  }\n"
304    << "  return Value;\n"
305    << "}\n\n";
306}
307