1//===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file is part of the X86 Disassembler Emitter. 11// It contains the interface of a single recognizable instruction. 12// Documentation for the disassembler emitter in general can be found in 13// X86DisasemblerEmitter.h. 14// 15//===----------------------------------------------------------------------===// 16 17#ifndef X86RECOGNIZABLEINSTR_H 18#define X86RECOGNIZABLEINSTR_H 19 20#include "CodeGenTarget.h" 21#include "X86DisassemblerTables.h" 22#include "llvm/ADT/SmallVector.h" 23#include "llvm/Support/DataTypes.h" 24#include "llvm/TableGen/Record.h" 25 26namespace llvm { 27 28namespace X86Disassembler { 29 30/// RecognizableInstr - Encapsulates all information required to decode a single 31/// instruction, as extracted from the LLVM instruction tables. Has methods 32/// to interpret the information available in the LLVM tables, and to emit the 33/// instruction into DisassemblerTables. 34class RecognizableInstr { 35private: 36 /// The opcode of the instruction, as used in an MCInst 37 InstrUID UID; 38 /// The record from the .td files corresponding to this instruction 39 const Record* Rec; 40 /// The prefix field from the record 41 uint8_t Prefix; 42 /// The opcode field from the record; this is the opcode used in the Intel 43 /// encoding and therefore distinct from the UID 44 uint8_t Opcode; 45 /// The form field from the record 46 uint8_t Form; 47 /// The segment override field from the record 48 uint8_t SegOvr; 49 /// The hasOpSizePrefix field from the record 50 bool HasOpSizePrefix; 51 /// The hasAdSizePrefix field from the record 52 bool HasAdSizePrefix; 53 /// The hasREX_WPrefix field from the record 54 bool HasREX_WPrefix; 55 /// The hasVEXPrefix field from the record 56 bool HasVEXPrefix; 57 /// The hasVEX_4VPrefix field from the record 58 bool HasVEX_4VPrefix; 59 /// The hasVEX_4VOp3Prefix field from the record 60 bool HasVEX_4VOp3Prefix; 61 /// The hasVEX_WPrefix field from the record 62 bool HasVEX_WPrefix; 63 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set 64 bool HasVEX_LPrefix; 65 /// The hasMemOp4Prefix field from the record 66 bool HasMemOp4Prefix; 67 /// The ignoreVEX_L field from the record 68 bool IgnoresVEX_L; 69 /// The hasEVEXPrefix field from the record 70 bool HasEVEXPrefix; 71 /// The hasEVEX_L2Prefix field from the record 72 bool HasEVEX_L2Prefix; 73 /// The hasEVEX_K field from the record 74 bool HasEVEX_K; 75 /// The hasEVEX_B field from the record 76 bool HasEVEX_B; 77 /// The hasLockPrefix field from the record 78 bool HasLockPrefix; 79 /// The isCodeGenOnly filed from the record 80 bool IsCodeGenOnly; 81 // Whether the instruction has the predicate "In64BitMode" 82 bool Is64Bit; 83 // Whether the instruction has the predicate "In32BitMode" 84 bool Is32Bit; 85 86 /// The instruction name as listed in the tables 87 std::string Name; 88 /// The AT&T AsmString for the instruction 89 std::string AsmString; 90 91 /// Indicates whether the instruction is SSE 92 bool IsSSE; 93 /// Indicates whether the instruction has FR operands - MOVs with FR operands 94 /// are typically ignored 95 bool HasFROperands; 96 /// Indicates whether the instruction should be emitted into the decode 97 /// tables; regardless, it will be emitted into the instruction info table 98 bool ShouldBeEmitted; 99 100 /// The operands of the instruction, as listed in the CodeGenInstruction. 101 /// They are not one-to-one with operands listed in the MCInst; for example, 102 /// memory operands expand to 5 operands in the MCInst 103 const std::vector<CGIOperandList::OperandInfo>* Operands; 104 105 /// The description of the instruction that is emitted into the instruction 106 /// info table 107 InstructionSpecifier* Spec; 108 109 /// insnContext - Returns the primary context in which the instruction is 110 /// valid. 111 /// 112 /// @return - The context in which the instruction is valid. 113 InstructionContext insnContext() const; 114 115 enum filter_ret { 116 FILTER_STRONG, // instruction has no place in the instruction tables 117 FILTER_WEAK, // instruction may conflict, and should be eliminated if 118 // it does 119 FILTER_NORMAL // instruction should have high priority and generate an 120 // error if it conflcits with any other FILTER_NORMAL 121 // instruction 122 }; 123 124 /// filter - Determines whether the instruction should be decodable. Some 125 /// instructions are pure intrinsics and use unencodable operands; many 126 /// synthetic instructions are duplicates of other instructions; other 127 /// instructions only differ in the logical way in which they are used, and 128 /// have the same decoding. Because these would cause decode conflicts, 129 /// they must be filtered out. 130 /// 131 /// @return - The degree of filtering to be applied (see filter_ret). 132 filter_ret filter() const; 133 134 /// hasFROperands - Returns true if any operand is a FR operand. 135 bool hasFROperands() const; 136 137 /// typeFromString - Translates an operand type from the string provided in 138 /// the LLVM tables to an OperandType for use in the operand specifier. 139 /// 140 /// @param s - The string, as extracted by calling Rec->getName() 141 /// on a CodeGenInstruction::OperandInfo. 142 /// @param isSSE - Indicates whether the instruction is an SSE 143 /// instruction. For SSE instructions, immediates are 144 /// fixed-size rather than being affected by the 145 /// mandatory OpSize prefix. 146 /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W 147 /// prefix. If it does, 32-bit register operands stay 148 /// 32-bit regardless of the operand size. 149 /// @param hasOpSizePrefix Indicates whether the instruction has an OpSize 150 /// prefix. If it does not, then 16-bit register 151 /// operands stay 16-bit. 152 /// @return - The operand's type. 153 static OperandType typeFromString(const std::string& s, 154 bool isSSE, 155 bool hasREX_WPrefix, 156 bool hasOpSizePrefix); 157 158 /// immediateEncodingFromString - Translates an immediate encoding from the 159 /// string provided in the LLVM tables to an OperandEncoding for use in 160 /// the operand specifier. 161 /// 162 /// @param s - See typeFromString(). 163 /// @param hasOpSizePrefix - Indicates whether the instruction has an OpSize 164 /// prefix. If it does not, then 16-bit immediate 165 /// operands stay 16-bit. 166 /// @return - The operand's encoding. 167 static OperandEncoding immediateEncodingFromString(const std::string &s, 168 bool hasOpSizePrefix); 169 170 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 171 /// handles operands that are in the REG field of the ModR/M byte. 172 static OperandEncoding rmRegisterEncodingFromString(const std::string &s, 173 bool hasOpSizePrefix); 174 175 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 176 /// handles operands that are in the REG field of the ModR/M byte. 177 static OperandEncoding roRegisterEncodingFromString(const std::string &s, 178 bool hasOpSizePrefix); 179 static OperandEncoding memoryEncodingFromString(const std::string &s, 180 bool hasOpSizePrefix); 181 static OperandEncoding relocationEncodingFromString(const std::string &s, 182 bool hasOpSizePrefix); 183 static OperandEncoding opcodeModifierEncodingFromString(const std::string &s, 184 bool hasOpSizePrefix); 185 static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s, 186 bool HasOpSizePrefix); 187 static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s, 188 bool HasOpSizePrefix); 189 190 /// handleOperand - Converts a single operand from the LLVM table format to 191 /// the emitted table format, handling any duplicate operands it encounters 192 /// and then one non-duplicate. 193 /// 194 /// @param optional - Determines whether to assert that the 195 /// operand exists. 196 /// @param operandIndex - The index into the generated operand table. 197 /// Incremented by this function one or more 198 /// times to reflect possible duplicate 199 /// operands). 200 /// @param physicalOperandIndex - The index of the current operand into the 201 /// set of non-duplicate ('physical') operands. 202 /// Incremented by this function once. 203 /// @param numPhysicalOperands - The number of non-duplicate operands in the 204 /// instructions. 205 /// @param operandMapping - The operand mapping, which has an entry for 206 /// each operand that indicates whether it is a 207 /// duplicate, and of what. 208 void handleOperand(bool optional, 209 unsigned &operandIndex, 210 unsigned &physicalOperandIndex, 211 unsigned &numPhysicalOperands, 212 const unsigned *operandMapping, 213 OperandEncoding (*encodingFromString) 214 (const std::string&, 215 bool hasOpSizePrefix)); 216 217 /// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter() 218 /// filters out many instructions, at various points in decoding we 219 /// determine that the instruction should not actually be decodable. In 220 /// particular, MMX MOV instructions aren't emitted, but they're only 221 /// identified during operand parsing. 222 /// 223 /// @return - true if at this point we believe the instruction should be 224 /// emitted; false if not. This will return false if filter() returns false 225 /// once emitInstructionSpecifier() has been called. 226 bool shouldBeEmitted() const { 227 return ShouldBeEmitted; 228 } 229 230 /// emitInstructionSpecifier - Loads the instruction specifier for the current 231 /// instruction into a DisassemblerTables. 232 /// 233 /// \param tables The DisassemblerTables to populate with the specifier for 234 /// the current instruction. 235 void emitInstructionSpecifier(DisassemblerTables &tables); 236 237 /// emitDecodePath - Populates the proper fields in the decode tables 238 /// corresponding to the decode paths for this instruction. 239 /// 240 /// \param tables The DisassemblerTables to populate with the decode 241 /// decode information for the current instruction. 242 void emitDecodePath(DisassemblerTables &tables) const; 243 244 /// Constructor - Initializes a RecognizableInstr with the appropriate fields 245 /// from a CodeGenInstruction. 246 /// 247 /// \param tables The DisassemblerTables that the specifier will be added to. 248 /// \param insn The CodeGenInstruction to extract information from. 249 /// \param uid The unique ID of the current instruction. 250 RecognizableInstr(DisassemblerTables &tables, 251 const CodeGenInstruction &insn, 252 InstrUID uid); 253public: 254 /// processInstr - Accepts a CodeGenInstruction and loads decode information 255 /// for it into a DisassemblerTables if appropriate. 256 /// 257 /// \param tables The DiassemblerTables to be populated with decode 258 /// information. 259 /// \param insn The CodeGenInstruction to be used as a source for this 260 /// information. 261 /// \param uid The unique ID of the instruction. 262 static void processInstr(DisassemblerTables &tables, 263 const CodeGenInstruction &insn, 264 InstrUID uid); 265}; 266 267} // namespace X86Disassembler 268 269} // namespace llvm 270 271#endif 272