nv50_screen.c revision 587c221a29fe01e24c69952a7a9b0034f7652e4e
1/* 2 * Copyright 2010 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23#include "util/u_format.h" 24#include "util/u_format_s3tc.h" 25#include "pipe/p_screen.h" 26 27#include "nv50_context.h" 28#include "nv50_screen.h" 29 30#include "nouveau/nv_object.xml.h" 31 32#ifndef NOUVEAU_GETPARAM_GRAPH_UNITS 33# define NOUVEAU_GETPARAM_GRAPH_UNITS 13 34#endif 35 36static boolean 37nv50_screen_is_format_supported(struct pipe_screen *pscreen, 38 enum pipe_format format, 39 enum pipe_texture_target target, 40 unsigned sample_count, 41 unsigned bindings) 42{ 43 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */ 44 return FALSE; 45 if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128) 46 return FALSE; 47 48 if (!util_format_is_supported(format, bindings)) 49 return FALSE; 50 51 switch (format) { 52 case PIPE_FORMAT_Z16_UNORM: 53 if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS) 54 return FALSE; 55 break; 56 case PIPE_FORMAT_R8G8B8A8_UNORM: 57 case PIPE_FORMAT_R8G8B8X8_UNORM: 58 /* HACK: GL requires equal formats for MS resolve and window is BGRA */ 59 if (bindings & PIPE_BIND_RENDER_TARGET) 60 return FALSE; 61 default: 62 break; 63 } 64 65 /* transfers & shared are always supported */ 66 bindings &= ~(PIPE_BIND_TRANSFER_READ | 67 PIPE_BIND_TRANSFER_WRITE | 68 PIPE_BIND_SHARED); 69 70 return (nv50_format_table[format].usage & bindings) == bindings; 71} 72 73static int 74nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) 75{ 76 switch (param) { 77 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 78 return 64; 79 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 80 return 14; 81 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 82 return 12; 83 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 84 return 14; 85 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: /* shader support missing */ 86 return 0; 87 case PIPE_CAP_MIN_TEXEL_OFFSET: 88 return -8; 89 case PIPE_CAP_MAX_TEXEL_OFFSET: 90 return 7; 91 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 92 case PIPE_CAP_TEXTURE_SWIZZLE: 93 case PIPE_CAP_TEXTURE_SHADOW_MAP: 94 case PIPE_CAP_NPOT_TEXTURES: 95 case PIPE_CAP_ANISOTROPIC_FILTER: 96 case PIPE_CAP_SCALED_RESOLVE: 97 return 1; 98 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 99 case PIPE_CAP_SEAMLESS_CUBE_MAP: 100 return nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS; 101 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 102 return 0; 103 case PIPE_CAP_TWO_SIDED_STENCIL: 104 case PIPE_CAP_DEPTH_CLIP_DISABLE: 105 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 106 case PIPE_CAP_POINT_SPRITE: 107 return 1; 108 case PIPE_CAP_SM3: 109 return 1; 110 case PIPE_CAP_GLSL_FEATURE_LEVEL: 111 return 130; 112 case PIPE_CAP_MAX_RENDER_TARGETS: 113 return 8; 114 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: 115 return 1; 116 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 117 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 118 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 119 return 1; 120 case PIPE_CAP_TIMER_QUERY: 121 case PIPE_CAP_OCCLUSION_QUERY: 122 return 1; 123 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 124 return 0; 125 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 126 return 128; 127 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 128 return 32; 129 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 130 case PIPE_CAP_INDEP_BLEND_ENABLE: 131 return 1; 132 case PIPE_CAP_INDEP_BLEND_FUNC: 133 return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS; 134 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 135 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 136 return 1; 137 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 138 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 139 return 0; 140 case PIPE_CAP_SHADER_STENCIL_EXPORT: 141 return 0; 142 case PIPE_CAP_PRIMITIVE_RESTART: 143 case PIPE_CAP_TGSI_INSTANCEID: 144 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 145 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 146 case PIPE_CAP_CONDITIONAL_RENDER: 147 case PIPE_CAP_TEXTURE_BARRIER: 148 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 149 return 1; 150 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS: 151 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 152 return 0; /* state trackers will know better */ 153 case PIPE_CAP_USER_VERTEX_BUFFERS: 154 return 1; 155 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 156 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 157 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 158 return 0; 159 default: 160 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); 161 return 0; 162 } 163} 164 165static int 166nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, 167 enum pipe_shader_cap param) 168{ 169 switch (shader) { 170 case PIPE_SHADER_VERTEX: 171 case PIPE_SHADER_GEOMETRY: 172 case PIPE_SHADER_FRAGMENT: 173 break; 174 default: 175 return 0; 176 } 177 178 switch (param) { 179 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 180 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 181 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 182 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 183 return 16384; 184 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 185 return 4; 186 case PIPE_SHADER_CAP_MAX_INPUTS: 187 if (shader == PIPE_SHADER_VERTEX) 188 return 32; 189 return 0x300 / 16; 190 case PIPE_SHADER_CAP_MAX_CONSTS: 191 return 65536 / 16; 192 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 193 return 14; 194 case PIPE_SHADER_CAP_MAX_ADDRS: 195 return 1; 196 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 197 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 198 return shader != PIPE_SHADER_FRAGMENT; 199 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 200 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 201 return 1; 202 case PIPE_SHADER_CAP_MAX_PREDS: 203 return 0; 204 case PIPE_SHADER_CAP_MAX_TEMPS: 205 return NV50_CAP_MAX_PROGRAM_TEMPS; 206 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 207 return 1; 208 case PIPE_SHADER_CAP_SUBROUTINES: 209 return 0; /* please inline, or provide function declarations */ 210 case PIPE_SHADER_CAP_INTEGERS: 211 return 1; 212 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 213 return 32; 214 default: 215 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param); 216 return 0; 217 } 218} 219 220static float 221nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) 222{ 223 switch (param) { 224 case PIPE_CAPF_MAX_LINE_WIDTH: 225 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 226 return 10.0f; 227 case PIPE_CAPF_MAX_POINT_WIDTH: 228 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 229 return 64.0f; 230 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 231 return 16.0f; 232 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 233 return 4.0f; 234 default: 235 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); 236 return 0.0f; 237 } 238} 239 240static void 241nv50_screen_destroy(struct pipe_screen *pscreen) 242{ 243 struct nv50_screen *screen = nv50_screen(pscreen); 244 245 if (screen->base.fence.current) { 246 nouveau_fence_wait(screen->base.fence.current); 247 nouveau_fence_ref (NULL, &screen->base.fence.current); 248 } 249 if (screen->base.pushbuf) 250 screen->base.pushbuf->user_priv = NULL; 251 252 if (screen->blitctx) 253 FREE(screen->blitctx); 254 255 nouveau_bo_ref(NULL, &screen->code); 256 nouveau_bo_ref(NULL, &screen->tls_bo); 257 nouveau_bo_ref(NULL, &screen->stack_bo); 258 nouveau_bo_ref(NULL, &screen->txc); 259 nouveau_bo_ref(NULL, &screen->uniforms); 260 nouveau_bo_ref(NULL, &screen->fence.bo); 261 262 nouveau_heap_destroy(&screen->vp_code_heap); 263 nouveau_heap_destroy(&screen->gp_code_heap); 264 nouveau_heap_destroy(&screen->fp_code_heap); 265 266 if (screen->tic.entries) 267 FREE(screen->tic.entries); 268 269 nouveau_object_del(&screen->tesla); 270 nouveau_object_del(&screen->eng2d); 271 nouveau_object_del(&screen->m2mf); 272 nouveau_object_del(&screen->sync); 273 274 nouveau_screen_fini(&screen->base); 275 276 FREE(screen); 277} 278 279static void 280nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence) 281{ 282 struct nv50_screen *screen = nv50_screen(pscreen); 283 struct nouveau_pushbuf *push = screen->base.pushbuf; 284 285 /* we need to do it after possible flush in MARK_RING */ 286 *sequence = ++screen->base.fence.sequence; 287 288 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4)); 289 PUSH_DATAh(push, screen->fence.bo->offset); 290 PUSH_DATA (push, screen->fence.bo->offset); 291 PUSH_DATA (push, *sequence); 292 PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 | 293 NV50_3D_QUERY_GET_UNK4 | 294 NV50_3D_QUERY_GET_UNIT_CROP | 295 NV50_3D_QUERY_GET_TYPE_QUERY | 296 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO | 297 NV50_3D_QUERY_GET_SHORT); 298} 299 300static u32 301nv50_screen_fence_update(struct pipe_screen *pscreen) 302{ 303 return nv50_screen(pscreen)->fence.map[0]; 304} 305 306static int 307nv50_screen_init_hwctx(struct nv50_screen *screen, unsigned tls_space) 308{ 309 struct nouveau_pushbuf *push = screen->base.pushbuf; 310 struct nv04_fifo *fifo; 311 unsigned i; 312 313 fifo = (struct nv04_fifo *)screen->base.channel->data; 314 315 BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1); 316 PUSH_DATA (push, screen->m2mf->handle); 317 BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3); 318 PUSH_DATA (push, screen->sync->handle); 319 PUSH_DATA (push, fifo->vram); 320 PUSH_DATA (push, fifo->vram); 321 322 BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1); 323 PUSH_DATA (push, screen->eng2d->handle); 324 BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4); 325 PUSH_DATA (push, screen->sync->handle); 326 PUSH_DATA (push, fifo->vram); 327 PUSH_DATA (push, fifo->vram); 328 PUSH_DATA (push, fifo->vram); 329 BEGIN_NV04(push, NV50_2D(OPERATION), 1); 330 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY); 331 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1); 332 PUSH_DATA (push, 0); 333 BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1); 334 PUSH_DATA (push, 0); 335 BEGIN_NV04(push, SUBC_2D(0x0888), 1); 336 PUSH_DATA (push, 1); 337 338 BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1); 339 PUSH_DATA (push, screen->tesla->handle); 340 341 BEGIN_NV04(push, NV50_3D(COND_MODE), 1); 342 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS); 343 344 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1); 345 PUSH_DATA (push, screen->sync->handle); 346 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11); 347 for (i = 0; i < 11; ++i) 348 PUSH_DATA(push, fifo->vram); 349 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN); 350 for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i) 351 PUSH_DATA(push, fifo->vram); 352 353 BEGIN_NV04(push, NV50_3D(REG_MODE), 1); 354 PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED); 355 BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1); 356 PUSH_DATA (push, 0xf); 357 358 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) { 359 BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1); 360 PUSH_DATA (push, 0x18); 361 } 362 363 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1); 364 PUSH_DATA (push, 1); 365 366 BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1); 367 PUSH_DATA (push, 0); 368 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1); 369 PUSH_DATA (push, 0); 370 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1); 371 PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1); 372 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1); 373 PUSH_DATA (push, 0); 374 BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1); 375 PUSH_DATA (push, 0); 376 BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1); 377 PUSH_DATA (push, 1); 378 379 if (screen->tesla->oclass >= NVA0_3D_CLASS) { 380 BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1); 381 PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP); 382 } 383 384 BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1); 385 PUSH_DATA (push, 0); 386 BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2); 387 PUSH_DATA (push, 0); 388 PUSH_DATA (push, 0); 389 BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1); 390 PUSH_DATA (push, 0x3f); 391 392 BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2); 393 PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2)); 394 PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2)); 395 396 BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2); 397 PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2)); 398 PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2)); 399 400 BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2); 401 PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2)); 402 PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2)); 403 404 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3); 405 PUSH_DATAh(push, screen->tls_bo->offset); 406 PUSH_DATA (push, screen->tls_bo->offset); 407 PUSH_DATA (push, util_logbase2(tls_space / 8)); 408 409 BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3); 410 PUSH_DATAh(push, screen->stack_bo->offset); 411 PUSH_DATA (push, screen->stack_bo->offset); 412 PUSH_DATA (push, 4); 413 414 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); 415 PUSH_DATAh(push, screen->uniforms->offset + (0 << 16)); 416 PUSH_DATA (push, screen->uniforms->offset + (0 << 16)); 417 PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000); 418 419 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); 420 PUSH_DATAh(push, screen->uniforms->offset + (1 << 16)); 421 PUSH_DATA (push, screen->uniforms->offset + (1 << 16)); 422 PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000); 423 424 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); 425 PUSH_DATAh(push, screen->uniforms->offset + (2 << 16)); 426 PUSH_DATA (push, screen->uniforms->offset + (2 << 16)); 427 PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000); 428 429 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); 430 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16)); 431 PUSH_DATA (push, screen->uniforms->offset + (3 << 16)); 432 PUSH_DATA (push, (NV50_CB_AUX << 16) | 0x0200); 433 434 BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 6); 435 PUSH_DATA (push, (NV50_CB_PVP << 12) | 0x001); 436 PUSH_DATA (push, (NV50_CB_PGP << 12) | 0x021); 437 PUSH_DATA (push, (NV50_CB_PFP << 12) | 0x031); 438 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01); 439 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21); 440 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31); 441 442 /* max TIC (bits 4:8) & TSC bindings, per program type */ 443 for (i = 0; i < 3; ++i) { 444 BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1); 445 PUSH_DATA (push, 0x54); 446 } 447 448 BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3); 449 PUSH_DATAh(push, screen->txc->offset); 450 PUSH_DATA (push, screen->txc->offset); 451 PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1); 452 453 BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3); 454 PUSH_DATAh(push, screen->txc->offset + 65536); 455 PUSH_DATA (push, screen->txc->offset + 65536); 456 PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1); 457 458 BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1); 459 PUSH_DATA (push, 0); 460 461 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1); 462 PUSH_DATA (push, 0); 463 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1); 464 PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY); 465 BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2); 466 for (i = 0; i < 8 * 2; ++i) 467 PUSH_DATA(push, 0); 468 BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1); 469 PUSH_DATA (push, 0); 470 471 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1); 472 PUSH_DATA (push, 1); 473 BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(0)), 2); 474 PUSH_DATAf(push, 0.0f); 475 PUSH_DATAf(push, 1.0f); 476 477 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1); 478#ifdef NV50_SCISSORS_CLIPPING 479 PUSH_DATA (push, 0x0000); 480#else 481 PUSH_DATA (push, 0x1080); 482#endif 483 484 BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1); 485 PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT); 486 487 /* We use scissors instead of exact view volume clipping, 488 * so they're always enabled. 489 */ 490 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 3); 491 PUSH_DATA (push, 1); 492 PUSH_DATA (push, 8192 << 16); 493 PUSH_DATA (push, 8192 << 16); 494 495 BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1); 496 PUSH_DATA (push, 1); 497 BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1); 498 PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL); 499 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1); 500 PUSH_DATA (push, 0x11111111); 501 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1); 502 PUSH_DATA (push, 1); 503 504 PUSH_KICK (push); 505 506 return 0; 507} 508 509#define FAIL_SCREEN_INIT(str, err) \ 510 do { \ 511 NOUVEAU_ERR(str, err); \ 512 nv50_screen_destroy(pscreen); \ 513 return NULL; \ 514 } while(0) 515 516struct pipe_screen * 517nv50_screen_create(struct nouveau_device *dev) 518{ 519 struct nv50_screen *screen; 520 struct pipe_screen *pscreen; 521 struct nouveau_object *chan; 522 uint64_t value; 523 uint32_t tesla_class; 524 unsigned stack_size, max_warps, tls_space; 525 int ret; 526 527 screen = CALLOC_STRUCT(nv50_screen); 528 if (!screen) 529 return NULL; 530 pscreen = &screen->base.base; 531 532 screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER; 533 534 ret = nouveau_screen_init(&screen->base, dev); 535 if (ret) 536 FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret); 537 538 screen->base.pushbuf->user_priv = screen; 539 screen->base.pushbuf->rsvd_kick = 5; 540 541 chan = screen->base.channel; 542 543 pscreen->destroy = nv50_screen_destroy; 544 pscreen->context_create = nv50_create; 545 pscreen->is_format_supported = nv50_screen_is_format_supported; 546 pscreen->get_param = nv50_screen_get_param; 547 pscreen->get_shader_param = nv50_screen_get_shader_param; 548 pscreen->get_paramf = nv50_screen_get_paramf; 549 550 nv50_screen_init_resource_functions(pscreen); 551 552 nouveau_screen_init_vdec(&screen->base); 553 554 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, 555 NULL, &screen->fence.bo); 556 if (ret) 557 goto fail; 558 nouveau_bo_map(screen->fence.bo, 0, NULL); 559 screen->fence.map = screen->fence.bo->map; 560 screen->base.fence.emit = nv50_screen_fence_emit; 561 screen->base.fence.update = nv50_screen_fence_update; 562 563 ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS, 564 &(struct nv04_notify){ .length = 32 }, 565 sizeof(struct nv04_notify), &screen->sync); 566 if (ret) 567 FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret); 568 569 570 ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS, 571 NULL, 0, &screen->m2mf); 572 if (ret) 573 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret); 574 575 576 ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS, 577 NULL, 0, &screen->eng2d); 578 if (ret) 579 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret); 580 581 switch (dev->chipset & 0xf0) { 582 case 0x50: 583 tesla_class = NV50_3D_CLASS; 584 break; 585 case 0x80: 586 case 0x90: 587 tesla_class = NV84_3D_CLASS; 588 break; 589 case 0xa0: 590 switch (dev->chipset) { 591 case 0xa0: 592 case 0xaa: 593 case 0xac: 594 tesla_class = NVA0_3D_CLASS; 595 break; 596 case 0xaf: 597 tesla_class = NVAF_3D_CLASS; 598 break; 599 default: 600 tesla_class = NVA3_3D_CLASS; 601 break; 602 } 603 break; 604 default: 605 FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev->chipset); 606 break; 607 } 608 screen->base.class_3d = tesla_class; 609 610 ret = nouveau_object_new(chan, 0xbeef5097, tesla_class, 611 NULL, 0, &screen->tesla); 612 if (ret) 613 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret); 614 615 616 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 617 3 << NV50_CODE_BO_SIZE_LOG2, NULL, &screen->code); 618 if (ret) 619 goto fail; 620 621 nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2); 622 nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2); 623 nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2); 624 625 nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value); 626 627 max_warps = util_bitcount(value & 0xffff); 628 max_warps *= util_bitcount((value >> 24) & 0xf) * 32; 629 630 stack_size = max_warps * 64 * 8; 631 632 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL, 633 &screen->stack_bo); 634 if (ret) 635 FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret); 636 637 tls_space = NV50_CAP_MAX_PROGRAM_TEMPS * 16; 638 639 screen->tls_size = tls_space * max_warps * 32; 640 641 if (nouveau_mesa_debug) 642 debug_printf("max_warps = %i, tls_size = %"PRIu64" KiB\n", 643 max_warps, screen->tls_size >> 10); 644 645 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, screen->tls_size, NULL, 646 &screen->tls_bo); 647 if (ret) 648 FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret); 649 650 651 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL, 652 &screen->uniforms); 653 if (ret) 654 goto fail; 655 656 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL, 657 &screen->txc); 658 if (ret) 659 FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret); 660 661 screen->tic.entries = CALLOC(4096, sizeof(void *)); 662 screen->tsc.entries = screen->tic.entries + 2048; 663 664 665 if (!nv50_blitctx_create(screen)) 666 goto fail; 667 668 if (nv50_screen_init_hwctx(screen, tls_space)) 669 goto fail; 670 671 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE); 672 673 return pscreen; 674 675fail: 676 nv50_screen_destroy(pscreen); 677 return NULL; 678} 679 680int 681nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry) 682{ 683 int i = screen->tic.next; 684 685 while (screen->tic.lock[i / 32] & (1 << (i % 32))) 686 i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1); 687 688 screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1); 689 690 if (screen->tic.entries[i]) 691 nv50_tic_entry(screen->tic.entries[i])->id = -1; 692 693 screen->tic.entries[i] = entry; 694 return i; 695} 696 697int 698nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry) 699{ 700 int i = screen->tsc.next; 701 702 while (screen->tsc.lock[i / 32] & (1 << (i % 32))) 703 i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1); 704 705 screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1); 706 707 if (screen->tsc.entries[i]) 708 nv50_tsc_entry(screen->tsc.entries[i])->id = -1; 709 710 screen->tsc.entries[i] = entry; 711 return i; 712} 713