nv50_screen.c revision 672ad90f54539ed38a5d03b47b58ec17f250b63d
1/* 2 * Copyright 2010 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23#include "util/u_format.h" 24#include "util/u_format_s3tc.h" 25#include "pipe/p_screen.h" 26 27#include "nv50_context.h" 28#include "nv50_screen.h" 29 30#include "nouveau/nv_object.xml.h" 31 32#ifndef NOUVEAU_GETPARAM_GRAPH_UNITS 33# define NOUVEAU_GETPARAM_GRAPH_UNITS 13 34#endif 35 36extern int nouveau_device_get_param(struct nouveau_device *dev, 37 uint64_t param, uint64_t *value); 38 39static boolean 40nv50_screen_is_format_supported(struct pipe_screen *pscreen, 41 enum pipe_format format, 42 enum pipe_texture_target target, 43 unsigned sample_count, 44 unsigned bindings) 45{ 46 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */ 47 return FALSE; 48 if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128) 49 return FALSE; 50 51 if (!util_format_is_supported(format, bindings)) 52 return FALSE; 53 54 switch (format) { 55 case PIPE_FORMAT_Z16_UNORM: 56 if (nv50_screen(pscreen)->tesla->grclass < NVA0_3D) 57 return FALSE; 58 break; 59 case PIPE_FORMAT_R8G8B8A8_UNORM: 60 case PIPE_FORMAT_R8G8B8X8_UNORM: 61 /* HACK: GL requires equal formats for MS resolve and window is BGRA */ 62 if (bindings & PIPE_BIND_RENDER_TARGET) 63 return FALSE; 64 default: 65 break; 66 } 67 68 /* transfers & shared are always supported */ 69 bindings &= ~(PIPE_BIND_TRANSFER_READ | 70 PIPE_BIND_TRANSFER_WRITE | 71 PIPE_BIND_SHARED); 72 73 return (nv50_format_table[format].usage & bindings) == bindings; 74} 75 76static int 77nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) 78{ 79 switch (param) { 80 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 81 return 64; 82 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 83 return 14; 84 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 85 return 12; 86 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 87 return 14; 88 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: /* shader support missing */ 89 return 0; 90 case PIPE_CAP_MIN_TEXEL_OFFSET: 91 return 0 /* -8, TODO */; 92 case PIPE_CAP_MAX_TEXEL_OFFSET: 93 return 0 /* +7, TODO */; 94 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 95 case PIPE_CAP_TEXTURE_SWIZZLE: 96 case PIPE_CAP_TEXTURE_SHADOW_MAP: 97 case PIPE_CAP_NPOT_TEXTURES: 98 case PIPE_CAP_ANISOTROPIC_FILTER: 99 case PIPE_CAP_SCALED_RESOLVE: 100 return 1; 101 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 102 case PIPE_CAP_SEAMLESS_CUBE_MAP: 103 return nv50_screen(pscreen)->tesla->grclass >= NVA0_3D; 104 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 105 return 0; 106 case PIPE_CAP_TWO_SIDED_STENCIL: 107 case PIPE_CAP_DEPTH_CLIP_DISABLE: 108 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 109 case PIPE_CAP_POINT_SPRITE: 110 return 1; 111 case PIPE_CAP_SM3: 112 return 1; 113 case PIPE_CAP_GLSL_FEATURE_LEVEL: 114 return 120; 115 case PIPE_CAP_MAX_RENDER_TARGETS: 116 return 8; 117 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 118 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 119 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 120 return 1; 121 case PIPE_CAP_TIMER_QUERY: 122 case PIPE_CAP_OCCLUSION_QUERY: 123 return 1; 124 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 125 return 0; 126 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 127 return 128; 128 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 129 return 32; 130 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 131 case PIPE_CAP_INDEP_BLEND_ENABLE: 132 return 1; 133 case PIPE_CAP_INDEP_BLEND_FUNC: 134 return nv50_screen(pscreen)->tesla->grclass >= NVA3_3D; 135 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 136 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 137 return 1; 138 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 139 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 140 return 0; 141 case PIPE_CAP_SHADER_STENCIL_EXPORT: 142 return 0; 143 case PIPE_CAP_PRIMITIVE_RESTART: 144 case PIPE_CAP_TGSI_INSTANCEID: 145 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 146 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 147 case PIPE_CAP_CONDITIONAL_RENDER: 148 case PIPE_CAP_TEXTURE_BARRIER: 149 return 1; 150 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS: 151 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 152 return 0; /* state trackers will know better */ 153 default: 154 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); 155 return 0; 156 } 157} 158 159static int 160nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, 161 enum pipe_shader_cap param) 162{ 163 switch (shader) { 164 case PIPE_SHADER_VERTEX: 165 case PIPE_SHADER_GEOMETRY: 166 case PIPE_SHADER_FRAGMENT: 167 break; 168 default: 169 return 0; 170 } 171 172 switch (param) { 173 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 174 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 175 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 176 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 177 return 16384; 178 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 179 return 4; 180 case PIPE_SHADER_CAP_MAX_INPUTS: 181 if (shader == PIPE_SHADER_VERTEX) 182 return 32; 183 return 0x300 / 16; 184 case PIPE_SHADER_CAP_MAX_CONSTS: 185 return 65536 / 16; 186 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 187 return 14; 188 case PIPE_SHADER_CAP_MAX_ADDRS: 189 return 1; 190 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 191 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 192 return shader != PIPE_SHADER_FRAGMENT; 193 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 194 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 195 return 1; 196 case PIPE_SHADER_CAP_MAX_PREDS: 197 return 0; 198 case PIPE_SHADER_CAP_MAX_TEMPS: 199 return NV50_CAP_MAX_PROGRAM_TEMPS; 200 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 201 return 1; 202 case PIPE_SHADER_CAP_SUBROUTINES: 203 return 0; /* please inline, or provide function declarations */ 204 case PIPE_SHADER_CAP_INTEGERS: 205 return 0; 206 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 207 return 32; 208 case PIPE_SHADER_CAP_OUTPUT_READ: 209 return 0; /* maybe support this for fragment shaders ? */ 210 default: 211 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param); 212 return 0; 213 } 214} 215 216static float 217nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) 218{ 219 switch (param) { 220 case PIPE_CAPF_MAX_LINE_WIDTH: 221 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 222 return 10.0f; 223 case PIPE_CAPF_MAX_POINT_WIDTH: 224 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 225 return 64.0f; 226 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 227 return 16.0f; 228 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 229 return 4.0f; 230 default: 231 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); 232 return 0.0f; 233 } 234} 235 236static void 237nv50_screen_destroy(struct pipe_screen *pscreen) 238{ 239 struct nv50_screen *screen = nv50_screen(pscreen); 240 241 if (screen->base.fence.current) { 242 nouveau_fence_wait(screen->base.fence.current); 243 nouveau_fence_ref (NULL, &screen->base.fence.current); 244 } 245 if (screen->base.channel) 246 screen->base.channel->user_private = NULL; 247 if (screen->blitctx) 248 FREE(screen->blitctx); 249 250 nouveau_bo_ref(NULL, &screen->code); 251 nouveau_bo_ref(NULL, &screen->tls_bo); 252 nouveau_bo_ref(NULL, &screen->stack_bo); 253 nouveau_bo_ref(NULL, &screen->txc); 254 nouveau_bo_ref(NULL, &screen->uniforms); 255 nouveau_bo_ref(NULL, &screen->fence.bo); 256 257 nouveau_resource_destroy(&screen->vp_code_heap); 258 nouveau_resource_destroy(&screen->gp_code_heap); 259 nouveau_resource_destroy(&screen->fp_code_heap); 260 261 if (screen->tic.entries) 262 FREE(screen->tic.entries); 263 264 nouveau_mm_destroy(screen->mm_VRAM_fe0); 265 266 nouveau_grobj_free(&screen->tesla); 267 nouveau_grobj_free(&screen->eng2d); 268 nouveau_grobj_free(&screen->m2mf); 269 270 nouveau_notifier_free(&screen->sync); 271 272 nouveau_screen_fini(&screen->base); 273 274 FREE(screen); 275} 276 277static void 278nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence) 279{ 280 struct nv50_screen *screen = nv50_screen(pscreen); 281 struct nouveau_channel *chan = screen->base.channel; 282 283 MARK_RING (chan, 5, 2); 284 285 /* we need to do it after possible flush in MARK_RING */ 286 *sequence = ++screen->base.fence.sequence; 287 288 BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4); 289 OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR); 290 OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR); 291 OUT_RING (chan, *sequence); 292 OUT_RING (chan, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 | 293 NV50_3D_QUERY_GET_UNK4 | 294 NV50_3D_QUERY_GET_UNIT_CROP | 295 NV50_3D_QUERY_GET_TYPE_QUERY | 296 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO | 297 NV50_3D_QUERY_GET_SHORT); 298} 299 300static u32 301nv50_screen_fence_update(struct pipe_screen *pscreen) 302{ 303 struct nv50_screen *screen = nv50_screen(pscreen); 304 return screen->fence.map[0]; 305} 306 307#define FAIL_SCREEN_INIT(str, err) \ 308 do { \ 309 NOUVEAU_ERR(str, err); \ 310 nv50_screen_destroy(pscreen); \ 311 return NULL; \ 312 } while(0) 313 314struct pipe_screen * 315nv50_screen_create(struct nouveau_device *dev) 316{ 317 struct nv50_screen *screen; 318 struct nouveau_channel *chan; 319 struct pipe_screen *pscreen; 320 uint64_t value; 321 uint32_t tesla_class; 322 unsigned stack_size, max_warps, tls_space; 323 int ret; 324 unsigned i, base; 325 326 screen = CALLOC_STRUCT(nv50_screen); 327 if (!screen) 328 return NULL; 329 pscreen = &screen->base.base; 330 331 screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER; 332 333 ret = nouveau_screen_init(&screen->base, dev); 334 if (ret) 335 FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret); 336 337 chan = screen->base.channel; 338 chan->user_private = screen; 339 340 pscreen->destroy = nv50_screen_destroy; 341 pscreen->context_create = nv50_create; 342 pscreen->is_format_supported = nv50_screen_is_format_supported; 343 pscreen->get_param = nv50_screen_get_param; 344 pscreen->get_shader_param = nv50_screen_get_shader_param; 345 pscreen->get_paramf = nv50_screen_get_paramf; 346 347 nv50_screen_init_resource_functions(pscreen); 348 349 nouveau_screen_init_vdec(&screen->base); 350 351 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, 352 &screen->fence.bo); 353 if (ret) 354 goto fail; 355 nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR); 356 screen->fence.map = screen->fence.bo->map; 357 nouveau_bo_unmap(screen->fence.bo); 358 screen->base.fence.emit = nv50_screen_fence_emit; 359 screen->base.fence.update = nv50_screen_fence_update; 360 361 ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync); 362 if (ret) 363 FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret); 364 365 ret = nouveau_grobj_alloc(chan, 0xbeef5039, NV50_M2MF, &screen->m2mf); 366 if (ret) 367 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret); 368 369 BIND_RING (chan, screen->m2mf, NV50_SUBCH_MF); 370 BEGIN_RING(chan, RING_MF_(NV04_M2MF_DMA_NOTIFY), 3); 371 OUT_RING (chan, screen->sync->handle); 372 OUT_RING (chan, chan->vram->handle); 373 OUT_RING (chan, chan->vram->handle); 374 375 ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d); 376 if (ret) 377 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret); 378 379 BIND_RING (chan, screen->eng2d, NV50_SUBCH_2D); 380 BEGIN_RING(chan, RING_2D(DMA_NOTIFY), 4); 381 OUT_RING (chan, screen->sync->handle); 382 OUT_RING (chan, chan->vram->handle); 383 OUT_RING (chan, chan->vram->handle); 384 OUT_RING (chan, chan->vram->handle); 385 BEGIN_RING(chan, RING_2D(OPERATION), 1); 386 OUT_RING (chan, NV50_2D_OPERATION_SRCCOPY); 387 BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1); 388 OUT_RING (chan, 0); 389 BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1); 390 OUT_RING (chan, 0); 391 BEGIN_RING(chan, RING_2D_(0x0888), 1); 392 OUT_RING (chan, 1); 393 394 switch (dev->chipset & 0xf0) { 395 case 0x50: 396 tesla_class = NV50_3D; 397 break; 398 case 0x80: 399 case 0x90: 400 tesla_class = NV84_3D; 401 break; 402 case 0xa0: 403 switch (dev->chipset) { 404 case 0xa0: 405 case 0xaa: 406 case 0xac: 407 tesla_class = NVA0_3D; 408 break; 409 case 0xaf: 410 tesla_class = NVAF_3D; 411 break; 412 default: 413 tesla_class = NVA3_3D; 414 break; 415 } 416 break; 417 default: 418 FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev->chipset); 419 break; 420 } 421 422 ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class, &screen->tesla); 423 if (ret) 424 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret); 425 426 BIND_RING (chan, screen->tesla, NV50_SUBCH_3D); 427 428 BEGIN_RING(chan, RING_3D(COND_MODE), 1); 429 OUT_RING (chan, NV50_3D_COND_MODE_ALWAYS); 430 431 BEGIN_RING(chan, RING_3D(DMA_NOTIFY), 1); 432 OUT_RING (chan, screen->sync->handle); 433 BEGIN_RING(chan, RING_3D(DMA_ZETA), 11); 434 for (i = 0; i < 11; ++i) 435 OUT_RING(chan, chan->vram->handle); 436 BEGIN_RING(chan, RING_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN); 437 for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i) 438 OUT_RING(chan, chan->vram->handle); 439 440 BEGIN_RING(chan, RING_3D(REG_MODE), 1); 441 OUT_RING (chan, NV50_3D_REG_MODE_STRIPED); 442 BEGIN_RING(chan, RING_3D(UNK1400_LANES), 1); 443 OUT_RING (chan, 0xf); 444 445 BEGIN_RING(chan, RING_3D(RT_CONTROL), 1); 446 OUT_RING (chan, 1); 447 448 BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1); 449 OUT_RING (chan, 0); 450 BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1); 451 OUT_RING (chan, 0); 452 BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1); 453 OUT_RING (chan, NV50_3D_MULTISAMPLE_MODE_MS1); 454 BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1); 455 OUT_RING (chan, 0); 456 BEGIN_RING(chan, RING_3D(LINE_LAST_PIXEL), 1); 457 OUT_RING (chan, 0); 458 BEGIN_RING(chan, RING_3D(BLEND_SEPARATE_ALPHA), 1); 459 OUT_RING (chan, 1); 460 461 if (tesla_class >= NVA0_3D) { 462 BEGIN_RING(chan, RING_3D_(NVA0_3D_TEX_MISC), 1); 463 OUT_RING (chan, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP); 464 } 465 466 BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1); 467 OUT_RING (chan, 0); 468 BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2); 469 OUT_RING (chan, 0); 470 OUT_RING (chan, 0); 471 BEGIN_RING(chan, RING_3D(ZCULL_REGION), 1); /* deactivate ZCULL */ 472 OUT_RING (chan, 0x3f); 473 474 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 475 3 << NV50_CODE_BO_SIZE_LOG2, &screen->code); 476 if (ret) 477 goto fail; 478 479 nouveau_resource_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2); 480 nouveau_resource_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2); 481 nouveau_resource_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2); 482 483 base = 1 << NV50_CODE_BO_SIZE_LOG2; 484 485 BEGIN_RING(chan, RING_3D(VP_ADDRESS_HIGH), 2); 486 OUT_RELOCh(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 487 OUT_RELOCl(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 488 489 BEGIN_RING(chan, RING_3D(FP_ADDRESS_HIGH), 2); 490 OUT_RELOCh(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 491 OUT_RELOCl(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 492 493 BEGIN_RING(chan, RING_3D(GP_ADDRESS_HIGH), 2); 494 OUT_RELOCh(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 495 OUT_RELOCl(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 496 497 nouveau_device_get_param(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value); 498 499 max_warps = util_bitcount(value & 0xffff); 500 max_warps *= util_bitcount((value >> 24) & 0xf) * 32; 501 502 stack_size = max_warps * 64 * 8; 503 504 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, 505 &screen->stack_bo); 506 if (ret) 507 FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret); 508 509 BEGIN_RING(chan, RING_3D(STACK_ADDRESS_HIGH), 3); 510 OUT_RELOCh(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); 511 OUT_RELOCl(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); 512 OUT_RING (chan, 4); 513 514 tls_space = NV50_CAP_MAX_PROGRAM_TEMPS * 16; 515 516 screen->tls_size = tls_space * max_warps * 32; 517 518 if (nouveau_mesa_debug) 519 debug_printf("max_warps = %i, tls_size = %"PRIu64" KiB\n", 520 max_warps, screen->tls_size >> 10); 521 522 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, screen->tls_size, 523 &screen->tls_bo); 524 if (ret) 525 FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret); 526 527 BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 3); 528 OUT_RELOCh(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); 529 OUT_RELOCl(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); 530 OUT_RING (chan, util_logbase2(tls_space / 8)); 531 532 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, 533 &screen->uniforms); 534 if (ret) 535 goto fail; 536 537 BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3); 538 OUT_RELOCh(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 539 OUT_RELOCl(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 540 OUT_RING (chan, (NV50_CB_PVP << 16) | 0x0000); 541 542 BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3); 543 OUT_RELOCh(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 544 OUT_RELOCl(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 545 OUT_RING (chan, (NV50_CB_PGP << 16) | 0x0000); 546 547 BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3); 548 OUT_RELOCh(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 549 OUT_RELOCl(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 550 OUT_RING (chan, (NV50_CB_PFP << 16) | 0x0000); 551 552 BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3); 553 OUT_RELOCh(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 554 OUT_RELOCl(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 555 OUT_RING (chan, (NV50_CB_AUX << 16) | 0x0200); 556 557 BEGIN_RING_NI(chan, RING_3D(SET_PROGRAM_CB), 6); 558 OUT_RING (chan, (NV50_CB_PVP << 12) | 0x001); 559 OUT_RING (chan, (NV50_CB_PGP << 12) | 0x021); 560 OUT_RING (chan, (NV50_CB_PFP << 12) | 0x031); 561 OUT_RING (chan, (NV50_CB_AUX << 12) | 0xf01); 562 OUT_RING (chan, (NV50_CB_AUX << 12) | 0xf21); 563 OUT_RING (chan, (NV50_CB_AUX << 12) | 0xf31); 564 565 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, 566 &screen->txc); 567 if (ret) 568 FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret); 569 570 /* max TIC (bits 4:8) & TSC bindings, per program type */ 571 for (i = 0; i < 3; ++i) { 572 BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1); 573 OUT_RING (chan, 0x54); 574 } 575 576 BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3); 577 OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 578 OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 579 OUT_RING (chan, NV50_TIC_MAX_ENTRIES - 1); 580 581 BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3); 582 OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 583 OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 584 OUT_RING (chan, NV50_TSC_MAX_ENTRIES - 1); 585 586 BEGIN_RING(chan, RING_3D(LINKED_TSC), 1); 587 OUT_RING (chan, 0); 588 589 BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1); 590 OUT_RING (chan, 0); 591 BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1); 592 OUT_RING (chan, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY); 593 BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2); 594 for (i = 0; i < 8 * 2; ++i) 595 OUT_RING(chan, 0); 596 BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1); 597 OUT_RING (chan, 0); 598 599 BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1); 600 OUT_RING (chan, 1); 601 BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2); 602 OUT_RINGf (chan, 0.0f); 603 OUT_RINGf (chan, 1.0f); 604 605 BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1); 606#ifdef NV50_SCISSORS_CLIPPING 607 OUT_RING (chan, 0x0000); 608#else 609 OUT_RING (chan, 0x1080); 610#endif 611 612 BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1); 613 OUT_RING (chan, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT); 614 615 /* We use scissors instead of exact view volume clipping, 616 * so they're always enabled. 617 */ 618 BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3); 619 OUT_RING (chan, 1); 620 OUT_RING (chan, 8192 << 16); 621 OUT_RING (chan, 8192 << 16); 622 623 BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1); 624 OUT_RING (chan, 1); 625 BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1); 626 OUT_RING (chan, NV50_3D_POINT_RASTER_RULES_OGL); 627 BEGIN_RING(chan, RING_3D(FRAG_COLOR_CLAMP_EN), 1); 628 OUT_RING (chan, 0x11111111); 629 BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1); 630 OUT_RING (chan, 1); 631 632 FIRE_RING (chan); 633 634 screen->tic.entries = CALLOC(4096, sizeof(void *)); 635 screen->tsc.entries = screen->tic.entries + 2048; 636 637 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0); 638 639 if (!nv50_blitctx_create(screen)) 640 goto fail; 641 642 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE); 643 644 return pscreen; 645 646fail: 647 nv50_screen_destroy(pscreen); 648 return NULL; 649} 650 651void 652nv50_screen_make_buffers_resident(struct nv50_screen *screen) 653{ 654 struct nouveau_channel *chan = screen->base.channel; 655 656 const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD; 657 658 MARK_RING(chan, 0, 5); 659 nouveau_bo_validate(chan, screen->code, flags); 660 nouveau_bo_validate(chan, screen->uniforms, flags); 661 nouveau_bo_validate(chan, screen->txc, flags); 662 nouveau_bo_validate(chan, screen->tls_bo, flags); 663 nouveau_bo_validate(chan, screen->stack_bo, flags); 664} 665 666int 667nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry) 668{ 669 int i = screen->tic.next; 670 671 while (screen->tic.lock[i / 32] & (1 << (i % 32))) 672 i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1); 673 674 screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1); 675 676 if (screen->tic.entries[i]) 677 nv50_tic_entry(screen->tic.entries[i])->id = -1; 678 679 screen->tic.entries[i] = entry; 680 return i; 681} 682 683int 684nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry) 685{ 686 int i = screen->tsc.next; 687 688 while (screen->tsc.lock[i / 32] & (1 << (i % 32))) 689 i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1); 690 691 screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1); 692 693 if (screen->tsc.entries[i]) 694 nv50_tsc_entry(screen->tsc.entries[i])->id = -1; 695 696 screen->tsc.entries[i] = entry; 697 return i; 698} 699