nv50_screen.c revision 8b4f7b0672d663273310fffa9490ad996f5b914a
1/* 2 * Copyright 2010 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23#include "util/u_format.h" 24#include "util/u_format_s3tc.h" 25#include "pipe/p_screen.h" 26 27#include "nv50_context.h" 28#include "nv50_screen.h" 29 30#include "nouveau/nv_object.xml.h" 31 32#ifndef NOUVEAU_GETPARAM_GRAPH_UNITS 33# define NOUVEAU_GETPARAM_GRAPH_UNITS 13 34#endif 35 36extern int nouveau_device_get_param(struct nouveau_device *dev, 37 uint64_t param, uint64_t *value); 38 39static boolean 40nv50_screen_is_format_supported(struct pipe_screen *pscreen, 41 enum pipe_format format, 42 enum pipe_texture_target target, 43 unsigned sample_count, 44 unsigned bindings) 45{ 46 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */ 47 return FALSE; 48 if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128) 49 return FALSE; 50 51 if (!util_format_is_supported(format, bindings)) 52 return FALSE; 53 54 switch (format) { 55 case PIPE_FORMAT_Z16_UNORM: 56 if (nv50_screen(pscreen)->tesla->grclass < NVA0_3D) 57 return FALSE; 58 break; 59 case PIPE_FORMAT_R8G8B8A8_UNORM: 60 case PIPE_FORMAT_R8G8B8X8_UNORM: 61 /* HACK: GL requires equal formats for MS resolve and window is BGRA */ 62 if (bindings & PIPE_BIND_RENDER_TARGET) 63 return FALSE; 64 default: 65 break; 66 } 67 68 /* transfers & shared are always supported */ 69 bindings &= ~(PIPE_BIND_TRANSFER_READ | 70 PIPE_BIND_TRANSFER_WRITE | 71 PIPE_BIND_SHARED); 72 73 return (nv50_format_table[format].usage & bindings) == bindings; 74} 75 76static int 77nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) 78{ 79 switch (param) { 80 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 81 return 64; 82 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 83 return 14; 84 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 85 return 12; 86 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 87 return 14; 88 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: /* shader support missing */ 89 return 0; 90 case PIPE_CAP_MIN_TEXEL_OFFSET: 91 return 0 /* -8, TODO */; 92 case PIPE_CAP_MAX_TEXEL_OFFSET: 93 return 0 /* +7, TODO */; 94 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 95 case PIPE_CAP_TEXTURE_SWIZZLE: 96 case PIPE_CAP_TEXTURE_SHADOW_MAP: 97 case PIPE_CAP_NPOT_TEXTURES: 98 case PIPE_CAP_ANISOTROPIC_FILTER: 99 case PIPE_CAP_SCALED_RESOLVE: 100 return 1; 101 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 102 case PIPE_CAP_SEAMLESS_CUBE_MAP: 103 return nv50_screen(pscreen)->tesla->grclass >= NVA0_3D; 104 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 105 return 0; 106 case PIPE_CAP_TWO_SIDED_STENCIL: 107 case PIPE_CAP_DEPTH_CLIP_DISABLE: 108 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 109 case PIPE_CAP_POINT_SPRITE: 110 return 1; 111 case PIPE_CAP_SM3: 112 return 1; 113 case PIPE_CAP_GLSL_FEATURE_LEVEL: 114 return 120; 115 case PIPE_CAP_MAX_RENDER_TARGETS: 116 return 8; 117 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 118 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 119 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 120 return 1; 121 case PIPE_CAP_TIMER_QUERY: 122 case PIPE_CAP_OCCLUSION_QUERY: 123 return 1; 124 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 125 return 0; 126 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 127 return 128; 128 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 129 return 32; 130 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 131 case PIPE_CAP_INDEP_BLEND_ENABLE: 132 return 1; 133 case PIPE_CAP_INDEP_BLEND_FUNC: 134 return nv50_screen(pscreen)->tesla->grclass >= NVA3_3D; 135 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 136 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 137 return 1; 138 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 139 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 140 return 0; 141 case PIPE_CAP_SHADER_STENCIL_EXPORT: 142 return 0; 143 case PIPE_CAP_PRIMITIVE_RESTART: 144 case PIPE_CAP_TGSI_INSTANCEID: 145 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 146 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 147 case PIPE_CAP_CONDITIONAL_RENDER: 148 case PIPE_CAP_TEXTURE_BARRIER: 149 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 150 return 1; 151 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS: 152 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 153 return 0; /* state trackers will know better */ 154 default: 155 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); 156 return 0; 157 } 158} 159 160static int 161nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, 162 enum pipe_shader_cap param) 163{ 164 switch (shader) { 165 case PIPE_SHADER_VERTEX: 166 case PIPE_SHADER_GEOMETRY: 167 case PIPE_SHADER_FRAGMENT: 168 break; 169 default: 170 return 0; 171 } 172 173 switch (param) { 174 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 175 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 176 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 177 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 178 return 16384; 179 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 180 return 4; 181 case PIPE_SHADER_CAP_MAX_INPUTS: 182 if (shader == PIPE_SHADER_VERTEX) 183 return 32; 184 return 0x300 / 16; 185 case PIPE_SHADER_CAP_MAX_CONSTS: 186 return 65536 / 16; 187 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 188 return 14; 189 case PIPE_SHADER_CAP_MAX_ADDRS: 190 return 1; 191 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 192 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 193 return shader != PIPE_SHADER_FRAGMENT; 194 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 195 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 196 return 1; 197 case PIPE_SHADER_CAP_MAX_PREDS: 198 return 0; 199 case PIPE_SHADER_CAP_MAX_TEMPS: 200 return NV50_CAP_MAX_PROGRAM_TEMPS; 201 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 202 return 1; 203 case PIPE_SHADER_CAP_SUBROUTINES: 204 return 0; /* please inline, or provide function declarations */ 205 case PIPE_SHADER_CAP_INTEGERS: 206 return 0; 207 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 208 return 32; 209 case PIPE_SHADER_CAP_OUTPUT_READ: 210 return 0; /* maybe support this for fragment shaders ? */ 211 default: 212 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param); 213 return 0; 214 } 215} 216 217static float 218nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) 219{ 220 switch (param) { 221 case PIPE_CAPF_MAX_LINE_WIDTH: 222 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 223 return 10.0f; 224 case PIPE_CAPF_MAX_POINT_WIDTH: 225 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 226 return 64.0f; 227 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 228 return 16.0f; 229 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 230 return 4.0f; 231 default: 232 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); 233 return 0.0f; 234 } 235} 236 237static void 238nv50_screen_destroy(struct pipe_screen *pscreen) 239{ 240 struct nv50_screen *screen = nv50_screen(pscreen); 241 242 if (screen->base.fence.current) { 243 nouveau_fence_wait(screen->base.fence.current); 244 nouveau_fence_ref (NULL, &screen->base.fence.current); 245 } 246 if (screen->base.channel) 247 screen->base.channel->user_private = NULL; 248 if (screen->blitctx) 249 FREE(screen->blitctx); 250 251 nouveau_bo_ref(NULL, &screen->code); 252 nouveau_bo_ref(NULL, &screen->tls_bo); 253 nouveau_bo_ref(NULL, &screen->stack_bo); 254 nouveau_bo_ref(NULL, &screen->txc); 255 nouveau_bo_ref(NULL, &screen->uniforms); 256 nouveau_bo_ref(NULL, &screen->fence.bo); 257 258 nouveau_resource_destroy(&screen->vp_code_heap); 259 nouveau_resource_destroy(&screen->gp_code_heap); 260 nouveau_resource_destroy(&screen->fp_code_heap); 261 262 if (screen->tic.entries) 263 FREE(screen->tic.entries); 264 265 nouveau_mm_destroy(screen->mm_VRAM_fe0); 266 267 nouveau_grobj_free(&screen->tesla); 268 nouveau_grobj_free(&screen->eng2d); 269 nouveau_grobj_free(&screen->m2mf); 270 271 nouveau_notifier_free(&screen->sync); 272 273 nouveau_screen_fini(&screen->base); 274 275 FREE(screen); 276} 277 278static void 279nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence) 280{ 281 struct nv50_screen *screen = nv50_screen(pscreen); 282 struct nouveau_channel *chan = screen->base.channel; 283 284 MARK_RING (chan, 5, 2); 285 286 /* we need to do it after possible flush in MARK_RING */ 287 *sequence = ++screen->base.fence.sequence; 288 289 BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4); 290 OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR); 291 OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR); 292 OUT_RING (chan, *sequence); 293 OUT_RING (chan, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 | 294 NV50_3D_QUERY_GET_UNK4 | 295 NV50_3D_QUERY_GET_UNIT_CROP | 296 NV50_3D_QUERY_GET_TYPE_QUERY | 297 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO | 298 NV50_3D_QUERY_GET_SHORT); 299} 300 301static u32 302nv50_screen_fence_update(struct pipe_screen *pscreen) 303{ 304 struct nv50_screen *screen = nv50_screen(pscreen); 305 return screen->fence.map[0]; 306} 307 308#define FAIL_SCREEN_INIT(str, err) \ 309 do { \ 310 NOUVEAU_ERR(str, err); \ 311 nv50_screen_destroy(pscreen); \ 312 return NULL; \ 313 } while(0) 314 315struct pipe_screen * 316nv50_screen_create(struct nouveau_device *dev) 317{ 318 struct nv50_screen *screen; 319 struct nouveau_channel *chan; 320 struct pipe_screen *pscreen; 321 uint64_t value; 322 uint32_t tesla_class; 323 unsigned stack_size, max_warps, tls_space; 324 int ret; 325 unsigned i, base; 326 327 screen = CALLOC_STRUCT(nv50_screen); 328 if (!screen) 329 return NULL; 330 pscreen = &screen->base.base; 331 332 screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER; 333 334 ret = nouveau_screen_init(&screen->base, dev); 335 if (ret) 336 FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret); 337 338 chan = screen->base.channel; 339 chan->user_private = screen; 340 341 pscreen->destroy = nv50_screen_destroy; 342 pscreen->context_create = nv50_create; 343 pscreen->is_format_supported = nv50_screen_is_format_supported; 344 pscreen->get_param = nv50_screen_get_param; 345 pscreen->get_shader_param = nv50_screen_get_shader_param; 346 pscreen->get_paramf = nv50_screen_get_paramf; 347 348 nv50_screen_init_resource_functions(pscreen); 349 350 nouveau_screen_init_vdec(&screen->base); 351 352 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, 353 &screen->fence.bo); 354 if (ret) 355 goto fail; 356 nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR); 357 screen->fence.map = screen->fence.bo->map; 358 nouveau_bo_unmap(screen->fence.bo); 359 screen->base.fence.emit = nv50_screen_fence_emit; 360 screen->base.fence.update = nv50_screen_fence_update; 361 362 ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync); 363 if (ret) 364 FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret); 365 366 ret = nouveau_grobj_alloc(chan, 0xbeef5039, NV50_M2MF, &screen->m2mf); 367 if (ret) 368 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret); 369 370 BIND_RING (chan, screen->m2mf, NV50_SUBCH_MF); 371 BEGIN_RING(chan, RING_MF_(NV04_M2MF_DMA_NOTIFY), 3); 372 OUT_RING (chan, screen->sync->handle); 373 OUT_RING (chan, chan->vram->handle); 374 OUT_RING (chan, chan->vram->handle); 375 376 ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d); 377 if (ret) 378 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret); 379 380 BIND_RING (chan, screen->eng2d, NV50_SUBCH_2D); 381 BEGIN_RING(chan, RING_2D(DMA_NOTIFY), 4); 382 OUT_RING (chan, screen->sync->handle); 383 OUT_RING (chan, chan->vram->handle); 384 OUT_RING (chan, chan->vram->handle); 385 OUT_RING (chan, chan->vram->handle); 386 BEGIN_RING(chan, RING_2D(OPERATION), 1); 387 OUT_RING (chan, NV50_2D_OPERATION_SRCCOPY); 388 BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1); 389 OUT_RING (chan, 0); 390 BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1); 391 OUT_RING (chan, 0); 392 BEGIN_RING(chan, RING_2D_(0x0888), 1); 393 OUT_RING (chan, 1); 394 395 switch (dev->chipset & 0xf0) { 396 case 0x50: 397 tesla_class = NV50_3D; 398 break; 399 case 0x80: 400 case 0x90: 401 tesla_class = NV84_3D; 402 break; 403 case 0xa0: 404 switch (dev->chipset) { 405 case 0xa0: 406 case 0xaa: 407 case 0xac: 408 tesla_class = NVA0_3D; 409 break; 410 case 0xaf: 411 tesla_class = NVAF_3D; 412 break; 413 default: 414 tesla_class = NVA3_3D; 415 break; 416 } 417 break; 418 default: 419 FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev->chipset); 420 break; 421 } 422 423 ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class, &screen->tesla); 424 if (ret) 425 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret); 426 427 BIND_RING (chan, screen->tesla, NV50_SUBCH_3D); 428 429 BEGIN_RING(chan, RING_3D(COND_MODE), 1); 430 OUT_RING (chan, NV50_3D_COND_MODE_ALWAYS); 431 432 BEGIN_RING(chan, RING_3D(DMA_NOTIFY), 1); 433 OUT_RING (chan, screen->sync->handle); 434 BEGIN_RING(chan, RING_3D(DMA_ZETA), 11); 435 for (i = 0; i < 11; ++i) 436 OUT_RING(chan, chan->vram->handle); 437 BEGIN_RING(chan, RING_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN); 438 for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i) 439 OUT_RING(chan, chan->vram->handle); 440 441 BEGIN_RING(chan, RING_3D(REG_MODE), 1); 442 OUT_RING (chan, NV50_3D_REG_MODE_STRIPED); 443 BEGIN_RING(chan, RING_3D(UNK1400_LANES), 1); 444 OUT_RING (chan, 0xf); 445 446 BEGIN_RING(chan, RING_3D(RT_CONTROL), 1); 447 OUT_RING (chan, 1); 448 449 BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1); 450 OUT_RING (chan, 0); 451 BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1); 452 OUT_RING (chan, 0); 453 BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1); 454 OUT_RING (chan, NV50_3D_MULTISAMPLE_MODE_MS1); 455 BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1); 456 OUT_RING (chan, 0); 457 BEGIN_RING(chan, RING_3D(LINE_LAST_PIXEL), 1); 458 OUT_RING (chan, 0); 459 BEGIN_RING(chan, RING_3D(BLEND_SEPARATE_ALPHA), 1); 460 OUT_RING (chan, 1); 461 462 if (tesla_class >= NVA0_3D) { 463 BEGIN_RING(chan, RING_3D_(NVA0_3D_TEX_MISC), 1); 464 OUT_RING (chan, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP); 465 } 466 467 BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1); 468 OUT_RING (chan, 0); 469 BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2); 470 OUT_RING (chan, 0); 471 OUT_RING (chan, 0); 472 BEGIN_RING(chan, RING_3D(ZCULL_REGION), 1); /* deactivate ZCULL */ 473 OUT_RING (chan, 0x3f); 474 475 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 476 3 << NV50_CODE_BO_SIZE_LOG2, &screen->code); 477 if (ret) 478 goto fail; 479 480 nouveau_resource_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2); 481 nouveau_resource_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2); 482 nouveau_resource_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2); 483 484 base = 1 << NV50_CODE_BO_SIZE_LOG2; 485 486 BEGIN_RING(chan, RING_3D(VP_ADDRESS_HIGH), 2); 487 OUT_RELOCh(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 488 OUT_RELOCl(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 489 490 BEGIN_RING(chan, RING_3D(FP_ADDRESS_HIGH), 2); 491 OUT_RELOCh(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 492 OUT_RELOCl(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 493 494 BEGIN_RING(chan, RING_3D(GP_ADDRESS_HIGH), 2); 495 OUT_RELOCh(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 496 OUT_RELOCl(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 497 498 nouveau_device_get_param(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value); 499 500 max_warps = util_bitcount(value & 0xffff); 501 max_warps *= util_bitcount((value >> 24) & 0xf) * 32; 502 503 stack_size = max_warps * 64 * 8; 504 505 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, 506 &screen->stack_bo); 507 if (ret) 508 FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret); 509 510 BEGIN_RING(chan, RING_3D(STACK_ADDRESS_HIGH), 3); 511 OUT_RELOCh(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); 512 OUT_RELOCl(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); 513 OUT_RING (chan, 4); 514 515 tls_space = NV50_CAP_MAX_PROGRAM_TEMPS * 16; 516 517 screen->tls_size = tls_space * max_warps * 32; 518 519 if (nouveau_mesa_debug) 520 debug_printf("max_warps = %i, tls_size = %"PRIu64" KiB\n", 521 max_warps, screen->tls_size >> 10); 522 523 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, screen->tls_size, 524 &screen->tls_bo); 525 if (ret) 526 FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret); 527 528 BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 3); 529 OUT_RELOCh(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); 530 OUT_RELOCl(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); 531 OUT_RING (chan, util_logbase2(tls_space / 8)); 532 533 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, 534 &screen->uniforms); 535 if (ret) 536 goto fail; 537 538 BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3); 539 OUT_RELOCh(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 540 OUT_RELOCl(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 541 OUT_RING (chan, (NV50_CB_PVP << 16) | 0x0000); 542 543 BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3); 544 OUT_RELOCh(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 545 OUT_RELOCl(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 546 OUT_RING (chan, (NV50_CB_PGP << 16) | 0x0000); 547 548 BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3); 549 OUT_RELOCh(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 550 OUT_RELOCl(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 551 OUT_RING (chan, (NV50_CB_PFP << 16) | 0x0000); 552 553 BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3); 554 OUT_RELOCh(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 555 OUT_RELOCl(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 556 OUT_RING (chan, (NV50_CB_AUX << 16) | 0x0200); 557 558 BEGIN_RING_NI(chan, RING_3D(SET_PROGRAM_CB), 6); 559 OUT_RING (chan, (NV50_CB_PVP << 12) | 0x001); 560 OUT_RING (chan, (NV50_CB_PGP << 12) | 0x021); 561 OUT_RING (chan, (NV50_CB_PFP << 12) | 0x031); 562 OUT_RING (chan, (NV50_CB_AUX << 12) | 0xf01); 563 OUT_RING (chan, (NV50_CB_AUX << 12) | 0xf21); 564 OUT_RING (chan, (NV50_CB_AUX << 12) | 0xf31); 565 566 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, 567 &screen->txc); 568 if (ret) 569 FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret); 570 571 /* max TIC (bits 4:8) & TSC bindings, per program type */ 572 for (i = 0; i < 3; ++i) { 573 BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1); 574 OUT_RING (chan, 0x54); 575 } 576 577 BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3); 578 OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 579 OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 580 OUT_RING (chan, NV50_TIC_MAX_ENTRIES - 1); 581 582 BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3); 583 OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 584 OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 585 OUT_RING (chan, NV50_TSC_MAX_ENTRIES - 1); 586 587 BEGIN_RING(chan, RING_3D(LINKED_TSC), 1); 588 OUT_RING (chan, 0); 589 590 BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1); 591 OUT_RING (chan, 0); 592 BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1); 593 OUT_RING (chan, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY); 594 BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2); 595 for (i = 0; i < 8 * 2; ++i) 596 OUT_RING(chan, 0); 597 BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1); 598 OUT_RING (chan, 0); 599 600 BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1); 601 OUT_RING (chan, 1); 602 BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2); 603 OUT_RINGf (chan, 0.0f); 604 OUT_RINGf (chan, 1.0f); 605 606 BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1); 607#ifdef NV50_SCISSORS_CLIPPING 608 OUT_RING (chan, 0x0000); 609#else 610 OUT_RING (chan, 0x1080); 611#endif 612 613 BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1); 614 OUT_RING (chan, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT); 615 616 /* We use scissors instead of exact view volume clipping, 617 * so they're always enabled. 618 */ 619 BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3); 620 OUT_RING (chan, 1); 621 OUT_RING (chan, 8192 << 16); 622 OUT_RING (chan, 8192 << 16); 623 624 BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1); 625 OUT_RING (chan, 1); 626 BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1); 627 OUT_RING (chan, NV50_3D_POINT_RASTER_RULES_OGL); 628 BEGIN_RING(chan, RING_3D(FRAG_COLOR_CLAMP_EN), 1); 629 OUT_RING (chan, 0x11111111); 630 BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1); 631 OUT_RING (chan, 1); 632 633 FIRE_RING (chan); 634 635 screen->tic.entries = CALLOC(4096, sizeof(void *)); 636 screen->tsc.entries = screen->tic.entries + 2048; 637 638 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0); 639 640 if (!nv50_blitctx_create(screen)) 641 goto fail; 642 643 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE); 644 645 return pscreen; 646 647fail: 648 nv50_screen_destroy(pscreen); 649 return NULL; 650} 651 652void 653nv50_screen_make_buffers_resident(struct nv50_screen *screen) 654{ 655 struct nouveau_channel *chan = screen->base.channel; 656 657 const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD; 658 659 MARK_RING(chan, 0, 5); 660 nouveau_bo_validate(chan, screen->code, flags); 661 nouveau_bo_validate(chan, screen->uniforms, flags); 662 nouveau_bo_validate(chan, screen->txc, flags); 663 nouveau_bo_validate(chan, screen->tls_bo, flags); 664 nouveau_bo_validate(chan, screen->stack_bo, flags); 665} 666 667int 668nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry) 669{ 670 int i = screen->tic.next; 671 672 while (screen->tic.lock[i / 32] & (1 << (i % 32))) 673 i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1); 674 675 screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1); 676 677 if (screen->tic.entries[i]) 678 nv50_tic_entry(screen->tic.entries[i])->id = -1; 679 680 screen->tic.entries[i] = entry; 681 return i; 682} 683 684int 685nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry) 686{ 687 int i = screen->tsc.next; 688 689 while (screen->tsc.lock[i / 32] & (1 << (i % 32))) 690 i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1); 691 692 screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1); 693 694 if (screen->tsc.entries[i]) 695 nv50_tsc_entry(screen->tsc.entries[i])->id = -1; 696 697 screen->tsc.entries[i] = entry; 698 return i; 699} 700