nv50_screen.c revision 90dcd6c89ab4afa55ca19d572a1a695cf55cb1b2
1/* 2 * Copyright 2010 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23#include "util/u_format.h" 24#include "util/u_format_s3tc.h" 25#include "pipe/p_screen.h" 26 27#include "nv50_context.h" 28#include "nv50_screen.h" 29 30#include "nouveau/nv_object.xml.h" 31 32#ifndef NOUVEAU_GETPARAM_GRAPH_UNITS 33# define NOUVEAU_GETPARAM_GRAPH_UNITS 13 34#endif 35 36extern int nouveau_device_get_param(struct nouveau_device *dev, 37 uint64_t param, uint64_t *value); 38 39static boolean 40nv50_screen_is_format_supported(struct pipe_screen *pscreen, 41 enum pipe_format format, 42 enum pipe_texture_target target, 43 unsigned sample_count, 44 unsigned bindings) 45{ 46 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */ 47 return FALSE; 48 if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128) 49 return FALSE; 50 51 if (!util_format_is_supported(format, bindings)) 52 return FALSE; 53 54 switch (format) { 55 case PIPE_FORMAT_Z16_UNORM: 56 if (nv50_screen(pscreen)->tesla->grclass < NVA0_3D) 57 return FALSE; 58 break; 59 case PIPE_FORMAT_R8G8B8A8_UNORM: 60 case PIPE_FORMAT_R8G8B8X8_UNORM: 61 /* HACK: GL requires equal formats for MS resolve and window is BGRA */ 62 if (bindings & PIPE_BIND_RENDER_TARGET) 63 return FALSE; 64 default: 65 break; 66 } 67 68 /* transfers & shared are always supported */ 69 bindings &= ~(PIPE_BIND_TRANSFER_READ | 70 PIPE_BIND_TRANSFER_WRITE | 71 PIPE_BIND_SHARED); 72 73 return (nv50_format_table[format].usage & bindings) == bindings; 74} 75 76static int 77nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) 78{ 79 switch (param) { 80 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 81 return 64; 82 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 83 return 13; 84 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 85 return 10; 86 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 87 return 13; 88 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: /* shader support missing */ 89 return 0; 90 case PIPE_CAP_MIN_TEXEL_OFFSET: 91 return 0 /* -8, TODO */; 92 case PIPE_CAP_MAX_TEXEL_OFFSET: 93 return 0 /* +7, TODO */; 94 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 95 case PIPE_CAP_TEXTURE_SWIZZLE: 96 case PIPE_CAP_TEXTURE_SHADOW_MAP: 97 case PIPE_CAP_NPOT_TEXTURES: 98 case PIPE_CAP_ANISOTROPIC_FILTER: 99 case PIPE_CAP_SCALED_RESOLVE: 100 return 1; 101 case PIPE_CAP_SEAMLESS_CUBE_MAP: 102 return nv50_screen(pscreen)->tesla->grclass >= NVA0_3D; 103 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 104 return 0; 105 case PIPE_CAP_TWO_SIDED_STENCIL: 106 case PIPE_CAP_DEPTH_CLAMP: 107 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 108 case PIPE_CAP_POINT_SPRITE: 109 return 1; 110 case PIPE_CAP_GLSL: 111 case PIPE_CAP_SM3: 112 return 1; 113 case PIPE_CAP_MAX_RENDER_TARGETS: 114 return 8; 115 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL: 116 return 1; 117 case PIPE_CAP_TIMER_QUERY: 118 case PIPE_CAP_OCCLUSION_QUERY: 119 return 1; 120 case PIPE_CAP_STREAM_OUTPUT: 121 return 0; 122 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 123 case PIPE_CAP_INDEP_BLEND_ENABLE: 124 return 1; 125 case PIPE_CAP_INDEP_BLEND_FUNC: 126 return nv50_screen(pscreen)->tesla->grclass >= NVA3_3D; 127 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 128 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 129 return 1; 130 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 131 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 132 return 0; 133 case PIPE_CAP_SHADER_STENCIL_EXPORT: 134 return 0; 135 case PIPE_CAP_PRIMITIVE_RESTART: 136 case PIPE_CAP_TGSI_INSTANCEID: 137 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 138 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 139 case PIPE_CAP_CONDITIONAL_RENDER: 140 case PIPE_CAP_TEXTURE_BARRIER: 141 return 1; 142 default: 143 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); 144 return 0; 145 } 146} 147 148static int 149nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, 150 enum pipe_shader_cap param) 151{ 152 switch (shader) { 153 case PIPE_SHADER_VERTEX: 154 case PIPE_SHADER_GEOMETRY: 155 case PIPE_SHADER_FRAGMENT: 156 break; 157 default: 158 return 0; 159 } 160 161 switch (param) { 162 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 163 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 164 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 165 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 166 return 16384; 167 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 168 return 4; 169 case PIPE_SHADER_CAP_MAX_INPUTS: 170 if (shader == PIPE_SHADER_VERTEX) 171 return 32; 172 return 0x300 / 16; 173 case PIPE_SHADER_CAP_MAX_CONSTS: 174 return 65536 / 16; 175 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 176 return 14; 177 case PIPE_SHADER_CAP_MAX_ADDRS: 178 return 1; 179 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 180 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 181 return shader != PIPE_SHADER_FRAGMENT; 182 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 183 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 184 return 1; 185 case PIPE_SHADER_CAP_MAX_PREDS: 186 return 0; 187 case PIPE_SHADER_CAP_MAX_TEMPS: 188 return NV50_CAP_MAX_PROGRAM_TEMPS; 189 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 190 return 1; 191 case PIPE_SHADER_CAP_SUBROUTINES: 192 return 0; /* please inline, or provide function declarations */ 193 case PIPE_SHADER_CAP_INTEGERS: 194 return 0; 195 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 196 return 32; 197 default: 198 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param); 199 return 0; 200 } 201} 202 203static float 204nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param) 205{ 206 switch (param) { 207 case PIPE_CAP_MAX_LINE_WIDTH: 208 case PIPE_CAP_MAX_LINE_WIDTH_AA: 209 return 10.0f; 210 case PIPE_CAP_MAX_POINT_WIDTH: 211 case PIPE_CAP_MAX_POINT_WIDTH_AA: 212 return 64.0f; 213 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY: 214 return 16.0f; 215 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS: 216 return 4.0f; 217 default: 218 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); 219 return 0.0f; 220 } 221} 222 223static void 224nv50_screen_destroy(struct pipe_screen *pscreen) 225{ 226 struct nv50_screen *screen = nv50_screen(pscreen); 227 228 if (screen->base.fence.current) { 229 nouveau_fence_wait(screen->base.fence.current); 230 nouveau_fence_ref (NULL, &screen->base.fence.current); 231 } 232 screen->base.channel->user_private = NULL; 233 if (screen->blitctx) 234 FREE(screen->blitctx); 235 236 nouveau_bo_ref(NULL, &screen->code); 237 nouveau_bo_ref(NULL, &screen->tls_bo); 238 nouveau_bo_ref(NULL, &screen->stack_bo); 239 nouveau_bo_ref(NULL, &screen->txc); 240 nouveau_bo_ref(NULL, &screen->uniforms); 241 nouveau_bo_ref(NULL, &screen->fence.bo); 242 243 nouveau_resource_destroy(&screen->vp_code_heap); 244 nouveau_resource_destroy(&screen->gp_code_heap); 245 nouveau_resource_destroy(&screen->fp_code_heap); 246 247 if (screen->tic.entries) 248 FREE(screen->tic.entries); 249 250 nouveau_mm_destroy(screen->mm_VRAM_fe0); 251 252 nouveau_grobj_free(&screen->tesla); 253 nouveau_grobj_free(&screen->eng2d); 254 nouveau_grobj_free(&screen->m2mf); 255 256 nouveau_notifier_free(&screen->sync); 257 258 nouveau_screen_fini(&screen->base); 259 260 FREE(screen); 261} 262 263static void 264nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence) 265{ 266 struct nv50_screen *screen = nv50_screen(pscreen); 267 struct nouveau_channel *chan = screen->base.channel; 268 269 MARK_RING (chan, 5, 2); 270 271 /* we need to do it after possible flush in MARK_RING */ 272 *sequence = ++screen->base.fence.sequence; 273 274 BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4); 275 OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR); 276 OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR); 277 OUT_RING (chan, *sequence); 278 OUT_RING (chan, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 | 279 NV50_3D_QUERY_GET_UNK4 | 280 NV50_3D_QUERY_GET_UNIT_CROP | 281 NV50_3D_QUERY_GET_TYPE_QUERY | 282 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO | 283 NV50_3D_QUERY_GET_SHORT); 284} 285 286static u32 287nv50_screen_fence_update(struct pipe_screen *pscreen) 288{ 289 struct nv50_screen *screen = nv50_screen(pscreen); 290 return screen->fence.map[0]; 291} 292 293#define FAIL_SCREEN_INIT(str, err) \ 294 do { \ 295 NOUVEAU_ERR(str, err); \ 296 nv50_screen_destroy(pscreen); \ 297 return NULL; \ 298 } while(0) 299 300struct pipe_screen * 301nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev) 302{ 303 struct nv50_screen *screen; 304 struct nouveau_channel *chan; 305 struct pipe_screen *pscreen; 306 uint64_t value; 307 uint32_t tesla_class; 308 unsigned stack_size, max_warps, tls_space; 309 int ret; 310 unsigned i, base; 311 312 screen = CALLOC_STRUCT(nv50_screen); 313 if (!screen) 314 return NULL; 315 pscreen = &screen->base.base; 316 317 screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER; 318 319 ret = nouveau_screen_init(&screen->base, dev); 320 if (ret) 321 FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret); 322 323 chan = screen->base.channel; 324 chan->user_private = screen; 325 326 pscreen->winsys = ws; 327 pscreen->destroy = nv50_screen_destroy; 328 pscreen->context_create = nv50_create; 329 pscreen->is_format_supported = nv50_screen_is_format_supported; 330 pscreen->get_param = nv50_screen_get_param; 331 pscreen->get_shader_param = nv50_screen_get_shader_param; 332 pscreen->get_paramf = nv50_screen_get_paramf; 333 334 nv50_screen_init_resource_functions(pscreen); 335 336 nouveau_screen_init_vdec(&screen->base); 337 338 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, 339 &screen->fence.bo); 340 if (ret) 341 goto fail; 342 nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR); 343 screen->fence.map = screen->fence.bo->map; 344 nouveau_bo_unmap(screen->fence.bo); 345 screen->base.fence.emit = nv50_screen_fence_emit; 346 screen->base.fence.update = nv50_screen_fence_update; 347 348 ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync); 349 if (ret) 350 FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret); 351 352 ret = nouveau_grobj_alloc(chan, 0xbeef5039, NV50_M2MF, &screen->m2mf); 353 if (ret) 354 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret); 355 356 BIND_RING (chan, screen->m2mf, NV50_SUBCH_MF); 357 BEGIN_RING(chan, RING_MF_(NV04_M2MF_DMA_NOTIFY), 3); 358 OUT_RING (chan, screen->sync->handle); 359 OUT_RING (chan, chan->vram->handle); 360 OUT_RING (chan, chan->vram->handle); 361 362 ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d); 363 if (ret) 364 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret); 365 366 BIND_RING (chan, screen->eng2d, NV50_SUBCH_2D); 367 BEGIN_RING(chan, RING_2D(DMA_NOTIFY), 4); 368 OUT_RING (chan, screen->sync->handle); 369 OUT_RING (chan, chan->vram->handle); 370 OUT_RING (chan, chan->vram->handle); 371 OUT_RING (chan, chan->vram->handle); 372 BEGIN_RING(chan, RING_2D(OPERATION), 1); 373 OUT_RING (chan, NV50_2D_OPERATION_SRCCOPY); 374 BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1); 375 OUT_RING (chan, 0); 376 BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1); 377 OUT_RING (chan, 0); 378 BEGIN_RING(chan, RING_2D_(0x0888), 1); 379 OUT_RING (chan, 1); 380 381 switch (dev->chipset & 0xf0) { 382 case 0x50: 383 tesla_class = NV50_3D; 384 break; 385 case 0x80: 386 case 0x90: 387 tesla_class = NV84_3D; 388 break; 389 case 0xa0: 390 switch (dev->chipset) { 391 case 0xa0: 392 case 0xaa: 393 case 0xac: 394 tesla_class = NVA0_3D; 395 break; 396 case 0xaf: 397 tesla_class = NVAF_3D; 398 break; 399 default: 400 tesla_class = NVA3_3D; 401 break; 402 } 403 break; 404 default: 405 FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev->chipset); 406 break; 407 } 408 409 ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class, &screen->tesla); 410 if (ret) 411 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret); 412 413 BIND_RING (chan, screen->tesla, NV50_SUBCH_3D); 414 415 BEGIN_RING(chan, RING_3D(COND_MODE), 1); 416 OUT_RING (chan, NV50_3D_COND_MODE_ALWAYS); 417 418 BEGIN_RING(chan, RING_3D(DMA_NOTIFY), 1); 419 OUT_RING (chan, screen->sync->handle); 420 BEGIN_RING(chan, RING_3D(DMA_ZETA), 11); 421 for (i = 0; i < 11; ++i) 422 OUT_RING(chan, chan->vram->handle); 423 BEGIN_RING(chan, RING_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN); 424 for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i) 425 OUT_RING(chan, chan->vram->handle); 426 427 BEGIN_RING(chan, RING_3D(REG_MODE), 1); 428 OUT_RING (chan, NV50_3D_REG_MODE_STRIPED); 429 BEGIN_RING(chan, RING_3D(UNK1400_LANES), 1); 430 OUT_RING (chan, 0xf); 431 432 BEGIN_RING(chan, RING_3D(RT_CONTROL), 1); 433 OUT_RING (chan, 1); 434 435 BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1); 436 OUT_RING (chan, 0); 437 BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1); 438 OUT_RING (chan, 0); 439 BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1); 440 OUT_RING (chan, NV50_3D_MULTISAMPLE_MODE_MS1); 441 BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1); 442 OUT_RING (chan, 0); 443 BEGIN_RING(chan, RING_3D(LINE_LAST_PIXEL), 1); 444 OUT_RING (chan, 0); 445 BEGIN_RING(chan, RING_3D(BLEND_SEPARATE_ALPHA), 1); 446 OUT_RING (chan, 1); 447 448 if (tesla_class >= NVA0_3D) { 449 BEGIN_RING(chan, RING_3D_(NVA0_3D_TEX_MISC), 1); 450 OUT_RING (chan, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP); 451 } 452 453 BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1); 454 OUT_RING (chan, 0); 455 BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2); 456 OUT_RING (chan, 0); 457 OUT_RING (chan, 0); 458 BEGIN_RING(chan, RING_3D(ZCULL_REGION), 1); /* deactivate ZCULL */ 459 OUT_RING (chan, 0x3f); 460 461 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 462 3 << NV50_CODE_BO_SIZE_LOG2, &screen->code); 463 if (ret) 464 goto fail; 465 466 nouveau_resource_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2); 467 nouveau_resource_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2); 468 nouveau_resource_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2); 469 470 base = 1 << NV50_CODE_BO_SIZE_LOG2; 471 472 BEGIN_RING(chan, RING_3D(VP_ADDRESS_HIGH), 2); 473 OUT_RELOCh(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 474 OUT_RELOCl(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 475 476 BEGIN_RING(chan, RING_3D(FP_ADDRESS_HIGH), 2); 477 OUT_RELOCh(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 478 OUT_RELOCl(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 479 480 BEGIN_RING(chan, RING_3D(GP_ADDRESS_HIGH), 2); 481 OUT_RELOCh(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 482 OUT_RELOCl(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 483 484 nouveau_device_get_param(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value); 485 486 max_warps = util_bitcount(value & 0xffff); 487 max_warps *= util_bitcount((value >> 24) & 0xf) * 32; 488 489 stack_size = max_warps * 64 * 8; 490 491 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, 492 &screen->stack_bo); 493 if (ret) 494 FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret); 495 496 BEGIN_RING(chan, RING_3D(STACK_ADDRESS_HIGH), 3); 497 OUT_RELOCh(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); 498 OUT_RELOCl(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); 499 OUT_RING (chan, 4); 500 501 tls_space = NV50_CAP_MAX_PROGRAM_TEMPS * 16; 502 503 screen->tls_size = tls_space * max_warps * 32; 504 505 if (nouveau_mesa_debug) 506 debug_printf("max_warps = %i, tls_size = %"PRIu64" KiB\n", 507 max_warps, screen->tls_size >> 10); 508 509 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, screen->tls_size, 510 &screen->tls_bo); 511 if (ret) 512 FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret); 513 514 BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 3); 515 OUT_RELOCh(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); 516 OUT_RELOCl(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); 517 OUT_RING (chan, util_logbase2(tls_space / 8)); 518 519 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, 520 &screen->uniforms); 521 if (ret) 522 goto fail; 523 524 BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3); 525 OUT_RELOCh(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 526 OUT_RELOCl(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 527 OUT_RING (chan, (NV50_CB_PVP << 16) | 0x0000); 528 529 BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3); 530 OUT_RELOCh(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 531 OUT_RELOCl(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 532 OUT_RING (chan, (NV50_CB_PGP << 16) | 0x0000); 533 534 BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3); 535 OUT_RELOCh(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 536 OUT_RELOCl(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 537 OUT_RING (chan, (NV50_CB_PFP << 16) | 0x0000); 538 539 BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3); 540 OUT_RELOCh(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 541 OUT_RELOCl(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 542 OUT_RING (chan, (NV50_CB_AUX << 16) | 0x0200); 543 544 BEGIN_RING_NI(chan, RING_3D(SET_PROGRAM_CB), 6); 545 OUT_RING (chan, (NV50_CB_PVP << 12) | 0x001); 546 OUT_RING (chan, (NV50_CB_PGP << 12) | 0x021); 547 OUT_RING (chan, (NV50_CB_PFP << 12) | 0x031); 548 OUT_RING (chan, (NV50_CB_AUX << 12) | 0xf01); 549 OUT_RING (chan, (NV50_CB_AUX << 12) | 0xf21); 550 OUT_RING (chan, (NV50_CB_AUX << 12) | 0xf31); 551 552 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, 553 &screen->txc); 554 if (ret) 555 FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret); 556 557 /* max TIC (bits 4:8) & TSC bindings, per program type */ 558 for (i = 0; i < 3; ++i) { 559 BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1); 560 OUT_RING (chan, 0x54); 561 } 562 563 BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3); 564 OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 565 OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 566 OUT_RING (chan, NV50_TIC_MAX_ENTRIES - 1); 567 568 BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3); 569 OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 570 OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); 571 OUT_RING (chan, NV50_TSC_MAX_ENTRIES - 1); 572 573 BEGIN_RING(chan, RING_3D(LINKED_TSC), 1); 574 OUT_RING (chan, 0); 575 576 BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1); 577 OUT_RING (chan, 0); 578 BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1); 579 OUT_RING (chan, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY); 580 BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2); 581 for (i = 0; i < 8 * 2; ++i) 582 OUT_RING(chan, 0); 583 BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1); 584 OUT_RING (chan, 0); 585 586 BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1); 587 OUT_RING (chan, 1); 588 BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2); 589 OUT_RINGf (chan, 0.0f); 590 OUT_RINGf (chan, 1.0f); 591 592 BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1); 593#ifdef NV50_SCISSORS_CLIPPING 594 OUT_RING (chan, 0x0000); 595#else 596 OUT_RING (chan, 0x1080); 597#endif 598 599 BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1); 600 OUT_RING (chan, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT); 601 602 /* We use scissors instead of exact view volume clipping, 603 * so they're always enabled. 604 */ 605 BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3); 606 OUT_RING (chan, 1); 607 OUT_RING (chan, 8192 << 16); 608 OUT_RING (chan, 8192 << 16); 609 610 BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1); 611 OUT_RING (chan, 1); 612 BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1); 613 OUT_RING (chan, NV50_3D_POINT_RASTER_RULES_OGL); 614 BEGIN_RING(chan, RING_3D(FRAG_COLOR_CLAMP_EN), 1); 615 OUT_RING (chan, 0x11111111); 616 BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1); 617 OUT_RING (chan, 1); 618 619 FIRE_RING (chan); 620 621 screen->tic.entries = CALLOC(4096, sizeof(void *)); 622 screen->tsc.entries = screen->tic.entries + 2048; 623 624 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0); 625 626 if (!nv50_blitctx_create(screen)) 627 goto fail; 628 629 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE); 630 631 return pscreen; 632 633fail: 634 nv50_screen_destroy(pscreen); 635 return NULL; 636} 637 638void 639nv50_screen_make_buffers_resident(struct nv50_screen *screen) 640{ 641 struct nouveau_channel *chan = screen->base.channel; 642 643 const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD; 644 645 MARK_RING(chan, 0, 5); 646 nouveau_bo_validate(chan, screen->code, flags); 647 nouveau_bo_validate(chan, screen->uniforms, flags); 648 nouveau_bo_validate(chan, screen->txc, flags); 649 nouveau_bo_validate(chan, screen->tls_bo, flags); 650 nouveau_bo_validate(chan, screen->stack_bo, flags); 651} 652 653int 654nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry) 655{ 656 int i = screen->tic.next; 657 658 while (screen->tic.lock[i / 32] & (1 << (i % 32))) 659 i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1); 660 661 screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1); 662 663 if (screen->tic.entries[i]) 664 nv50_tic_entry(screen->tic.entries[i])->id = -1; 665 666 screen->tic.entries[i] = entry; 667 return i; 668} 669 670int 671nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry) 672{ 673 int i = screen->tsc.next; 674 675 while (screen->tsc.lock[i / 32] & (1 << (i % 32))) 676 i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1); 677 678 screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1); 679 680 if (screen->tsc.entries[i]) 681 nv50_tsc_entry(screen->tsc.entries[i])->id = -1; 682 683 screen->tsc.entries[i] = entry; 684 return i; 685} 686