r600_blit.c revision 0bba7796a33d3c47295a9676dc82984da1615fe5
1/* 2 * Copyright 2009 Marek Olšák <maraeo@gmail.com> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 * Marek Olšák 26 */ 27#include <errno.h> 28#include <pipe/p_screen.h> 29#include <util/u_blitter.h> 30#include <util/u_inlines.h> 31#include <util/u_memory.h> 32#include "util/u_surface.h" 33#include "r600_screen.h" 34#include "r600_context.h" 35#include "r600d.h" 36 37static void r600_blitter_save_states(struct pipe_context *ctx) 38{ 39 struct r600_context *rctx = r600_context(ctx); 40 41 util_blitter_save_blend(rctx->blitter, rctx->blend); 42 util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->dsa); 43 if (rctx->stencil_ref) { 44 util_blitter_save_stencil_ref(rctx->blitter, 45 &rctx->stencil_ref->state.stencil_ref); 46 } 47 util_blitter_save_rasterizer(rctx->blitter, rctx->rasterizer); 48 util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader); 49 util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader); 50 util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements); 51 if (rctx->viewport) { 52 util_blitter_save_viewport(rctx->blitter, &rctx->viewport->state.viewport); 53 } 54 if (rctx->clip) { 55 util_blitter_save_clip(rctx->blitter, &rctx->clip->state.clip); 56 } 57 util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer, 58 rctx->vertex_buffer); 59 60 /* remove ptr so they don't get deleted */ 61 rctx->blend = NULL; 62 rctx->clip = NULL; 63 rctx->vs_shader = NULL; 64 rctx->ps_shader = NULL; 65 rctx->rasterizer = NULL; 66 rctx->dsa = NULL; 67 rctx->vertex_elements = NULL; 68 69 /* suspend queries */ 70 r600_queries_suspend(ctx); 71} 72 73static void r600_clear(struct pipe_context *ctx, unsigned buffers, 74 const float *rgba, double depth, unsigned stencil) 75{ 76 struct r600_context *rctx = r600_context(ctx); 77 struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer; 78 79 r600_blitter_save_states(ctx); 80 util_blitter_clear(rctx->blitter, fb->width, fb->height, 81 fb->nr_cbufs, buffers, rgba, depth, 82 stencil); 83 /* resume queries */ 84 r600_queries_resume(ctx); 85} 86 87static void r600_clear_render_target(struct pipe_context *ctx, 88 struct pipe_surface *dst, 89 const float *rgba, 90 unsigned dstx, unsigned dsty, 91 unsigned width, unsigned height) 92{ 93 struct r600_context *rctx = r600_context(ctx); 94 struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer; 95 96 r600_blitter_save_states(ctx); 97 util_blitter_save_framebuffer(rctx->blitter, fb); 98 99 util_blitter_clear_render_target(rctx->blitter, dst, rgba, 100 dstx, dsty, width, height); 101 /* resume queries */ 102 r600_queries_resume(ctx); 103} 104 105static void r600_clear_depth_stencil(struct pipe_context *ctx, 106 struct pipe_surface *dst, 107 unsigned clear_flags, 108 double depth, 109 unsigned stencil, 110 unsigned dstx, unsigned dsty, 111 unsigned width, unsigned height) 112{ 113 struct r600_context *rctx = r600_context(ctx); 114 struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer; 115 116 r600_blitter_save_states(ctx); 117 util_blitter_save_framebuffer(rctx->blitter, fb); 118 119 util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil, 120 dstx, dsty, width, height); 121 /* resume queries */ 122 r600_queries_resume(ctx); 123} 124 125 126static void r600_resource_copy_region(struct pipe_context *ctx, 127 struct pipe_resource *dst, 128 struct pipe_subresource subdst, 129 unsigned dstx, unsigned dsty, unsigned dstz, 130 struct pipe_resource *src, 131 struct pipe_subresource subsrc, 132 unsigned srcx, unsigned srcy, unsigned srcz, 133 unsigned width, unsigned height) 134{ 135 util_resource_copy_region(pipe, dst, subdst, dstx, dsty, dstz, 136 src, subsrc, srcx, srcy, srcz, width, height); 137} 138 139void r600_init_blit_functions(struct r600_context *rctx) 140{ 141 rctx->context.clear = r600_clear; 142 rctx->context.clear_render_target = r600_clear_render_target; 143 rctx->context.clear_depth_stencil = r600_clear_depth_stencil; 144 rctx->context.resource_copy_region = r600_resource_copy_region; 145} 146 147 148struct r600_blit_states { 149 struct radeon_state *rasterizer; 150 struct radeon_state *dsa; 151 struct radeon_state *blend; 152 struct radeon_state *cb_cntl; 153 struct radeon_state *config; 154 struct radeon_state *vgt; 155 struct radeon_state *draw; 156 struct radeon_state *vs_constant0; 157 struct radeon_state *vs_constant1; 158 struct radeon_state *vs_constant2; 159 struct radeon_state *vs_constant3; 160 struct radeon_state *ps_shader; 161 struct radeon_state *vs_shader; 162 struct radeon_state *vs_resource0; 163 struct radeon_state *vs_resource1; 164}; 165 166static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600_blit_states *bstates) 167{ 168 struct radeon_state *rstate; 169 struct radeon_bo *bo; 170 u32 vbo[] = { 171 0xBF800000, 0xBF800000, 0x3F800000, 0x3F800000, 172 0x3F000000, 0x3F000000, 0x3F000000, 0x00000000, 173 0x3F800000, 0xBF800000, 0x3F800000, 0x3F800000, 174 0x3F000000, 0x3F000000, 0x3F000000, 0x00000000, 175 0x3F800000, 0x3F800000, 0x3F800000, 0x3F800000, 176 0x3F000000, 0x3F000000, 0x3F000000, 0x00000000, 177 0xBF800000, 0x3F800000, 0x3F800000, 0x3F800000, 178 0x3F000000, 0x3F000000, 0x3F000000, 0x00000000 179 }; 180 181 /* simple shader */ 182 bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL); 183 if (bo == NULL) { 184 return -ENOMEM; 185 } 186 if (radeon_bo_map(rscreen->rw, bo)) { 187 radeon_bo_decref(rscreen->rw, bo); 188 return -ENOMEM; 189 } 190 memcpy(bo->data, vbo, 128); 191 radeon_bo_unmap(rscreen->rw, bo); 192 193 rstate = radeon_state_shader(rscreen->rw, R600_STATE_RESOURCE, 0, R600_SHADER_VS); 194 if (rstate == NULL) { 195 radeon_bo_decref(rscreen->rw, bo); 196 return -ENOMEM; 197 } 198 199 /* set states (most default value are 0 and struct already 200 * initialized to 0, thus avoid resetting them) 201 */ 202 rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000000; 203 rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000080; 204 rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000; 205 rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000; 206 rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000; 207 rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000; 208 rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000; 209 rstate->bo[0] = bo; 210 rstate->nbo = 1; 211 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; 212 if (radeon_state_pm4(rstate)) { 213 radeon_state_decref(rstate); 214 return -ENOMEM; 215 } 216 bstates->vs_resource0 = rstate; 217 218 rstate = radeon_state_shader(rscreen->rw, R600_STATE_RESOURCE, 1, R600_SHADER_VS); 219 if (rstate == NULL) { 220 return -ENOMEM; 221 } 222 rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000010; 223 rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000070; 224 rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000; 225 rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000; 226 rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000; 227 rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000; 228 rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000; 229 rstate->bo[0] = radeon_bo_incref(rscreen->rw, bo); 230 rstate->nbo = 1; 231 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; 232 if (radeon_state_pm4(rstate)) { 233 radeon_state_decref(rstate); 234 return -ENOMEM; 235 } 236 bstates->vs_resource1 = rstate; 237 238 return 0; 239} 240 241static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscreen) 242{ 243 struct radeon_state *rstate; 244 struct radeon_bo *bo; 245 u32 shader_bc_r600[] = { 246 0x00000004, 0x81000400, 247 0x00000008, 0xA01C0000, 248 0xC001A03C, 0x94000688, 249 0xC0024000, 0x94200688, 250 0x7C000000, 0x002D1001, 251 0x00080000, 0x00000000, 252 0x7C000100, 0x002D1002, 253 0x00080000, 0x00000000, 254 0x00000001, 0x00601910, 255 0x00000401, 0x20601910, 256 0x00000801, 0x40601910, 257 0x80000C01, 0x60601910, 258 0x00000002, 0x00801910, 259 0x00000402, 0x20801910, 260 0x00000802, 0x40801910, 261 0x80000C02, 0x60801910 262 }; 263 u32 shader_bc_r700[] = { 264 0x00000004, 0x81000400, 265 0x00000008, 0xA01C0000, 266 0xC001A03C, 0x94000688, 267 0xC0024000, 0x94200688, 268 0x7C000000, 0x002D1001, 269 0x00080000, 0x00000000, 270 0x7C000100, 0x002D1002, 271 0x00080000, 0x00000000, 272 0x00000001, 0x00600C90, 273 0x00000401, 0x20600C90, 274 0x00000801, 0x40600C90, 275 0x80000C01, 0x60600C90, 276 0x00000002, 0x00800C90, 277 0x00000402, 0x20800C90, 278 0x00000802, 0x40800C90, 279 0x80000C02, 0x60800C90 280 }; 281 282 /* simple shader */ 283 bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL); 284 if (bo == NULL) { 285 return NULL; 286 } 287 if (radeon_bo_map(rscreen->rw, bo)) { 288 radeon_bo_decref(rscreen->rw, bo); 289 return NULL; 290 } 291 switch (rscreen->chip_class) { 292 case R600: 293 memcpy(bo->data, shader_bc_r600, 128); 294 break; 295 case R700: 296 memcpy(bo->data, shader_bc_r700, 128); 297 break; 298 default: 299 R600_ERR("unsupported chip family\n"); 300 radeon_bo_unmap(rscreen->rw, bo); 301 radeon_bo_decref(rscreen->rw, bo); 302 return NULL; 303 } 304 radeon_bo_unmap(rscreen->rw, bo); 305 306 rstate = radeon_state_shader(rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS); 307 if (rstate == NULL) { 308 radeon_bo_decref(rscreen->rw, bo); 309 return NULL; 310 } 311 312 /* set states (most default value are 0 and struct already 313 * initialized to 0, thus avoid resetting them) 314 */ 315 rstate->states[R600_VS_SHADER__SPI_VS_OUT_ID_0] = 0x03020100; 316 rstate->states[R600_VS_SHADER__SPI_VS_OUT_ID_1] = 0x07060504; 317 rstate->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = 0x00000005; 318 319 rstate->bo[0] = bo; 320 rstate->bo[1] = radeon_bo_incref(rscreen->rw, bo); 321 rstate->nbo = 2; 322 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; 323 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT; 324 325 if (radeon_state_pm4(rstate)) { 326 radeon_state_decref(rstate); 327 return NULL; 328 } 329 return rstate; 330} 331 332static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscreen) 333{ 334 struct radeon_state *rstate; 335 struct radeon_bo *bo; 336 u32 shader_bc_r600[] = { 337 0x00000002, 0xA00C0000, 338 0xC0008000, 0x94200688, 339 0x00000000, 0x00201910, 340 0x00000400, 0x20201910, 341 0x00000800, 0x40201910, 342 0x80000C00, 0x60201910 343 }; 344 u32 shader_bc_r700[] = { 345 0x00000002, 0xA00C0000, 346 0xC0008000, 0x94200688, 347 0x00000000, 0x00200C90, 348 0x00000400, 0x20200C90, 349 0x00000800, 0x40200C90, 350 0x80000C00, 0x60200C90 351 }; 352 353 /* simple shader */ 354 bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL); 355 if (bo == NULL) { 356 radeon_bo_decref(rscreen->rw, bo); 357 return NULL; 358 } 359 if (radeon_bo_map(rscreen->rw, bo)) { 360 return NULL; 361 } 362 switch (rscreen->chip_class) { 363 case R600: 364 memcpy(bo->data, shader_bc_r600, 48); 365 break; 366 case R700: 367 memcpy(bo->data, shader_bc_r700, 48); 368 break; 369 default: 370 R600_ERR("unsupported chip family\n"); 371 radeon_bo_unmap(rscreen->rw, bo); 372 radeon_bo_decref(rscreen->rw, bo); 373 return NULL; 374 } 375 radeon_bo_unmap(rscreen->rw, bo); 376 377 rstate = radeon_state_shader(rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS); 378 if (rstate == NULL) { 379 radeon_bo_decref(rscreen->rw, bo); 380 return NULL; 381 } 382 383 /* set states (most default value are 0 and struct already 384 * initialized to 0, thus avoid resetting them) 385 */ 386 rstate->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0] = 0x00000C00; 387 rstate->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = 0x10000001; 388 rstate->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = 0x00000002; 389 rstate->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = 0x00000002; 390 391 rstate->bo[0] = bo; 392 rstate->nbo = 1; 393 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; 394 395 if (radeon_state_pm4(rstate)) { 396 radeon_state_decref(rstate); 397 return NULL; 398 } 399 return rstate; 400} 401 402static struct radeon_state *r600_blit_state_vgt(struct r600_screen *rscreen) 403{ 404 struct radeon_state *rstate; 405 406 rstate = radeon_state(rscreen->rw, R600_STATE_VGT, 0); if (rstate == NULL) 407 return NULL; 408 409 /* set states (most default value are 0 and struct already 410 * initialized to 0, thus avoid resetting them) 411 */ 412 rstate->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001; 413 rstate->states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF; 414 rstate->states[R600_VGT__VGT_PRIMITIVE_TYPE] = 0x00000005; 415 416 if (radeon_state_pm4(rstate)) { 417 radeon_state_decref(rstate); 418 return NULL; 419 } 420 return rstate; 421} 422 423static struct radeon_state *r600_blit_state_draw(struct r600_screen *rscreen) 424{ 425 struct radeon_state *rstate; 426 427 rstate = radeon_state(rscreen->rw, R600_STATE_DRAW, 0); 428 if (rstate == NULL) 429 return NULL; 430 431 /* set states (most default value are 0 and struct already 432 * initialized to 0, thus avoid resetting them) 433 */ 434 rstate->states[R600_DRAW__VGT_DRAW_INITIATOR] = 0x00000002; 435 rstate->states[R600_DRAW__VGT_NUM_INDICES] = 0x00000004; 436 437 if (radeon_state_pm4(rstate)) { 438 radeon_state_decref(rstate); 439 return NULL; 440 } 441 return rstate; 442} 443 444static struct radeon_state *r600_blit_state_vs_constant(struct r600_screen *rscreen, 445 unsigned id, float c0, float c1, 446 float c2, float c3) 447{ 448 struct radeon_state *rstate; 449 450 rstate = radeon_state_shader(rscreen->rw, R600_STATE_CONSTANT, id, R600_SHADER_VS); 451 if (rstate == NULL) 452 return NULL; 453 454 /* set states (most default value are 0 and struct already 455 * initialized to 0, thus avoid resetting them) 456 */ 457 rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256] = fui(c0); 458 rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256] = fui(c1); 459 rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256] = fui(c2); 460 rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256] = fui(c3); 461 462 if (radeon_state_pm4(rstate)) { 463 radeon_state_decref(rstate); 464 return NULL; 465 } 466 return rstate; 467} 468 469static struct radeon_state *r600_blit_state_rasterizer(struct r600_screen *rscreen) 470{ 471 struct radeon_state *rstate; 472 473 rstate = radeon_state(rscreen->rw, R600_STATE_RASTERIZER, 0); 474 if (rstate == NULL) 475 return NULL; 476 477 /* set states (most default value are 0 and struct already 478 * initialized to 0, thus avoid resetting them) 479 */ 480 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000; 481 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000; 482 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000; 483 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000; 484 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400; 485 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005; 486 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008; 487 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000; 488 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080004; 489 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001; 490 491 if (radeon_state_pm4(rstate)) { 492 radeon_state_decref(rstate); 493 return NULL; 494 } 495 return rstate; 496} 497 498static struct radeon_state *r600_blit_state_dsa(struct r600_screen *rscreen) 499{ 500 struct radeon_state *rstate; 501 502 rstate = radeon_state(rscreen->rw, R600_STATE_DSA, 0); 503 if (rstate == NULL) 504 return NULL; 505 506 /* set states (most default value are 0 and struct already 507 * initialized to 0, thus avoid resetting them) 508 */ 509 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00; 510 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000; 511 rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060; 512 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A; 513 rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210; 514 515 if (radeon_state_pm4(rstate)) { 516 radeon_state_decref(rstate); 517 return NULL; 518 } 519 return rstate; 520} 521 522static struct radeon_state *r600_blit_state_blend(struct r600_screen *rscreen) 523{ 524 struct radeon_state *rstate; 525 526 rstate = radeon_state(rscreen->rw, R600_STATE_BLEND, 0); 527 if (rstate == NULL) 528 return NULL; 529 530 /* set states (most default value are 0 and struct already 531 * initialized to 0, thus avoid resetting them) 532 */ 533 534 if (radeon_state_pm4(rstate)) { 535 radeon_state_decref(rstate); 536 return NULL; 537 } 538 return rstate; 539} 540 541static struct radeon_state *r600_blit_state_cb_cntl(struct r600_screen *rscreen) 542{ 543 struct radeon_state *rstate; 544 545 rstate = radeon_state(rscreen->rw, R600_STATE_CB_CNTL, 0); 546 if (rstate == NULL) 547 return NULL; 548 549 /* set states (most default value are 0 and struct already 550 * initialized to 0, thus avoid resetting them) 551 */ 552 rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000; 553 rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF; 554 rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF; 555 rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = 0x00CC0080; 556 rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F; 557 rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x0000000F; 558 rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF; 559 560 if (radeon_state_pm4(rstate)) { 561 radeon_state_decref(rstate); 562 return NULL; 563 } 564 return rstate; 565} 566 567static int r600_blit_states_init(struct pipe_context *ctx, struct r600_blit_states *bstates) 568{ 569 struct r600_screen *rscreen = r600_screen(ctx->screen); 570 struct r600_context *rctx = r600_context(ctx); 571 int r; 572 573 bstates->ps_shader = r600_blit_state_ps_shader(rscreen); 574 if (bstates->ps_shader == NULL) { 575 R600_ERR("failed creating ps_shader state\n"); 576 return -ENOMEM; 577 } 578 bstates->vs_shader = r600_blit_state_vs_shader(rscreen); 579 if (bstates->vs_shader == NULL) { 580 R600_ERR("failed creating vs_shader state\n"); 581 return -ENOMEM; 582 } 583 bstates->vgt = r600_blit_state_vgt(rscreen); 584 if (bstates->vgt == NULL) { 585 R600_ERR("failed creating vgt state\n"); 586 return -ENOMEM; 587 } 588 bstates->draw = r600_blit_state_draw(rscreen); 589 if (bstates->draw == NULL) { 590 R600_ERR("failed creating draw state\n"); 591 return -ENOMEM; 592 } 593 bstates->vs_constant0 = r600_blit_state_vs_constant(rscreen, 0, 1.0, 0.0, 0.0, 0.0); 594 if (bstates->vs_constant0 == NULL) { 595 R600_ERR("failed creating vs_constant0 state\n"); 596 return -ENOMEM; 597 } 598 bstates->vs_constant1 = r600_blit_state_vs_constant(rscreen, 1, 0.0, 1.0, 0.0, 0.0); 599 if (bstates->vs_constant1 == NULL) { 600 R600_ERR("failed creating vs_constant1 state\n"); 601 return -ENOMEM; 602 } 603 bstates->vs_constant2 = r600_blit_state_vs_constant(rscreen, 2, 0.0, 0.0, -0.00199900055, 0.0); 604 if (bstates->vs_constant2 == NULL) { 605 R600_ERR("failed creating vs_constant2 state\n"); 606 return -ENOMEM; 607 } 608 bstates->vs_constant3 = r600_blit_state_vs_constant(rscreen, 3, 0.0, 0.0, -0.99900049, 1.0); 609 if (bstates->vs_constant3 == NULL) { 610 R600_ERR("failed creating vs_constant3 state\n"); 611 return -ENOMEM; 612 } 613 bstates->rasterizer = r600_blit_state_rasterizer(rscreen); 614 if (bstates->rasterizer == NULL) { 615 R600_ERR("failed creating rasterizer state\n"); 616 return -ENOMEM; 617 } 618 bstates->dsa = r600_blit_state_dsa(rscreen); 619 if (bstates->dsa == NULL) { 620 R600_ERR("failed creating dsa state\n"); 621 return -ENOMEM; 622 } 623 bstates->blend = r600_blit_state_blend(rscreen); 624 if (bstates->blend == NULL) { 625 R600_ERR("failed creating blend state\n"); 626 return -ENOMEM; 627 } 628 bstates->cb_cntl = r600_blit_state_cb_cntl(rscreen); 629 if (bstates->cb_cntl == NULL) { 630 R600_ERR("failed creating cb_cntl state\n"); 631 return -ENOMEM; 632 } 633 r = r600_blit_state_vs_resources(rscreen, bstates); 634 if (r) { 635 R600_ERR("failed creating vs_resource state\n"); 636 return r; 637 } 638 bstates->config = radeon_state_incref(rctx->hw_states.config); 639 return 0; 640} 641 642static void r600_blit_states_destroy(struct pipe_context *ctx, struct r600_blit_states *bstates) 643{ 644 radeon_state_decref(bstates->rasterizer); 645 radeon_state_decref(bstates->dsa); 646 radeon_state_decref(bstates->blend); 647 radeon_state_decref(bstates->cb_cntl); 648 radeon_state_decref(bstates->config); 649 radeon_state_decref(bstates->vgt); 650 radeon_state_decref(bstates->draw); 651 radeon_state_decref(bstates->vs_constant0); 652 radeon_state_decref(bstates->vs_constant1); 653 radeon_state_decref(bstates->vs_constant2); 654 radeon_state_decref(bstates->vs_constant3); 655 radeon_state_decref(bstates->ps_shader); 656 radeon_state_decref(bstates->vs_shader); 657 radeon_state_decref(bstates->vs_resource0); 658 radeon_state_decref(bstates->vs_resource1); 659} 660 661int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level) 662{ 663 struct r600_screen *rscreen = r600_screen(ctx->screen); 664 struct r600_context *rctx = r600_context(ctx); 665 struct radeon_draw *draw = NULL; 666 struct r600_blit_states bstates; 667 int r; 668 669 r = r600_texture_scissor(ctx, rtexture, level); 670 if (r) { 671 return r; 672 } 673 r = r600_texture_cb0(ctx, rtexture, level); 674 if (r) { 675 return r; 676 } 677 r = r600_texture_db(ctx, rtexture, level); 678 if (r) { 679 return r; 680 } 681 r = r600_texture_viewport(ctx, rtexture, level); 682 if (r) { 683 return r; 684 } 685 686 r = r600_blit_states_init(ctx, &bstates); 687 if (r) { 688 return r; 689 } 690 bstates.dsa->states[R600_DSA__DB_RENDER_CONTROL] = 0x0000008C; 691 bstates.cb_cntl->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x00000001; 692 /* force rebuild */ 693 bstates.dsa->cpm4 = bstates.cb_cntl->cpm4 = 0; 694 if (radeon_state_pm4(bstates.dsa)) { 695 goto out; 696 } 697 if (radeon_state_pm4(bstates.cb_cntl)) { 698 goto out; 699 } 700 701 draw = radeon_draw(rscreen->rw); 702 if (draw == NULL) { 703 R600_ERR("failed creating draw for uncompressing textures\n"); 704 goto out; 705 } 706 707 r = radeon_draw_set(draw, bstates.vs_shader); 708 if (r) { 709 goto out; 710 } 711 r = radeon_draw_set(draw, bstates.ps_shader); 712 if (r) { 713 goto out; 714 } 715 r = radeon_draw_set(draw, bstates.rasterizer); 716 if (r) { 717 goto out; 718 } 719 r = radeon_draw_set(draw, bstates.dsa); 720 if (r) { 721 goto out; 722 } 723 r = radeon_draw_set(draw, bstates.blend); 724 if (r) { 725 goto out; 726 } 727 r = radeon_draw_set(draw, bstates.cb_cntl); 728 if (r) { 729 goto out; 730 } 731 r = radeon_draw_set(draw, bstates.config); 732 if (r) { 733 goto out; 734 } 735 r = radeon_draw_set(draw, bstates.vgt); 736 if (r) { 737 goto out; 738 } 739 r = radeon_draw_set(draw, bstates.draw); 740 if (r) { 741 goto out; 742 } 743 r = radeon_draw_set(draw, bstates.vs_resource0); 744 if (r) { 745 goto out; 746 } 747 r = radeon_draw_set(draw, bstates.vs_resource1); 748 if (r) { 749 goto out; 750 } 751 r = radeon_draw_set(draw, bstates.vs_constant0); 752 if (r) { 753 goto out; 754 } 755 r = radeon_draw_set(draw, bstates.vs_constant1); 756 if (r) { 757 goto out; 758 } 759 r = radeon_draw_set(draw, bstates.vs_constant2); 760 if (r) { 761 goto out; 762 } 763 r = radeon_draw_set(draw, bstates.vs_constant3); 764 if (r) { 765 goto out; 766 } 767 r = radeon_draw_set(draw, rtexture->viewport[level]); 768 if (r) { 769 goto out; 770 } 771 r = radeon_draw_set(draw, rtexture->scissor[level]); 772 if (r) { 773 goto out; 774 } 775 r = radeon_draw_set(draw, rtexture->cb0[level]); 776 if (r) { 777 goto out; 778 } 779 r = radeon_draw_set(draw, rtexture->db[level]); 780 if (r) { 781 goto out; 782 } 783 784 /* suspend queries */ 785 r600_queries_suspend(ctx); 786 787 /* schedule draw*/ 788 r = radeon_ctx_set_draw_new(rctx->ctx, draw); 789 if (r == -EBUSY) { 790 r600_flush(ctx, 0, NULL); 791 r = radeon_ctx_set_draw_new(rctx->ctx, draw); 792 } 793 if (r) { 794 goto out; 795 } 796 797 /* resume queries */ 798 r600_queries_resume(ctx); 799 800out: 801 r600_blit_states_destroy(ctx, &bstates); 802 return r; 803} 804