r600_blit.c revision bd25e23bf3740f59ce8859848c715daeb9e9821f
1/* 2 * Copyright 2009 Marek Olšák <maraeo@gmail.com> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 * Marek Olšák 26 */ 27#include <errno.h> 28#include <pipe/p_screen.h> 29#include <util/u_blitter.h> 30#include <util/u_inlines.h> 31#include <util/u_memory.h> 32#include "util/u_surface.h" 33#include "r600_screen.h" 34#include "r600_context.h" 35#include "r600d.h" 36 37static void r600_blitter_save_states(struct pipe_context *ctx) 38{ 39 struct r600_context *rctx = r600_context(ctx); 40 41 util_blitter_save_blend(rctx->blitter, rctx->blend); 42 util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->dsa); 43 if (rctx->stencil_ref) { 44 util_blitter_save_stencil_ref(rctx->blitter, 45 &rctx->stencil_ref->state.stencil_ref); 46 } 47 util_blitter_save_rasterizer(rctx->blitter, rctx->rasterizer); 48 util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader); 49 util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader); 50 util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements); 51 if (rctx->viewport) { 52 util_blitter_save_viewport(rctx->blitter, &rctx->viewport->state.viewport); 53 } 54 if (rctx->clip) { 55 util_blitter_save_clip(rctx->blitter, &rctx->clip->state.clip); 56 } 57 util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer, 58 rctx->vertex_buffer); 59 60 /* remove ptr so they don't get deleted */ 61 rctx->blend = NULL; 62 rctx->clip = NULL; 63 rctx->vs_shader = NULL; 64 rctx->ps_shader = NULL; 65 rctx->rasterizer = NULL; 66 rctx->dsa = NULL; 67 rctx->vertex_elements = NULL; 68 69 /* suspend queries */ 70 r600_queries_suspend(ctx); 71} 72 73static void r600_clear(struct pipe_context *ctx, unsigned buffers, 74 const float *rgba, double depth, unsigned stencil) 75{ 76 struct r600_context *rctx = r600_context(ctx); 77 struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer; 78 79 r600_blitter_save_states(ctx); 80 util_blitter_clear(rctx->blitter, fb->width, fb->height, 81 fb->nr_cbufs, buffers, rgba, depth, 82 stencil); 83 /* resume queries */ 84 r600_queries_resume(ctx); 85} 86 87static void r600_clear_render_target(struct pipe_context *ctx, 88 struct pipe_surface *dst, 89 const float *rgba, 90 unsigned dstx, unsigned dsty, 91 unsigned width, unsigned height) 92{ 93 struct r600_context *rctx = r600_context(ctx); 94 struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer; 95 96 r600_blitter_save_states(ctx); 97 util_blitter_save_framebuffer(rctx->blitter, fb); 98 99 util_blitter_clear_render_target(rctx->blitter, dst, rgba, 100 dstx, dsty, width, height); 101 /* resume queries */ 102 r600_queries_resume(ctx); 103} 104 105static void r600_clear_depth_stencil(struct pipe_context *ctx, 106 struct pipe_surface *dst, 107 unsigned clear_flags, 108 double depth, 109 unsigned stencil, 110 unsigned dstx, unsigned dsty, 111 unsigned width, unsigned height) 112{ 113 struct r600_context *rctx = r600_context(ctx); 114 struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer; 115 116 r600_blitter_save_states(ctx); 117 util_blitter_save_framebuffer(rctx->blitter, fb); 118 119 util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil, 120 dstx, dsty, width, height); 121 /* resume queries */ 122 r600_queries_resume(ctx); 123} 124 125 126static void r600_resource_copy_region(struct pipe_context *ctx, 127 struct pipe_resource *dst, 128 struct pipe_subresource subdst, 129 unsigned dstx, unsigned dsty, unsigned dstz, 130 struct pipe_resource *src, 131 struct pipe_subresource subsrc, 132 unsigned srcx, unsigned srcy, unsigned srcz, 133 unsigned width, unsigned height) 134{ 135 util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz, 136 src, subsrc, srcx, srcy, srcz, width, height); 137} 138 139void r600_init_blit_functions(struct r600_context *rctx) 140{ 141 rctx->context.clear = r600_clear; 142 rctx->context.clear_render_target = r600_clear_render_target; 143 rctx->context.clear_depth_stencil = r600_clear_depth_stencil; 144 rctx->context.resource_copy_region = r600_resource_copy_region; 145} 146 147 148struct r600_blit_states { 149 struct radeon_state *rasterizer; 150 struct radeon_state *dsa; 151 struct radeon_state *blend; 152 struct radeon_state *cb_cntl; 153 struct radeon_state *config; 154 struct radeon_state *vgt; 155 struct radeon_state *draw; 156 struct radeon_state *vs_constant0; 157 struct radeon_state *vs_constant1; 158 struct radeon_state *vs_constant2; 159 struct radeon_state *vs_constant3; 160 struct radeon_state *ps_shader; 161 struct radeon_state *vs_shader; 162 struct radeon_state *vs_resource0; 163 struct radeon_state *vs_resource1; 164}; 165 166static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600_blit_states *bstates) 167{ 168 struct radeon_state *rstate; 169 struct radeon_bo *bo; 170 u32 vbo[] = { 171 0xBF800000, 0xBF800000, 0x3F800000, 0x3F800000, 172 0x3F000000, 0x3F000000, 0x3F000000, 0x00000000, 173 0x3F800000, 0xBF800000, 0x3F800000, 0x3F800000, 174 0x3F000000, 0x3F000000, 0x3F000000, 0x00000000, 175 0x3F800000, 0x3F800000, 0x3F800000, 0x3F800000, 176 0x3F000000, 0x3F000000, 0x3F000000, 0x00000000, 177 0xBF800000, 0x3F800000, 0x3F800000, 0x3F800000, 178 0x3F000000, 0x3F000000, 0x3F000000, 0x00000000 179 }; 180 181 /* simple shader */ 182 bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL); 183 if (bo == NULL) { 184 return -ENOMEM; 185 } 186 if (radeon_bo_map(rscreen->rw, bo)) { 187 radeon_bo_decref(rscreen->rw, bo); 188 return -ENOMEM; 189 } 190 memcpy(bo->data, vbo, 128); 191 radeon_bo_unmap(rscreen->rw, bo); 192 193 rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + 0); 194 if (rstate == NULL) { 195 radeon_bo_decref(rscreen->rw, bo); 196 return -ENOMEM; 197 } 198 199 /* set states (most default value are 0 and struct already 200 * initialized to 0, thus avoid resetting them) 201 */ 202 rstate->states[R600_RESOURCE__RESOURCE_WORD0] = 0x00000000; 203 rstate->states[R600_RESOURCE__RESOURCE_WORD1] = 0x00000080; 204 rstate->states[R600_RESOURCE__RESOURCE_WORD2] = 0x02302000; 205 rstate->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000; 206 rstate->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000; 207 rstate->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000; 208 rstate->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000; 209 rstate->bo[0] = bo; 210 rstate->nbo = 1; 211 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; 212 rstate->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID; 213 rstate->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID; 214 if (radeon_state_pm4(rstate)) { 215 radeon_state_decref(rstate); 216 return -ENOMEM; 217 } 218 bstates->vs_resource0 = rstate; 219 220 rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + 1); 221 if (rstate == NULL) { 222 return -ENOMEM; 223 } 224 rstate->states[R600_RESOURCE__RESOURCE_WORD0] = 0x00000010; 225 rstate->states[R600_RESOURCE__RESOURCE_WORD1] = 0x00000070; 226 rstate->states[R600_RESOURCE__RESOURCE_WORD2] = 0x02302000; 227 rstate->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000; 228 rstate->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000; 229 rstate->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000; 230 rstate->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000; 231 rstate->bo[0] = radeon_bo_incref(rscreen->rw, bo); 232 rstate->nbo = 1; 233 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; 234 if (radeon_state_pm4(rstate)) { 235 radeon_state_decref(rstate); 236 return -ENOMEM; 237 } 238 bstates->vs_resource1 = rstate; 239 240 return 0; 241} 242 243static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscreen) 244{ 245 struct radeon_state *rstate; 246 struct radeon_bo *bo; 247 u32 shader_bc_r600[] = { 248 0x00000004, 0x81000400, 249 0x00000008, 0xA01C0000, 250 0xC001A03C, 0x94000688, 251 0xC0024000, 0x94200688, 252 0x7C000000, 0x002D1001, 253 0x00080000, 0x00000000, 254 0x7C000100, 0x002D1002, 255 0x00080000, 0x00000000, 256 0x00000001, 0x00601910, 257 0x00000401, 0x20601910, 258 0x00000801, 0x40601910, 259 0x80000C01, 0x60601910, 260 0x00000002, 0x00801910, 261 0x00000402, 0x20801910, 262 0x00000802, 0x40801910, 263 0x80000C02, 0x60801910 264 }; 265 u32 shader_bc_r700[] = { 266 0x00000004, 0x81000400, 267 0x00000008, 0xA01C0000, 268 0xC001A03C, 0x94000688, 269 0xC0024000, 0x94200688, 270 0x7C000000, 0x002D1001, 271 0x00080000, 0x00000000, 272 0x7C000100, 0x002D1002, 273 0x00080000, 0x00000000, 274 0x00000001, 0x00600C90, 275 0x00000401, 0x20600C90, 276 0x00000801, 0x40600C90, 277 0x80000C01, 0x60600C90, 278 0x00000002, 0x00800C90, 279 0x00000402, 0x20800C90, 280 0x00000802, 0x40800C90, 281 0x80000C02, 0x60800C90 282 }; 283 284 /* simple shader */ 285 bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL); 286 if (bo == NULL) { 287 return NULL; 288 } 289 if (radeon_bo_map(rscreen->rw, bo)) { 290 radeon_bo_decref(rscreen->rw, bo); 291 return NULL; 292 } 293 switch (rscreen->chip_class) { 294 case R600: 295 memcpy(bo->data, shader_bc_r600, 128); 296 break; 297 case R700: 298 memcpy(bo->data, shader_bc_r700, 128); 299 break; 300 default: 301 R600_ERR("unsupported chip family\n"); 302 radeon_bo_unmap(rscreen->rw, bo); 303 radeon_bo_decref(rscreen->rw, bo); 304 return NULL; 305 } 306 radeon_bo_unmap(rscreen->rw, bo); 307 308 rstate = radeon_state(rscreen->rw, R600_VS_SHADER); 309 if (rstate == NULL) { 310 radeon_bo_decref(rscreen->rw, bo); 311 return NULL; 312 } 313 314 /* set states (most default value are 0 and struct already 315 * initialized to 0, thus avoid resetting them) 316 */ 317 rstate->states[R600_VS_SHADER__SPI_VS_OUT_ID_0] = 0x03020100; 318 rstate->states[R600_VS_SHADER__SPI_VS_OUT_ID_1] = 0x07060504; 319 rstate->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = 0x00000005; 320 321 rstate->bo[0] = bo; 322 rstate->bo[1] = radeon_bo_incref(rscreen->rw, bo); 323 rstate->nbo = 2; 324 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; 325 rstate->placement[2] = RADEON_GEM_DOMAIN_GTT; 326 rstate->reloc_pm4_id[0] = R600_VS_SHADER__SQ_PGM_START_VS_BO_ID; 327 rstate->reloc_pm4_id[1] = R600_VS_SHADER__SQ_PGM_START_FS_BO_ID; 328 329 if (radeon_state_pm4(rstate)) { 330 radeon_state_decref(rstate); 331 return NULL; 332 } 333 return rstate; 334} 335 336static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscreen) 337{ 338 struct radeon_state *rstate; 339 struct radeon_bo *bo; 340 u32 shader_bc_r600[] = { 341 0x00000002, 0xA00C0000, 342 0xC0008000, 0x94200688, 343 0x00000000, 0x00201910, 344 0x00000400, 0x20201910, 345 0x00000800, 0x40201910, 346 0x80000C00, 0x60201910 347 }; 348 u32 shader_bc_r700[] = { 349 0x00000002, 0xA00C0000, 350 0xC0008000, 0x94200688, 351 0x00000000, 0x00200C90, 352 0x00000400, 0x20200C90, 353 0x00000800, 0x40200C90, 354 0x80000C00, 0x60200C90 355 }; 356 357 /* simple shader */ 358 bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL); 359 if (bo == NULL) { 360 radeon_bo_decref(rscreen->rw, bo); 361 return NULL; 362 } 363 if (radeon_bo_map(rscreen->rw, bo)) { 364 return NULL; 365 } 366 switch (rscreen->chip_class) { 367 case R600: 368 memcpy(bo->data, shader_bc_r600, 48); 369 break; 370 case R700: 371 memcpy(bo->data, shader_bc_r700, 48); 372 break; 373 default: 374 R600_ERR("unsupported chip family\n"); 375 radeon_bo_unmap(rscreen->rw, bo); 376 radeon_bo_decref(rscreen->rw, bo); 377 return NULL; 378 } 379 radeon_bo_unmap(rscreen->rw, bo); 380 381 rstate = radeon_state(rscreen->rw, R600_PS_SHADER); 382 if (rstate == NULL) { 383 radeon_bo_decref(rscreen->rw, bo); 384 return NULL; 385 } 386 387 /* set states (most default value are 0 and struct already 388 * initialized to 0, thus avoid resetting them) 389 */ 390 rstate->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0] = 0x00000C00; 391 rstate->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = 0x10000001; 392 rstate->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = 0x00000002; 393 rstate->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = 0x00000002; 394 395 rstate->bo[0] = bo; 396 rstate->nbo = 1; 397 rstate->placement[0] = RADEON_GEM_DOMAIN_GTT; 398 rstate->reloc_pm4_id[0] = R600_PS_SHADER__SQ_PGM_START_PS_BO_ID; 399 400 if (radeon_state_pm4(rstate)) { 401 radeon_state_decref(rstate); 402 return NULL; 403 } 404 return rstate; 405} 406 407static struct radeon_state *r600_blit_state_vgt(struct r600_screen *rscreen) 408{ 409 struct radeon_state *rstate; 410 411 rstate = radeon_state(rscreen->rw, R600_VGT); 412 if (rstate == NULL) 413 return NULL; 414 415 /* set states (most default value are 0 and struct already 416 * initialized to 0, thus avoid resetting them) 417 */ 418 rstate->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001; 419 rstate->states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF; 420 rstate->states[R600_VGT__VGT_PRIMITIVE_TYPE] = 0x00000005; 421 422 if (radeon_state_pm4(rstate)) { 423 radeon_state_decref(rstate); 424 return NULL; 425 } 426 return rstate; 427} 428 429static struct radeon_state *r600_blit_state_draw(struct r600_screen *rscreen) 430{ 431 struct radeon_state *rstate; 432 433 rstate = radeon_state(rscreen->rw, R600_DRAW); 434 if (rstate == NULL) 435 return NULL; 436 437 /* set states (most default value are 0 and struct already 438 * initialized to 0, thus avoid resetting them) 439 */ 440 rstate->states[R600_DRAW__VGT_DRAW_INITIATOR] = 0x00000002; 441 rstate->states[R600_DRAW__VGT_NUM_INDICES] = 0x00000004; 442 443 if (radeon_state_pm4(rstate)) { 444 radeon_state_decref(rstate); 445 return NULL; 446 } 447 return rstate; 448} 449 450static struct radeon_state *r600_blit_state_vs_constant(struct r600_screen *rscreen, 451 unsigned id, float c0, float c1, 452 float c2, float c3) 453{ 454 struct radeon_state *rstate; 455 456 rstate = radeon_state(rscreen->rw, R600_VS_CONSTANT0 + id); 457 if (rstate == NULL) 458 return NULL; 459 460 /* set states (most default value are 0 and struct already 461 * initialized to 0, thus avoid resetting them) 462 */ 463 rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256] = fui(c0); 464 rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256] = fui(c1); 465 rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256] = fui(c2); 466 rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256] = fui(c3); 467 468 if (radeon_state_pm4(rstate)) { 469 radeon_state_decref(rstate); 470 return NULL; 471 } 472 return rstate; 473} 474 475static struct radeon_state *r600_blit_state_rasterizer(struct r600_screen *rscreen) 476{ 477 struct radeon_state *rstate; 478 479 rstate = radeon_state(rscreen->rw, R600_RASTERIZER); 480 if (rstate == NULL) 481 return NULL; 482 483 /* set states (most default value are 0 and struct already 484 * initialized to 0, thus avoid resetting them) 485 */ 486 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000; 487 rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000; 488 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000; 489 rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000; 490 rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400; 491 rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005; 492 rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008; 493 rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000; 494 rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080004; 495 rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001; 496 497 if (radeon_state_pm4(rstate)) { 498 radeon_state_decref(rstate); 499 return NULL; 500 } 501 return rstate; 502} 503 504static struct radeon_state *r600_blit_state_dsa(struct r600_screen *rscreen) 505{ 506 struct radeon_state *rstate; 507 508 rstate = radeon_state(rscreen->rw, R600_DSA); 509 if (rstate == NULL) 510 return NULL; 511 512 /* set states (most default value are 0 and struct already 513 * initialized to 0, thus avoid resetting them) 514 */ 515 rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00; 516 rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000; 517 rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060; 518 rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A; 519 rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210; 520 521 if (radeon_state_pm4(rstate)) { 522 radeon_state_decref(rstate); 523 return NULL; 524 } 525 return rstate; 526} 527 528static struct radeon_state *r600_blit_state_blend(struct r600_screen *rscreen) 529{ 530 struct radeon_state *rstate; 531 532 rstate = radeon_state(rscreen->rw, R600_BLEND); 533 if (rstate == NULL) 534 return NULL; 535 536 /* set states (most default value are 0 and struct already 537 * initialized to 0, thus avoid resetting them) 538 */ 539 540 if (radeon_state_pm4(rstate)) { 541 radeon_state_decref(rstate); 542 return NULL; 543 } 544 return rstate; 545} 546 547static struct radeon_state *r600_blit_state_cb_cntl(struct r600_screen *rscreen) 548{ 549 struct radeon_state *rstate; 550 551 rstate = radeon_state(rscreen->rw, R600_CB_CNTL); 552 if (rstate == NULL) 553 return NULL; 554 555 /* set states (most default value are 0 and struct already 556 * initialized to 0, thus avoid resetting them) 557 */ 558 rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000; 559 rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF; 560 rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF; 561 rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = 0x00CC0080; 562 rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F; 563 rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x0000000F; 564 rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF; 565 566 if (radeon_state_pm4(rstate)) { 567 radeon_state_decref(rstate); 568 return NULL; 569 } 570 return rstate; 571} 572 573static int r600_blit_states_init(struct pipe_context *ctx, struct r600_blit_states *bstates) 574{ 575 struct r600_screen *rscreen = r600_screen(ctx->screen); 576 struct r600_context *rctx = r600_context(ctx); 577 int r; 578 579 bstates->ps_shader = r600_blit_state_ps_shader(rscreen); 580 if (bstates->ps_shader == NULL) { 581 R600_ERR("failed creating ps_shader state\n"); 582 return -ENOMEM; 583 } 584 bstates->vs_shader = r600_blit_state_vs_shader(rscreen); 585 if (bstates->vs_shader == NULL) { 586 R600_ERR("failed creating vs_shader state\n"); 587 return -ENOMEM; 588 } 589 bstates->vgt = r600_blit_state_vgt(rscreen); 590 if (bstates->vgt == NULL) { 591 R600_ERR("failed creating vgt state\n"); 592 return -ENOMEM; 593 } 594 bstates->draw = r600_blit_state_draw(rscreen); 595 if (bstates->draw == NULL) { 596 R600_ERR("failed creating draw state\n"); 597 return -ENOMEM; 598 } 599 bstates->vs_constant0 = r600_blit_state_vs_constant(rscreen, 0, 1.0, 0.0, 0.0, 0.0); 600 if (bstates->vs_constant0 == NULL) { 601 R600_ERR("failed creating vs_constant0 state\n"); 602 return -ENOMEM; 603 } 604 bstates->vs_constant1 = r600_blit_state_vs_constant(rscreen, 1, 0.0, 1.0, 0.0, 0.0); 605 if (bstates->vs_constant1 == NULL) { 606 R600_ERR("failed creating vs_constant1 state\n"); 607 return -ENOMEM; 608 } 609 bstates->vs_constant2 = r600_blit_state_vs_constant(rscreen, 2, 0.0, 0.0, -0.00199900055, 0.0); 610 if (bstates->vs_constant2 == NULL) { 611 R600_ERR("failed creating vs_constant2 state\n"); 612 return -ENOMEM; 613 } 614 bstates->vs_constant3 = r600_blit_state_vs_constant(rscreen, 3, 0.0, 0.0, -0.99900049, 1.0); 615 if (bstates->vs_constant3 == NULL) { 616 R600_ERR("failed creating vs_constant3 state\n"); 617 return -ENOMEM; 618 } 619 bstates->rasterizer = r600_blit_state_rasterizer(rscreen); 620 if (bstates->rasterizer == NULL) { 621 R600_ERR("failed creating rasterizer state\n"); 622 return -ENOMEM; 623 } 624 bstates->dsa = r600_blit_state_dsa(rscreen); 625 if (bstates->dsa == NULL) { 626 R600_ERR("failed creating dsa state\n"); 627 return -ENOMEM; 628 } 629 bstates->blend = r600_blit_state_blend(rscreen); 630 if (bstates->blend == NULL) { 631 R600_ERR("failed creating blend state\n"); 632 return -ENOMEM; 633 } 634 bstates->cb_cntl = r600_blit_state_cb_cntl(rscreen); 635 if (bstates->cb_cntl == NULL) { 636 R600_ERR("failed creating cb_cntl state\n"); 637 return -ENOMEM; 638 } 639 r = r600_blit_state_vs_resources(rscreen, bstates); 640 if (r) { 641 R600_ERR("failed creating vs_resource state\n"); 642 return r; 643 } 644 bstates->config = radeon_state_incref(rctx->hw_states.config); 645 return 0; 646} 647 648static void r600_blit_states_destroy(struct pipe_context *ctx, struct r600_blit_states *bstates) 649{ 650 radeon_state_decref(bstates->rasterizer); 651 radeon_state_decref(bstates->dsa); 652 radeon_state_decref(bstates->blend); 653 radeon_state_decref(bstates->cb_cntl); 654 radeon_state_decref(bstates->config); 655 radeon_state_decref(bstates->vgt); 656 radeon_state_decref(bstates->draw); 657 radeon_state_decref(bstates->vs_constant0); 658 radeon_state_decref(bstates->vs_constant1); 659 radeon_state_decref(bstates->vs_constant2); 660 radeon_state_decref(bstates->vs_constant3); 661 radeon_state_decref(bstates->ps_shader); 662 radeon_state_decref(bstates->vs_shader); 663 radeon_state_decref(bstates->vs_resource0); 664 radeon_state_decref(bstates->vs_resource1); 665} 666 667int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level) 668{ 669 struct r600_screen *rscreen = r600_screen(ctx->screen); 670 struct r600_context *rctx = r600_context(ctx); 671 struct radeon_draw *draw = NULL; 672 struct r600_blit_states bstates; 673 int r; 674 675 r = r600_texture_scissor(ctx, rtexture, level); 676 if (r) { 677 return r; 678 } 679 r = r600_texture_cb0(ctx, rtexture, level); 680 if (r) { 681 return r; 682 } 683 r = r600_texture_db(ctx, rtexture, level); 684 if (r) { 685 return r; 686 } 687 r = r600_texture_viewport(ctx, rtexture, level); 688 if (r) { 689 return r; 690 } 691 692 r = r600_blit_states_init(ctx, &bstates); 693 if (r) { 694 return r; 695 } 696 bstates.dsa->states[R600_DSA__DB_RENDER_CONTROL] = 0x0000008C; 697 bstates.cb_cntl->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x00000001; 698 /* force rebuild */ 699 bstates.dsa->cpm4 = bstates.cb_cntl->cpm4 = 0; 700 if (radeon_state_pm4(bstates.dsa)) { 701 goto out; 702 } 703 if (radeon_state_pm4(bstates.cb_cntl)) { 704 goto out; 705 } 706 707 draw = radeon_draw(rscreen->rw); 708 if (draw == NULL) { 709 R600_ERR("failed creating draw for uncompressing textures\n"); 710 goto out; 711 } 712 713 r = radeon_draw_set(draw, bstates.vs_shader); 714 if (r) { 715 goto out; 716 } 717 r = radeon_draw_set(draw, bstates.ps_shader); 718 if (r) { 719 goto out; 720 } 721 r = radeon_draw_set(draw, bstates.rasterizer); 722 if (r) { 723 goto out; 724 } 725 r = radeon_draw_set(draw, bstates.dsa); 726 if (r) { 727 goto out; 728 } 729 r = radeon_draw_set(draw, bstates.blend); 730 if (r) { 731 goto out; 732 } 733 r = radeon_draw_set(draw, bstates.cb_cntl); 734 if (r) { 735 goto out; 736 } 737 r = radeon_draw_set(draw, bstates.config); 738 if (r) { 739 goto out; 740 } 741 r = radeon_draw_set(draw, bstates.vgt); 742 if (r) { 743 goto out; 744 } 745 r = radeon_draw_set(draw, bstates.draw); 746 if (r) { 747 goto out; 748 } 749 r = radeon_draw_set(draw, bstates.vs_resource0); 750 if (r) { 751 goto out; 752 } 753 r = radeon_draw_set(draw, bstates.vs_resource1); 754 if (r) { 755 goto out; 756 } 757 r = radeon_draw_set(draw, bstates.vs_constant0); 758 if (r) { 759 goto out; 760 } 761 r = radeon_draw_set(draw, bstates.vs_constant1); 762 if (r) { 763 goto out; 764 } 765 r = radeon_draw_set(draw, bstates.vs_constant2); 766 if (r) { 767 goto out; 768 } 769 r = radeon_draw_set(draw, bstates.vs_constant3); 770 if (r) { 771 goto out; 772 } 773 r = radeon_draw_set(draw, rtexture->viewport[level]); 774 if (r) { 775 goto out; 776 } 777 r = radeon_draw_set(draw, rtexture->scissor[level]); 778 if (r) { 779 goto out; 780 } 781 r = radeon_draw_set(draw, rtexture->cb0[level]); 782 if (r) { 783 goto out; 784 } 785 r = radeon_draw_set(draw, rtexture->db[level]); 786 if (r) { 787 goto out; 788 } 789 790 /* suspend queries */ 791 r600_queries_suspend(ctx); 792 793 /* schedule draw*/ 794 r = radeon_ctx_set_draw(rctx->ctx, draw); 795 if (r == -EBUSY) { 796 r600_flush(ctx, 0, NULL); 797 r = radeon_ctx_set_draw(rctx->ctx, draw); 798 } 799 if (r) { 800 goto out; 801 } 802 803 /* resume queries */ 804 r600_queries_resume(ctx); 805 806out: 807 r600_blit_states_destroy(ctx, &bstates); 808 return r; 809} 810