1
2/*---------------------------------------------------------------*/
3/*--- begin                                  guest_arm_defs.h ---*/
4/*---------------------------------------------------------------*/
5/*
6   This file is part of Valgrind, a dynamic binary instrumentation
7   framework.
8
9   Copyright (C) 2004-2012 OpenWorks LLP
10      info@open-works.net
11
12   This program is free software; you can redistribute it and/or
13   modify it under the terms of the GNU General Public License as
14   published by the Free Software Foundation; either version 2 of the
15   License, or (at your option) any later version.
16
17   This program is distributed in the hope that it will be useful, but
18   WITHOUT ANY WARRANTY; without even the implied warranty of
19   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
20   General Public License for more details.
21
22   You should have received a copy of the GNU General Public License
23   along with this program; if not, write to the Free Software
24   Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25   02110-1301, USA.
26
27   The GNU General Public License is contained in the file COPYING.
28*/
29
30/* Only to be used within the guest-arm directory. */
31
32#ifndef __VEX_GUEST_ARM_DEFS_H
33#define __VEX_GUEST_ARM_DEFS_H
34
35
36/*---------------------------------------------------------*/
37/*--- arm to IR conversion                              ---*/
38/*---------------------------------------------------------*/
39
40/* Convert one ARM insn to IR.  See the type DisOneInstrFn in
41   bb_to_IR.h. */
42extern
43DisResult disInstr_ARM ( IRSB*        irbb,
44                         Bool         (*resteerOkFn) ( void*, Addr64 ),
45                         Bool         resteerCisOk,
46                         void*        callback_opaque,
47                         UChar*       guest_code,
48                         Long         delta,
49                         Addr64       guest_IP,
50                         VexArch      guest_arch,
51                         VexArchInfo* archinfo,
52                         VexAbiInfo*  abiinfo,
53                         Bool         host_bigendian );
54
55/* Used by the optimiser to specialise calls to helpers. */
56extern
57IRExpr* guest_arm_spechelper ( HChar*   function_name,
58                               IRExpr** args,
59                               IRStmt** precedingStmts,
60                               Int      n_precedingStmts );
61
62/* Describes to the optimser which part of the guest state require
63   precise memory exceptions.  This is logically part of the guest
64   state description. */
65extern
66Bool guest_arm_state_requires_precise_mem_exns ( Int, Int );
67
68extern
69VexGuestLayout armGuest_layout;
70
71
72/*---------------------------------------------------------*/
73/*--- arm guest helpers                                 ---*/
74/*---------------------------------------------------------*/
75
76/* --- CLEAN HELPERS --- */
77
78/* Calculate NZCV from the supplied thunk components, in the positions
79   they appear in the CPSR, viz bits 31:28 for N Z V C respectively.
80   Returned bits 27:0 are zero. */
81extern
82UInt armg_calculate_flags_nzcv ( UInt cc_op, UInt cc_dep1,
83                                 UInt cc_dep2, UInt cc_dep3 );
84
85/* Calculate the C flag from the thunk components, in the lowest bit
86   of the word (bit 0). */
87extern
88UInt armg_calculate_flag_c ( UInt cc_op, UInt cc_dep1,
89                             UInt cc_dep2, UInt cc_dep3 );
90
91/* Calculate the V flag from the thunk components, in the lowest bit
92   of the word (bit 0). */
93extern
94UInt armg_calculate_flag_v ( UInt cc_op, UInt cc_dep1,
95                             UInt cc_dep2, UInt cc_dep3 );
96
97/* Calculate the specified condition from the thunk components, in the
98   lowest bit of the word (bit 0). */
99extern
100UInt armg_calculate_condition ( UInt cond_n_op /* ARMCondcode << 4 | cc_op */,
101                                UInt cc_dep1,
102                                UInt cc_dep2, UInt cc_dep3 );
103
104/* Calculate the QC flag from the thunk components, in the lowest bit
105   of the word (bit 0). */
106extern
107UInt armg_calculate_flag_qc ( UInt resL1, UInt resL2,
108                              UInt resR1, UInt resR2 );
109
110
111/*---------------------------------------------------------*/
112/*--- Condition code stuff                              ---*/
113/*---------------------------------------------------------*/
114
115/* Flags masks.  Defines positions of flags bits in the CPSR. */
116#define ARMG_CC_SHIFT_N  31
117#define ARMG_CC_SHIFT_Z  30
118#define ARMG_CC_SHIFT_C  29
119#define ARMG_CC_SHIFT_V  28
120#define ARMG_CC_SHIFT_Q  27
121
122#define ARMG_CC_MASK_N    (1 << ARMG_CC_SHIFT_N)
123#define ARMG_CC_MASK_Z    (1 << ARMG_CC_SHIFT_Z)
124#define ARMG_CC_MASK_C    (1 << ARMG_CC_SHIFT_C)
125#define ARMG_CC_MASK_V    (1 << ARMG_CC_SHIFT_V)
126#define ARMG_CC_MASK_Q    (1 << ARMG_CC_SHIFT_Q)
127
128/* Flag thunk descriptors.  A four-word thunk is used to record
129   details of the most recent flag-setting operation, so NZCV can
130   be computed later if needed.
131
132   The four words are:
133
134      CC_OP, which describes the operation.
135
136      CC_DEP1, CC_DEP2, CC_DEP3.  These are arguments to the
137         operation.  We want set up the mcx_masks in flag helper calls
138         involving these fields so that Memcheck "believes" that the
139         resulting flags are data-dependent on both CC_DEP1 and
140         CC_DEP2.  Hence the name DEP.
141
142   When building the thunk, it is always necessary to write words into
143   CC_DEP1/2/3, even if those args are not used given the
144   CC_OP field.  This is important because otherwise Memcheck could
145   give false positives as it does not understand the relationship
146   between the CC_OP field and CC_DEP1/2/3, and so believes
147   that the definedness of the stored flags always depends on
148   all 3 DEP values.
149
150   Fields carrying only 1 or 2 bits of useful information (old_C,
151   shifter_co, old_V, oldC:oldV) must have their top 31 or 30 bits
152   (respectively) zero.  The text "31x0:" or "30x0:" denotes this.
153
154   A summary of the field usages is:
155
156   OP                DEP1              DEP2              DEP3
157   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
158
159   OP_COPY           curr_NZCV:28x0    unused            unused
160   OP_ADD            argL              argR              unused
161   OP_SUB            argL              argR              unused
162   OP_ADC            argL              argR              31x0:old_C
163   OP_SBB            argL              argR              31x0:old_C
164   OP_LOGIC          result            31x0:shifter_co   31x0:old_V
165   OP_MUL            result            unused            30x0:old_C:old_V
166   OP_MULL           resLO32           resHI32           30x0:old_C:old_V
167*/
168
169enum {
170   ARMG_CC_OP_COPY=0,  /* DEP1 = NZCV in 31:28, DEP2 = 0, DEP3 = 0
171                          just copy DEP1 to output */
172
173   ARMG_CC_OP_ADD,     /* DEP1 = argL (Rn), DEP2 = argR (shifter_op),
174                          DEP3 = 0 */
175
176   ARMG_CC_OP_SUB,     /* DEP1 = argL (Rn), DEP2 = argR (shifter_op),
177                          DEP3 = 0 */
178
179   ARMG_CC_OP_ADC,     /* DEP1 = argL (Rn), DEP2 = arg2 (shifter_op),
180                          DEP3 = oldC (in LSB) */
181
182   ARMG_CC_OP_SBB,     /* DEP1 = argL (Rn), DEP2 = arg2 (shifter_op),
183                          DEP3 = oldC (in LSB) */
184
185   ARMG_CC_OP_LOGIC,   /* DEP1 = result, DEP2 = shifter_carry_out (in LSB),
186                          DEP3 = old V flag (in LSB) */
187
188   ARMG_CC_OP_MUL,     /* DEP1 = result, DEP2 = 0, DEP3 = oldC:old_V
189                          (in bits 1:0) */
190
191   ARMG_CC_OP_MULL,    /* DEP1 = resLO32, DEP2 = resHI32, DEP3 = oldC:old_V
192                          (in bits 1:0) */
193
194   ARMG_CC_OP_NUMBER
195};
196
197/* XXXX because of the calling conventions for
198   armg_calculate_condition, all this OP values MUST be in the range
199   0 .. 15 only (viz, 4-bits). */
200
201
202
203/* Defines conditions which we can ask for (ARM ARM 2e page A3-6) */
204
205typedef
206   enum {
207      ARMCondEQ     = 0,  /* equal                         : Z=1 */
208      ARMCondNE     = 1,  /* not equal                     : Z=0 */
209
210      ARMCondHS     = 2,  /* >=u (higher or same)          : C=1 */
211      ARMCondLO     = 3,  /* <u  (lower)                   : C=0 */
212
213      ARMCondMI     = 4,  /* minus (negative)              : N=1 */
214      ARMCondPL     = 5,  /* plus (zero or +ve)            : N=0 */
215
216      ARMCondVS     = 6,  /* overflow                      : V=1 */
217      ARMCondVC     = 7,  /* no overflow                   : V=0 */
218
219      ARMCondHI     = 8,  /* >u   (higher)                 : C=1 && Z=0 */
220      ARMCondLS     = 9,  /* <=u  (lower or same)          : C=0 || Z=1 */
221
222      ARMCondGE     = 10, /* >=s (signed greater or equal) : N=V */
223      ARMCondLT     = 11, /* <s  (signed less than)        : N!=V */
224
225      ARMCondGT     = 12, /* >s  (signed greater)          : Z=0 && N=V */
226      ARMCondLE     = 13, /* <=s (signed less or equal)    : Z=1 || N!=V */
227
228      ARMCondAL     = 14, /* always (unconditional)        : 1 */
229      ARMCondNV     = 15  /* never (unconditional):        : 0 */
230      /* NB: ARM have deprecated the use of the NV condition code.
231         You are now supposed to use MOV R0,R0 as a noop rather than
232         MOVNV R0,R0 as was previously recommended.  Future processors
233         may have the NV condition code reused to do other things.  */
234   }
235   ARMCondcode;
236
237#endif /* ndef __VEX_GUEST_ARM_DEFS_H */
238
239/*---------------------------------------------------------------*/
240/*--- end                                    guest_arm_defs.h ---*/
241/*---------------------------------------------------------------*/
242