host_ppc_defs.h revision 8f943afc22a6a683b78271836c8ddc462b4824a9 
1
2/*---------------------------------------------------------------*/
3/*--- begin                                   host_ppc_defs.h ---*/
4/*---------------------------------------------------------------*/
5
6/*
7   This file is part of Valgrind, a dynamic binary instrumentation
8   framework.
9
10   Copyright (C) 2004-2011 OpenWorks LLP
11      info@open-works.net
12
13   This program is free software; you can redistribute it and/or
14   modify it under the terms of the GNU General Public License as
15   published by the Free Software Foundation; either version 2 of the
16   License, or (at your option) any later version.
17
18   This program is distributed in the hope that it will be useful, but
19   WITHOUT ANY WARRANTY; without even the implied warranty of
20   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
21   General Public License for more details.
22
23   You should have received a copy of the GNU General Public License
24   along with this program; if not, write to the Free Software
25   Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
26   02110-1301, USA.
27
28   The GNU General Public License is contained in the file COPYING.
29
30   Neither the names of the U.S. Department of Energy nor the
31   University of California nor the names of its contributors may be
32   used to endorse or promote products derived from this software
33   without prior written permission.
34*/
35
36#ifndef __VEX_HOST_PPC_DEFS_H
37#define __VEX_HOST_PPC_DEFS_H
38
39/* Num registers used for function calls */
40#define PPC_N_REGPARMS 8
41
42
43/* --------- Registers. --------- */
44
45/* The usual HReg abstraction.  There are 32 real int regs,
46   32 real float regs, and 32 real vector regs.
47*/
48
49extern void ppHRegPPC ( HReg );
50
51extern HReg hregPPC_GPR0  ( Bool mode64 ); // scratch reg / zero reg
52extern HReg hregPPC_GPR1  ( Bool mode64 ); // Stack Frame Pointer
53extern HReg hregPPC_GPR2  ( Bool mode64 ); // not used: TOC pointer
54extern HReg hregPPC_GPR3  ( Bool mode64 );
55extern HReg hregPPC_GPR4  ( Bool mode64 );
56extern HReg hregPPC_GPR5  ( Bool mode64 );
57extern HReg hregPPC_GPR6  ( Bool mode64 );
58extern HReg hregPPC_GPR7  ( Bool mode64 );
59extern HReg hregPPC_GPR8  ( Bool mode64 );
60extern HReg hregPPC_GPR9  ( Bool mode64 );
61extern HReg hregPPC_GPR10 ( Bool mode64 );
62extern HReg hregPPC_GPR11 ( Bool mode64 );
63extern HReg hregPPC_GPR12 ( Bool mode64 );
64extern HReg hregPPC_GPR13 ( Bool mode64 );
65extern HReg hregPPC_GPR14 ( Bool mode64 );
66extern HReg hregPPC_GPR15 ( Bool mode64 );
67extern HReg hregPPC_GPR16 ( Bool mode64 );
68extern HReg hregPPC_GPR17 ( Bool mode64 );
69extern HReg hregPPC_GPR18 ( Bool mode64 );
70extern HReg hregPPC_GPR19 ( Bool mode64 );
71extern HReg hregPPC_GPR20 ( Bool mode64 );
72extern HReg hregPPC_GPR21 ( Bool mode64 );
73extern HReg hregPPC_GPR22 ( Bool mode64 );
74extern HReg hregPPC_GPR23 ( Bool mode64 );
75extern HReg hregPPC_GPR24 ( Bool mode64 );
76extern HReg hregPPC_GPR25 ( Bool mode64 );
77extern HReg hregPPC_GPR26 ( Bool mode64 );
78extern HReg hregPPC_GPR27 ( Bool mode64 );
79extern HReg hregPPC_GPR28 ( Bool mode64 );
80extern HReg hregPPC_GPR29 ( Bool mode64 ); // reserved for dispatcher
81extern HReg hregPPC_GPR30 ( Bool mode64 ); // used as VMX spill temp
82extern HReg hregPPC_GPR31 ( Bool mode64 ); // GuestStatePtr (callee-saved)
83
84extern HReg hregPPC_FPR0  ( void );
85extern HReg hregPPC_FPR1  ( void );
86extern HReg hregPPC_FPR2  ( void );
87extern HReg hregPPC_FPR3  ( void );
88extern HReg hregPPC_FPR4  ( void );
89extern HReg hregPPC_FPR5  ( void );
90extern HReg hregPPC_FPR6  ( void );
91extern HReg hregPPC_FPR7  ( void );
92extern HReg hregPPC_FPR8  ( void );
93extern HReg hregPPC_FPR9  ( void );
94extern HReg hregPPC_FPR10 ( void );
95extern HReg hregPPC_FPR11 ( void );
96extern HReg hregPPC_FPR12 ( void );
97extern HReg hregPPC_FPR13 ( void );
98extern HReg hregPPC_FPR14 ( void );
99extern HReg hregPPC_FPR15 ( void );
100extern HReg hregPPC_FPR16 ( void );
101extern HReg hregPPC_FPR17 ( void );
102extern HReg hregPPC_FPR18 ( void );
103extern HReg hregPPC_FPR19 ( void );
104extern HReg hregPPC_FPR20 ( void );
105extern HReg hregPPC_FPR21 ( void );
106extern HReg hregPPC_FPR22 ( void );
107extern HReg hregPPC_FPR23 ( void );
108extern HReg hregPPC_FPR24 ( void );
109extern HReg hregPPC_FPR25 ( void );
110extern HReg hregPPC_FPR26 ( void );
111extern HReg hregPPC_FPR27 ( void );
112extern HReg hregPPC_FPR28 ( void );
113extern HReg hregPPC_FPR29 ( void );
114extern HReg hregPPC_FPR30 ( void );
115extern HReg hregPPC_FPR31 ( void );
116
117extern HReg hregPPC_VR0  ( void );
118extern HReg hregPPC_VR1  ( void );
119extern HReg hregPPC_VR2  ( void );
120extern HReg hregPPC_VR3  ( void );
121extern HReg hregPPC_VR4  ( void );
122extern HReg hregPPC_VR5  ( void );
123extern HReg hregPPC_VR6  ( void );
124extern HReg hregPPC_VR7  ( void );
125extern HReg hregPPC_VR8  ( void );
126extern HReg hregPPC_VR9  ( void );
127extern HReg hregPPC_VR10 ( void );
128extern HReg hregPPC_VR11 ( void );
129extern HReg hregPPC_VR12 ( void );
130extern HReg hregPPC_VR13 ( void );
131extern HReg hregPPC_VR14 ( void );
132extern HReg hregPPC_VR15 ( void );
133extern HReg hregPPC_VR16 ( void );
134extern HReg hregPPC_VR17 ( void );
135extern HReg hregPPC_VR18 ( void );
136extern HReg hregPPC_VR19 ( void );
137extern HReg hregPPC_VR20 ( void );
138extern HReg hregPPC_VR21 ( void );
139extern HReg hregPPC_VR22 ( void );
140extern HReg hregPPC_VR23 ( void );
141extern HReg hregPPC_VR24 ( void );
142extern HReg hregPPC_VR25 ( void );
143extern HReg hregPPC_VR26 ( void );
144extern HReg hregPPC_VR27 ( void );
145extern HReg hregPPC_VR28 ( void );
146extern HReg hregPPC_VR29 ( void );
147extern HReg hregPPC_VR30 ( void );
148extern HReg hregPPC_VR31 ( void );
149
150#define StackFramePtr(_mode64) hregPPC_GPR1(_mode64)
151#define GuestStatePtr(_mode64) hregPPC_GPR31(_mode64)
152
153
154
155/* --------- Condition codes --------- */
156
157/* This gives names from bitfields in CR; hence it names BI numbers */
158/* Using IBM/hardware indexing convention */
159typedef
160   enum {
161      // CR7, which we use for integer compares
162      Pcf_7LT  = 28,  /* neg  | lt          */
163      Pcf_7GT  = 29,  /* pos  | gt          */
164      Pcf_7EQ  = 30,  /* zero | equal       */
165      Pcf_7SO  = 31,  /* summary overflow   */
166      Pcf_NONE = 32   /* no condition; used with Pct_ALWAYS */
167   }
168   PPCCondFlag;
169
170typedef
171   enum {   /* Maps bc bitfield BO */
172      Pct_FALSE  = 0x4, /* associated PPCCondFlag must not be Pcf_NONE */
173      Pct_TRUE   = 0xC, /* associated PPCCondFlag must not be Pcf_NONE */
174      Pct_ALWAYS = 0x14 /* associated PPCCondFlag must be Pcf_NONE */
175   }
176   PPCCondTest;
177
178typedef
179   struct {
180      PPCCondFlag flag;
181      PPCCondTest test;
182   }
183   PPCCondCode;
184
185extern HChar* showPPCCondCode ( PPCCondCode );
186
187/* constructor */
188extern PPCCondCode mk_PPCCondCode ( PPCCondTest, PPCCondFlag );
189
190/* false->true, true->false */
191extern PPCCondTest invertCondTest ( PPCCondTest );
192
193
194
195
196/* --------- Memory address expressions (amodes). --------- */
197
198typedef
199   enum {
200     Pam_IR=1,      /* Immediate (signed 16-bit) + Reg */
201     Pam_RR=2       /* Reg1 + Reg2     */
202   }
203   PPCAModeTag;
204
205typedef
206   struct {
207      PPCAModeTag tag;
208      union {
209         struct {
210            HReg base;
211            Int  index;
212         } IR;
213         struct {
214            HReg base;
215            HReg index;
216         } RR;
217      } Pam;
218   }
219   PPCAMode;
220
221extern PPCAMode* PPCAMode_IR ( Int,  HReg );
222extern PPCAMode* PPCAMode_RR ( HReg, HReg );
223
224extern PPCAMode* dopyPPCAMode ( PPCAMode* );
225
226extern void ppPPCAMode ( PPCAMode* );
227
228
229/* --------- Operand, which can be a reg or a u16/s16. --------- */
230/* ("RH" == "Register or Halfword immediate") */
231typedef
232   enum {
233      Prh_Imm=3,
234      Prh_Reg=4
235   }
236   PPCRHTag;
237
238typedef
239   struct {
240      PPCRHTag tag;
241      union {
242         struct {
243            Bool   syned;
244            UShort imm16;
245         } Imm;
246         struct {
247            HReg reg;
248         } Reg;
249      }
250      Prh;
251   }
252   PPCRH;
253
254extern PPCRH* PPCRH_Imm ( Bool, UShort );
255extern PPCRH* PPCRH_Reg ( HReg );
256
257extern void ppPPCRH ( PPCRH* );
258
259
260/* --------- Operand, which can be a reg or a u32/64. --------- */
261
262typedef
263   enum {
264      Pri_Imm=5,
265      Pri_Reg=6
266   }
267   PPCRITag;
268
269typedef
270   struct {
271      PPCRITag tag;
272      union {
273         ULong Imm;
274         HReg  Reg;
275      }
276      Pri;
277   }
278   PPCRI;
279
280extern PPCRI* PPCRI_Imm ( ULong );
281extern PPCRI* PPCRI_Reg( HReg );
282
283extern void ppPPCRI ( PPCRI* );
284
285
286/* --------- Operand, which can be a vector reg or a s6. --------- */
287/* ("VI" == "Vector Register or Immediate") */
288typedef
289   enum {
290      Pvi_Imm=7,
291      Pvi_Reg=8
292   }
293   PPCVI5sTag;
294
295typedef
296   struct {
297      PPCVI5sTag tag;
298      union {
299         Char Imm5s;
300         HReg Reg;
301      }
302      Pvi;
303   }
304   PPCVI5s;
305
306extern PPCVI5s* PPCVI5s_Imm ( Char );
307extern PPCVI5s* PPCVI5s_Reg ( HReg );
308
309extern void ppPPCVI5s ( PPCVI5s* );
310
311
312/* --------- Instructions. --------- */
313
314/* --------- */
315typedef
316   enum {
317      Pun_NEG,
318      Pun_NOT,
319      Pun_CLZ32,
320      Pun_CLZ64,
321      Pun_EXTSW
322   }
323   PPCUnaryOp;
324
325extern HChar* showPPCUnaryOp ( PPCUnaryOp );
326
327
328/* --------- */
329typedef
330   enum {
331      Palu_INVALID,
332      Palu_ADD, Palu_SUB,
333      Palu_AND, Palu_OR, Palu_XOR,
334   }
335   PPCAluOp;
336
337extern
338HChar* showPPCAluOp ( PPCAluOp,
339                      Bool /* is the 2nd operand an immediate? */);
340
341
342/* --------- */
343typedef
344   enum {
345      Pshft_INVALID,
346      Pshft_SHL, Pshft_SHR, Pshft_SAR,
347   }
348   PPCShftOp;
349
350extern
351HChar* showPPCShftOp ( PPCShftOp,
352                       Bool /* is the 2nd operand an immediate? */,
353                       Bool /* is this a 32bit or 64bit op? */ );
354
355
356/* --------- */
357typedef
358   enum {
359      Pfp_INVALID,
360
361      /* Ternary */
362      Pfp_MADDD, Pfp_MSUBD,
363      Pfp_MADDS, Pfp_MSUBS,
364
365      /* Binary */
366      Pfp_ADDD, Pfp_SUBD, Pfp_MULD, Pfp_DIVD,
367      Pfp_ADDS, Pfp_SUBS, Pfp_MULS, Pfp_DIVS,
368
369      /* Unary */
370      Pfp_SQRT, Pfp_ABS, Pfp_NEG, Pfp_MOV, Pfp_RES, Pfp_RSQRTE,
371      Pfp_FRIN, Pfp_FRIM, Pfp_FRIP, Pfp_FRIZ
372   }
373   PPCFpOp;
374
375extern HChar* showPPCFpOp ( PPCFpOp );
376
377
378/* --------- */
379typedef
380   enum {
381      Pav_INVALID,
382
383      /* Integer Unary */
384      Pav_MOV,                             /* Mov */
385      Pav_NOT,                             /* Bitwise */
386      Pav_UNPCKH8S,  Pav_UNPCKH16S,        /* Unpack */
387      Pav_UNPCKL8S,  Pav_UNPCKL16S,
388      Pav_UNPCKHPIX, Pav_UNPCKLPIX,
389
390      /* Integer Binary */
391      Pav_AND, Pav_OR, Pav_XOR,            /* Bitwise */
392      Pav_ADDU, Pav_QADDU, Pav_QADDS,
393      Pav_SUBU, Pav_QSUBU, Pav_QSUBS,
394      Pav_OMULU, Pav_OMULS, Pav_EMULU, Pav_EMULS,
395      Pav_AVGU, Pav_AVGS,
396      Pav_MAXU, Pav_MAXS,
397      Pav_MINU, Pav_MINS,
398
399      /* Compare (always affects CR field 6) */
400      Pav_CMPEQU, Pav_CMPGTU, Pav_CMPGTS,
401
402      /* Shift */
403      Pav_SHL, Pav_SHR, Pav_SAR, Pav_ROTL,
404
405      /* Pack */
406      Pav_PACKUU, Pav_QPACKUU, Pav_QPACKSU, Pav_QPACKSS,
407      Pav_PACKPXL,
408
409      /* Merge */
410      Pav_MRGHI, Pav_MRGLO,
411   }
412   PPCAvOp;
413
414extern HChar* showPPCAvOp ( PPCAvOp );
415
416
417/* --------- */
418typedef
419   enum {
420      Pavfp_INVALID,
421
422      /* Floating point binary */
423      Pavfp_ADDF, Pavfp_SUBF, Pavfp_MULF,
424      Pavfp_MAXF, Pavfp_MINF,
425      Pavfp_CMPEQF, Pavfp_CMPGTF, Pavfp_CMPGEF,
426
427      /* Floating point unary */
428      Pavfp_RCPF, Pavfp_RSQRTF,
429      Pavfp_CVTU2F, Pavfp_CVTS2F, Pavfp_QCVTF2U, Pavfp_QCVTF2S,
430      Pavfp_ROUNDM, Pavfp_ROUNDP, Pavfp_ROUNDN, Pavfp_ROUNDZ,
431   }
432   PPCAvFpOp;
433
434extern HChar* showPPCAvFpOp ( PPCAvFpOp );
435
436
437/* --------- */
438typedef
439   enum {
440      Pin_LI,         /* load word (32/64-bit) immediate (fake insn) */
441      Pin_Alu,        /* word add/sub/and/or/xor */
442      Pin_Shft,       /* word shl/shr/sar */
443      Pin_AddSubC,    /* add/sub with read/write carry */
444      Pin_Cmp,        /* word compare */
445      Pin_Unary,      /* not, neg, clz */
446      Pin_MulL,       /* widening multiply */
447      Pin_Div,        /* div */
448      Pin_Call,       /* call to address in register */
449      Pin_Goto,       /* conditional/unconditional jmp to dst */
450      Pin_CMov,       /* conditional move */
451      Pin_Load,       /* zero-extending load a 8|16|32|64 bit value from mem */
452      Pin_LoadL,      /* load-linked (lwarx/ldarx) 32|64 bit value from mem */
453      Pin_Store,      /* store a 8|16|32|64 bit value to mem */
454      Pin_StoreC,     /* store-conditional (stwcx./stdcx.) 32|64 bit val */
455      Pin_Set,        /* convert condition code to value 0 or 1 */
456      Pin_MfCR,       /* move from condition register to GPR */
457      Pin_MFence,     /* mem fence */
458
459      Pin_FpUnary,    /* FP unary op */
460      Pin_FpBinary,   /* FP binary op */
461      Pin_FpMulAcc,   /* FP multipy-accumulate style op */
462      Pin_FpLdSt,     /* FP load/store */
463      Pin_FpSTFIW,    /* stfiwx */
464      Pin_FpRSP,      /* FP round IEEE754 double to IEEE754 single */
465      Pin_FpCftI,     /* fcfid[u,s,us]/fctid[u]/fctiw[u] */
466      Pin_FpCMov,     /* FP floating point conditional move */
467      Pin_FpLdFPSCR,  /* mtfsf */
468      Pin_FpCmp,      /* FP compare, generating value into int reg */
469
470      Pin_RdWrLR,     /* Read/Write Link Register */
471
472      Pin_AvLdSt,     /* AV load/store (kludging for AMode_IR) */
473      Pin_AvUnary,    /* AV unary general reg=>reg */
474
475      Pin_AvBinary,   /* AV binary general reg,reg=>reg */
476      Pin_AvBin8x16,  /* AV binary, 8x4 */
477      Pin_AvBin16x8,  /* AV binary, 16x4 */
478      Pin_AvBin32x4,  /* AV binary, 32x4 */
479
480      Pin_AvBin32Fx4, /* AV FP binary, 32Fx4 */
481      Pin_AvUn32Fx4,  /* AV FP unary,  32Fx4 */
482
483      Pin_AvPerm,     /* AV permute (shuffle) */
484      Pin_AvSel,      /* AV select */
485      Pin_AvShlDbl,   /* AV shift-left double by imm */
486      Pin_AvSplat,    /* One elem repeated throughout dst */
487      Pin_AvLdVSCR,   /* mtvscr */
488      Pin_AvCMov      /* AV conditional move */
489   }
490   PPCInstrTag;
491
492/* Destinations are on the LEFT (first operand) */
493
494typedef
495   struct {
496      PPCInstrTag tag;
497      union {
498         /* Get a 32/64-bit literal into a register.
499            May turn into a number of real insns. */
500         struct {
501            HReg dst;
502            ULong imm64;
503         } LI;
504         /* Integer add/sub/and/or/xor.  Limitations:
505            - For add, the immediate, if it exists, is a signed 16.
506            - For sub, the immediate, if it exists, is a signed 16
507              which may not be -32768, since no such instruction
508              exists, and so we have to emit addi with +32768, but
509              that is not possible.
510            - For and/or/xor,  the immediate, if it exists,
511              is an unsigned 16.
512         */
513         struct {
514            PPCAluOp op;
515            HReg     dst;
516            HReg     srcL;
517            PPCRH*   srcR;
518         } Alu;
519         /* Integer shl/shr/sar.
520            Limitations: the immediate, if it exists,
521            is a signed 5-bit value between 1 and 31 inclusive.
522         */
523         struct {
524            PPCShftOp op;
525            Bool      sz32;   /* mode64 has both 32 and 64bit shft */
526            HReg      dst;
527            HReg      srcL;
528            PPCRH*    srcR;
529         } Shft;
530         /*  */
531         struct {
532            Bool isAdd;  /* else sub */
533            Bool setC;   /* else read carry */
534            HReg dst;
535            HReg srcL;
536            HReg srcR;
537         } AddSubC;
538         /* If signed, the immediate, if it exists, is a signed 16,
539            else it is an unsigned 16. */
540         struct {
541            Bool   syned;
542            Bool   sz32;    /* mode64 has both 32 and 64bit cmp */
543            UInt   crfD;
544            HReg   srcL;
545            PPCRH* srcR;
546         } Cmp;
547         /* Not, Neg, Clz32/64, Extsw */
548         struct {
549            PPCUnaryOp op;
550            HReg       dst;
551            HReg       src;
552         } Unary;
553         struct {
554            Bool syned;  /* meaningless if hi32==False */
555            Bool hi;     /* False=>low, True=>high */
556            Bool sz32;   /* mode64 has both 32 & 64bit mull */
557            HReg dst;
558            HReg srcL;
559            HReg srcR;
560         } MulL;
561         /* ppc32 div/divu instruction. */
562         struct {
563            Bool extended;
564            Bool syned;
565            Bool sz32;   /* mode64 has both 32 & 64bit div */
566            HReg dst;
567            HReg srcL;
568            HReg srcR;
569         } Div;
570         /* Pseudo-insn.  Call target (an absolute address), on given
571            condition (which could be Pct_ALWAYS).  argiregs indicates
572            which of r3 .. r10 carries argument values for this call,
573            using a bit mask (1<<N is set if rN holds an arg, for N in
574            3 .. 10 inclusive). */
575         struct {
576            PPCCondCode cond;
577            Addr64      target;
578            UInt        argiregs;
579         } Call;
580         /* Pseudo-insn.  Goto dst, on given condition (which could be
581            Pct_ALWAYS). */
582         struct {
583            IRJumpKind  jk;
584            PPCCondCode cond;
585            PPCRI*      dst;
586         } Goto;
587         /* Mov src to dst on the given condition, which may not
588            be the bogus Pct_ALWAYS. */
589         struct {
590            PPCCondCode cond;
591            HReg        dst;
592            PPCRI*      src;
593         } CMov;
594         /* Zero extending loads.  Dst size is host word size */
595         struct {
596            UChar     sz; /* 1|2|4|8 */
597            HReg      dst;
598            PPCAMode* src;
599         } Load;
600         /* Load-and-reserve (lwarx, ldarx) */
601         struct {
602            UChar sz; /* 4|8 */
603            HReg  dst;
604            HReg  src;
605         } LoadL;
606         /* 64/32/16/8 bit stores */
607         struct {
608            UChar     sz; /* 1|2|4|8 */
609            PPCAMode* dst;
610            HReg      src;
611         } Store;
612         /* Store-conditional (stwcx., stdcx.) */
613         struct {
614            UChar sz; /* 4|8 */
615            HReg  dst;
616            HReg  src;
617         } StoreC;
618         /* Convert a ppc condition code to value 0 or 1. */
619         struct {
620            PPCCondCode cond;
621            HReg        dst;
622         } Set;
623         /* Move the entire CR to a GPR */
624         struct {
625            HReg dst;
626         } MfCR;
627         /* Mem fence.  In short, an insn which flushes all preceding
628            loads and stores as much as possible before continuing.
629            On PPC we emit a "sync". */
630         struct {
631         } MFence;
632
633         /* PPC Floating point */
634         struct {
635            PPCFpOp op;
636            HReg    dst;
637            HReg    src;
638         } FpUnary;
639         struct {
640            PPCFpOp op;
641            HReg    dst;
642            HReg    srcL;
643            HReg    srcR;
644         } FpBinary;
645         struct {
646            PPCFpOp op;
647            HReg    dst;
648            HReg    srcML;
649            HReg    srcMR;
650            HReg    srcAcc;
651         } FpMulAcc;
652         struct {
653            Bool      isLoad;
654            UChar     sz; /* only 4 (IEEE single) or 8 (IEEE double) */
655            HReg      reg;
656            PPCAMode* addr;
657         } FpLdSt;
658         struct {
659            HReg addr; /* int reg */
660            HReg data; /* float reg */
661         } FpSTFIW;
662         /* Round 64-bit FP value to 32-bit FP value in an FP reg. */
663         struct {
664            HReg src;
665            HReg dst;
666         } FpRSP;
667         /* fcfid[u,s,us]/fctid[u]/fctiw[u].  Only some combinations
668            of the various fields are allowed.  This is asserted for
669            and documented in the code for the constructor,
670            PPCInstr_FpCftI, in host_ppc_defs.c.  */
671         struct {
672            Bool fromI; /* True== I->F,    False== F->I */
673            Bool int32; /* True== I is 32, False== I is 64 */
674            Bool syned;
675            Bool flt64; /* True== F is 64, False== F is 32 */
676            HReg src;
677            HReg dst;
678         } FpCftI;
679         /* FP mov src to dst on the given condition. */
680         struct {
681            PPCCondCode cond;
682            HReg        dst;
683            HReg        src;
684         } FpCMov;
685         /* Load FP Status & Control Register */
686         struct {
687            HReg src;
688         } FpLdFPSCR;
689         /* Do a compare, generating result into an int register. */
690         struct {
691            UChar crfD;
692            HReg  dst;
693            HReg  srcL;
694            HReg  srcR;
695         } FpCmp;
696
697         /* Read/Write Link Register */
698         struct {
699            Bool wrLR;
700            HReg gpr;
701         } RdWrLR;
702
703         /* Simplistic AltiVec */
704         struct {
705            Bool      isLoad;
706            UChar     sz;      /* 8|16|32|128 */
707            HReg      reg;
708            PPCAMode* addr;
709         } AvLdSt;
710         struct {
711            PPCAvOp op;
712            HReg    dst;
713            HReg    src;
714         } AvUnary;
715         struct {
716            PPCAvOp op;
717            HReg    dst;
718            HReg    srcL;
719            HReg    srcR;
720         } AvBinary;
721         struct {
722            PPCAvOp op;
723            HReg    dst;
724            HReg    srcL;
725            HReg    srcR;
726         } AvBin8x16;
727         struct {
728            PPCAvOp op;
729            HReg    dst;
730            HReg    srcL;
731            HReg    srcR;
732         } AvBin16x8;
733         struct {
734            PPCAvOp op;
735            HReg    dst;
736            HReg    srcL;
737            HReg    srcR;
738         } AvBin32x4;
739         struct {
740            PPCAvFpOp op;
741            HReg      dst;
742            HReg      srcL;
743            HReg      srcR;
744         } AvBin32Fx4;
745         struct {
746            PPCAvFpOp op;
747            HReg      dst;
748            HReg      src;
749         } AvUn32Fx4;
750         /* Perm,Sel,SlDbl,Splat are all weird AV permutations */
751         struct {
752            HReg dst;
753            HReg srcL;
754            HReg srcR;
755            HReg ctl;
756         } AvPerm;
757         struct {
758            HReg dst;
759            HReg srcL;
760            HReg srcR;
761            HReg ctl;
762         } AvSel;
763         struct {
764            UChar shift;
765            HReg  dst;
766            HReg  srcL;
767            HReg  srcR;
768         } AvShlDbl;
769         struct {
770            UChar    sz;   /* 8,16,32 */
771            HReg     dst;
772            PPCVI5s* src;
773         } AvSplat;
774         /* Mov src to dst on the given condition, which may not
775            be the bogus Xcc_ALWAYS. */
776         struct {
777            PPCCondCode cond;
778            HReg        dst;
779            HReg        src;
780         } AvCMov;
781         /* Load AltiVec Status & Control Register */
782         struct {
783            HReg src;
784         } AvLdVSCR;
785       } Pin;
786   }
787   PPCInstr;
788
789
790extern PPCInstr* PPCInstr_LI         ( HReg, ULong, Bool );
791extern PPCInstr* PPCInstr_Alu        ( PPCAluOp, HReg, HReg, PPCRH* );
792extern PPCInstr* PPCInstr_Shft       ( PPCShftOp, Bool sz32, HReg, HReg, PPCRH* );
793extern PPCInstr* PPCInstr_AddSubC    ( Bool, Bool, HReg, HReg, HReg );
794extern PPCInstr* PPCInstr_Cmp        ( Bool, Bool, UInt, HReg, PPCRH* );
795extern PPCInstr* PPCInstr_Unary      ( PPCUnaryOp op, HReg dst, HReg src );
796extern PPCInstr* PPCInstr_MulL       ( Bool syned, Bool hi32, Bool sz32, HReg, HReg, HReg );
797extern PPCInstr* PPCInstr_Div        ( Bool extended, Bool syned, Bool sz32, HReg dst, HReg srcL, HReg srcR );
798extern PPCInstr* PPCInstr_Call       ( PPCCondCode, Addr64, UInt );
799extern PPCInstr* PPCInstr_Goto       ( IRJumpKind, PPCCondCode cond, PPCRI* dst );
800extern PPCInstr* PPCInstr_CMov       ( PPCCondCode, HReg dst, PPCRI* src );
801extern PPCInstr* PPCInstr_Load       ( UChar sz,
802                                       HReg dst, PPCAMode* src, Bool mode64 );
803extern PPCInstr* PPCInstr_LoadL      ( UChar sz,
804                                       HReg dst, HReg src, Bool mode64 );
805extern PPCInstr* PPCInstr_Store      ( UChar sz, PPCAMode* dst,
806                                       HReg src, Bool mode64 );
807extern PPCInstr* PPCInstr_StoreC     ( UChar sz, HReg dst, HReg src,
808                                       Bool mode64 );
809extern PPCInstr* PPCInstr_Set        ( PPCCondCode cond, HReg dst );
810extern PPCInstr* PPCInstr_MfCR       ( HReg dst );
811extern PPCInstr* PPCInstr_MFence     ( void );
812
813extern PPCInstr* PPCInstr_FpUnary    ( PPCFpOp op, HReg dst, HReg src );
814extern PPCInstr* PPCInstr_FpBinary   ( PPCFpOp op, HReg dst, HReg srcL, HReg srcR );
815extern PPCInstr* PPCInstr_FpMulAcc   ( PPCFpOp op, HReg dst, HReg srcML,
816                                                   HReg srcMR, HReg srcAcc );
817extern PPCInstr* PPCInstr_FpLdSt     ( Bool isLoad, UChar sz, HReg, PPCAMode* );
818extern PPCInstr* PPCInstr_FpSTFIW    ( HReg addr, HReg data );
819extern PPCInstr* PPCInstr_FpRSP      ( HReg dst, HReg src );
820extern PPCInstr* PPCInstr_FpCftI     ( Bool fromI, Bool int32, Bool syned,
821                                       Bool dst64, HReg dst, HReg src );
822extern PPCInstr* PPCInstr_FpCMov     ( PPCCondCode, HReg dst, HReg src );
823extern PPCInstr* PPCInstr_FpLdFPSCR  ( HReg src );
824extern PPCInstr* PPCInstr_FpCmp      ( HReg dst, HReg srcL, HReg srcR );
825
826extern PPCInstr* PPCInstr_RdWrLR     ( Bool wrLR, HReg gpr );
827
828extern PPCInstr* PPCInstr_AvLdSt     ( Bool isLoad, UChar sz, HReg, PPCAMode* );
829extern PPCInstr* PPCInstr_AvUnary    ( PPCAvOp op, HReg dst, HReg src );
830extern PPCInstr* PPCInstr_AvBinary   ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
831extern PPCInstr* PPCInstr_AvBin8x16  ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
832extern PPCInstr* PPCInstr_AvBin16x8  ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
833extern PPCInstr* PPCInstr_AvBin32x4  ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
834extern PPCInstr* PPCInstr_AvBin32Fx4 ( PPCAvFpOp op, HReg dst, HReg srcL, HReg srcR );
835extern PPCInstr* PPCInstr_AvUn32Fx4  ( PPCAvFpOp op, HReg dst, HReg src );
836extern PPCInstr* PPCInstr_AvPerm     ( HReg dst, HReg srcL, HReg srcR, HReg ctl );
837extern PPCInstr* PPCInstr_AvSel      ( HReg ctl, HReg dst, HReg srcL, HReg srcR );
838extern PPCInstr* PPCInstr_AvShlDbl   ( UChar shift, HReg dst, HReg srcL, HReg srcR );
839extern PPCInstr* PPCInstr_AvSplat    ( UChar sz, HReg dst, PPCVI5s* src );
840extern PPCInstr* PPCInstr_AvCMov     ( PPCCondCode, HReg dst, HReg src );
841extern PPCInstr* PPCInstr_AvLdVSCR   ( HReg src );
842
843extern void ppPPCInstr ( PPCInstr*, Bool mode64 );
844
845/* Some functions that insulate the register allocator from details
846   of the underlying instruction set. */
847extern void         getRegUsage_PPCInstr ( HRegUsage*, PPCInstr*, Bool mode64 );
848extern void         mapRegs_PPCInstr     ( HRegRemap*, PPCInstr* , Bool mode64);
849extern Bool         isMove_PPCInstr      ( PPCInstr*, HReg*, HReg* );
850extern Int          emit_PPCInstr        ( UChar* buf, Int nbuf, PPCInstr*,
851                                           Bool mode64,
852                                           void* dispatch_unassisted,
853                                           void* dispatch_assisted );
854
855extern void genSpill_PPC  ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
856                            HReg rreg, Int offsetB, Bool mode64 );
857extern void genReload_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
858                            HReg rreg, Int offsetB, Bool mode64 );
859
860extern void         getAllocableRegs_PPC ( Int*, HReg**, Bool mode64 );
861extern HInstrArray* iselSB_PPC           ( IRSB*, VexArch,
862                                                  VexArchInfo*,
863                                                  VexAbiInfo* );
864
865#endif /* ndef __VEX_HOST_PPC_DEFS_H */
866
867/*---------------------------------------------------------------*/
868/*--- end                                     host_ppc_defs.h ---*/
869/*---------------------------------------------------------------*/
870