| 0780179d532d20b6b01ba0f1434c93f81b7faea8 |
01-Aug-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
EVEX and compressed displacement encoding for AVX512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187576 91177308-0d34-0410-b5e6-96231b3b80d8
vx512-encodings.s
|
| 6ee1464ba599f1afbed502fa1b3ac18c8577fd97 |
26-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Add test cases for the various instruction alias and Intel syntax fixes that have gone in lately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187188 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
86-32-coverage.s
86-64.s
|
| 9b8b830f3fa6dca2275dcd86bdaf0d78ab1651a1 |
23-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Don't let x86 asm printer use the no operand movsd alias. It should use the normal movsl instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186924 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
86-64.s
|
| 877d123bdb0198705884e4ca7980d2ab845d9888 |
22-Jul-2013 |
Kevin Enderby <enderby@apple.com> |
Fix the move to/from accumulator register instructions that use a full 64-bit
absolute address encoded in the instruction.
rdar://8612627 and rdar://14299221
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186878 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 4e3170b63a31c515644846ce7a77631429d93050 |
22-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Recommit r186813: More Intel syntax alias fixes. With the addition of suppressing some of the aliases from being emitted by the asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186869 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 73477b9f32da6488f2883f33fd17fa0de61f2bd1 |
03-Jul-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Prefix failing commands with not to make clear they are expected to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185554 91177308-0d34-0410-b5e6-96231b3b80d8
lignedBundling/align-mode-argument-error.s
lignedBundling/bundle-group-too-large-error.s
lignedBundling/bundle-lock-option-error.s
lignedBundling/lock-without-bundle-mode-error.s
lignedBundling/switch-section-locked-error.s
lignedBundling/unlock-without-lock-error.s
|
| 23306deb92e2424165f2145895e21e223c3887eb |
18-Jun-2013 |
Stefanus Du Toit <stefanus.du.toit@intel.com> |
Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.
For decoding, keep the current behavior of always decoding these as their REP
versions. In the future, this could be improved to recognize the cases where
these behave as XACQUIRE and XRELEASE and decode them as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184207 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-hle-encoding.s
|
| 19b30d56b224ab3507f7a93743eac2b01c5861dd |
13-Jun-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Make the cmov aliases work with intel syntax too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183907 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| ffc49cbea41c08132587a3e622bb65191fa576a2 |
10-May-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Fix a crasher when we fail on a direct match.
The issue was that the MatchingInlineAsm and VariantID args to the
MatchInstructionImpl function weren't being set properly. Specifically, when
parsing intel syntax, the parser thought it was parsing inline assembly in the
at&t dialect; that will never be the case.
The crash was caused when the emitter tried to emit the instruction, but the
operands weren't set. When parsing inline assembly we only set the opcode, not
the operands, which is used to lookup the instruction descriptor.
rdar://13854391 and PR15945
Also, this commit reverts r176036. Now that we're correctly parsing the intel
syntax the pushad/popad don't match properly. I've reimplemented that fix using
a MnemonicAlias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181620 91177308-0d34-0410-b5e6-96231b3b80d8
86_errors.s
|
| a70d02ff2841d535875fe80bd3d3c25ba90613da |
10-May-2013 |
Chad Rosier <mcrosier@apple.com> |
[x86AsmParser] It's valid to stop parsing an operand at an immediate.
rdar://13854369 and PR15944
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181564 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| f74d82d8e49ec54953c106a89e0a5951466d4e6b |
23-Apr-2013 |
Chad Rosier <mcrosier@apple.com> |
Add test case for PR15779, which has previously been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180058 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| 3f1f9c37986953250cbda7a7bfb7123571449be7 |
19-Apr-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Apply the condition code mnemonic aliases to both the Intel and
AT&T dialect. Test case for r179804 as well.
rdar://13674398 and PR13340.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179813 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| d58f773b96fdb5539d9da2192b8cf2ff6112239f |
17-Apr-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support for the minus unary operator. Previously, we were
unable to handle cases such as __asm mov eax, 8*-8.
This patch also attempts to simplify the state machine. Further, the error
reporting has been improved. Test cases included, but more will be added to
the clang side shortly.
rdar://13668445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179719 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| 02d2e612521954b5ff7c1ba6fd53e36bc51e1c48 |
11-Apr-2013 |
Michael Liao <michael.liao@intel.com> |
Add CLAC/STAC instruction encoding/decoding support
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| e112453fc39b97147ea3f23bf0b1973cd9f739b1 |
05-Apr-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support for numeric displacement expressions in bracketed
memory operands.
Essentially, this layers an infix calculator on top of the parsing state
machine. The scale on the index register is still expected to be an immediate
__asm mov eax, [eax + ebx*4]
and will not work with more complex expressions. For example,
__asm mov eax, [eax + ebx*(2*2)]
The plus and minus binary operators assume the numeric value of a register is
zero so as to not change the displacement. Register operands should never
be an operand for a multiply or divide operation; the scale*indexreg
expression is always replaced with a zero on the operand stack to prevent
such a case.
rdar://13521380
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178881 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| c26392aa5d9c2dbca2909d6874d181455f8aeb8f |
29-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Add support of RDSEED defined in AVX2 extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178314 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-rand-encoding.s
|
| 30509ee8a348116335475beaf9e5504471c86e73 |
28-Mar-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move test since it depends on the X86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178249 91177308-0d34-0410-b5e6-96231b3b80d8
de-reloc.s
|
| dd40e8cd54805aa81c8548ac8c87755c562c1723 |
27-Mar-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support of imm displacement before bracketed memory
expression. Specifically, this syntax:
ImmDisp [ BaseReg + Scale*IndexReg + Disp ]
We don't currently support:
ImmDisp [ Symbol ]
rdar://13518671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178186 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-ms-inline-asm.s
|
| 9b3939983fd0103b102c7aec0ed08d1e8bd28214 |
25-Mar-2013 |
Dave Zarzycki <zarzycki@apple.com> |
x86 -- add the XTEST instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-rtm-encoding.s
|
| 8ee1c1cfaff9eece05ecabfa267cd68c98af5dd2 |
18-Mar-2013 |
Craig Topper <craig.topper@gmail.com> |
Post process ADC/SBB and use a shorter encoding if they use a sign extended immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177243 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax-encoding.s
|
| 4bef961baf9660f1ac5a5b80378631cd942636b2 |
18-Mar-2013 |
Craig Topper <craig.topper@gmail.com> |
Refactor some duplicated code into helper functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177242 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax-encoding.s
|
| 9d3f3c5f400578855f6f7b71670cb8514b4fac0f |
14-Mar-2013 |
Craig Topper <craig.topper@gmail.com> |
Fix a bug in the calculation of the VEX.B bit for FMA4 rr with the VEX.W bit set. The VEX.B was being calculated from the wrong operand. Fixes at least some portion of PR14185.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177014 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-fma4-encoding.s
|
| 1ab326310cc9fddf0cc17b981f4f9996f1a19e76 |
05-Mar-2013 |
Eli Bendersky <eliben@google.com> |
Fixes a test by replacing .align by .p2align and setting triples explicitly.
Patch by David Sehr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176502 91177308-0d34-0410-b5e6-96231b3b80d8
86_long_nop.s
|
| 81ee0f73685f966ea279b01cbb9587c70ad91bed |
05-Mar-2013 |
David Sehr <sehr@google.com> |
Add a test that .align directives on capable processors use long NOPs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176490 91177308-0d34-0410-b5e6-96231b3b80d8
86_long_nop.s
|
| 6c4265a541c9e431961113c1a5d92fb4628bfe13 |
05-Mar-2013 |
David Sehr <sehr@google.com> |
The current X86 NOP padding uses one long NOP followed by the remainder in
one-byte NOPs. If the processor actually executes those NOPs, as it sometimes
does with aligned bundling, this can have a performance impact. From my
micro-benchmarks run on my one machine, a 15-byte NOP followed by twelve
one-byte NOPs is about 20% worse than a 15 followed by a 12. This patch
changes NOP emission to emit as many 15-byte (the maximum) as possible followed
by at most one shorter NOP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176464 91177308-0d34-0410-b5e6-96231b3b80d8
lignedBundling/long-nop-pad.s
|
| dca83187b7c4465ad6ff8507052223d31c0ea66a |
25-Feb-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support for the pushad/popad mnemonics.
rdar://13254235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176036 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-ms-inline-asm.s
|
| 50e75bfc29269def44981ab5f109334d95f55007 |
25-Feb-2013 |
Matt Beaumont-Gay <matthewbg@google.com> |
'Hexadecimal' has two 'a's and only one 'i'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176031 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax-hex.s
|
| e186d7191c2cf95753a9790b1490df8a07416daa |
14-Feb-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert r15266. This fixes llvm.org/pr15266.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175173 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax-binary.s
|
| 8915e27704b2afd362a69c6be1111fb06bbcc727 |
12-Feb-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support for lexing binary integers with a [bB] suffix.
This is complicated by backward labels (e.g., 0b can be both a backward label
and a binary zero). The current implementation assumes [0-9]b is always a
label and thus it's possible for 0b and 1b to not be interpreted correctly for
ms-style inline assembly. However, this is relatively simple to fix in the
inline assembly (i.e., drop the [bB]).
This patch also limits backward labels to [0-9]b, so that only 0b and 1b are
ambiguous.
Part of rdar://12470373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174983 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax-binary.s
|
| d556fd129026f6e3fa6ea9c2c70ba489bff18954 |
12-Feb-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support for lexing hexidecimal integers with a [hH] suffix.
Part of rdar://12470373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174926 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax-hex.s
|
| f918d7fd7393049bc87bc03fda2d2cd3cec1dacb |
05-Feb-2013 |
Derek Schuff <dschuff@google.com> |
[MC] Bundle alignment: Invalidate relaxed fragments
Currently, when a fragment is relaxed, its size is modified, but its
offset is not (it gets laid out as a side effect of checking whether
it needs relaxation), then all subsequent fragments are invalidated
because their offsets need to change. When bundling is enabled,
relaxed fragments need to get laid out again, because the increase in
size may push it over a bundle boundary. So instead of only
invalidating subsequent fragments, also invalidate the fragment that
gets relaxed, which causes it to get laid out again.
This patch also fixes some trailing whitespace and fixes the
bundling-related debug output of MCFragments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174401 91177308-0d34-0410-b5e6-96231b3b80d8
lignedBundling/relax-at-bundle-end.s
|
| b11917c1aa7348a67d80149fa9613f09a8d56f14 |
31-Jan-2013 |
Derek Schuff <dschuff@google.com> |
[MC] bundle alignment: prevent padding instructions from crossing bundle boundaries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174067 91177308-0d34-0410-b5e6-96231b3b80d8
lignedBundling/autogen-inst-offset-align-to-end.s
lignedBundling/pad-align-to-bundle-end.s
|
| e6482fabd20a2a5b4f81aff55812782f3b617514 |
29-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Merge SSE and AVX shuffle instructions in the comment printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173777 91177308-0d34-0410-b5e6-96231b3b80d8
huffle-comments.s
|
| 467016e58d57021b14f2ae562d221f00b07cb254 |
28-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Fix 256-bit PALIGNR comment decoding to understand that it works on independent 256-bit lanes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173674 91177308-0d34-0410-b5e6-96231b3b80d8
huffle-comments.s
|
| 200b306f2006533a0e7a0ca75cb3103620e7aa84 |
26-Jan-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Decode PALIGN operands so I don't have to do it in my head.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173572 91177308-0d34-0410-b5e6-96231b3b80d8
huffle-comments.s
|
| 767295f1143db4ed844ea9d25f9758e624c35302 |
25-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Now that llvm-dwarfdump supports flags to specify which DWARF section to dump,
use them in tests that run llvm-dwarfdump. This is in order to make tests as
specific as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173498 91177308-0d34-0410-b5e6-96231b3b80d8
nux32-dwarf-gen.s
|
| aaf483ff1775a6b7b0022158c59e73e404d568ef |
22-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Add forgotten test case for the x32 commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173181 91177308-0d34-0410-b5e6-96231b3b80d8
nux32-dwarf-gen.s
|
| 341c5fbe840cffedc4155a2cf130626d2bba11b5 |
22-Jan-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Make sure we account for the FMA4 register immediate value, otherwise rip-rel relocations will be off by one byte.
PR15040.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173176 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-fma4-encoding.s
|
| dd2e8950222ab74157b1c083ffa77b0fbaf1d210 |
14-Jan-2013 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Extend support for parsing Intel bracketed memory operands that
have an arbitrary ordering of the base register, index register and displacement.
rdar://12527141
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172484 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| 59d152197d741ab930dfc99ced3cac1b8bc8bef9 |
08-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Add some additional tests for the .bundle_lock align_to_end feature that didn't
make into the last commit.
Also, update the test-generation script to generate an exhaustive test for
align_to_end as well, and include the generated test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171811 91177308-0d34-0410-b5e6-96231b3b80d8
lignedBundling/autogen-inst-offset-align-to-end.s
lignedBundling/bundle-lock-option-error.s
lignedBundling/pad-align-to-bundle-end.s
|
| 6c1d4972cf1cd6b6072e31c05f97abb1ed7a8497 |
07-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Add the align_to_end option to .bundle_lock in the MC implementation of aligned
bundling. The document describing this feature and the implementation has also
been updated:
https://sites.google.com/a/chromium.org/dev/nativeclient/pnacl/aligned-bundling-support-in-llvm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171797 91177308-0d34-0410-b5e6-96231b3b80d8
lignedBundling/asm-printing-bundle-directives.s
|
| f564a9389da68266f44314fe38ab399fd2211134 |
06-Jan-2013 |
Craig Topper <craig.topper@gmail.com> |
Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior.
cvtsi2* should parse with an 'l' or 'q' suffix or no suffix at all. No suffix should be treated the same as 'l' suffix. Printing should always print a suffix. Previously we didn't parse or print an 'l' suffix.
cvtt*2si/cvt*2si should parse with an 'l' or 'q' suffix or not suffix at all. No suffix should use the destination register size to choose encoding. Printing should not print a suffix.
Original 'l' suffix issue with cvtsi2* pointed out by Michael Kuperstein.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171668 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-avx.s
86-32-coverage.s
86-64.s
86_64-avx-encoding.s
|
| 5bf3a28b36c5d95ad3732b749db651630027b09c |
02-Jan-2013 |
Kevin Enderby <enderby@apple.com> |
Adds missing aliases for fcom and fcomp instructions without arguments.
Patch by Michael M Kuperstein!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171414 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-coverage.s
|
| 15019a8814b7877367ca7bcd7d173710259f7c20 |
20-Dec-2012 |
Eli Bendersky <eliben@google.com> |
Change Lit error redirection to FileCheck to a more common syntax since it
can potentially cause some bots to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170726 91177308-0d34-0410-b5e6-96231b3b80d8
lignedBundling/align-mode-argument-error.s
lignedBundling/asm-printing-bundle-directives.s
lignedBundling/bundle-group-too-large-error.s
lignedBundling/lock-without-bundle-mode-error.s
lignedBundling/switch-section-locked-error.s
lignedBundling/unlock-without-lock-error.s
|
| b17201f1b8c35414e3bbd71c3f37ee6313d77e86 |
20-Dec-2012 |
Eli Bendersky <eliben@google.com> |
Add a largish auto-generated test for the aligned bundling feature, along with
the script generating it. The test should never be modified manually. If anyone
needs to change it, please change the script and re-run it.
The script is placed into utils/testgen - I couldn't think of a better place,
and after some discussion on IRC this looked like a logical location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170720 91177308-0d34-0410-b5e6-96231b3b80d8
lignedBundling/autogen-inst-offset-padding.s
|
| 16996c4940ad4248dc2a874d060b30e94e55b672 |
20-Dec-2012 |
Eli Bendersky <eliben@google.com> |
Tests for the aligned bundling support added in r170718
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170719 91177308-0d34-0410-b5e6-96231b3b80d8
lignedBundling/align-mode-argument-error.s
lignedBundling/asm-printing-bundle-directives.s
lignedBundling/bundle-group-too-large-error.s
lignedBundling/different-sections.s
lignedBundling/lit.local.cfg
lignedBundling/lock-without-bundle-mode-error.s
lignedBundling/pad-bundle-groups.s
lignedBundling/relax-in-bundle-group.s
lignedBundling/single-inst-bundling.s
lignedBundling/switch-section-locked-error.s
lignedBundling/unlock-without-lock-error.s
|
| 25953bfb0763047df28c01057183493490667531 |
13-Dec-2012 |
Eli Bendersky <eliben@google.com> |
Make this Lit config file a bit slimmer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170083 91177308-0d34-0410-b5e6-96231b3b80d8
it.local.cfg
|
| 3ca6382120c16e30151e19175d40480ee72de641 |
14-Nov-2012 |
Jim Grosbach <grosbach@apple.com> |
X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches.
When an instruction as written requires 32-bit mode and we're assembling
in 64-bit mode, or vice-versa, issue a more specific diagnostic about
what's wrong.
rdar://12700702
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167937 91177308-0d34-0410-b5e6-96231b3b80d8
86_errors.s
|
| be02a90de17f857ba65bbd8a11653ca1bad30adc |
08-Nov-2012 |
Michael Liao <michael.liao@intel.com> |
Add support of RTM from TSX extension
- Add RTM code generation support throught 3 X86 intrinsics:
xbegin()/xend() to start/end a transaction region, and xabort() to abort a
tranaction region
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-rtm-encoding.s
|
| 2fbc239e4fbdd12c24fb2cf9e3e915861fc12030 |
29-Oct-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support for the [] operator. Essentially, [expr1][expr2] is
equivalent to [expr1 + expr2]. See test cases for more examples.
rdar://12470392
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166949 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-ms-inline-asm.s
|
| d95666c226e41218a07541aaa2cc1fba823c25e4 |
25-Oct-2012 |
Chad Rosier <mcrosier@apple.com> |
Tell llvm-mc we're using intel syntax, so we don't have to use directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166640 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-ms-inline-asm.s
|
| b3009eec47d2aaa61cc848a66a7bbd69ad9e0f19 |
25-Oct-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add back-end test case for r166632. Make sure we emit the
correct .s output as well as get the correct encoding by the integrated
assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166638 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-ms-inline-asm.s
|
| 08b6b81ec57e7d8b99844b7f4a211942570ffff1 |
13-Oct-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Depending on the local semantics of .align this test can also emit a nopl instead of nopw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165880 91177308-0d34-0410-b5e6-96231b3b80d8
86_nop.s
|
| 126afcbf654e42dc3f659a1a66bfa8a784e7bd46 |
13-Oct-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Disable long nops for all cpus prior to pentiumpro/i686.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165878 91177308-0d34-0410-b5e6-96231b3b80d8
86_nop.s
|
| 2811ae66a857691b47fbcf98a12521380c05aad0 |
19-Sep-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
llvm/test/MC/X86/x86_nop.s: Make sure -arch=x86 when -mcpu=geode.
-mcpu doesn't infer -arch. Consider non-x86 host.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164185 91177308-0d34-0410-b5e6-96231b3b80d8
86_nop.s
|
| 36b07f2f07d3dbd4b803a2ac899d6c3c2202ae8c |
18-Sep-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Add test for r164132.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164134 91177308-0d34-0410-b5e6-96231b3b80d8
86_nop.s
|
| 2cfe90b1191ea770ce5e47f6536508e89b829b17 |
11-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
Add newline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163565 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax-2.s
|
| 3c4ecd7dab5567017ad573769b0af484479bac6f |
10-Sep-2012 |
Chad Rosier <mcrosier@apple.com> |
[ms-inline asm] Add support for .att_syntax directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163542 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax-2.s
|
| 9765c6ecde9ca96c37fe3e27d360aadc387b6942 |
31-Aug-2012 |
Jim Grosbach <grosbach@apple.com> |
X86: Fix encoding of 'movd %xmm0, %rax'
The assembly string for the VMOVPQIto64rr instruction incorrectly lacked the 'v'
prefix, resulting in mis-assembly of the vanilla movd instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162963 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 7f76cb6666194d7269bbd6ee0966eacc709dd10a |
26-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160775 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-avx.s
86_64-avx-encoding.s
|
| 75dc33a60b65bbbf2253b0b916df1d36a4da4237 |
18-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160420 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
86_64-avx-encoding.s
|
| 97a0c6bc91bf31fa701dda478d9616c2de6b2393 |
10-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Reverse assembler/disassembler operand order for gather instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159983 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-avx-encoding.s
|
| a101014026be32a27e9d77d01e01ef08eb57e465 |
03-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Add aliases for pblendvb, blendvpd, and blendvps instructions with the implicit xmm0 operand specified. Fixes PR13252.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159644 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-coverage.s
|
| 40307c7dbe2d104784763c28697d7926793674af |
29-Jun-2012 |
Manman Ren <mren@apple.com> |
X86: add more GATHER intrinsics in LLVM
Corrected type for index of llvm.x86.avx2.gather.d.pd.256
from 256-bit to 128-bit.
Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256
from 256-bit to 128-bit.
Support the following intrinsics:
llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q
llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256
llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d
llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159402 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-avx-encoding.s
|
| 1f7a1b68a07ea6bdf521525a7928f4a8c5216713 |
26-Jun-2012 |
Manman Ren <mren@apple.com> |
X86: add GATHER intrinsics (AVX2) in LLVM
Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256
Modified Disassembler to handle VSIB addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-avx-encoding.s
|
| 952caee4f66a968f54588cca48215a5008283ea3 |
26-Jun-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove some duplicate instructions that exist only to given different mnemonics for the assembler. Use InstAlias instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159184 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-avx.s
86_64-avx-encoding.s
|
| 1386e9b7b16a8138ae7060c2dbb8b029f7c4fce2 |
29-May-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-sse4a.s
|
| 0d82fe77f2b6f48b5fab131c1671169d154f8c69 |
11-Apr-2012 |
Charles Davis <cdavis@mines.edu> |
Add retw and lretw instructions. Also, fix Intel syntax parsing for all
ret instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154468 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax-encoding.s
86-32.s
86-64.s
|
| 769bbfd951018f9b36f3d2f0d70a23d81f2d3287 |
03-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-avx-encoding.s
|
| 4fd3d292753bd8232a76d5ac6b107f5899e5bfaa |
21-Mar-2012 |
Joerg Sonnenberger <joerg@bec.de> |
Fix generation of the address size override prefix. Add assertions for
the invalid cases. At least 16bit operand in 64bit mode is currently not
rejected in the parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153166 91177308-0d34-0410-b5e6-96231b3b80d8
ddress-size.s
|
| 0f5ab7c5f392d8207a4b0c5bf1f8b274a9f410df |
13-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Change the X86 assembler to not require a segment register on string
instruction's destination operand like it does for the source operand.
Also fix a typo in the comment for X86AsmParser::isSrcOp().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152654 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 84faf659125cb354794e457fa5a8a8daad84760d |
12-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Added a missing error check for X86 assembly with mismatched base and index
registers not both being 64-bit or both being 32-bit registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152580 91177308-0d34-0410-b5e6-96231b3b80d8
86_errors.s
|
| 58dfaa14651f36fc9fce2031eb011e65ae267b9f |
09-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Add the missing call to Error when a bad X86 scale expression is parsed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152443 91177308-0d34-0410-b5e6-96231b3b80d8
86_errors.s
|
| 63054f99af1fd013322e8081227b29656d49a2d2 |
09-Mar-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
test/MC/X86/lit.local.cfg: Fix up to detect 'X86' in targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152406 91177308-0d34-0410-b5e6-96231b3b80d8
it.local.cfg
|
| 54427e52197ecd8c748736d7bbb431f2bf65c90e |
06-Mar-2012 |
Eli Friedman <eli.friedman@gmail.com> |
Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152136 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| ec93b6decad4b95fd8a9531dc024b2b1881019bf |
05-Mar-2012 |
Eli Friedman <eli.friedman@gmail.com> |
Make aliases for shld and shrd match gas. PR12173.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152014 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| b80d571ea85db5d52fafed0523cf59e693502198 |
23-Feb-2012 |
Kevin Enderby <enderby@apple.com> |
Updated the llvm-mc disassembler C API to support for the X86 target.
rdar://10873652
As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back. If there is a
getOpInfo call back that is tried first and then if that gets no information
then the SymbolLookUp is called. I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo. And also don't use any
values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683
For the X86 target also fixed bugs so the annotations get printed.
Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions. rdar://10878166
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151267 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
|
| 28a713b20ad17f9a02d4677d8a2fea0edb208418 |
19-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Add vmfunc instruction to X86 assembler and disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150899 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-coverage.s
86-32.s
|
| 9e3d0b335111b2df73984a6cfd9ef1cd5d323872 |
18-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150873 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-coverage.s
86-32.s
|
| 0f0c411079cd21bb3a81a1b70bf8c67539a16c22 |
16-Feb-2012 |
Eli Bendersky <eli.bendersky@intel.com> |
Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed.
Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150664 91177308-0d34-0410-b5e6-96231b3b80d8
g.exp
it.local.cfg
|
| 885f65b4a1c1ec80cd800a0617c57a2289472165 |
30-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149291 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax-encoding.s
|
| be3e310d5ed8717f070acc71b0f4dae28cb08c4d |
30-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax. Support .intel_syntax directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149270 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax-2.s
|
| a28101e61aa3aeed5baf3d5b91d0f8bcb4e9e12a |
27-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149142 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| 3b96e1fe3b695e6d845668ea90d75016f0f46a17 |
24-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148864 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax-encoding.s
|
| f2d213745e07e884c1616f2f3d0b78f9e918e5db |
23-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Robustify parsing of memory operand's displacement experssion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148737 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| 3e08131185d5b3245065eb027900aed56b607970 |
23-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148721 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| 7c64fe651ad4581ac66b6407116144442a8a7f03 |
23-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Parse segment registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148712 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| 1aea430b8834f7bed3a14eda5027eac2133d6496 |
20-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Robustify register parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148591 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| fdd3b30151bc391efce74f4592a9a3bb595565a2 |
20-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Parse ... PTR [-8]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148570 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax-encoding.s
|
| cf0e269d16f3d784b428c9b1b1e22d1f9e8bb91d |
20-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148569 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax-encoding.s
|
| a951f77ca31b43551bd41765504519d6d76e6cbf |
19-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Post process 'and', 'sub' instructions and select better encoding, if available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148489 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax-encoding.s
|
| e60540f380cc9466f3b2f7d17adfd37db137689c |
19-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: There is no need to create unary expr for simple negative displacement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148486 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax-encoding.s
|
| ac0f0486022fb1798579c9a550154e839770efa9 |
19-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148485 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax-encoding.s
|
| b8ba13f0096b560ee618512019ca86969a9fa772 |
18-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Process instructions after match to select alternative encoding which may be more desirable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148431 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| 2f8af1d643cde711b292117e50b30452877432ef |
17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Fix parser match class to check memory operand size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148338 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| 6220fea2a877e5cff559ed38e98c59a076ea9825 |
17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Parse "BYTE PTR [RDX + RCX]"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148334 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| 9a3d293cf3f72b3c0ed5d4474fc5d4d12fd36be2 |
17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Do not unncessarily create plus expression for memory operand displacement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148321 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| 40bced0306e953c3d0fec19db4c4770b0e3c787e |
17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Ignore mnemonic aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148316 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| d37ad247cc04c2a436e537767ac1aec709901594 |
17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Robustify memory operand parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148312 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| 4a5c0fd70e7a2001b682c8972dab6b0127313c8f |
13-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Add new test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148128 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.s
|
| 989a6814643dba79d5add649695c0523edafc026 |
12-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Remove test case, as Chris suggested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148039 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.ll
|
| 21d3c40fb04a8d9d9c44597c662b31569e74ff69 |
12-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Add test case to check intel syntax parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148034 91177308-0d34-0410-b5e6-96231b3b80d8
ntel-syntax.ll
|
| 7e840efc238db1123ea625b3d4e9893d6ea1bc50 |
16-Dec-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146709 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-avx-encoding.s
|
| 37e7ecf52b2f4e282b58ab81e59adc8b9b4ec336 |
12-Dec-2011 |
Jan Sjödin <jan_sjodin@yahoo.com> |
XOP instructions and encoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146407 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-xop-encoding.s
|
| dd649e35e522f5e0b5da3f9d172e06a375c12f77 |
30-Nov-2011 |
Jan Sjödin <jan_sjodin@yahoo.com> |
Support for encoding all FMA4 instructions and tablegen patterns for all
remaining FMA4 instructions and intrinsics with tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-fma4-encoding.s
|
| 1b9b377975b3f437acef8c2ba90de582add52f65 |
25-Nov-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
This patch contains support for encoding FMA4 instructions and
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.
Patch by Jan Sjodin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145133 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-fma4-encoding.s
|
| 9d399b1fc2f7dfad72f5ff3328983acb805eaf10 |
24-Nov-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: alias cqo to cqto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145121 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 5e6d54806570db81bbc8bdb480ce049f4bad05cc |
31-Oct-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Move test to the X86 directory, note the PR number and only run MC once.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143352 91177308-0d34-0410-b5e6-96231b3b80d8
011-09-06-NoNewline.s
|
| 55c4127134d127ccd52cc2f4115af00084b28807 |
27-Oct-2011 |
Kevin Enderby <enderby@apple.com> |
Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and
not depend on In32BitMode. Use the sysexitq mnemonic for the version with the
REX.W prefix and only allow it only In64BitMode. rdar://9738584
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143112 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-coverage.s
86-64.s
86_errors.s
|
| 5679ec3b528fb897739251b1f66037767ce2f208 |
24-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 SARX, SHRX, and SHLX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142779 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-bmi-encoding.s
|
| 75485d6746f8b5b23c17cf6d2364e7e1e0705992 |
23-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 RORX instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-bmi-encoding.s
|
| 717cdb0df88ddf704f057fb70ed7093836222609 |
19-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-bmi-encoding.s
|
| ee62e4f6d192ee31d1ad9dd0ba0c41db6663d3c7 |
16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 PEXTR and PDEP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-bmi-encoding.s
|
| b53fa8bf19a51f0c49a9f8b6ede3e2ff3bdfb961 |
16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 BZHI instruction as well as BMI2 feature detection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-bmi-encoding.s
|
| d8b7aa26134d2abee777f745c32005e63dea2455 |
16-Oct-2011 |
Chris Lattner <sabre@nondot.org> |
Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance
the X86 asmparser to produce ranges in the one case that was annoying me, for example:
test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
^~~~~~~
It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use
ranges where appropriate if someone is interested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142106 91177308-0d34-0410-b5e6-96231b3b80d8
86_errors.s
|
| 17730847d59c919d97f097d46a3fcba1888e5300 |
16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-bmi-encoding.s
|
| 566f233ba64c0bb2773b5717cb18753c7564f4b7 |
15-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-bmi-encoding.s
|
| acbaecd4c8e4d19207e63624dcd9e01947b51757 |
12-Oct-2011 |
Kevin Enderby <enderby@apple.com> |
Finish supporting cpp #file/line comments in assembler for error messages. So
for cpp pre-processed assembly we give correct filename and line numbers when
reporting errors in assembly files when using clang and -integrated-as on .s
files. rdar://8998895
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141814 91177308-0d34-0410-b5e6-96231b3b80d8
86_errors.s
|
| 25f6dfd108801d1dc5877c420ef0dd47131aeda7 |
07-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
86-64.s
|
| 7ea16b01fad5236cc132cb5fc3e443fcbf70d3b8 |
06-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
86-64.s
|
| 448d98685847a1daf7451b95904ae92a3cbab2ac |
20-Sep-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
The wrong relocation was being emitted for several SSSE3 instructions.
This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen
declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140184 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-avx-encoding.s
|
| d91c6e058b3f21a5299e6a2e8b9ed2f6899e0b19 |
20-Sep-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix PR10949. Fix the encoding of VMOVPQIto64rr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140098 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-avx-encoding.s
|
| 0c9acfcb50a844eefe92556e59c81fc302f32d1c |
20-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Re-write part of VEX encoding logic, to be more easy to read! Also fix
a bug and add a testcase!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138123 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-avx-encoding.s
|
| 863e0f25b7b53f6c7f43cdb8a0b900003096595e |
19-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the
implementation!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138029 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-avx-encoding.s
|
| 1deddbbd5659edc92028c2278018d21375ce3c81 |
16-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reorder declarations of vmovmskp* and also put the necessary AVX
predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137684 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-avx.s
|
| 5de728cfe1a922ac9b13546dca94526b2fa693b6 |
28-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.
rdar://8204588
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8
DNow.s
86-32-coverage.s
86_errors.s
|
| c37d4bbf1f33c5e4b1c2f1bf1a6e2cae2ae5603a |
28-Jul-2011 |
Kevin Enderby <enderby@apple.com> |
Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored. The others remain unchanged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136287 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-avx.s
86-32-coverage.s
|
| d521f2d2f1a866ba9f9e73ca566e2b486c15dc74 |
06-Jul-2011 |
Kevin Enderby <enderby@apple.com> |
Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a
push with a small constant produces a 2-byte push.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134501 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| af45b3d8cb1b88d3cf775542996d78d8ce009274 |
05-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134424 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| ca0ede7655cbe126441dd13599eafdf442eff3a9 |
30-Jun-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Recognize the xstorerng alias for VIA PadLock's xstore instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134126 91177308-0d34-0410-b5e6-96231b3b80d8
adlock.s
|
| a390a1aa48d8fa5085aa51b950f00d79dbb0c646 |
23-Jun-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Add support for movntil/movntiq mnemonics. Reported on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133759 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-coverage.s
86-64.s
|
| 94d4c91bc5b2a84e6b93250599b6742777dbd35e |
22-Jun-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Add support for assembling "movq" when it's correct to do so, while continuing
to emit "movd" across the board to continue supporting a Darwin assembler bug.
This is the reincarnation of r133452.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133565 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 38c892624bc66cad98a81e080d235f4e33122562 |
21-Jun-2011 |
Bob Wilson <bob.wilson@apple.com> |
Revert r133452: "Emit movq for 64-bit register to XMM register moves..."
This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using
the integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133524 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
86_64-avx-encoding.s
|
| 1bd15700a0eb3057d3e2d65070c3fc6b99e0d8a2 |
20-Jun-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Emit movq for 64-bit register to XMM register moves, but continue to accept
movd when assembling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133452 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
86_64-avx-encoding.s
|
| 393c4047c05b6d7b5851d339e51bb2cc35f630c2 |
15-Jun-2011 |
Bill Wendling <isanbard@gmail.com> |
Improve the heuristic to emit the alias if the number of hard-coded registers
are also greater than the alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133038 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 740e5b3586a474f1cea371cf6f652850e5420b90 |
14-Jun-2011 |
Bill Wendling <isanbard@gmail.com> |
Heuristic: If the number of operands in the alias are more than the number of
operands in the aliasee, don't print the alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132963 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| d521d8bf923b2f4b3e44a4ae2ebd0dcb59d7b23b |
23-May-2011 |
Chris Lattner <sabre@nondot.org> |
add test from PR9164
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131876 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
|
| b8a21ad91556903d055bb1de47f75655ca4e9ba6 |
23-May-2011 |
Chris Lattner <sabre@nondot.org> |
testcase for PR9378
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131875 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
|
| b65122c8736e6f8795043ca9885feb676781af4a |
04-May-2011 |
Eric Christopher <echristo@apple.com> |
Remove some random comments that snuck in from somewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130812 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-coverage.s
|
| 2fc496fcf5c5caf3e6af755d2c8fc97686cc2dd2 |
03-May-2011 |
Eric Christopher <echristo@apple.com> |
xmm0 is an implicit parameter in this and so shouldn't be in the
string template.
Fixes rdar://8493866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130747 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-coverage.s
|
| c25e8d8cea7af83b5538ac0e521366d06c9720d9 |
15-Apr-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Add encoding tests for flds/filds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129589 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-coverage.s
86_64-encoding.s
|
| d336de318eafd7643f65a901315920ec10ce05cd |
14-Apr-2011 |
Bill Wendling <isanbard@gmail.com> |
As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias
(movzx/movsx) because they give more information. Revert that part of the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129498 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| c6df9883da99915d1cfa491b381ffa703c61ed90 |
14-Apr-2011 |
Bill Wendling <isanbard@gmail.com> |
Have the X86 back-end emit the alias instead of what's being aliased. In most
cases, it's much nicer and more informative reading the alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
86-64.s
|
| 15f895179953b258e4ca20860d0d58f25f3a3edb |
09-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately,
InstAlias doesn't allow matching immediate operands, so we have to write
C++ code to do this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129223 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 4a8ac8de1ddfeaadb9ff13ce361bfc6435f18028 |
04-Apr-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Add support for the VIA PadLock instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
adlock.s
|
| 96622aa063435b1de085489f0e3e49b5912c22da |
18-Mar-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Support explicit argument forms for the X86 string instructions.
For now, only the default segments are supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127875 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
86-64.s
|
| 86d822df6d9a484b3672b2a909641262663a45dc |
04-Mar-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Followup to r126970: add 64-bit encoding tests for str with reg operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126987 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| ac39bd534be9a8022c09cc8be81db2de109baecb |
04-Mar-2011 |
Eli Friedman <eli.friedman@gmail.com> |
PR9377: Handle x86 str with register operand in a way consistent with gas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126970 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
|
| 00743c2218ff3f0f4edce972e2d88893a19e6ef8 |
22-Feb-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Use the same (%dx) hack for in[bwl] as for out[bwl].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126244 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| d86f482e4a9d71596e4f81afb0f7912ab3e40a7f |
22-Feb-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Recognize loopz and loopnz as aliases for loope and loopne.
From Dimitry Andric.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126168 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
86-64.s
|
| 87ca0e077d91b96a765b3b24cadfa8891026a33a |
22-Feb-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement xgetbv and xsetbv.
Patch by Jai Menon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126165 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 824a9076eaf8d109bc79f53e51b7d7a045f42552 |
19-Feb-2011 |
Chris Lattner <sabre@nondot.org> |
implement PR9264: disambiguating 'bt mem, imm' as a btl.
This is reasonable to do since all bt-mem forms do the
same thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126047 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 5ad596f9d27a67767118857471e63b55bfb152d6 |
18-Feb-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Recognize monitor/mwait with explicit register arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125805 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
86-64.s
|
| 97755a063eb65705e928550b048ecb921c83545c |
18-Feb-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Recognize leavel and leaveq aliases for leave.
Validate encoding of leave in 64bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125795 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-coverage.s
86_64-encoding.s
|
| 26f23100ac8165c510c00f7a37f1ab13bf66f141 |
13-Feb-2011 |
Reid Kleckner <reid@kleckner.net> |
Add encodings and mnemonics for FXSAVE64 and FXRSTOR64.
These are just FXSAVE and FXRSTOR with REX.W prefixes. These versions use
64-bit pointer values instead of 32-bit pointer values in the memory map they
dump and restore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125446 91177308-0d34-0410-b5e6-96231b3b80d8
86_64-encoding.s
|
| 3a5004dc3ee789bcbafd5b9733d3302e73e1187d |
11-Jan-2011 |
Chris Lattner <sabre@nondot.org> |
Fix PR8946, a missing reg/reg form of movdqu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123242 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| c00210cef28b48b17408eb79e94691779da9d474 |
30-Dec-2010 |
Nick Lewycky <nicholas@mxc.ca> |
Add another non-commutable instruction that gas accepts commuted forms for.
Fixes PR8861.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122641 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 7ab3cc32d6bd3c3166184e27713c91f5317c7f85 |
25-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
Generalize a previous change, fixing PR8855 - an valid large immediate
rejected by the mc assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122557 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 76331754d4a06e2394c15ae8f4870f4aeaf5ca1f |
09-Dec-2010 |
Kevin Enderby <enderby@apple.com> |
Allow a slash, '/', as a prefix separator for X86. rdar://8741045
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121320 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| d8f717911dcdccb1a60b3049ea22c7767970dcb7 |
28-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
fix PR8686, accepting a 'b' suffix at the end of all the setcc
instructions. I choose to handle this with an asmparser hack,
though it could be handled by changing all the instruction definitions
to allow be "setneb" instead of "setne". The asm parser hack is
better in this case, because we want the disassembler to produce
setne, not setneb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120260 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
|
| bfd2d26159c87262fcf462ea442f99478a2093c9 |
27-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Implement the data16 prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120224 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 5c7106b2e375edca4b63ab48b218654f978698a4 |
24-Nov-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Testcase for r120017.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120099 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| cbf5d74e6a99b6e38c9c05e08b6319ed0ce49650 |
21-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement PR8524, apparently mainline gas accepts movq as an alias for movd
when transfering between i64 gprs and mmx regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119931 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 269f10b316b41fde5c9bf3f6e5c471f371862834 |
12-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
accept lret as an alias for lretl, fixing the reopened part of PR8592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118916 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 6b5e3978e3f720f6d2828068157b9d9687aee711 |
12-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118903 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 689cf3cb6222652b92fdbd52e96c1d2f421ac44e |
06-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement aliases for div/idiv that have an explicit A register operand,
implementing rdar://8431864
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118364 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 04a75abe234f1093f69a065d799b3271ccd09f99 |
06-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add aliases for movs between seg registers and mem. There are multiple
different forms of this instruction (movw/movl/movq) which we reported
as being ambiguous. Since they all do the same thing, gas just picks the
one with the shortest encoding. Follow its lead here.
This implements rdar://8208615
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118362 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| db28788e4ae01c3fa8003773fc236768e87f6917 |
06-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
go to great lengths to work around a GAS bug my previous patch
exposed:
GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.
Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).
As such, switch the canonical form of this instruction to "pi" instead
of "ip". This makes the code generator and disassembler generate pi,
avoiding the gas bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118356 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-coverage.s
86-32.s
|
| 8c24b0c6996a8f03ff32766f0695dcf19577af59 |
06-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
rework the rotate-by-1 instructions to be defined like the
shift-by-1 instructions, where the asmstring doesn't contain
the implicit 1. It turns out that a bunch of these rotate
instructions were completely broken because they used 1
instead of $1.
This fixes assembly mismatches on "rclb $1, %bl" and friends,
where we used to generate the 3 byte form, we now generate the
proper 2-byte form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118355 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 235705b9ca08b66532528930adf9d9c23fd7b42b |
06-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
change the fp comparison instructions to not have %st0 explicitly
listed in its asm string, for consistency with the other similar
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118354 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-coverage.s
86-32.s
86-64.s
|
| fb7000fcbde3b5257ac055e1e5abdee5df21842b |
06-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
correct suffix matching to search for s/l/t suffixes on
floating point stack instructions instead of looking for b/w/l/q.
This fixes issues where we'd accidentally match fistp to fistpl,
when it is in fact an ambiguous instruction.
This changes the behavior of llvm-mc to reject fstp, which was the
correct fix for rdar://8456389:
t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt')
fstp (%rax)
it also causes us to correctly reject fistp and fist, which addresses
PR8528:
t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl')
fistp (%rax)
^
t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl')
fist (%rax)
^
Thanks to Ismail Donmez for tracking down the issue here!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118346 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| acc473fcf9860567d4da60625944d48b075d28f8 |
01-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
"mov[zs]x (mem), GR16" are not ambiguous: the mem
must be 8 bits. Support this memory form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117902 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| b501d4f673c0db267a76800339f9943f2ce6fe33 |
01-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
Implement enough of the missing instalias support to get
aliases installed and working. They now work when the
matched pattern and the result instruction have exactly
the same operand list.
This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.
Note that we do not accept instructions like:
movzx 0(%rsp), %rsi
GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand. It could be 8/16/32 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117901 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
|
| 4164f6bbbf4ebce676e8a6c0a0cf7a78ef46a0f3 |
01-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
make the asm matcher emitter reject instructions that have comments
in their asmstring. Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117897 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-coverage.s
|
| 1a1ecc9f3c2684249bd765d1299302d629aaf4fe |
30-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
fix an encoding mismatch where "sal %eax, 1" was not using the short encoding
for shl. Caught by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117820 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
|
| 905b8f76142b43cd33c36c554d359ee8740f51d5 |
30-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
add a test for the ud2a alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117803 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
|
| 529b1a43986265fb399eecd0dcbf9c409d049853 |
27-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
Added the x86 instruction ud2b (2nd official undefined instruction).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117485 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
|
| e460890351ed36fa518960a417d85964c2b29eee |
27-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
Yet another tweak to X86 instructions to add ud2a as an alias to ud2
(still to add ud2b).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117435 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
|
| 5a378076a44ef3f507b91aa8e7715fabaec42074 |
27-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
Another tweak to X86 instructions to add the missing flex instruction (without
the wait prefix).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117434 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
|
| f4630ecc3f2b80440b2d9e59add56a3b422de684 |
27-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
Tweaks to X86 instructions to allow the 'w' suffix in places it makes
sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler
allows for these instructions. Done differently than in r117031 that
caused a valgrind error which was later reverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117433 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
|
| 41e8cc73cf570754fffdc6963321c153a8010458 |
27-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc
will accept versions that the darwin assembler allows. Forms ending in "pi" and
forms without all the operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117427 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
|
| 0966ec08610c02c8556105f2fff88a7e7247a549 |
22-Oct-2010 |
Andrew Trick <atrick@apple.com> |
Reverting r117031 to cleanup valgrind errors.
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117087 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-coverage.s
86-32.s
86-64.s
|
| 0b9325c97d031ab0e9a240d69a2be11ec1559e37 |
21-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
More tweaks to X86 instructions to allow the 'w' suffix in places it makes
sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler allows
for these instructions. Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117031 91177308-0d34-0410-b5e6-96231b3b80d8
86-32-coverage.s
86-32.s
86-64.s
|
| 87f4a1a4331e40cbba28e829561759d146273840 |
19-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
Added a few tweaks to the Intel Descriptor-table support instructions to allow
word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes. This is again for use just with assembly source for llvm-mc .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116773 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
86-64.s
|
| 7aef62ff8c72506cc9b77333d25f4aa8aa9cf9fe |
18-Oct-2010 |
Kevin Enderby <enderby@apple.com> |
Added a handful of x86-32 instructions that were missing so that llvm-mc would
be more complete. These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files. Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added. Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records. More missing instructions will be coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116716 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
86-64.s
|
| 508fc4708bb859391af8969614e67c84ab56c38c |
05-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
Replace a gross hack (the MOV64ri_alt instruction) with a slightly less
gross hack (having the asmmatcher handle the alias).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115685 91177308-0d34-0410-b5e6-96231b3b80d8
86-64.s
86_64-imm-widths.s
|
| d32d85e5ba2de223c853b2e1c9bd57a39ebab4ce |
03-Oct-2010 |
Eli Friedman <eli.friedman@gmail.com> |
Add 3DNowA instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115477 91177308-0d34-0410-b5e6-96231b3b80d8
DNow.s
|
| 591d76ea5a10062316e18075eccd4c62d60b5a80 |
03-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115473 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
|
| cc07d7116a7d398b2e1da9ad8bc17f7bf74164f5 |
03-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
add support for the prefetch/prefetchw instructions, move femms into
the right file. The assembler supports all the 3dnow instructions now,
but not the "3dnowa" ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115468 91177308-0d34-0410-b5e6-96231b3b80d8
DNow.s
|
| f132fa0e74b5faa5f7095cbe0dcf87e72939b588 |
03-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
what the heck, add support for the rest of the 3dNow! binary operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115467 91177308-0d34-0410-b5e6-96231b3b80d8
DNow.s
|
| 548abfcbd671b1144bf517b17643259dcae76f4f |
03-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
Implement support for the bizarre 3DNow! encoding (which is unlike anything
else in X86), and add support for pavgusb. This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.
If someone else is interested in banging out the rest of the 3DNow!
instructions, it should be quite easy now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115466 91177308-0d34-0410-b5e6-96231b3b80d8
DNow.s
|
| d47691460770c886cf2fdafaf0f53e0cd101ccf1 |
02-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
fix a regression introduced in r115243, in which the instruction
backing int_x86_ssse3_pshuf_w got removed. This caused PR8280.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115422 91177308-0d34-0410-b5e6-96231b3b80d8
86-32.s
|
| 3286db670c689104c0df4f98fbb4a66f6e4d2db5 |
01-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
move X86 subdir up a level
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115292 91177308-0d34-0410-b5e6-96231b3b80d8
g.exp
86-32-avx.s
86-32-coverage.s
86-32-fma3.s
86-32.s
86-64.s
86_64-avx-clmul-encoding.s
86_64-avx-encoding.s
86_64-encoding.s
86_64-fma3-encoding.s
86_64-imm-widths.s
86_directives.s
86_errors.s
86_operands.s
|