Lines Matching refs:reg
49 bool IsFpReg(int reg);
54 int TargetReg(SpecialTargetRegister reg);
55 RegisterInfo* GetRegInfo(int reg);
63 uint64_t GetRegMaskCommon(int reg);
66 void FlushReg(int reg);
71 void MarkPreservedSingle(int v_reg, int reg);
141 LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target);
143 LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target);
147 LIR* OpPcRelLoad(int reg, LIR* target);
175 void EmitOpReg(const X86EncodingMap* entry, uint8_t reg);
177 void EmitMemReg(const X86EncodingMap* entry, uint8_t base, int disp, uint8_t reg);
178 void EmitRegMem(const X86EncodingMap* entry, uint8_t reg, uint8_t base, int disp);
179 void EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index,
182 uint8_t reg);
183 void EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp);
186 void EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm);
188 void EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm);
189 void EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm);
190 void EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl);
191 void EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition);
196 void EmitPcRel(const X86EncodingMap* entry, uint8_t reg, int base_or_table, uint8_t index,
198 void EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset);