Lines Matching defs:cond
137 void ArmAssembler::EmitType01(Condition cond,
145 CHECK_NE(cond, kNoCondition);
146 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
157 void ArmAssembler::EmitType5(Condition cond, int offset, bool link) {
158 CHECK_NE(cond, kNoCondition);
159 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
166 void ArmAssembler::EmitMemOp(Condition cond,
172 CHECK_NE(cond, kNoCondition);
173 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
183 void ArmAssembler::EmitMemOpAddressMode3(Condition cond,
188 CHECK_NE(cond, kNoCondition);
189 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
198 void ArmAssembler::EmitMultiMemOp(Condition cond,
204 CHECK_NE(cond, kNoCondition);
205 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
215 void ArmAssembler::EmitShiftImmediate(Condition cond,
220 CHECK_NE(cond, kNoCondition);
222 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
232 void ArmAssembler::EmitShiftRegister(Condition cond,
237 CHECK_NE(cond, kNoCondition);
239 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
250 void ArmAssembler::EmitBranch(Condition cond, Label* label, bool link) {
252 EmitType5(cond, label->Position() - buffer_.Size(), link);
256 EmitType5(cond, label->position_, link);
262 Condition cond) {
263 EmitType01(cond, so.type(), AND, 0, rn, rd, so);
268 Condition cond) {
269 EmitType01(cond, so.type(), EOR, 0, rn, rd, so);
274 Condition cond) {
275 EmitType01(cond, so.type(), SUB, 0, rn, rd, so);
279 Condition cond) {
280 EmitType01(cond, so.type(), RSB, 0, rn, rd, so);
284 Condition cond) {
285 EmitType01(cond, so.type(), RSB, 1, rn, rd, so);
290 Condition cond) {
291 EmitType01(cond, so.type(), ADD, 0, rn, rd, so);
296 Condition cond) {
297 EmitType01(cond, so.type(), ADD, 1, rn, rd, so);
302 Condition cond) {
303 EmitType01(cond, so.type(), SUB, 1, rn, rd, so);
308 Condition cond) {
309 EmitType01(cond, so.type(), ADC, 0, rn, rd, so);
314 Condition cond) {
315 EmitType01(cond, so.type(), SBC, 0, rn, rd, so);
320 Condition cond) {
321 EmitType01(cond, so.type(), RSC, 0, rn, rd, so);
325 void ArmAssembler::tst(Register rn, ShifterOperand so, Condition cond) {
327 EmitType01(cond, so.type(), TST, 1, rn, R0, so);
331 void ArmAssembler::teq(Register rn, ShifterOperand so, Condition cond) {
333 EmitType01(cond, so.type(), TEQ, 1, rn, R0, so);
337 void ArmAssembler::cmp(Register rn, ShifterOperand so, Condition cond) {
338 EmitType01(cond, so.type(), CMP, 1, rn, R0, so);
342 void ArmAssembler::cmn(Register rn, ShifterOperand so, Condition cond) {
343 EmitType01(cond, so.type(), CMN, 1, rn, R0, so);
348 ShifterOperand so, Condition cond) {
349 EmitType01(cond, so.type(), ORR, 0, rn, rd, so);
354 ShifterOperand so, Condition cond) {
355 EmitType01(cond, so.type(), ORR, 1, rn, rd, so);
359 void ArmAssembler::mov(Register rd, ShifterOperand so, Condition cond) {
360 EmitType01(cond, so.type(), MOV, 0, R0, rd, so);
364 void ArmAssembler::movs(Register rd, ShifterOperand so, Condition cond) {
365 EmitType01(cond, so.type(), MOV, 1, R0, rd, so);
370 Condition cond) {
371 EmitType01(cond, so.type(), BIC, 0, rn, rd, so);
375 void ArmAssembler::mvn(Register rd, ShifterOperand so, Condition cond) {
376 EmitType01(cond, so.type(), MVN, 0, R0, rd, so);
380 void ArmAssembler::mvns(Register rd, ShifterOperand so, Condition cond) {
381 EmitType01(cond, so.type(), MVN, 1, R0, rd, so);
385 void ArmAssembler::clz(Register rd, Register rm, Condition cond) {
388 CHECK_NE(cond, kNoCondition);
391 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
399 void ArmAssembler::movw(Register rd, uint16_t imm16, Condition cond) {
400 CHECK_NE(cond, kNoCondition);
401 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
408 void ArmAssembler::movt(Register rd, uint16_t imm16, Condition cond) {
409 CHECK_NE(cond, kNoCondition);
410 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
417 void ArmAssembler::EmitMulOp(Condition cond, int32_t opcode,
424 CHECK_NE(cond, kNoCondition);
426 (static_cast<int32_t>(cond) << kConditionShift) |
436 void ArmAssembler::mul(Register rd, Register rn, Register rm, Condition cond) {
438 EmitMulOp(cond, 0, R0, rd, rn, rm);
443 Condition cond) {
445 EmitMulOp(cond, B21, ra, rd, rn, rm);
450 Condition cond) {
452 EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
457 Register rm, Condition cond) {
459 EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm);
463 void ArmAssembler::ldr(Register rd, Address ad, Condition cond) {
464 EmitMemOp(cond, true, false, rd, ad);
468 void ArmAssembler::str(Register rd, Address ad, Condition cond) {
469 EmitMemOp(cond, false, false, rd, ad);
473 void ArmAssembler::ldrb(Register rd, Address ad, Condition cond) {
474 EmitMemOp(cond, true, true, rd, ad);
478 void ArmAssembler::strb(Register rd, Address ad, Condition cond) {
479 EmitMemOp(cond, false, true, rd, ad);
483 void ArmAssembler::ldrh(Register rd, Address ad, Condition cond) {
484 EmitMemOpAddressMode3(cond, L | B7 | H | B4, rd, ad);
488 void ArmAssembler::strh(Register rd, Address ad, Condition cond) {
489 EmitMemOpAddressMode3(cond, B7 | H | B4, rd, ad);
493 void ArmAssembler::ldrsb(Register rd, Address ad, Condition cond) {
494 EmitMemOpAddressMode3(cond, L | B7 | B6 | B4, rd, ad);
498 void ArmAssembler::ldrsh(Register rd, Address ad, Condition cond) {
499 EmitMemOpAddressMode3(cond, L | B7 | B6 | H | B4, rd, ad);
503 void ArmAssembler::ldrd(Register rd, Address ad, Condition cond) {
505 EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, ad);
509 void ArmAssembler::strd(Register rd, Address ad, Condition cond) {
511 EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, ad);
518 Condition cond) {
519 EmitMultiMemOp(cond, am, true, base, regs);
526 Condition cond) {
527 EmitMultiMemOp(cond, am, false, base, regs);
531 void ArmAssembler::ldrex(Register rt, Register rn, Condition cond) {
534 CHECK_NE(cond, kNoCondition);
535 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
549 Condition cond) {
553 CHECK_NE(cond, kNoCondition);
554 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
572 void ArmAssembler::nop(Condition cond) {
573 CHECK_NE(cond, kNoCondition);
574 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
580 void ArmAssembler::vmovsr(SRegister sn, Register rt, Condition cond) {
585 CHECK_NE(cond, kNoCondition);
586 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
595 void ArmAssembler::vmovrs(Register rt, SRegister sn, Condition cond) {
600 CHECK_NE(cond, kNoCondition);
601 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
611 Condition cond) {
620 CHECK_NE(cond, kNoCondition);
621 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
632 Condition cond) {
642 CHECK_NE(cond, kNoCondition);
643 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
654 Condition cond) {
662 CHECK_NE(cond, kNoCondition);
663 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
674 Condition cond) {
683 CHECK_NE(cond, kNoCondition);
684 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
694 void ArmAssembler::vldrs(SRegister sd, Address ad, Condition cond) {
696 CHECK_NE(cond, kNoCondition);
697 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
706 void ArmAssembler::vstrs(SRegister sd, Address ad, Condition cond) {
709 CHECK_NE(cond, kNoCondition);
710 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
719 void ArmAssembler::vldrd(DRegister dd, Address ad, Condition cond) {
721 CHECK_NE(cond, kNoCondition);
722 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
731 void ArmAssembler::vstrd(DRegister dd, Address ad, Condition cond) {
734 CHECK_NE(cond, kNoCondition);
735 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
744 void ArmAssembler::EmitVFPsss(Condition cond, int32_t opcode,
749 CHECK_NE(cond, kNoCondition);
750 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
762 void ArmAssembler::EmitVFPddd(Condition cond, int32_t opcode,
767 CHECK_NE(cond, kNoCondition);
768 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
780 void ArmAssembler::vmovs(SRegister sd, SRegister sm, Condition cond) {
781 EmitVFPsss(cond, B23 | B21 | B20 | B6, sd, S0, sm);
785 void ArmAssembler::vmovd(DRegister dd, DRegister dm, Condition cond) {
786 EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm);
790 bool ArmAssembler::vmovs(SRegister sd, float s_imm, Condition cond) {
797 EmitVFPsss(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | (imm8 & 0xf),
805 bool ArmAssembler::vmovd(DRegister dd, double d_imm, Condition cond) {
812 EmitVFPddd(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | B8 | (imm8 & 0xf),
821 Condition cond) {
822 EmitVFPsss(cond, B21 | B20, sd, sn, sm);
827 Condition cond) {
828 EmitVFPddd(cond, B21 | B20, dd, dn, dm);
833 Condition cond) {
834 EmitVFPsss(cond, B21 | B20 | B6, sd, sn, sm);
839 Condition cond) {
840 EmitVFPddd(cond, B21 | B20 | B6, dd, dn, dm);
845 Condition cond) {
846 EmitVFPsss(cond, B21, sd, sn, sm);
851 Condition cond) {
852 EmitVFPddd(cond, B21, dd, dn, dm);
857 Condition cond) {
858 EmitVFPsss(cond, 0, sd, sn, sm);
863 Condition cond) {
864 EmitVFPddd(cond, 0, dd, dn, dm);
869 Condition cond) {
870 EmitVFPsss(cond, B6, sd, sn, sm);
875 Condition cond) {
876 EmitVFPddd(cond, B6, dd, dn, dm);
881 Condition cond) {
882 EmitVFPsss(cond, B23, sd, sn, sm);
887 Condition cond) {
888 EmitVFPddd(cond, B23, dd, dn, dm);
892 void ArmAssembler::vabss(SRegister sd, SRegister sm, Condition cond) {
893 EmitVFPsss(cond, B23 | B21 | B20 | B7 | B6, sd, S0, sm);
897 void ArmAssembler::vabsd(DRegister dd, DRegister dm, Condition cond) {
898 EmitVFPddd(cond, B23 | B21 | B20 | B7 | B6, dd, D0, dm);
902 void ArmAssembler::vnegs(SRegister sd, SRegister sm, Condition cond) {
903 EmitVFPsss(cond, B23 | B21 | B20 | B16 | B6, sd, S0, sm);
907 void ArmAssembler::vnegd(DRegister dd, DRegister dm, Condition cond) {
908 EmitVFPddd(cond, B23 | B21 | B20 | B16 | B6, dd, D0, dm);
912 void ArmAssembler::vsqrts(SRegister sd, SRegister sm, Condition cond) {
913 EmitVFPsss(cond, B23 | B21 | B20 | B16 | B7 | B6, sd, S0, sm);
916 void ArmAssembler::vsqrtd(DRegister dd, DRegister dm, Condition cond) {
917 EmitVFPddd(cond, B23 | B21 | B20 | B16 | B7 | B6, dd, D0, dm);
921 void ArmAssembler::EmitVFPsd(Condition cond, int32_t opcode,
925 CHECK_NE(cond, kNoCondition);
926 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
936 void ArmAssembler::EmitVFPds(Condition cond, int32_t opcode,
940 CHECK_NE(cond, kNoCondition);
941 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
951 void ArmAssembler::vcvtsd(SRegister sd, DRegister dm, Condition cond) {
952 EmitVFPsd(cond, B23 | B21 | B20 | B18 | B17 | B16 | B8 | B7 | B6, sd, dm);
956 void ArmAssembler::vcvtds(DRegister dd, SRegister sm, Condition cond) {
957 EmitVFPds(cond, B23 | B21 | B20 | B18 | B17 | B16 | B7 | B6, dd, sm);
961 void ArmAssembler::vcvtis(SRegister sd, SRegister sm, Condition cond) {
962 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6, sd, S0, sm);
966 void ArmAssembler::vcvtid(SRegister sd, DRegister dm, Condition cond) {
967 EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B16 | B8 | B7 | B6, sd, dm);
971 void ArmAssembler::vcvtsi(SRegister sd, SRegister sm, Condition cond) {
972 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B7 | B6, sd, S0, sm);
976 void ArmAssembler::vcvtdi(DRegister dd, SRegister sm, Condition cond) {
977 EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B7 | B6, dd, sm);
981 void ArmAssembler::vcvtus(SRegister sd, SRegister sm, Condition cond) {
982 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B7 | B6, sd, S0, sm);
986 void ArmAssembler::vcvtud(SRegister sd, DRegister dm, Condition cond) {
987 EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B8 | B7 | B6, sd, dm);
991 void ArmAssembler::vcvtsu(SRegister sd, SRegister sm, Condition cond) {
992 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B6, sd, S0, sm);
996 void ArmAssembler::vcvtdu(DRegister dd, SRegister sm, Condition cond) {
997 EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B6, dd, sm);
1001 void ArmAssembler::vcmps(SRegister sd, SRegister sm, Condition cond) {
1002 EmitVFPsss(cond, B23 | B21 | B20 | B18 | B6, sd, S0, sm);
1006 void ArmAssembler::vcmpd(DRegister dd, DRegister dm, Condition cond) {
1007 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B6, dd, D0, dm);
1011 void ArmAssembler::vcmpsz(SRegister sd, Condition cond) {
1012 EmitVFPsss(cond, B23 | B21 | B20 | B18 | B16 | B6, sd, S0, S0);
1016 void ArmAssembler::vcmpdz(DRegister dd, Condition cond) {
1017 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B16 | B6, dd, D0, D0);
1021 void ArmAssembler::vmstat(Condition cond) { // VMRS APSR_nzcv, FPSCR
1022 CHECK_NE(cond, kNoCondition);
1023 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
1045 void ArmAssembler::b(Label* label, Condition cond) {
1046 EmitBranch(cond, label, false);
1050 void ArmAssembler::bl(Label* label, Condition cond) {
1051 EmitBranch(cond, label, true);
1055 void ArmAssembler::blx(Register rm, Condition cond) {
1057 CHECK_NE(cond, kNoCondition);
1058 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
1064 void ArmAssembler::bx(Register rm, Condition cond) {
1066 CHECK_NE(cond, kNoCondition);
1067 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
1124 void ArmAssembler::AddConstant(Register rd, int32_t value, Condition cond) {
1125 AddConstant(rd, rd, value, cond);
1130 Condition cond) {
1133 mov(rd, ShifterOperand(rn), cond);
1142 add(rd, rn, shifter_op, cond);
1144 sub(rd, rn, shifter_op, cond);
1148 mvn(IP, shifter_op, cond);
1149 add(rd, rn, ShifterOperand(IP), cond);
1151 mvn(IP, shifter_op, cond);
1152 sub(rd, rn, ShifterOperand(IP), cond);
1154 movw(IP, Low16Bits(value), cond);
1157 movt(IP, value_high, cond);
1159 add(rd, rn, ShifterOperand(IP), cond);
1166 Condition cond) {
1169 adds(rd, rn, shifter_op, cond);
1171 subs(rd, rn, shifter_op, cond);
1175 mvn(IP, shifter_op, cond);
1176 adds(rd, rn, ShifterOperand(IP), cond);
1178 mvn(IP, shifter_op, cond);
1179 subs(rd, rn, ShifterOperand(IP), cond);
1181 movw(IP, Low16Bits(value), cond);
1184 movt(IP, value_high, cond);
1186 adds(rd, rn, ShifterOperand(IP), cond);
1192 void ArmAssembler::LoadImmediate(Register rd, int32_t value, Condition cond) {
1195 mov(rd, shifter_op, cond);
1197 mvn(rd, shifter_op, cond);
1199 movw(rd, Low16Bits(value), cond);
1202 movt(rd, value_high, cond);
1252 Condition cond) {
1255 LoadImmediate(IP, offset, cond);
1256 add(IP, IP, ShifterOperand(base), cond);
1263 ldrsb(reg, Address(base, offset), cond);
1266 ldrb(reg, Address(base, offset), cond);
1269 ldrsh(reg, Address(base, offset), cond);
1272 ldrh(reg, Address(base, offset), cond);
1275 ldr(reg, Address(base, offset), cond);
1278 ldrd(reg, Address(base, offset), cond);
1290 Condition cond) {
1293 LoadImmediate(IP, offset, cond);
1294 add(IP, IP, ShifterOperand(base), cond);
1299 vldrs(reg, Address(base, offset), cond);
1307 Condition cond) {
1310 LoadImmediate(IP, offset, cond);
1311 add(IP, IP, ShifterOperand(base), cond);
1316 vldrd(reg, Address(base, offset), cond);
1325 Condition cond) {
1329 LoadImmediate(IP, offset, cond);
1330 add(IP, IP, ShifterOperand(base), cond);
1337 strb(reg, Address(base, offset), cond);
1340 strh(reg, Address(base, offset), cond);
1343 str(reg, Address(base, offset), cond);
1346 strd(reg, Address(base, offset), cond);
1358 Condition cond) {
1361 LoadImmediate(IP, offset, cond);
1362 add(IP, IP, ShifterOperand(base), cond);
1367 vstrs(reg, Address(base, offset), cond);
1375 Condition cond) {
1378 LoadImmediate(IP, offset, cond);
1379 add(IP, IP, ShifterOperand(base), cond);
1384 vstrd(reg, Address(base, offset), cond);
1387 void ArmAssembler::Push(Register rd, Condition cond) {
1388 str(rd, Address(SP, -kRegisterSize, Address::PreIndex), cond);
1391 void ArmAssembler::Pop(Register rd, Condition cond) {
1392 ldr(rd, Address(SP, kRegisterSize, Address::PostIndex), cond);
1395 void ArmAssembler::PushList(RegList regs, Condition cond) {
1396 stm(DB_W, SP, regs, cond);
1399 void ArmAssembler::PopList(RegList regs, Condition cond) {
1400 ldm(IA_W, SP, regs, cond);
1403 void ArmAssembler::Mov(Register rd, Register rm, Condition cond) {
1405 mov(rd, ShifterOperand(rm), cond);
1410 Condition cond) {
1412 mov(rd, ShifterOperand(rm, LSL, shift_imm), cond);
1416 Condition cond) {
1419 mov(rd, ShifterOperand(rm, LSR, shift_imm), cond);
1423 Condition cond) {
1426 mov(rd, ShifterOperand(rm, ASR, shift_imm), cond);
1430 Condition cond) {
1432 mov(rd, ShifterOperand(rm, ROR, shift_imm), cond);
1435 void ArmAssembler::Rrx(Register rd, Register rm, Condition cond) {
1436 mov(rd, ShifterOperand(rm, ROR, 0), cond);