Lines Matching refs:cUnit
30 static void markCard(CompilationUnit *cUnit, int valReg, int tgtAddrReg)
32 int regCardBase = dvmCompilerAllocTemp(cUnit);
33 int regCardNo = dvmCompilerAllocTemp(cUnit);
34 ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondEq, valReg, 0);
35 loadWordDisp(cUnit, r6SELF, offsetof(Thread, cardTable),
37 opRegRegImm(cUnit, kOpLsr, regCardNo, tgtAddrReg, GC_CARD_SHIFT);
38 storeBaseIndexed(cUnit, regCardBase, regCardNo, regCardBase, 0,
40 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
43 dvmCompilerFreeTemp(cUnit, regCardBase);
44 dvmCompilerFreeTemp(cUnit, regCardNo);
47 static bool genConversionCall(CompilationUnit *cUnit, MIR *mir, void *funct,
56 dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
58 rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
59 loadValueDirectFixed(cUnit, rlSrc, r0);
61 rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
62 loadValueDirectWideFixed(cUnit, rlSrc, r0, r1);
64 LOAD_FUNC_ADDR(cUnit, r2, (int)funct);
65 opReg(cUnit, kOpBlx, r2);
66 dvmCompilerClobberCallRegs(cUnit);
69 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
70 rlResult = dvmCompilerGetReturn(cUnit);
71 storeValue(cUnit, rlDest, rlResult);
74 rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
75 rlResult = dvmCompilerGetReturnWide(cUnit);
76 storeValueWide(cUnit, rlDest, rlResult);
81 static bool genArithOpFloatPortable(CompilationUnit *cUnit, MIR *mir,
110 genNegFloat(cUnit, rlDest, rlSrc1);
116 dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
117 loadValueDirectFixed(cUnit, rlSrc1, r0);
118 loadValueDirectFixed(cUnit, rlSrc2, r1);
119 LOAD_FUNC_ADDR(cUnit, r2, (int)funct);
120 opReg(cUnit, kOpBlx, r2);
121 dvmCompilerClobberCallRegs(cUnit);
122 rlResult = dvmCompilerGetReturn(cUnit);
123 storeValue(cUnit, rlDest, rlResult);
127 static bool genArithOpDoublePortable(CompilationUnit *cUnit, MIR *mir,
156 genNegDouble(cUnit, rlDest, rlSrc1);
162 dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
163 LOAD_FUNC_ADDR(cUnit, r14lr, (int)funct);
164 loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1);
165 loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3);
166 opReg(cUnit, kOpBlx, r14lr);
167 dvmCompilerClobberCallRegs(cUnit);
168 rlResult = dvmCompilerGetReturnWide(cUnit);
169 storeValueWide(cUnit, rlDest, rlResult);
171 cUnit->usesLinkRegister = true;
176 static bool genConversionPortable(CompilationUnit *cUnit, MIR *mir)
182 return genConversionCall(cUnit, mir, (void*)__aeabi_i2f, 1, 1);
184 return genConversionCall(cUnit, mir, (void*)__aeabi_f2iz, 1, 1);
186 return genConversionCall(cUnit, mir, (void*)__aeabi_d2f, 2, 1);
188 return genConversionCall(cUnit, mir, (void*)__aeabi_f2d, 1, 2);
190 return genConversionCall(cUnit, mir, (void*)__aeabi_i2d, 1, 2);
192 return genConversionCall(cUnit, mir, (void*)__aeabi_d2iz, 2, 1);
194 return genConversionCall(cUnit, mir, (void*)dvmJitf2l, 1, 2);
196 return genConversionCall(cUnit, mir, (void*)__aeabi_l2f, 2, 1);
198 return genConversionCall(cUnit, mir, (void*)dvmJitd2l, 2, 2);
200 return genConversionCall(cUnit, mir, (void*)__aeabi_l2d, 2, 2);
244 static void selfVerificationBranchInsertPass(CompilationUnit *cUnit)
249 for (thisLIR = (ArmLIR *) cUnit->firstLIRInsn;
250 thisLIR != (ArmLIR *) cUnit->lastLIRInsn;
261 if (cUnit->usesLinkRegister) {
262 genSelfVerificationPreBranch(cUnit, thisLIR);
274 if (cUnit->usesLinkRegister) {
275 genSelfVerificationPostBranch(cUnit, thisLIR);
283 static ArmLIR *genConditionalBranch(CompilationUnit *cUnit,
287 ArmLIR *branch = opCondBranch(cUnit, cond);
293 static inline ArmLIR *genTrap(CompilationUnit *cUnit, int dOffset,
296 ArmLIR *branch = opNone(cUnit, kOpUncondBr);
297 return genCheckCommon(cUnit, dOffset, branch, pcrLabel);
301 static void genIGetWide(CompilationUnit *cUnit, MIR *mir, int fieldOffset)
303 RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
304 RegLocation rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
306 rlObj = loadValue(cUnit, rlObj, kCoreReg);
307 int regPtr = dvmCompilerAllocTemp(cUnit);
311 genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
313 opRegRegImm(cUnit, kOpAdd, regPtr, rlObj.lowReg, fieldOffset);
314 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
317 loadPair(cUnit, regPtr, rlResult.lowReg, rlResult.highReg);
320 dvmCompilerFreeTemp(cUnit, regPtr);
321 storeValueWide(cUnit, rlDest, rlResult);
325 static void genIPutWide(CompilationUnit *cUnit, MIR *mir, int fieldOffset)
327 RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
328 RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 2);
329 rlObj = loadValue(cUnit, rlObj, kCoreReg);
331 rlSrc = loadValueWide(cUnit, rlSrc, kAnyReg);
332 genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
334 regPtr = dvmCompilerAllocTemp(cUnit);
335 opRegRegImm(cUnit, kOpAdd, regPtr, rlObj.lowReg, fieldOffset);
338 storePair(cUnit, regPtr, rlSrc.lowReg, rlSrc.highReg);
341 dvmCompilerFreeTemp(cUnit, regPtr);
348 static void genIGet(CompilationUnit *cUnit, MIR *mir, OpSize size,
353 RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
354 RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
355 rlObj = loadValue(cUnit, rlObj, kCoreReg);
356 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, regClass, true);
357 genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
361 loadBaseDisp(cUnit, mir, rlObj.lowReg, fieldOffset, rlResult.lowReg,
365 dvmCompilerGenMemBarrier(cUnit, kSY);
368 storeValue(cUnit, rlDest, rlResult);
375 static void genIPut(CompilationUnit *cUnit, MIR *mir, OpSize size,
379 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
380 RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 1);
381 rlObj = loadValue(cUnit, rlObj, kCoreReg);
382 rlSrc = loadValue(cUnit, rlSrc, regClass);
383 genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
387 dvmCompilerGenMemBarrier(cUnit, kST);
390 storeBaseDisp(cUnit, rlObj.lowReg, fieldOffset, rlSrc.lowReg, size);
393 dvmCompilerGenMemBarrier(cUnit, kSY);
397 markCard(cUnit, rlSrc.lowReg, rlObj.lowReg);
405 static void genArrayGet(CompilationUnit *cUnit, MIR *mir, OpSize size,
413 rlArray = loadValue(cUnit, rlArray, kCoreReg);
414 rlIndex = loadValue(cUnit, rlIndex, kCoreReg);
421 pcrLabel = genNullCheck(cUnit, rlArray.sRegLow,
425 regPtr = dvmCompilerAllocTemp(cUnit);
428 int regLen = dvmCompilerAllocTemp(cUnit);
430 loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLen);
432 opRegRegImm(cUnit, kOpAdd, regPtr, rlArray.lowReg, dataOffset);
433 genBoundsCheck(cUnit, rlIndex.lowReg, regLen, mir->offset,
435 dvmCompilerFreeTemp(cUnit, regLen);
438 opRegRegImm(cUnit, kOpAdd, regPtr, rlArray.lowReg, dataOffset);
442 int rNewIndex = dvmCompilerAllocTemp(cUnit);
443 opRegRegImm(cUnit, kOpLsl, rNewIndex, rlIndex.lowReg, scale);
444 opRegReg(cUnit, kOpAdd, regPtr, rNewIndex);
445 dvmCompilerFreeTemp(cUnit, rNewIndex);
447 opRegReg(cUnit, kOpAdd, regPtr, rlIndex.lowReg);
449 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, regClass, true);
452 loadPair(cUnit, regPtr, rlResult.lowReg, rlResult.highReg);
455 dvmCompilerFreeTemp(cUnit, regPtr);
456 storeValueWide(cUnit, rlDest, rlResult);
458 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, regClass, true);
461 loadBaseIndexed(cUnit, regPtr, rlIndex.lowReg, rlResult.lowReg,
465 dvmCompilerFreeTemp(cUnit, regPtr);
466 storeValue(cUnit, rlDest, rlResult);
474 static void genArrayPut(CompilationUnit *cUnit, MIR *mir, OpSize size,
483 rlArray = loadValue(cUnit, rlArray, kCoreReg);
484 rlIndex = loadValue(cUnit, rlIndex, kCoreReg);
486 if (dvmCompilerIsTemp(cUnit, rlArray.lowReg)) {
487 dvmCompilerClobber(cUnit, rlArray.lowReg);
490 regPtr = dvmCompilerAllocTemp(cUnit);
491 genRegCopy(cUnit, regPtr, rlArray.lowReg);
498 pcrLabel = genNullCheck(cUnit, rlArray.sRegLow, rlArray.lowReg,
503 int regLen = dvmCompilerAllocTemp(cUnit);
506 loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLen);
508 opRegImm(cUnit, kOpAdd, regPtr, dataOffset);
509 genBoundsCheck(cUnit, rlIndex.lowReg, regLen, mir->offset,
511 dvmCompilerFreeTemp(cUnit, regLen);
514 opRegImm(cUnit, kOpAdd, regPtr, dataOffset);
520 int rNewIndex = dvmCompilerAllocTemp(cUnit);
521 opRegRegImm(cUnit, kOpLsl, rNewIndex, rlIndex.lowReg, scale);
522 opRegReg(cUnit, kOpAdd, regPtr, rNewIndex);
523 dvmCompilerFreeTemp(cUnit, rNewIndex);
525 opRegReg(cUnit, kOpAdd, regPtr, rlIndex.lowReg);
527 rlSrc = loadValueWide(cUnit, rlSrc, regClass);
530 storePair(cUnit, regPtr, rlSrc.lowReg, rlSrc.highReg);
533 dvmCompilerFreeTemp(cUnit, regPtr);
535 rlSrc = loadValue(cUnit, rlSrc, regClass);
538 storeBaseIndexed(cUnit, regPtr, rlIndex.lowReg, rlSrc.lowReg,
549 static void genArrayObjectPut(CompilationUnit *cUnit, MIR *mir,
556 dvmCompilerFlushAllRegs(cUnit);
563 loadValueDirectFixed(cUnit, rlArray, regArray);
564 loadValueDirectFixed(cUnit, rlIndex, regIndex);
570 pcrLabel = genNullCheck(cUnit, rlArray.sRegLow, regArray,
576 loadWordDisp(cUnit, regArray, lenOffset, regLen);
578 opRegRegImm(cUnit, kOpAdd, regPtr, regArray, dataOffset);
579 genBoundsCheck(cUnit, regIndex, regLen, mir->offset,
583 opRegRegImm(cUnit, kOpAdd, regPtr, regArray, dataOffset);
587 loadValueDirectFixed(cUnit, rlSrc, r0);
588 LOAD_FUNC_ADDR(cUnit, r2, (int)dvmCanPutArrayElement);
591 ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondEq, r0, 0);
594 loadWordDisp(cUnit, regArray, offsetof(Object, clazz), r1);
595 loadWordDisp(cUnit, r0, offsetof(Object, clazz), r0);
596 opReg(cUnit, kOpBlx, r2);
597 dvmCompilerClobberCallRegs(cUnit);
604 dvmCompilerLockTemp(cUnit, regPtr); // r4PC
605 dvmCompilerLockTemp(cUnit, regIndex); // r7
606 dvmCompilerLockTemp(cUnit, r0);
607 dvmCompilerLockTemp(cUnit, r1);
610 genRegImmCheck(cUnit, kArmCondEq, r0, 0, mir->offset, pcrLabel);
613 loadValueDirectFixed(cUnit, rlSrc, r0);
614 loadValueDirectFixed(cUnit, rlArray, r1);
616 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
621 storeBaseIndexed(cUnit, regPtr, regIndex, r0,
625 dvmCompilerFreeTemp(cUnit, regPtr);
626 dvmCompilerFreeTemp(cUnit, regIndex);
629 markCard(cUnit, r0, r1);
632 static bool genShiftOpLong(CompilationUnit *cUnit, MIR *mir,
642 loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1);
643 loadValueDirect(cUnit, rlShift, r2);
647 genDispatchToHandler(cUnit, TEMPLATE_SHL_LONG);
651 genDispatchToHandler(cUnit, TEMPLATE_SHR_LONG);
655 genDispatchToHandler(cUnit, TEMPLATE_USHR_LONG);
660 rlResult = dvmCompilerGetReturnWide(cUnit);
661 storeValueWide(cUnit, rlDest, rlResult);
665 static bool genArithOpLong(CompilationUnit *cUnit, MIR *mir,
679 rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
680 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
681 opRegReg(cUnit, kOpMvn, rlResult.lowReg, rlSrc2.lowReg);
682 opRegReg(cUnit, kOpMvn, rlResult.highReg, rlSrc2.highReg);
683 storeValueWide(cUnit, rlDest, rlResult);
698 genMulLong(cUnit, rlDest, rlSrc1, rlSrc2);
732 int tReg = dvmCompilerAllocTemp(cUnit);
733 rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
734 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
735 loadConstantNoClobber(cUnit, tReg, 0);
736 opRegRegReg(cUnit, kOpSub, rlResult.lowReg,
738 opRegReg(cUnit, kOpSbc, tReg, rlSrc2.highReg);
739 genRegCopy(cUnit, rlResult.highReg, tReg);
740 storeValueWide(cUnit, rlDest, rlResult);
745 dvmCompilerAbort(cUnit);
748 genLong3Addr(cUnit, mir, firstOp, secondOp, rlDest, rlSrc1, rlSrc2);
751 dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
752 loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3);
753 loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1);
754 LOAD_FUNC_ADDR(cUnit, r14lr, (int) callTgt);
757 opRegRegReg(cUnit, kOpOr, tReg, r2, r3);
758 genRegImmCheck(cUnit, kArmCondEq, tReg, 0, mir->offset, NULL);
760 opReg(cUnit, kOpBlx, r14lr);
761 dvmCompilerClobberCallRegs(cUnit);
763 rlResult = dvmCompilerGetReturnWide(cUnit);
765 rlResult = dvmCompilerGetReturnWideAlt(cUnit);
766 storeValueWide(cUnit, rlDest, rlResult);
768 cUnit->usesLinkRegister = true;
774 static bool genArithOpInt(CompilationUnit *cUnit, MIR *mir,
853 dvmCompilerAbort(cUnit);
856 rlSrc1 = loadValue(cUnit, rlSrc1, kCoreReg);
858 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
859 opRegReg(cUnit, op, rlResult.lowReg,
862 rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
864 int tReg = dvmCompilerAllocTemp(cUnit);
865 opRegRegImm(cUnit, kOpAnd, tReg, rlSrc2.lowReg, 31);
866 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
867 opRegRegReg(cUnit, op, rlResult.lowReg,
869 dvmCompilerFreeTemp(cUnit, tReg);
871 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
872 opRegRegReg(cUnit, op, rlResult.lowReg,
876 storeValue(cUnit, rlDest, rlResult);
879 dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
880 loadValueDirectFixed(cUnit, rlSrc2, r1);
881 LOAD_FUNC_ADDR(cUnit, r2, (int) callTgt);
882 loadValueDirectFixed(cUnit, rlSrc1, r0);
884 genNullCheck(cUnit, rlSrc2.sRegLow, r1, mir->offset, NULL);
886 opReg(cUnit, kOpBlx, r2);
887 dvmCompilerClobberCallRegs(cUnit);
889 rlResult = dvmCompilerGetReturn(cUnit);
891 rlResult = dvmCompilerGetReturnAlt(cUnit);
892 storeValue(cUnit, rlDest, rlResult);
897 static bool genArithOp(CompilationUnit *cUnit, MIR *mir)
905 rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
906 rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
908 rlSrc1 = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
909 rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 2);
911 rlSrc1 = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
912 rlSrc2 = dvmCompilerGetSrcWide(cUnit, mir, 2, 3);
916 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
919 rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
923 return genArithOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2);
926 return genArithOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2);
929 return genShiftOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2);
932 return genShiftOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2);
935 return genArithOpInt(cUnit,mir, rlDest, rlSrc1, rlSrc2);
938 return genArithOpInt(cUnit,mir, rlDest, rlSrc1, rlSrc2);
941 return genArithOpFloat(cUnit,mir, rlDest, rlSrc1, rlSrc2);
944 return genArithOpFloat(cUnit, mir, rlDest, rlSrc1, rlSrc2);
947 return genArithOpDouble(cUnit,mir, rlDest, rlSrc1, rlSrc2);
950 return genArithOpDouble(cUnit,mir, rlDest, rlSrc1, rlSrc2);
956 static ArmLIR *genUnconditionalBranch(CompilationUnit *cUnit, ArmLIR *target)
958 ArmLIR *branch = opNone(cUnit, kOpUncondBr);
964 static void genReturnCommon(CompilationUnit *cUnit, MIR *mir)
966 genDispatchToHandler(cUnit, gDvmJit.methodTraceSupport ?
971 int dPC = (int) (cUnit->method->insns + mir->offset);
973 ArmLIR *branch = genUnconditionalBranch(cUnit, NULL);
980 dvmInsertGrowableList(&cUnit->pcReconstructionList, (intptr_t) pcrLabel);
985 static void genProcessArgsNoRange(CompilationUnit *cUnit, MIR *mir,
999 dvmCompilerLockAllTemps(cUnit);
1002 rlArg = dvmCompilerGetSrc(cUnit, mir, numDone++);
1003 loadValueDirectFixed(cUnit, rlArg, i);
1007 opRegRegImm(cUnit, kOpSub, r7, r5FP,
1011 *pcrLabel = genNullCheck(cUnit, dvmCompilerSSASrc(mir, 0), r0,
1014 storeMultiple(cUnit, r7, regMask);
1018 static void genProcessArgsRange(CompilationUnit *cUnit, MIR *mir,
1033 dvmCompilerLockAllTemps(cUnit);
1039 opRegRegImm(cUnit, kOpAdd, r4PC, r5FP, srcOffset);
1046 if (numArgs != 0) loadMultiple(cUnit, r4PC, regMask);
1048 opRegRegImm(cUnit, kOpSub, r7, r5FP,
1052 *pcrLabel = genNullCheck(cUnit, dvmCompilerSSASrc(mir, 0), r0,
1066 opImm(cUnit, kOpPush, (1 << r0 | 1 << r5FP));
1069 loadConstant(cUnit, 5, ((numArgs - 4) >> 2) << 2);
1070 loopLabel = newLIR0(cUnit, kArmPseudoTargetLabel);
1073 storeMultiple(cUnit, r7, regMask);
1078 loadMultiple(cUnit, r4PC, regMask);
1081 opRegImm(cUnit, kOpSub, r5FP, 4);
1082 genConditionalBranch(cUnit, kArmCondNe, loopLabel);
1087 if (numArgs != 0) storeMultiple(cUnit, r7, regMask);
1096 loadMultiple(cUnit, r4PC, regMask);
1099 opImm(cUnit, kOpPop, (1 << r0 | 1 << r5FP));
1103 storeMultiple(cUnit, r7, regMask);
1111 static void genInvokeSingletonCommon(CompilationUnit *cUnit, MIR *mir,
1121 dvmCompilerLockAllTemps(cUnit);
1125 ArmLIR *addrRetChain = opRegRegImm(cUnit, kOpAdd, r1, r15pc, 0);
1128 loadConstant(cUnit, r4PC,
1129 (int) (cUnit->method->insns + mir->offset));
1133 loadConstant(cUnit, r7, calleeMethod->registersSize);
1142 genDispatchToHandler(cUnit, gDvmJit.methodTraceSupport ?
1150 loadConstant(cUnit, r2, calleeMethod->outsSize);
1151 genDispatchToHandler(cUnit, gDvmJit.methodTraceSupport ?
1158 genUnconditionalBranch(cUnit, &labelList[bb->taken->id]);
1161 genTrap(cUnit, mir->offset, pcrLabel);
1184 static void genInvokeVirtualCommon(CompilationUnit *cUnit, MIR *mir,
1196 dvmCompilerLockAllTemps(cUnit);
1207 loadConstant(cUnit, r4PC,
1208 (int) (cUnit->method->insns + mir->offset));
1211 ArmLIR *addrRetChain = opRegRegImm(cUnit, kOpAdd, r1, r15pc, 0);
1215 ArmLIR *predictedChainingCell = opRegRegImm(cUnit, kOpAdd, r2, r15pc, 0);
1218 genDispatchToHandler(cUnit, gDvmJit.methodTraceSupport ?
1223 genUnconditionalBranch(cUnit, predChainingCell);
1230 int dPC = (int) (cUnit->method->insns + mir->offset);
1236 dvmInsertGrowableList(&cUnit->pcReconstructionList,
1241 genUnconditionalBranch(cUnit, pcrLabel);
1253 loadWordDisp(cUnit, r7, methodIndex * 4, r0);
1256 ArmLIR *bypassRechaining = genCmpImmBranch(cUnit, kArmCondGt, r1, 0);
1258 LOAD_FUNC_ADDR(cUnit, r7, (int) dvmJitToPatchPredictedChain);
1260 genRegCopy(cUnit, r1, r6SELF);
1271 opReg(cUnit, kOpBlx, r7);
1274 addrRetChain = opRegRegImm(cUnit, kOpAdd, r1, r15pc, 0);
1283 genDispatchToHandler(cUnit, gDvmJit.methodTraceSupport ?
1290 genTrap(cUnit, mir->offset, pcrLabel);
1294 static void genInvokeVirtualWholeMethod(CompilationUnit *cUnit,
1300 dvmCompilerLockAllTemps(cUnit);
1302 loadClassPointer(cUnit, r1, (int) callsiteInfo);
1304 loadWordDisp(cUnit, r0, offsetof(Object, clazz), r2);
1306 opRegReg(cUnit, kOpCmp, r1, r2);
1311 ArmLIR *classCheck = opCondBranch(cUnit, kArmCondNe);
1314 loadConstant(cUnit, r0, (int) (cUnit->method->insns + mir->offset));
1316 newLIR2(cUnit, kThumbBl1, (int) calleeAddr, (int) calleeAddr);
1317 newLIR2(cUnit, kThumbBl2, (int) calleeAddr, (int) calleeAddr);
1318 genUnconditionalBranch(cUnit, retChainingCell);
1321 ArmLIR *slowPathLabel = newLIR0(cUnit, kArmPseudoTargetLabel);
1327 cUnit->printMe = true;
1330 static void genInvokeSingletonWholeMethod(CompilationUnit *cUnit,
1336 loadConstant(cUnit, r0, (int) (cUnit->method->insns + mir->offset));
1338 newLIR2(cUnit, kThumbBl1, (int) calleeAddr, (int) calleeAddr);
1339 newLIR2(cUnit, kThumbBl2, (int) calleeAddr, (int) calleeAddr);
1340 genUnconditionalBranch(cUnit, retChainingCell);
1343 cUnit->printMe = true;
1347 static void genPuntToInterp(CompilationUnit *cUnit, unsigned int offset)
1350 dvmCompilerFlushAllRegs(cUnit);
1351 loadConstant(cUnit, r0, (int) (cUnit->method->insns + offset));
1352 loadWordDisp(cUnit, r6SELF, offsetof(Thread,
1354 opReg(cUnit, kOpBlx, r1);
1361 static void genInterpSingleStep(CompilationUnit *cUnit, MIR *mir)
1367 if (cUnit->jitMode == kJitLoop) {
1368 cUnit->quitLoopMode = true;
1377 dvmCompilerFlushAllRegs(cUnit);
1380 genPuntToInterp(cUnit, mir->offset);
1385 loadWordDisp(cUnit, r6SELF, entryAddr, r2);
1387 loadConstant(cUnit, r0, (int) (cUnit->method->insns + mir->offset));
1389 loadConstant(cUnit, r1, (int) (cUnit->method->insns + mir->next->offset));
1390 opReg(cUnit, kOpBlx, r2);
1405 static void genMonitorPortable(CompilationUnit *cUnit, MIR *mir)
1408 genExportPC(cUnit, mir);
1409 dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
1410 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
1411 loadValueDirectFixed(cUnit, rlSrc, r1);
1412 genRegCopy(cUnit, r0, r6SELF);
1413 genNullCheck(cUnit, rlSrc.sRegLow, r1, mir->offset, NULL);
1416 loadConstant(cUnit, r4PC, (int)(cUnit->method->insns + mir->offset +
1418 genDispatchToHandler(cUnit, TEMPLATE_MONITOR_ENTER);
1420 LOAD_FUNC_ADDR(cUnit, r2, (int)dvmUnlockObject);
1422 opReg(cUnit, kOpBlx, r2);
1424 ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
1425 loadConstant(cUnit, r0,
1426 (int) (cUnit->method->insns + mir->offset +
1428 genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
1429 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
1432 dvmCompilerClobberCallRegs(cUnit);
1441 static void genSuspendPoll(CompilationUnit *cUnit, MIR *mir)
1443 int rTemp = dvmCompilerAllocTemp(cUnit);
1445 ld = loadBaseDisp(cUnit, NULL, r6SELF,
1449 genRegImmCheck(cUnit, kArmCondNe, rTemp, 0, mir->offset, NULL);
1458 static bool handleFmt10t_Fmt20t_Fmt30t(CompilationUnit *cUnit, MIR *mir,
1465 (gDvmJit.genSuspendPoll || cUnit->jitMode == kJitLoop)) {
1466 genSuspendPoll(cUnit, mir);
1476 cUnit->nextCodegenBlock = bb->taken;
1479 genUnconditionalBranch(cUnit, &labelList[bb->taken->id]);
1484 static bool handleFmt10x(CompilationUnit *cUnit, MIR *mir)
1493 dvmCompilerGenMemBarrier(cUnit, kST);
1496 genReturnCommon(cUnit,mir);
1512 static bool handleFmt11n_Fmt31i(CompilationUnit *cUnit, MIR *mir)
1517 rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
1519 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1525 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
1526 loadConstantNoClobber(cUnit, rlResult.lowReg, mir->dalvikInsn.vB);
1527 storeValue(cUnit, rlDest, rlResult);
1533 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
1534 loadConstantNoClobber(cUnit, rlResult.lowReg, mir->dalvikInsn.vB);
1535 opRegRegImm(cUnit, kOpAsr, rlResult.highReg,
1537 storeValueWide(cUnit, rlDest, rlResult);
1546 static bool handleFmt21h(CompilationUnit *cUnit, MIR *mir)
1551 rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
1553 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1555 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
1559 loadConstantNoClobber(cUnit, rlResult.lowReg,
1561 storeValue(cUnit, rlDest, rlResult);
1565 loadConstantValueWide(cUnit, rlResult.lowReg, rlResult.highReg,
1567 storeValueWide(cUnit, rlDest, rlResult);
1576 static bool handleFmt20bc(CompilationUnit *cUnit, MIR *mir)
1579 genInterpSingleStep(cUnit, mir);
1583 static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir)
1593 (cUnit->method->clazz->pDvmDex->pResStrings[mir->dalvikInsn.vB]);
1601 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1602 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
1603 loadConstantNoClobber(cUnit, rlResult.lowReg, (int) strPtr );
1604 storeValue(cUnit, rlDest, rlResult);
1609 (cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vB]);
1617 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1618 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
1619 loadConstantNoClobber(cUnit, rlResult.lowReg, (int) classPtr );
1620 storeValue(cUnit, rlDest, rlResult);
1632 int tReg = dvmCompilerAllocTemp(cUnit);
1635 mir->meta.calleeMethod : cUnit->method;
1662 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1663 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
1664 loadConstant(cUnit, tReg, (int) fieldPtr + valOffset);
1667 dvmCompilerGenMemBarrier(cUnit, kSY);
1670 loadWordDisp(cUnit, tReg, 0, rlResult.lowReg);
1673 storeValue(cUnit, rlDest, rlResult);
1679 mir->meta.calleeMethod : cUnit->method;
1689 int tReg = dvmCompilerAllocTemp(cUnit);
1690 rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
1691 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
1692 loadConstant(cUnit, tReg, (int) fieldPtr + valOffset);
1695 loadPair(cUnit, tReg, rlResult.lowReg, rlResult.highReg);
1698 storeValueWide(cUnit, rlDest, rlResult);
1710 int tReg = dvmCompilerAllocTemp(cUnit);
1715 mir->meta.calleeMethod : cUnit->method;
1737 rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
1738 rlSrc = loadValue(cUnit, rlSrc, kAnyReg);
1739 loadConstant(cUnit, tReg, (int) fieldPtr);
1741 objHead = dvmCompilerAllocTemp(cUnit);
1742 loadWordDisp(cUnit, tReg, OFFSETOF_MEMBER(Field, clazz), objHead);
1745 dvmCompilerGenMemBarrier(cUnit, kST);
1748 storeWordDisp(cUnit, tReg, valOffset ,rlSrc.lowReg);
1749 dvmCompilerFreeTemp(cUnit, tReg);
1752 dvmCompilerGenMemBarrier(cUnit, kSY);
1756 markCard(cUnit, rlSrc.lowReg, objHead);
1757 dvmCompilerFreeTemp(cUnit, objHead);
1763 int tReg = dvmCompilerAllocTemp(cUnit);
1766 mir->meta.calleeMethod : cUnit->method;
1776 rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
1777 rlSrc = loadValueWide(cUnit, rlSrc, kAnyReg);
1778 loadConstant(cUnit, tReg, (int) fieldPtr + valOffset);
1781 storePair(cUnit, tReg, rlSrc.lowReg, rlSrc.highReg);
1791 (cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vB]);
1804 dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
1805 genExportPC(cUnit, mir);
1806 LOAD_FUNC_ADDR(cUnit, r2, (int)dvmAllocObject);
1807 loadConstant(cUnit, r0, (int) classPtr);
1808 loadConstant(cUnit, r1, ALLOC_DONT_TRACK);
1809 opReg(cUnit, kOpBlx, r2);
1810 dvmCompilerClobberCallRegs(cUnit);
1812 ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
1816 loadConstant(cUnit, r0,
1817 (int) (cUnit->method->insns + mir->offset));
1818 genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
1821 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
1824 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1825 rlResult = dvmCompilerGetReturn(cUnit);
1826 storeValue(cUnit, rlDest, rlResult);
1835 (cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vB]);
1847 genInterpSingleStep(cUnit, mir);
1850 dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
1851 loadConstant(cUnit, r1, (int) classPtr );
1852 rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
1853 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
1855 ArmLIR *branch1 = genCmpImmBranch(cUnit, kArmCondEq,
1864 loadWordDisp(cUnit, rlSrc.lowReg, offsetof(Object, clazz), r0);
1865 LOAD_FUNC_ADDR(cUnit, r2, (int)dvmInstanceofNonTrivial);
1866 opRegReg(cUnit, kOpCmp, r0, r1);
1867 ArmLIR *branch2 = opCondBranch(cUnit, kArmCondEq);
1868 opReg(cUnit, kOpBlx, r2);
1869 dvmCompilerClobberCallRegs(cUnit);
1875 genZeroCheck(cUnit, r0, mir->offset, NULL);
1877 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
1885 genInterpSingleStep(cUnit, mir);
1908 static bool handleFmt11x(CompilationUnit *cUnit, MIR *mir)
1915 int resetReg = dvmCompilerAllocTemp(cUnit);
1916 RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1917 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
1918 loadWordDisp(cUnit, r6SELF, exOffset, rlResult.lowReg);
1919 loadConstant(cUnit, resetReg, 0);
1920 storeWordDisp(cUnit, r6SELF, exOffset, resetReg);
1921 storeValue(cUnit, rlDest, rlResult);
1929 RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1932 storeValue(cUnit, rlDest, rlSrc);
1939 RegLocation rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
1942 storeValueWide(cUnit, rlDest, rlSrc);
1946 RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
1949 storeValueWide(cUnit, rlDest, rlSrc);
1950 genReturnCommon(cUnit,mir);
1955 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
1958 storeValue(cUnit, rlDest, rlSrc);
1959 genReturnCommon(cUnit, mir);
1964 genMonitor(cUnit, mir);
1967 genInterpSingleStep(cUnit, mir);
1975 static bool handleFmt12x(CompilationUnit *cUnit, MIR *mir)
1983 return genArithOp( cUnit, mir );
1987 rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
1989 rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
1991 rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
1993 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
2006 return genConversion(cUnit, mir);
2009 return genArithOpInt(cUnit, mir, rlDest, rlSrc, rlSrc);
2012 return genArithOpLong(cUnit, mir, rlDest, rlSrc, rlSrc);
2014 return genArithOpFloat(cUnit, mir, rlDest, rlSrc, rlSrc);
2016 return genArithOpDouble(cUnit, mir, rlDest, rlSrc, rlSrc);
2018 storeValueWide(cUnit, rlDest, rlSrc);
2021 rlSrc = dvmCompilerUpdateLoc(cUnit, rlSrc);
2022 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2025 genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
2027 loadValueDirect(cUnit, rlSrc, rlResult.lowReg);
2029 opRegRegImm(cUnit, kOpAsr, rlResult.highReg,
2031 storeValueWide(cUnit, rlDest, rlResult);
2034 rlSrc = dvmCompilerUpdateLocWide(cUnit, rlSrc);
2035 rlSrc = dvmCompilerWideToNarrow(cUnit, rlSrc);
2039 storeValue(cUnit, rlDest, rlSrc);
2042 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2043 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2044 opRegReg(cUnit, kOp2Byte, rlResult.lowReg, rlSrc.lowReg);
2045 storeValue(cUnit, rlDest, rlResult);
2048 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2049 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2050 opRegReg(cUnit, kOp2Short, rlResult.lowReg, rlSrc.lowReg);
2051 storeValue(cUnit, rlDest, rlResult);
2054 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2055 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2056 opRegReg(cUnit, kOp2Char, rlResult.lowReg, rlSrc.lowReg);
2057 storeValue(cUnit, rlDest, rlResult);
2061 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2062 genNullCheck(cUnit, rlSrc.sRegLow, rlSrc.lowReg,
2064 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2065 loadWordDisp(cUnit, rlSrc.lowReg, lenOffset,
2067 storeValue(cUnit, rlDest, rlResult);
2076 static bool handleFmt21s(CompilationUnit *cUnit, MIR *mir)
2083 rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
2084 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2085 loadConstantNoClobber(cUnit, rlResult.lowReg, BBBB);
2087 opRegRegImm(cUnit, kOpAsr, rlResult.highReg, rlResult.lowReg, 31);
2088 storeValueWide(cUnit, rlDest, rlResult);
2090 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
2091 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
2092 loadConstantNoClobber(cUnit, rlResult.lowReg, BBBB);
2093 storeValue(cUnit, rlDest, rlResult);
2100 static bool handleFmt21t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
2109 (gDvmJit.genSuspendPoll || cUnit->jitMode == kJitLoop)) {
2110 genSuspendPoll(cUnit, mir);
2113 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
2114 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2138 dvmCompilerAbort(cUnit);
2140 ArmLIR* branch = genCmpImmBranch(cUnit, cond, rlSrc.lowReg, 0);
2143 genUnconditionalBranch(cUnit, &labelList[bb->fallThrough->id]);
2173 // Returns true if it added instructions to 'cUnit' to divide 'rlSrc' by 'lit'
2175 static bool handleEasyDivide(CompilationUnit *cUnit, Opcode dalvikOpcode,
2187 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2188 RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2190 int tReg = dvmCompilerAllocTemp(cUnit);
2193 opRegRegImm(cUnit, kOpLsr, tReg, rlSrc.lowReg, 32 - k);
2194 opRegRegReg(cUnit, kOpAdd, tReg, tReg, rlSrc.lowReg);
2195 opRegRegImm(cUnit, kOpAsr, rlResult.lowReg, tReg, k);
2197 opRegRegImm(cUnit, kOpAsr, tReg, rlSrc.lowReg, 31);
2198 opRegRegImm(cUnit, kOpLsr, tReg, tReg, 32 - k);
2199 opRegRegReg(cUnit, kOpAdd, tReg, tReg, rlSrc.lowReg);
2200 opRegRegImm(cUnit, kOpAsr, rlResult.lowReg, tReg, k);
2203 int cReg = dvmCompilerAllocTemp(cUnit);
2204 loadConstant(cUnit, cReg, lit - 1);
2205 int tReg1 = dvmCompilerAllocTemp(cUnit);
2206 int tReg2 = dvmCompilerAllocTemp(cUnit);
2208 opRegRegImm(cUnit, kOpLsr, tReg1, rlSrc.lowReg, 32 - k);
2209 opRegRegReg(cUnit, kOpAdd, tReg2, tReg1, rlSrc.lowReg);
2210 opRegRegReg(cUnit, kOpAnd, tReg2, tReg2, cReg);
2211 opRegRegReg(cUnit, kOpSub, rlResult.lowReg, tReg2, tReg1);
2213 opRegRegImm(cUnit, kOpAsr, tReg1, rlSrc.lowReg, 31);
2214 opRegRegImm(cUnit, kOpLsr, tReg1, tReg1, 32 - k);
2215 opRegRegReg(cUnit, kOpAdd, tReg2, tReg1, rlSrc.lowReg);
2216 opRegRegReg(cUnit, kOpAnd, tReg2, tReg2, cReg);
2217 opRegRegReg(cUnit, kOpSub, rlResult.lowReg, tReg2, tReg1);
2220 storeValue(cUnit, rlDest, rlResult);
2224 // Returns true if it added instructions to 'cUnit' to multiply 'rlSrc' by 'lit'
2226 static bool handleEasyMultiply(CompilationUnit *cUnit,
2245 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2246 RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2249 opRegRegImm(cUnit, kOpLsl, rlResult.lowReg, rlSrc.lowReg,
2255 genMultiplyByTwoBitMultiplier(cUnit, rlSrc, rlResult, lit,
2260 genMultiplyByShiftAndReverseSubtract(cUnit, rlSrc, rlResult, lowestSetBit(lit + 1));
2262 storeValue(cUnit, rlDest, rlResult);
2266 static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir)
2269 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
2270 RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
2282 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2283 tReg = dvmCompilerAllocTemp(cUnit);
2284 loadConstant(cUnit, tReg, lit);
2285 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2286 opRegRegReg(cUnit, kOpSub, rlResult.lowReg,
2288 storeValue(cUnit, rlDest, rlResult);
2299 if (handleEasyMultiply(cUnit, rlSrc, rlDest, lit)) {
2339 genInterpSingleStep(cUnit, mir);
2342 if (handleEasyDivide(cUnit, dalvikOpcode, rlSrc, rlDest, lit)) {
2345 dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
2346 loadValueDirectFixed(cUnit, rlSrc, r0);
2347 dvmCompilerClobber(cUnit, r0);
2350 LOAD_FUNC_ADDR(cUnit, r2, (int)__aeabi_idiv);
2353 LOAD_FUNC_ADDR(cUnit, r2, (int)__aeabi_idivmod);
2356 loadConstant(cUnit, r1, lit);
2357 opReg(cUnit, kOpBlx, r2);
2358 dvmCompilerClobberCallRegs(cUnit);
2360 rlResult = dvmCompilerGetReturn(cUnit);
2362 rlResult = dvmCompilerGetReturnAlt(cUnit);
2363 storeValue(cUnit, rlDest, rlResult);
2369 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2370 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2373 genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
2375 opRegRegImm(cUnit, op, rlResult.lowReg, rlSrc.lowReg, lit);
2377 storeValue(cUnit, rlDest, rlResult);
2381 static bool handleFmt22c(CompilationUnit *cUnit, MIR *mir)
2416 mir->meta.calleeMethod : cUnit->method;
2441 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
2442 RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
2445 (cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vC]);
2453 dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
2454 genExportPC(cUnit, mir);
2455 loadValueDirectFixed(cUnit, rlSrc, r1); /* Len */
2456 loadConstant(cUnit, r0, (int) classPtr );
2457 LOAD_FUNC_ADDR(cUnit, r3, (int)dvmAllocArrayByClass);
2462 genRegImmCheck(cUnit, kArmCondMi, r1, 0, mir->offset, NULL);
2463 loadConstant(cUnit, r2, ALLOC_DONT_TRACK);
2464 opReg(cUnit, kOpBlx, r3);
2465 dvmCompilerClobberCallRegs(cUnit);
2467 ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
2471 loadConstant(cUnit, r0,
2472 (int) (cUnit->method->insns + mir->offset));
2473 genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
2476 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
2479 rlResult = dvmCompilerGetReturn(cUnit);
2480 storeValue(cUnit, rlDest, rlResult);
2485 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
2486 RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
2489 (cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vC]);
2501 genInterpSingleStep(cUnit, mir);
2504 dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
2505 loadValueDirectFixed(cUnit, rlSrc, r0); /* Ref */
2506 loadConstant(cUnit, r2, (int) classPtr );
2508 ArmLIR *branch1 = genCmpImmBranch(cUnit, kArmCondEq, r0, 0);
2510 loadWordDisp(cUnit, r0, offsetof(Object, clazz), r1);
2512 LOAD_FUNC_ADDR(cUnit, r3, (int)dvmInstanceofNonTrivial);
2513 loadConstant(cUnit, r0, 1); /* Assume true */
2514 opRegReg(cUnit, kOpCmp, r1, r2);
2515 ArmLIR *branch2 = opCondBranch(cUnit, kArmCondEq);
2516 genRegCopy(cUnit, r0, r1);
2517 genRegCopy(cUnit, r1, r2);
2518 opReg(cUnit, kOpBlx, r3);
2519 dvmCompilerClobberCallRegs(cUnit);
2521 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
2523 rlResult = dvmCompilerGetReturn(cUnit);
2524 storeValue(cUnit, rlDest, rlResult);
2530 genIGetWide(cUnit, mir, fieldOffset);
2540 genIGet(cUnit, mir, kWord, fieldOffset, isVolatile);
2543 genIPutWide(cUnit, mir, fieldOffset);
2551 genIPut(cUnit, mir, kWord, fieldOffset, false, isVolatile);
2555 genIPut(cUnit, mir, kWord, fieldOffset, true, isVolatile);
2559 genInterpSingleStep(cUnit, mir);
2567 static bool handleFmt22cs(CompilationUnit *cUnit, MIR *mir)
2574 genIGet(cUnit, mir, kWord, fieldOffset, false);
2577 genIPut(cUnit, mir, kWord, fieldOffset, false, false);
2580 genIPut(cUnit, mir, kWord, fieldOffset, true, false);
2583 genIGetWide(cUnit, mir, fieldOffset);
2586 genIPutWide(cUnit, mir, fieldOffset);
2596 static bool handleFmt22t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
2605 (gDvmJit.genSuspendPoll || cUnit->jitMode == kJitLoop)) {
2606 genSuspendPoll(cUnit, mir);
2609 RegLocation rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
2610 RegLocation rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
2612 rlSrc1 = loadValue(cUnit, rlSrc1, kCoreReg);
2613 rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
2615 opRegReg(cUnit, kOpCmp, rlSrc1.lowReg, rlSrc2.lowReg);
2639 dvmCompilerAbort(cUnit);
2641 genConditionalBranch(cUnit, cond, &labelList[bb->taken->id]);
2643 genUnconditionalBranch(cUnit, &labelList[bb->fallThrough->id]);
2647 static bool handleFmt22x_Fmt32x(CompilationUnit *cUnit, MIR *mir)
2656 storeValue(cUnit, dvmCompilerGetDest(cUnit, mir, 0),
2657 dvmCompilerGetSrc(cUnit, mir, 0));
2662 storeValueWide(cUnit, dvmCompilerGetDestWide(cUnit, mir, 0, 1),
2663 dvmCompilerGetSrcWide(cUnit, mir, 0, 1));
2672 static bool handleFmt23x(CompilationUnit *cUnit, MIR *mir)
2680 return genArithOp( cUnit, mir );
2686 rlDest = dvmCompilerGetSrc(cUnit, mir, 0);
2687 rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 1);
2688 rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 2);
2691 rlDest = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
2692 rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 2);
2693 rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 3);
2698 rlSrc1 = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
2699 rlSrc2 = dvmCompilerGetSrcWide(cUnit, mir, 2, 3);
2702 rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
2703 rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
2706 rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
2709 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
2719 return genCmpFP(cUnit, mir, rlDest, rlSrc1, rlSrc2);
2721 genCmpLong(cUnit, mir, rlDest, rlSrc1, rlSrc2);
2724 genArrayGet(cUnit, mir, kLong, rlSrc1, rlSrc2, rlDest, 3);
2728 genArrayGet(cUnit, mir, kWord, rlSrc1, rlSrc2, rlDest, 2);
2731 genArrayGet(cUnit, mir, kUnsignedByte, rlSrc1, rlSrc2, rlDest, 0);
2734 genArrayGet(cUnit, mir, kSignedByte, rlSrc1, rlSrc2, rlDest, 0);
2737 genArrayGet(cUnit, mir, kUnsignedHalf, rlSrc1, rlSrc2, rlDest, 1);
2740 genArrayGet(cUnit, mir, kSignedHalf, rlSrc1, rlSrc2, rlDest, 1);
2743 genArrayPut(cUnit, mir, kLong, rlSrc1, rlSrc2, rlDest, 3);
2746 genArrayPut(cUnit, mir, kWord, rlSrc1, rlSrc2, rlDest, 2);
2749 genArrayObjectPut(cUnit, mir, rlSrc1, rlSrc2, rlDest, 2);
2753 genArrayPut(cUnit, mir, kUnsignedHalf, rlSrc1, rlSrc2, rlDest, 1);
2757 genArrayPut(cUnit, mir, kUnsignedByte, rlSrc1, rlSrc2, rlDest, 0);
2895 static bool handleFmt31t(CompilationUnit *cUnit, MIR *mir)
2900 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
2902 dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
2903 genExportPC(cUnit, mir);
2904 loadValueDirectFixed(cUnit, rlSrc, r0);
2905 LOAD_FUNC_ADDR(cUnit, r2, (int)dvmInterpHandleFillArrayData);
2906 loadConstant(cUnit, r1,
2907 (int) (cUnit->method->insns + mir->offset + mir->dalvikInsn.vB));
2908 opReg(cUnit, kOpBlx, r2);
2909 dvmCompilerClobberCallRegs(cUnit);
2911 ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
2912 loadConstant(cUnit, r0,
2913 (int) (cUnit->method->insns + mir->offset));
2914 genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
2915 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
2927 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
2928 dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
2929 loadValueDirectFixed(cUnit, rlSrc, r1);
2930 dvmCompilerLockAllTemps(cUnit);
2932 LOAD_FUNC_ADDR(cUnit, r4PC, (int)findPackedSwitchIndex);
2934 LOAD_FUNC_ADDR(cUnit, r4PC, (int)findSparseSwitchIndex);
2937 loadConstant(cUnit, r0,
2938 (int) (cUnit->method->insns + mir->offset + mir->dalvikInsn.vB));
2940 opRegReg(cUnit, kOpMov, r2, r15pc);
2941 opReg(cUnit, kOpBlx, r4PC);
2942 dvmCompilerClobberCallRegs(cUnit);
2944 opRegReg(cUnit, kOpMov, r15pc, r0);
2958 static void genLandingPadForMispredictedCallee(CompilationUnit *cUnit, MIR *mir,
2970 genUnconditionalBranch(cUnit, &labelList[fallThrough->id]);
2973 dvmCompilerResetRegPool(cUnit);
2974 dvmCompilerClobberAllRegs(cUnit);
2975 dvmCompilerResetNullCheck(cUnit);
2978 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
2984 static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir,
3008 cUnit->method->clazz->pDvmDex->pResMethods[dInsn->vB]->
3017 genLandingPadForMispredictedCallee(cUnit, mir, bb, labelList);
3021 genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
3023 genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
3025 genInvokeVirtualCommon(cUnit, mir, methodIndex,
3039 assert(calleeMethod == cUnit->method->clazz->super->vtable[
3040 cUnit->method->clazz->pDvmDex->
3044 genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
3046 genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
3052 genInvokeSingletonWholeMethod(cUnit, mir, calleeAddr,
3056 loadConstant(cUnit, r0, (int) calleeMethod);
3058 genInvokeSingletonCommon(cUnit, mir, bb, labelList, pcrLabel,
3069 cUnit->method->clazz->pDvmDex->pResMethods[dInsn->vB]);
3072 genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
3074 genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
3077 loadConstant(cUnit, r0, (int) calleeMethod);
3079 genInvokeSingletonCommon(cUnit, mir, bb, labelList, pcrLabel,
3089 cUnit->method->clazz->pDvmDex->pResMethods[dInsn->vB]);
3092 genProcessArgsNoRange(cUnit, mir, dInsn,
3095 genProcessArgsRange(cUnit, mir, dInsn,
3102 genInvokeSingletonWholeMethod(cUnit, mir, calleeAddr,
3106 loadConstant(cUnit, r0, (int) calleeMethod);
3108 genInvokeSingletonCommon(cUnit, mir, bb, labelList, pcrLabel,
3194 genLandingPadForMispredictedCallee(cUnit, mir, bb, labelList);
3198 genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
3200 genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
3205 loadConstant(cUnit, r4PC,
3206 (int) (cUnit->method->insns + mir->offset));
3210 opRegRegImm(cUnit, kOpAdd, r1, r15pc, 0);
3215 opRegRegImm(cUnit, kOpAdd, r2, r15pc, 0);
3218 genDispatchToHandler(cUnit, gDvmJit.methodTraceSupport ?
3223 genUnconditionalBranch(cUnit, predChainingCell);
3230 int dPC = (int) (cUnit->method->insns + mir->offset);
3236 dvmInsertGrowableList(&cUnit->pcReconstructionList,
3241 genUnconditionalBranch(cUnit, pcrLabel);
3253 genRegCopy(cUnit, r8, r1);
3254 genRegCopy(cUnit, r9, r2);
3255 genRegCopy(cUnit, r10, r3);
3258 genRegCopy(cUnit, r0, r3);
3261 loadConstant(cUnit, r1, dInsn->vB);
3264 loadConstant(cUnit, r2, (int) cUnit->method);
3267 loadConstant(cUnit, r3, (int) cUnit->method->clazz->pDvmDex);
3269 LOAD_FUNC_ADDR(cUnit, r7,
3271 opReg(cUnit, kOpBlx, r7);
3274 dvmCompilerClobberCallRegs(cUnit);
3276 ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
3280 loadConstant(cUnit, r0,
3281 (int) (cUnit->method->insns + mir->offset));
3282 genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
3285 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
3289 genRegCopy(cUnit, r1, r8);
3292 ArmLIR *bypassRechaining = genCmpImmBranch(cUnit, kArmCondGt,
3295 LOAD_FUNC_ADDR(cUnit, r7, (int) dvmJitToPatchPredictedChain);
3297 genRegCopy(cUnit, r1, r6SELF);
3298 genRegCopy(cUnit, r2, r9);
3299 genRegCopy(cUnit, r3, r10);
3310 opReg(cUnit, kOpBlx, r7);
3313 addrRetChain = opRegRegImm(cUnit, kOpAdd, r1, r15pc, 0);
3323 genDispatchToHandler(cUnit, gDvmJit.methodTraceSupport ?
3330 genTrap(cUnit, mir->offset, pcrLabel);
3337 genInterpSingleStep(cUnit, mir);
3346 static bool handleFmt35ms_3rms(CompilationUnit *cUnit, MIR *mir,
3370 genLandingPadForMispredictedCallee(cUnit, mir, bb, labelList);
3374 genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
3376 genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
3383 genInvokeVirtualWholeMethod(cUnit, mir, calleeAddr,
3387 genInvokeVirtualCommon(cUnit, mir, methodIndex,
3399 cUnit->method->clazz->super->vtable[dInsn->vB]);
3402 genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
3404 genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
3407 loadConstant(cUnit, r0, (int) calleeMethod);
3409 genInvokeSingletonCommon(cUnit, mir, bb, labelList, pcrLabel,
3425 static bool genInlinedCompareTo(CompilationUnit *cUnit, MIR *mir)
3428 return handleExecuteInlineC(cUnit, mir);
3431 RegLocation rlThis = dvmCompilerGetSrc(cUnit, mir, 0);
3432 RegLocation rlComp = dvmCompilerGetSrc(cUnit, mir, 1);
3434 loadValueDirectFixed(cUnit, rlThis, r0);
3435 loadValueDirectFixed(cUnit, rlComp, r1);
3437 rollback = genNullCheck(cUnit, rlThis.sRegLow, r0, mir->offset, NULL);
3438 genNullCheck(cUnit, rlComp.sRegLow, r1, mir->offset, rollback);
3444 genDispatchToHandler(cUnit, TEMPLATE_STRING_COMPARETO);
3445 storeValue(cUnit, inlinedTarget(cUnit, mir, false),
3446 dvmCompilerGetReturn(cUnit));
3451 static bool genInlinedFastIndexOf(CompilationUnit *cUnit, MIR *mir)
3454 return handleExecuteInlineC(cUnit, mir);
3456 RegLocation rlThis = dvmCompilerGetSrc(cUnit, mir, 0);
3457 RegLocation rlChar = dvmCompilerGetSrc(cUnit, mir, 1);
3459 loadValueDirectFixed(cUnit, rlThis, r0);
3460 loadValueDirectFixed(cUnit, rlChar, r1);
3461 RegLocation rlStart = dvmCompilerGetSrc(cUnit, mir, 2);
3462 loadValueDirectFixed(cUnit, rlStart, r2);
3464 genNullCheck(cUnit, rlThis.sRegLow, r0, mir->offset, NULL);
3465 genDispatchToHandler(cUnit, TEMPLATE_STRING_INDEXOF);
3466 storeValue(cUnit, inlinedTarget(cUnit, mir, false),
3467 dvmCompilerGetReturn(cUnit));
3473 static bool genInlinedStringIsEmptyOrLength(CompilationUnit *cUnit, MIR *mir,
3477 RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
3478 RegLocation rlDest = inlinedTarget(cUnit, mir, false);
3479 rlObj = loadValue(cUnit, rlObj, kCoreReg);
3480 RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
3481 genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset, NULL);
3482 loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_count,
3486 int tReg = dvmCompilerAllocTemp(cUnit);
3487 opRegReg(cUnit, kOpNeg, tReg, rlResult.lowReg);
3488 opRegRegReg(cUnit, kOpAdc, rlResult.lowReg, rlResult.lowReg, tReg);
3490 storeValue(cUnit, rlDest, rlResult);
3494 static bool genInlinedStringLength(CompilationUnit *cUnit, MIR *mir)
3496 return genInlinedStringIsEmptyOrLength(cUnit, mir, false);
3499 static bool genInlinedStringIsEmpty(CompilationUnit *cUnit, MIR *mir)
3501 return genInlinedStringIsEmptyOrLength(cUnit, mir, true);
3504 static bool genInlinedStringCharAt(CompilationUnit *cUnit, MIR *mir)
3507 RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
3508 RegLocation rlIdx = dvmCompilerGetSrc(cUnit, mir, 1);
3509 RegLocation rlDest = inlinedTarget(cUnit, mir, false);
3511 rlObj = loadValue(cUnit, rlObj, kCoreReg);
3512 rlIdx = loadValue(cUnit, rlIdx, kCoreReg);
3513 int regMax = dvmCompilerAllocTemp(cUnit);
3514 int regOff = dvmCompilerAllocTemp(cUnit);
3515 int regPtr = dvmCompilerAllocTemp(cUnit);
3516 ArmLIR *pcrLabel = genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg,
3518 loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_count, regMax);
3519 loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_offset, regOff);
3520 loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_value, regPtr);
3521 genBoundsCheck(cUnit, rlIdx.lowReg, regMax, mir->offset, pcrLabel);
3522 dvmCompilerFreeTemp(cUnit, regMax);
3523 opRegImm(cUnit, kOpAdd, regPtr, contents);
3524 opRegReg(cUnit, kOpAdd, regOff, rlIdx.lowReg);
3525 rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
3526 loadBaseIndexed(cUnit, regPtr, regOff, rlResult.lowReg, 1, kUnsignedHalf);
3527 storeValue(cUnit, rlDest, rlResult);
3531 static bool genInlinedAbsInt(CompilationUnit *cUnit, MIR *mir)
3533 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
3534 rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
3535 RegLocation rlDest = inlinedTarget(cUnit, mir, false);
3536 RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
3537 int signReg = dvmCompilerAllocTemp(cUnit);
3543 opRegRegImm(cUnit, kOpAsr, signReg, rlSrc.lowReg, 31);
3544 opRegRegReg(cUnit, kOpAdd, rlResult.lowReg, rlSrc.lowReg, signReg);
3545 opRegReg(cUnit, kOpXor, rlResult.lowReg, signReg);
3546 storeValue(cUnit, rlDest, rlResult);
3550 static bool genInlinedAbsLong(CompilationUnit *cUnit, MIR *mir)
3552 RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
3553 RegLocation rlDest = inlinedTargetWide(cUnit, mir, false);
3554 rlSrc = loadValueWide(cUnit, rlSrc, kCoreReg);
3555 RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
3556 int signReg = dvmCompilerAllocTemp(cUnit);
3563 opRegRegImm(cUnit, kOpAsr, signReg, rlSrc.highReg, 31);
3564 opRegRegReg(cUnit, kOpAdd, rlResult.lowReg, rlSrc.lowReg, signReg);
3565 opRegRegReg(cUnit, kOpAdc, rlResult.highReg, rlSrc.highReg, signReg);
3566 opRegReg(cUnit, kOpXor, rlResult.lowReg, signReg);
3567 opRegReg(cUnit, kOpXor, rlResult.highReg, signReg);
3568 storeValueWide(cUnit, rlDest, rlResult);
3572 static bool genInlinedIntFloatConversion(CompilationUnit *cUnit, MIR *mir)
3575 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
3576 RegLocation rlDest = inlinedTarget(cUnit, mir, false);
3577 storeValue(cUnit, rlDest, rlSrc);
3581 static bool genInlinedLongDoubleConversion(CompilationUnit *cUnit, MIR *mir)
3584 RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
3585 RegLocation rlDest = inlinedTargetWide(cUnit, mir, false);
3586 storeValueWide(cUnit, rlDest, rlSrc);
3595 static bool handleExecuteInlineC(CompilationUnit *cUnit, MIR *mir)
3603 dvmCompilerAbort(cUnit);
3605 dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
3606 dvmCompilerClobberCallRegs(cUnit);
3607 dvmCompilerClobber(cUnit, r4PC);
3608 dvmCompilerClobber(cUnit, r7);
3610 opRegRegImm(cUnit, kOpAdd, r4PC, r6SELF, offset);
3611 opImm(cUnit, kOpPush, (1<<r4PC) | (1<<r7));
3612 LOAD_FUNC_ADDR(cUnit, r4PC, fn);
3613 genExportPC(cUnit, mir);
3615 loadValueDirect(cUnit, dvmCompilerGetSrc(cUnit, mir, i), i);
3617 opReg(cUnit, kOpBlx, r4PC);
3618 opRegImm(cUnit, kOpAdd, r13sp, 8);
3620 ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondNe, r0, 0);
3621 loadConstant(cUnit, r0, (int) (cUnit->method->insns + mir->offset));
3622 genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
3623 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
3633 static bool handleExecuteInline(CompilationUnit *cUnit, MIR *mir)
3645 return genInlinedStringCharAt(cUnit, mir);
3647 return genInlinedStringLength(cUnit, mir);
3649 return genInlinedStringIsEmpty(cUnit, mir);
3651 return genInlinedCompareTo(cUnit, mir);
3653 return genInlinedFastIndexOf(cUnit, mir);
3657 return genInlinedAbsInt(cUnit, mir);
3660 return genInlinedAbsLong(cUnit, mir);
3663 return genInlinedMinMaxInt(cUnit, mir, true);
3666 return genInlinedMinMaxInt(cUnit, mir, false);
3669 return genInlineSqrt(cUnit, mir);
3672 return genInlinedAbsFloat(cUnit, mir);
3675 return genInlinedAbsDouble(cUnit, mir);
3679 return genInlinedIntFloatConversion(cUnit, mir);
3682 return genInlinedLongDoubleConversion(cUnit, mir);
3693 return handleExecuteInlineC(cUnit, mir);
3695 dvmCompilerAbort(cUnit);
3699 static bool handleFmt51l(CompilationUnit *cUnit, MIR *mir)
3702 RegLocation rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
3703 RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
3704 loadConstantNoClobber(cUnit, rlResult.lowReg,
3706 loadConstantNoClobber(cUnit, rlResult.highReg,
3708 storeValueWide(cUnit, rlDest, rlResult);
3730 static void insertChainingSwitch(CompilationUnit *cUnit)
3732 ArmLIR *branch = newLIR0(cUnit, kThumbBUncond);
3733 newLIR2(cUnit, kThumbOrr, r0, r0);
3734 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
3740 static void handleNormalChainingCell(CompilationUnit *cUnit,
3747 insertChainingSwitch(cUnit);
3748 newLIR3(cUnit, kThumbLdrRRI5, r0, r6SELF,
3751 newLIR1(cUnit, kThumbBlxR, r0);
3752 addWordData(cUnit, NULL, (int) (cUnit->method->insns + offset));
3759 static void handleHotChainingCell(CompilationUnit *cUnit,
3766 insertChainingSwitch(cUnit);
3767 newLIR3(cUnit, kThumbLdrRRI5, r0, r6SELF,
3770 newLIR1(cUnit, kThumbBlxR, r0);
3771 addWordData(cUnit, NULL, (int) (cUnit->method->insns + offset));
3775 static void handleBackwardBranchChainingCell(CompilationUnit *cUnit,
3782 insertChainingSwitch(cUnit);
3784 newLIR3(cUnit, kThumbLdrRRI5, r0, r6SELF,
3788 newLIR3(cUnit, kThumbLdrRRI5, r0, r6SELF,
3791 newLIR1(cUnit, kThumbBlxR, r0);
3792 addWordData(cUnit, NULL, (int) (cUnit->method->insns + offset));
3796 static void handleInvokeSingletonChainingCell(CompilationUnit *cUnit,
3803 insertChainingSwitch(cUnit);
3804 newLIR3(cUnit, kThumbLdrRRI5, r0, r6SELF,
3807 newLIR1(cUnit, kThumbBlxR, r0);
3808 addWordData(cUnit, NULL, (int) (callee->insns));
3812 static void handleInvokePredictedChainingCell(CompilationUnit *cUnit)
3816 addWordData(cUnit, NULL, PREDICTED_CHAIN_BX_PAIR_INIT);
3818 addWordData(cUnit, NULL, PREDICTED_CHAIN_CLAZZ_INIT);
3820 addWordData(cUnit, NULL, PREDICTED_CHAIN_METHOD_INIT);
3825 addWordData(cUnit, NULL, PREDICTED_CHAIN_COUNTER_INIT);
3829 static void handlePCReconstruction(CompilationUnit *cUnit,
3833 (ArmLIR **) cUnit->pcReconstructionList.elemList;
3834 int numElems = cUnit->pcReconstructionList.numUsed;
3842 newLIR0(cUnit, kThumbUndefined);
3846 dvmCompilerAppendLIR(cUnit, (LIR *) pcrLabel[i]);
3848 loadConstant(cUnit, r0, pcrLabel[i]->operands[0]);
3849 genUnconditionalBranch(cUnit, targetLabel);
3870 static void genHoistedChecksForCountUpLoop(CompilationUnit *cUnit, MIR *mir)
3882 RegLocation rlArray = cUnit->regLocation[mir->dalvikInsn.vA];
3883 RegLocation rlIdxEnd = cUnit->regLocation[mir->dalvikInsn.vC];
3886 rlArray = loadValue(cUnit, rlArray, kCoreReg);
3887 rlIdxEnd = loadValue(cUnit, rlIdxEnd, kCoreReg);
3888 genRegImmCheck(cUnit, kArmCondEq, rlArray.lowReg, 0, 0,
3889 (ArmLIR *) cUnit->loopAnalysis->branchToPCR);
3892 regLength = dvmCompilerAllocTemp(cUnit);
3893 loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLength);
3905 int tReg = dvmCompilerAllocTemp(cUnit);
3906 opRegRegImm(cUnit, kOpAdd, tReg, rlIdxEnd.lowReg, delta);
3908 dvmCompilerFreeTemp(cUnit, tReg);
3911 genRegRegCheck(cUnit, kArmCondGe, rlIdxEnd.lowReg, regLength, 0,
3912 (ArmLIR *) cUnit->loopAnalysis->branchToPCR);
3923 static void genHoistedChecksForCountDownLoop(CompilationUnit *cUnit, MIR *mir)
3927 const int regLength = dvmCompilerAllocTemp(cUnit);
3929 RegLocation rlArray = cUnit->regLocation[mir->dalvikInsn.vA];
3930 RegLocation rlIdxInit = cUnit->regLocation[mir->dalvikInsn.vB];
3933 rlArray = loadValue(cUnit, rlArray, kCoreReg);
3934 rlIdxInit = loadValue(cUnit, rlIdxInit, kCoreReg);
3935 genRegImmCheck(cUnit, kArmCondEq, rlArray.lowReg, 0, 0,
3936 (ArmLIR *) cUnit->loopAnalysis->branchToPCR);
3939 loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLength);
3942 int tReg = dvmCompilerAllocTemp(cUnit);
3943 opRegRegImm(cUnit, kOpAdd, tReg, rlIdxInit.lowReg, maxC);
3945 dvmCompilerFreeTemp(cUnit, tReg);
3949 genRegRegCheck(cUnit, kArmCondGe, rlIdxInit.lowReg, regLength, 0,
3950 (ArmLIR *) cUnit->loopAnalysis->branchToPCR);
3957 static void genHoistedLowerBoundCheck(CompilationUnit *cUnit, MIR *mir)
3961 RegLocation rlIdx = cUnit->regLocation[mir->dalvikInsn.vA];
3964 rlIdx = loadValue(cUnit, rlIdx, kCoreReg);
3967 genRegImmCheck(cUnit, kArmCondLt, rlIdx.lowReg, -minC, 0,
3968 (ArmLIR *) cUnit->loopAnalysis->branchToPCR);
4055 static void genValidationForPredictedInline(CompilationUnit *cUnit, MIR *mir)
4058 RegLocation rlThis = cUnit->regLocation[mir->dalvikInsn.vC];
4060 rlThis = loadValue(cUnit, rlThis, kCoreReg);
4061 int regPredictedClass = dvmCompilerAllocTemp(cUnit);
4062 loadClassPointer(cUnit, regPredictedClass, (int) callsiteInfo);
4063 genNullCheck(cUnit, rlThis.sRegLow, rlThis.lowReg, mir->offset,
4065 int regActualClass = dvmCompilerAllocTemp(cUnit);
4066 loadWordDisp(cUnit, rlThis.lowReg, offsetof(Object, clazz), regActualClass);
4067 opRegReg(cUnit, kOpCmp, regPredictedClass, regActualClass);
4072 callsiteInfo->misPredBranchOver = (LIR *) opCondBranch(cUnit, kArmCondNe);
4076 static void handleExtendedMIR(CompilationUnit *cUnit, MIR *mir)
4082 newLIR1(cUnit, kArmPseudoExtended, (int) msg);
4086 char *ssaString = dvmCompilerGetSSAString(cUnit, mir->ssaRep);
4087 newLIR1(cUnit, kArmPseudoSSARep, (int) ssaString);
4091 genHoistedChecksForCountUpLoop(cUnit, mir);
4095 genHoistedChecksForCountDownLoop(cUnit, mir);
4099 genHoistedLowerBoundCheck(cUnit, mir);
4103 genUnconditionalBranch(cUnit,
4104 (ArmLIR *) cUnit->loopAnalysis->branchToPCR);
4108 genValidationForPredictedInline(cUnit, mir);
4123 static void setupLoopEntryBlock(CompilationUnit *cUnit, BasicBlock *entry,
4130 (int) (cUnit->method->insns + entry->startOffset);
4133 dvmInsertGrowableList(&cUnit->pcReconstructionList, (intptr_t) pcrLabel);
4143 cUnit->loopAnalysis->branchToBody = (LIR *) branchToBody;
4149 cUnit->loopAnalysis->branchToPCR = (LIR *) branchToPCR;
4179 void dvmCompilerMIR2LIR(CompilationUnit *cUnit)
4183 (ArmLIR *) dvmCompilerNew(sizeof(ArmLIR) * cUnit->numBlocks, true);
4196 dvmCompilerDataFlowAnalysisDispatcher(cUnit, dvmCompilerClearVisitedFlag,
4200 dvmGrowableListIteratorInit(&cUnit->blockList, &iterator);
4203 cUnit->profileCodeSize = genTraceProfileEntry(cUnit);
4217 newLIR0(cUnit, kArmPseudoPseudoAlign4);
4223 dvmCompilerAppendLIR(cUnit, (LIR *) &labelList[i]);
4231 setupLoopEntryBlock(cUnit, bb,
4241 dvmCompilerResetRegPool(cUnit);
4242 dvmCompilerClobberAllRegs(cUnit);
4243 dvmCompilerResetNullCheck(cUnit);
4286 handlePCReconstruction(cUnit,
4287 &labelList[cUnit->puntBlock->id]);
4291 if (cUnit->pcReconstructionList.numUsed) {
4292 loadWordDisp(cUnit, r6SELF, offsetof(Thread,
4295 opReg(cUnit, kOpBlx, r1);
4317 for (BasicBlock *nextBB = bb; nextBB != NULL; nextBB = cUnit->nextCodegenBlock) {
4320 cUnit->nextCodegenBlock = NULL;
4324 dvmCompilerResetRegPool(cUnit);
4326 dvmCompilerClobberAllRegs(cUnit);
4330 dvmCompilerResetDefTracking(cUnit);
4334 handleExtendedMIR(cUnit, mir);
4358 if (headLIR == NULL || cUnit->printMe == true) {
4360 newLIR2(cUnit, kArmPseudoDalvikByteCodeBoundary,
4375 if (cUnit->printMe && mir->ssaRep) {
4376 char *ssaString = dvmCompilerGetSSAString(cUnit,
4378 newLIR1(cUnit, kArmPseudoSSARep, (int) ssaString);
4392 if (singleStepMe || cUnit->allSingleStep) {
4394 genInterpSingleStep(cUnit, mir);
4401 notHandled = handleFmt10t_Fmt20t_Fmt30t(cUnit,
4405 notHandled = handleFmt10x(cUnit, mir);
4409 notHandled = handleFmt11n_Fmt31i(cUnit, mir);
4412 notHandled = handleFmt11x(cUnit, mir);
4415 notHandled = handleFmt12x(cUnit, mir);
4418 notHandled = handleFmt20bc(cUnit, mir);
4422 notHandled = handleFmt21c_Fmt31c(cUnit, mir);
4425 notHandled = handleFmt21h(cUnit, mir);
4428 notHandled = handleFmt21s(cUnit, mir);
4431 notHandled = handleFmt21t(cUnit, mir, bb,
4436 notHandled = handleFmt22b_Fmt22s(cUnit, mir);
4439 notHandled = handleFmt22c(cUnit, mir);
4442 notHandled = handleFmt22cs(cUnit, mir);
4445 notHandled = handleFmt22t(cUnit, mir, bb,
4450 notHandled = handleFmt22x_Fmt32x(cUnit, mir);
4453 notHandled = handleFmt23x(cUnit, mir);
4456 notHandled = handleFmt31t(cUnit, mir);
4460 notHandled = handleFmt35c_3rc(cUnit, mir, bb,
4465 notHandled = handleFmt35ms_3rms(cUnit, mir, bb,
4470 notHandled = handleExecuteInline(cUnit, mir);
4473 notHandled = handleFmt51l(cUnit, mir);
4485 dvmCompilerAbort(cUnit);
4492 dvmCompilerAppendLIR(cUnit,
4493 (LIR *) cUnit->loopAnalysis->branchToBody);
4494 dvmCompilerAppendLIR(cUnit,
4495 (LIR *) cUnit->loopAnalysis->branchToPCR);
4503 dvmCompilerApplyLocalOptimizations(cUnit, (LIR *) headLIR,
4504 cUnit->lastLIRInsn);
4515 genUnconditionalBranch(cUnit, &labelList[bb->fallThrough->id]);
4524 cUnit->numChainingCells[i] = chainingListByType[i].numUsed;
4527 if (cUnit->numChainingCells[i] == 0)
4531 cUnit->firstChainingLIR[i] = (LIR *) &labelList[blockIdList[0]];
4536 (BasicBlock *) dvmGrowableListGetElement(&cUnit->blockList,
4540 newLIR0(cUnit, kArmPseudoPseudoAlign4);
4543 dvmCompilerAppendLIR(cUnit, (LIR *) &labelList[blockId]);
4548 handleNormalChainingCell(cUnit, chainingBlock->startOffset);
4551 handleInvokeSingletonChainingCell(cUnit,
4555 handleInvokePredictedChainingCell(cUnit);
4558 handleHotChainingCell(cUnit, chainingBlock->startOffset);
4561 handleBackwardBranchChainingCell(cUnit,
4566 dvmCompilerAbort(cUnit);
4572 cUnit->chainingCellBottom = (LIR *) newLIR0(cUnit, kArmChainingCellBottom);
4578 if (cUnit->switchOverflowPad) {
4579 loadConstant(cUnit, r0, (int) cUnit->switchOverflowPad);
4580 loadWordDisp(cUnit, r6SELF, offsetof(Thread,
4582 opRegReg(cUnit, kOpAdd, r1, r1);
4583 opRegRegReg(cUnit, kOpAdd, r4PC, r0, r1);
4585 loadConstant(cUnit, r0, kSwitchOverflow);
4587 opReg(cUnit, kOpBlx, r2);
4590 dvmCompilerApplyGlobalOptimizations(cUnit);
4593 selfVerificationBranchInsertPass(cUnit);
4724 ArmLIR* dvmCompilerRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
4726 return genRegCopyNoInsert(cUnit, rDest, rSrc);
4730 ArmLIR* dvmCompilerRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
4732 return genRegCopy(cUnit, rDest, rSrc);
4736 void dvmCompilerRegCopyWide(CompilationUnit *cUnit, int destLo, int destHi,
4739 genRegCopyWide(cUnit, destLo, destHi, srcLo, srcHi);
4742 void dvmCompilerFlushRegImpl(CompilationUnit *cUnit, int rBase,
4745 storeBaseDisp(cUnit, rBase, displacement, rSrc, size);
4748 void dvmCompilerFlushRegWideImpl(CompilationUnit *cUnit, int rBase,
4751 storeBaseDispWide(cUnit, rBase, displacement, rSrcLo, rSrcHi);