Lines Matching refs:ptr
40 inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
42 return Barrier_AtomicIncrement(ptr, increment);
49 inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
52 return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
55 inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
58 return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
61 inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
62 *ptr = value;
65 inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
66 NoBarrier_AtomicExchange(ptr, value);
70 inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
71 *ptr = value; // works w/o barrier for current Intel chips as of June 2005
75 inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
76 return *ptr;
79 inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
80 Atomic32 value = *ptr;
84 inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
86 return *ptr;
93 inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
95 return Barrier_AtomicIncrement(ptr, increment);
98 inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
99 *ptr = value;
102 inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
103 NoBarrier_AtomicExchange(ptr, value);
107 inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
108 *ptr = value; // works w/o barrier for current Intel chips as of June 2005
118 inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
119 return *ptr;
122 inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
123 Atomic64 value = *ptr;
127 inline Atomic64 Release_Load(volatile const Atomic64* ptr) {
129 return *ptr;
132 inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
135 return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
138 inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
141 return NoBarrier_CompareAndSwap(ptr, old_value, new_value);