Cross Reference: /external/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

Lines Matching defs:Insn
141 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
145 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
150                                               unsigned Insn,
471 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
474   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
475   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
476   unsigned ImmS = fieldFromInstruction(Insn, 10, 6);
477   unsigned ImmR = fieldFromInstruction(Insn, 16, 6);
478   unsigned SF = fieldFromInstruction(Insn, 31, 1);
483   Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2);
563 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
568   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
569   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
570   unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
588                                               unsigned Insn,
592   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
593   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
594   unsigned Rt2 = fieldFromInstruction(Insn, 10, 5);
595   unsigned SImm7 = fieldFromInstruction(Insn, 15, 7);
596   unsigned L = fieldFromInstruction(Insn, 22, 1);
597   unsigned V = fieldFromInstruction(Insn, 26, 1);
598   unsigned Opc = fieldFromInstruction(Insn, 30, 2);
602   unsigned Indexed = fieldFromInstruction(Insn, 23, 1);
752                                                    unsigned Insn,
755   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
756   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
757   unsigned Imm9 = fieldFromInstruction(Insn, 12, 9);
759   unsigned Opc = fieldFromInstruction(Insn, 22, 2);
760   unsigned V = fieldFromInstruction(Insn, 26, 1);
761   unsigned Size = fieldFromInstruction(Insn, 30, 2);