Cross Reference: /external/qemu/target-arm/cpu.h

Lines Matching refs:env
247 uint32_t do_arm_semihosting(CPUARMState *env);
254 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
258 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
260   env->cp15.c13_tls2 = newtls;
289 uint32_t cpsr_read(CPUARMState *env);
291 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
294 static inline uint32_t xpsr_read(CPUARMState *env)
297     ZF = (env->ZF == 0);
298     return (env->NF & 0x80000000) | (ZF << 30)
299         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
300         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
301         | ((env->condexec_bits & 0xfc) << 8)
302         | env->v7m.exception;
306 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
309         env->ZF = (~val) & CPSR_Z;
310         env->NF = val;
311         env->CF = (val >> 29) & 1;
312         env->VF = (val << 3) & 0x80000000;
315         env->QF = ((val & CPSR_Q) != 0);
317         env->thumb = ((val & (1 << 24)) != 0);
319         env->condexec_bits &= ~3;
320         env->condexec_bits |= (val >> 25) & 3;
323         env->condexec_bits &= 3;
324         env->condexec_bits |= (val >> 8) & 0xfc;
327         env->v7m.exception = val & 0x1ff;
332 uint32_t vfp_get_fpscr(CPUARMState *env);
333 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
389 static inline int arm_feature(CPUARMState *env, int feature)
391     return (env->features & (1u << feature)) != 0;
401 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
409 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
410 #define ARM_CPUID(env) (env->cp15.c0_cpuid)
464 static inline int cpu_mmu_index (CPUState *env)
466     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
469 static inline int is_cpu_user (CPUState *env)
474     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR;
479 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
482         env->regs[13] = newsp;
483     env->regs[0] = 0;
518 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
522     *pc = env->regs[15];
524     *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
525         | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
526         | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
527         | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT);
528     if (arm_feature(env, ARM_FEATURE_M)) {
529         privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
531         privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
536     if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {