Lines Matching defs:XT
272 /* Extract XT (destination register) field, instr[0,25:21] */
11624 UChar XT = ifieldRegXT( theInstr );
11697 DIP("xscvdpsxds v%u,v%u\n", (UInt)XT, (UInt)XB);
11698 putVSReg( XT,
11705 DIP("xscvdpsxws v%u,v%u\n", (UInt)XT, (UInt)XB);
11706 putVSReg( XT,
11716 DIP("xscvdpuxds v%u,v%u\n", (UInt)XT, (UInt)XB);
11717 putVSReg( XT,
11727 DIP("xscvsxddp v%u,v%u\n", (UInt)XT, (UInt)XB);
11728 putVSReg( XT,
11737 DIP("xscvuxddp v%u,v%u\n", (UInt)XT, (UInt)XB);
11738 putVSReg( XT,
11751 DIP("xvcvdpsxws v%u,v%u\n", (UInt)XT, (UInt)XB);
11754 putVSReg( XT,
11775 DIP("xvcvsp%sxws v%u,v%u\n", un_signed ? "u" : "s", (UInt)XT, (UInt)XB);
11807 putVSReg( XT,
11815 DIP("xscvdpsp v%u,v%u\n", (UInt)XT, (UInt)XB);
11816 putVSReg( XT,
11829 DIP("xscvdpuxws v%u,v%u\n", (UInt)XT, (UInt)XB);
11830 putVSReg( XT,
11840 DIP("xscvspdp v%u,v%u\n", (UInt)XT, (UInt)XB);
11841 putVSReg( XT,
11850 DIP("xvcvdpsp v%u,v%u\n", (UInt)XT, (UInt)XB);
11851 putVSReg( XT,
11871 DIP("xvcvdpuxds v%u,v%u\n", (UInt)XT, (UInt)XB);
11872 putVSReg( XT,
11879 DIP("xvcvdpuxws v%u,v%u\n", (UInt)XT, (UInt)XB);
11880 putVSReg( XT,
11894 DIP("xvcvspdp v%u,v%u\n", (UInt)XT, (UInt)XB);
11895 putVSReg( XT,
11906 DIP("xvcvspsxds v%u,v%u\n", (UInt)XT, (UInt)XB);
11907 putVSReg( XT,
11920 DIP("xvcvspuxds v%u,v%u\n", (UInt)XT, (UInt)XB);
11921 putVSReg( XT,
11934 DIP("xvcvdpsxds v%u,v%u\n", (UInt)XT, (UInt)XB);
11935 putVSReg( XT,
11942 DIP("xvcvsxddp v%u,v%u\n", (UInt)XT, (UInt)XB);
11943 putVSReg( XT,
11956 DIP("xvcvuxddp v%u,v%u\n", (UInt)XT, (UInt)XB);
11957 putVSReg( XT,
11971 DIP("xvcvsxddp v%u,v%u\n", (UInt)XT, (UInt)XB);
11972 putVSReg( XT,
11995 DIP("xvcvuxddp v%u,v%u\n", (UInt)XT, (UInt)XB);
11996 putVSReg( XT,
12019 DIP("xvcvsxwdp v%u,v%u\n", (UInt)XT, (UInt)XB);
12020 putVSReg( XT,
12030 DIP("xvcvuxwdp v%u,v%u\n", (UInt)XT, (UInt)XB);
12031 putVSReg( XT,
12041 DIP("xvcvsxwsp v%u,v%u\n", (UInt)XT, (UInt)XB);
12042 putVSReg( XT, unop( Iop_I32StoFx4, getVSReg( XB ) ) );
12045 DIP("xvcvuxwsp v%u,v%u\n", (UInt)XT, (UInt)XB);
12046 putVSReg( XT, unop( Iop_I32UtoFx4, getVSReg( XB ) ) );
12064 UChar XT = ifieldRegXT( theInstr );
12114 DIP("xv%sdp v%d,v%d,v%d\n", oper_name, (UInt)XT, (UInt)XA, (UInt)XB);
12122 putVSReg( XT,
12130 DIP("xvsqrtdp v%d,v%d\n", (UInt)XT, (UInt)XB);
12138 putVSReg( XT,
12147 /* xvm{add|sub}mdp XT,XA,XB is element-wise equivalent to fm{add|sub} FRT,FRA,FRC,FRB with . . .
12148 * XT == FRC
12153 * XT == FRB
12194 (UInt)XT, (UInt)XA, (UInt)XB);
12195 assign(frT, unop(Iop_ReinterpI64asF64, unop(Iop_V128HIto64, getVSReg( XT ) ) ) );
12196 assign(frT2, unop(Iop_ReinterpI64asF64, unop(Iop_V128to64, getVSReg( XT ) ) ) );
12212 putVSReg( XT,
12307 UChar XT = ifieldRegXT( theInstr );
12328 DIP("xvaddsp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
12329 putVSReg( XT, binop(Iop_Add32Fx4, getVSReg( XA ), getVSReg( XB )) );
12333 DIP("xvmulsp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
12334 putVSReg( XT, binop(Iop_Mul32Fx4, getVSReg( XA ), getVSReg( XB )) );
12338 DIP("xvsubsp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
12339 putVSReg( XT, binop(Iop_Sub32Fx4, getVSReg( XA ), getVSReg( XB )) );
12352 DIP("xvdivsp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
12373 putVSReg( XT,
12381 DIP("xvsqrtsp v%d,v%d\n", (UInt)XT, (UInt)XB);
12406 putVSReg( XT,
12453 (UInt)XT, (UInt)XA, (UInt)XB);
12458 breakV128to4xF64( getVSReg( XT ), &t3, &t2, &t1, &t0 );
12493 putVSReg( XT,
12905 UChar XT = ifieldRegXT( theInstr );
12928 DIP("%s v%d,v%d\n", redp ? "xvredp" : "xvrsqrtedp", (UInt)XT, (UInt)XB);
12939 putVSReg( XT,
12976 DIP("%s v%d,v%d\n", resp ? "xvresp" : "xvrsqrtesp", (UInt)XT, (UInt)XB);
13014 putVSReg( XT,
13043 DIP("%s v%d,v%d v%d\n", isMin ? "xvminsp" : "xvmaxsp", (UInt)XT, (UInt)XA, (UInt)XB);
13074 putVSReg( XT,
13094 DIP("%s v%d,v%d v%d\n", isMin ? "xvmindp" : "xvmaxdp", (UInt)XT, (UInt)XA, (UInt)XB);
13095 putVSReg( XT, binop( Iop_64HLtoV128, get_max_min_fp(frA, frB, isMin), get_max_min_fp(frA2, frB2, isMin) ) );
13111 DIP("xvcpsgndp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
13112 putVSReg( XT,
13140 DIP("xvcpsgnsp v%d,v%d v%d\n",(UInt)XT, (UInt)XA, (UInt)XB);
13178 putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( resHi ), mkexpr( resLo ) ) );
13192 DIP("xv%sabsdp v%d,v%d\n", make_negative ? "n" : "", (UInt)XT, (UInt)XB);
13201 putVSReg( XT, binop( Iop_64HLtoV128,
13238 putVSReg( XT,
13243 putVSReg( XT, mkexpr( absVal_vector ) );
13253 DIP("xvnegdp v%d,v%d\n", (UInt)XT, (UInt)XB);
13254 putVSReg( XT,
13279 DIP("xvrdpi%s v%d,v%d\n", insn_suffix, (UInt)XT, (UInt)XB);
13280 putVSReg( XT,
13318 DIP("xvrspi%s v%d,v%d\n", insn_suffix, (UInt)XT, (UInt)XB);
13319 putVSReg( XT, unop( op, getVSReg(XB) ) );
13344 DIP("xvrspic v%d,v%d\n", (UInt)XT, (UInt)XB);
13345 putVSReg( XT,
13373 UChar XT = ifieldRegXT( theInstr );
13389 * of VSX[XT] are undefined after the operation; therefore, we can simply set
13394 DIP("xsadddp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
13395 putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64,
13402 DIP("xsdivdp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
13403 putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64,
13413 DIP("xsmadd%sdp v%d,v%d,v%d\n", mdp ? "m" : "a", (UInt)XT, (UInt)XA, (UInt)XB);
13415 getVSReg( XT ) ) ) );
13416 putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64,
13428 DIP("xsmsub%sdp v%d,v%d,v%d\n", mdp ? "m" : "a", (UInt)XT, (UInt)XA, (UInt)XB);
13430 getVSReg( XT ) ) ) );
13431 putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64,
13452 DIP("xsnmadd%sdp v%d,v%d,v%d\n", mdp ? "m" : "a", (UInt)XT, (UInt)XA, (UInt)XB);
13454 getVSReg( XT ) ) ) );
13460 putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( getNegatedResult(maddResult) ),
13470 DIP("xsnmsub%sdp v%d,v%d,v%d\n", mdp ? "m" : "a", (UInt)XT, (UInt)XA, (UInt)XB);
13472 getVSReg( XT ) ) ) );
13480 putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( getNegatedResult(msubResult) ), mkU64( 0 ) ) );
13486 DIP("xsmuldp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
13487 putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64,
13494 DIP("xssubdp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
13495 putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64,
13503 DIP("xssqrtdp v%d,v%d\n", (UInt)XT, (UInt)XB);
13504 putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64,
13528 DIP("xstsqrtdp v%d,v%d\n", (UInt)XT, (UInt)XB);
13592 do_vvec_fp_cmp ( IRTemp vA, IRTemp vB, UChar XT, UChar flag_rC,
13648 putVSReg( XT,
13684 UChar XT = ifieldRegXT ( theInstr );
13703 (UInt)XT, (UInt)XA, (UInt)XB);
13704 do_vvec_fp_cmp(vA, vB, XT, flag_rC, PPC_CMP_EQ);
13711 (UInt)XT, (UInt)XA, (UInt)XB);
13712 do_vvec_fp_cmp(vA, vB, XT, flag_rC, PPC_CMP_GE);
13719 (UInt)XT, (UInt)XA, (UInt)XB);
13720 do_vvec_fp_cmp(vA, vB, XT, flag_rC, PPC_CMP_GT);
13729 (UInt)XT, (UInt)XA, (UInt)XB);
13731 putVSReg( XT, mkexpr(vD) );
13743 (UInt)XT, (UInt)XA, (UInt)XB);
13745 putVSReg( XT, mkexpr(vD) );
13757 (UInt)XT, (UInt)XA, (UInt)XB);
13759 putVSReg( XT, mkexpr(vD) );
13780 UChar XT = ifieldRegXT ( theInstr );
13795 * of VSX[XT] are undefined after the operation; therefore, we can simply
13802 /* Move abs val of dw 0 of VSX[XB] to dw 0 of VSX[XT]. */
13805 DIP("xsabsdp v%d,v%d\n", (UInt)XT, (UInt)XB);
13806 putVSReg(XT, mkexpr(absVal));
13815 DIP("xscpsgndp v%d,v%d v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
13825 putVSReg(XT, mkexpr(vec_result));
13832 DIP("xsnabsdp v%d,v%d\n", (UInt)XT, (UInt)XB);
13836 putVSReg(XT, binop(Iop_OrV128, mkexpr(vec_neg_signbit), mkexpr(vB)));
13844 DIP("xsnabsdp v%d,v%d\n", (UInt)XT, (UInt)XB);
13855 putVSReg( XT, binop( Iop_OrV128, mkexpr( vecB_no_signbit ),
13865 DIP("%s v%d,v%d v%d\n", isMin ? "xsmaxdp" : "xsmindp", (UInt)XT, (UInt)XA, (UInt)XB);
13869 putVSReg( XT, binop( Iop_64HLtoV128, get_max_min_fp(frA, frB, isMin), mkU64( 0 ) ) );
13886 DIP("xsrdpi%s v%d,v%d\n", insn_suffix, (UInt)XT, (UInt)XB);
13887 putVSReg( XT,
13902 DIP("%s v%d,v%d\n", redp ? "xsredp" : "xsrsqrtedp", (UInt)XT, (UInt)XB);
13912 putVSReg( XT,
13938 UChar XT = ifieldRegXT ( theInstr );
13954 DIP("xxlxor v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
13955 putVSReg( XT, binop( Iop_XorV128, mkexpr( vA ), mkexpr( vB ) ) );
13958 DIP("xxlor v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
13959 putVSReg( XT, binop( Iop_OrV128, mkexpr( vA ), mkexpr( vB ) ) );
13962 DIP("xxlnor v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
13963 putVSReg( XT, unop( Iop_NotV128, binop( Iop_OrV128, mkexpr( vA ),
13967 DIP("xxland v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
13968 putVSReg( XT, binop( Iop_AndV128, mkexpr( vA ), mkexpr( vB ) ) );
13971 DIP("xxlandc v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
13972 putVSReg( XT, binop( Iop_AndV128, mkexpr( vA ), unop( Iop_NotV128,
13991 UChar XT = ifieldRegXT ( theInstr );
14010 DIP("lxsdx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
14013 // we just performed is only a DW. But since the contents of VSR[XT] element 1
14015 putVSReg( XT, binop( Iop_64HLtoV128, exp, exp ) );
14024 DIP("lxvd2x %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
14029 putVSReg( XT, binop( Iop_64HLtoV128, high, low ) );
14035 DIP("lxvdsx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
14037 putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( data ), mkexpr( data ) ) );
14046 DIP("lxvw4x %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
14060 putVSReg( XT, binop( Iop_64HLtoV128, binop( Iop_32HLto64, t3, t2 ),
14162 UChar XT = ifieldRegXT ( theInstr );
14190 DIP("xxsldwi v%d,v%d,v%d,%d\n", (UInt)XT, (UInt)XA, (UInt)XB, (UInt)SHW);
14191 putVSReg( XT, mkexpr(result) );
14212 DIP("xxpermdi v%d,v%d,v%d,0x%x\n", (UInt)XT, (UInt)XA, (UInt)XB, (UInt)DM);
14213 putVSReg( XT, mkexpr( vT ) );
14240 DIP("xxmrg%cw v%d,v%d,v%d\n", type, (UInt)XT, (UInt)XA, (UInt)XB);
14241 putVSReg( XT, mkexpr( vT ) );
14249 DIP("xxsel v%d,v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB, (UInt)XC);
14251 putVSReg( XT, binop(Iop_OrV128,
14260 DIP("xxspltw v%d,v%d,%d\n", (UInt)XT, (UInt)XB, UIM);
14261 putVSReg( XT,