Lines Matching defs:r11
52 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" };
1084 vex_printf("movabsq $0x%llx,%%r11; ", i->Ain.XDirect.dstGA);
1085 vex_printf("movq %%r11,");
1088 vex_printf("movabsq $disp_cp_chain_me_to_%sEP,%%r11; call *%%r11 }",
1099 vex_printf("; movabsq $disp_indir,%%r11; jmp *%%r11 }");
1111 vex_printf("; movabsq $disp_assisted,%%r11; jmp *%%r11 }");
1317 vex_printf("(profInc) movabsq $NotKnownYet, %%r11; incq (%%r11)");
1393 These I believe to be: rax rcx rdx rsi rdi r8 r9 r10 r11
1432 loaded into a register. Fortunately, r11 is stated in the
1435 /* Upshot of this is that the assembler really must use r11,
1444 /* Don't bother to mention the write to %r11, since it is not
1449 /* Ditto re %r11 */
1454 /* Ditto re %r11 and %rbp (the baseblock ptr) */
1805 /* hardwires r11 -- nothing to modify. */
2667 getRegUsage_AMD64Instr above, %r11 is used as an address
2678 /* 7 bytes: movl sign-extend(imm32), %r11 */
2684 /* 10 bytes: movabsq $target, %r11 */
2689 /* 3 bytes: call *%r11 */
2705 HReg r11 = hregAMD64_R11();
2722 /* movl sign-extend(dstGA), %r11 */
2728 /* movabsq $dstGA, %r11 */
2734 /* movq %r11, amRIP */
2735 *p++ = rexAMode_M(r11, i->Ain.XDirect.amRIP);
2737 p = doAMode_M(p, r11, i->Ain.XDirect.amRIP);
2744 /* movabsq $disp_cp_chain_me_to_{slow,fast}EP,%r11; */
2751 /* call *%r11 */
2792 /* get $disp_cp_xindir into %r11 */
2795 /* movl sign-extend(disp_cp_xindir), %r11 */
2801 /* movabsq $disp_cp_xindir, %r11 */
2807 /* jmp *%r11 */
2866 /* movabsq $disp_assisted, %r11 */
2870 /* jmp *%r11 */
3473 /* We generate movabsq $0, %r11
3474 incq (%r11)
3524 movabsq $disp_cp_chain_me_EXPECTED, %r11
3525 call *%r11
3539 movabsq $place_to_jump_to, %r11
3540 jmpq *%r11
3611 movabsq $place_to_jump_to_EXPECTED, %r11
3612 jmpq *%r11
3649 movabsq $disp_cp_chain_me, %r11
3650 call *%r11