Cross Reference: /external/valgrind/main/VEX/priv/host_s390

Lines Matching defs:r11
653          HReg r10, r11, h1;
659          /* We use non-virtual registers r10 and r11 as pair */
661          r11  = make_gpr(11);
663          /* Move 1st operand into r11 and */
664          addInstr(env, s390_insn_move(8, r11, h1));
667          addInstr(env, s390_insn_divs(8, r10, r11, op2));
669          /* The result is in registers r10 (remainder) and r11 (quotient).
676          addInstr(env, s390_insn_move(8, *dst_lo, r11));
684             HReg r10, r11, h1;
692             /* We use non-virtual registers r10 and r11 as pair */
694             r11  = make_gpr(11);
696             /* Move the first operand to r11 */
697             addInstr(env, s390_insn_move(8, r11, h1));
700             addInstr(env, s390_insn_mul(8, r10, r11, op2, is_signed_multiply));
702             /* The result is in registers r10 and r11. Assign to two virtual regs
707             addInstr(env, s390_insn_move(8, *dst_lo, r11));
712          HReg r10, r11, hi, lo;
718          /* We use non-virtual registers r10 and r11 as pair */
720          r11  = make_gpr(11);
723             the low 64 bits into r11. */
725          addInstr(env, s390_insn_move(8, r11, lo));
728          addInstr(env, s390_insn_div(8, r10, r11, op2, is_signed_divide));
730          /* The result is in registers r10 (remainder) and r11 (quotient).
737          addInstr(env, s390_insn_move(8, *dst_lo, r11));
840             HReg r10, r11;
848             /* We use non-virtual registers r10 and r11 as pair */
850             r11  = make_gpr(11);
852             /* Move the first operand to r11 */
853             addInstr(env, s390_insn_move(arg_size, r11, h1));
856             addInstr(env, s390_insn_mul(arg_size, r10, r11, op2, is_signed_multiply));
858             /* The result is in registers r10 and r11. Combine them into a SIZE-bit
865             addInstr(env, s390_insn_alu(size, S390_ALU_AND, r11, value));
866             opnd = s390_opnd_reg(r11);
880             HReg r10, r11;
885             /* We use non-virtual registers r10 and r11 as pair */
887             r11  = make_gpr(11);
890                the low 32 bits into r11. */
892             addInstr(env, s390_insn_move(8, r11, h1));
897             addInstr(env, s390_insn_div(4, r10, r11, op2, is_signed_divide));
899             /* The result is in registers r10 (remainder) and r11 (quotient).
908             addInstr(env, s390_insn_alu(8, S390_ALU_AND, r11, value));
909             opnd = s390_opnd_reg(r11);
1308          HReg r10, r11;
1312             left-most zero bits) will be in r10. The value in r11 is unspecified
1315          r11  = make_gpr(11);
1317          addInstr(env, s390_insn_clz(8, r10, r11, opnd));
2503          HReg r8, r9, r10, r11, r1;
2518          /* Use non-virtual registers r10 and r11 as pair for op3
2521          r11 = make_gpr(11);
2523          addInstr(env, s390_insn_move(8, r11, op3_low));
2529             addInstr(env, s390_insn_cdas(4, r8, r9, op2, r10, r11,
2532             addInstr(env, s390_insn_cdas(8, r8, r9, op2, r10, r11,
2538          addInstr(env, s390_insn_move(8, op3_low,  r11));