Lines Matching defs:LL
94 static cache_t2 I1, D1, LL;
234 * Simple model: L1 & LL Write Through
308 if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;
316 if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;
326 * More complex model: L1 Write-through, LL Write-back
415 switch( cachesim_ref_wb( &LL, Read, a, size) ) {
427 switch( cachesim_ref_wb( &LL, Read, a, size) ) {
440 * the write to the LL to make the LL line dirty.
443 cachesim_ref_wb( &LL, Write, a, size);
446 switch( cachesim_ref_wb( &LL, Write, a, size) ) {
485 UInt block = ( a >> LL.line_size_bits);
497 cachesim_ref(&LL, a + 5 * LL.line_size,1);
507 cachesim_ref(&LL, a - 5 * LL.line_size,1);
523 if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;
532 if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;
544 switch( cachesim_ref_wb( &LL, Read, a, size) ) {
557 switch( cachesim_ref_wb( &LL, Read, a, size) ) {
571 * the write to the LL to make the LL line dirty.
574 cachesim_ref_wb( &LL, Write, a, size);
577 switch( cachesim_ref_wb( &LL, Write, a, size) ) {
739 Int miss1=0, miss2=0; /* 0: L1 hit, 1:L1 miss, 2:LL miss */ \
842 line_loaded* loaded = &(LL.loaded[idx]);
843 line_use* use = &(LL.use[idx]);
844 int i = ((32 - countBits(use->mask)) * LL.line_size)>>5;
846 CLG_DEBUG(2, " LL.miss [%d]: at %#lx accessing memline %#lx\n",
873 UInt setNo = (memline >> LL.line_size_bits) & (LL.sets_min_1);
874 UWord* set = &(LL.tags[setNo * LL.assoc]);
875 UWord tag = memline & LL.tag_mask;
880 CLG_DEBUG(6,"LL.Acc(Memline %#lx): Set %d\n", memline, setNo);
882 if (tag == (set[0] & LL.tag_mask)) {
883 idx = (setNo * LL.assoc) + (set[0] & ~LL.tag_mask);
884 l1_loaded->dep_use = &(LL.use[idx]);
887 idx, LL.loaded[idx].memline, LL.loaded[idx].iaddr,
888 LL.use[idx].mask, LL.use[idx].count);
891 for (i = 1; i < LL.assoc; i++) {
892 if (tag == (set[i] & LL.tag_mask)) {
898 idx = (setNo * LL.assoc) + (tmp_tag & ~LL.tag_mask);
899 l1_loaded->dep_use = &(LL.use[idx]);
902 i, idx, LL.loaded[idx].memline, LL.loaded[idx].iaddr,
903 LL.use[idx].mask, LL.use[idx].count);
909 tmp_tag = set[LL.assoc - 1] & ~LL.tag_mask;
910 for (j = LL.assoc - 1; j > 0; j--) {
914 idx = (setNo * LL.assoc) + tmp_tag;
915 l1_loaded->dep_use = &(LL.use[idx]);
946 /* FIXME (?): L1/LL line sizes must be equal ! */ \
994 if (LL.use)
995 for (i = 0; i < LL.sets * LL.assoc; i++)
996 if (LL.loaded[i].use_base)
1041 case LL_Hit: return "LL Hit ";
1042 case MemAccess: return "LL Miss";
1043 case WriteBackMemAccess: return "LL Miss (dirty)";
1308 LL.name = "LL";
1334 cachesim_initcache(LLc, &LL);
1415 cachesim_clearcache(&LL);
1426 VG_(sprintf)(buf+p, "desc: LL cache: %s\n", LL.desc_line);
1612 /* LL overall results */
1625 VG_(message)(Vg_UserMsg, "LL refs: %s (%s rd + %s wr)\n",
1639 VG_(message)(Vg_UserMsg, "LL misses: %s (%s rd + %s wr)\n",
1649 VG_(message)(Vg_UserMsg, "LL miss rate: %s (%s + %s )\n",