Lines Matching refs:uint32_t
42 #define MC_FC_INVALID ((uint32_t) 0 ) /**< Invalid FastCall ID */
43 #define MC_FC_INIT ((uint32_t)(-1)) /**< Initializing FastCall. */
44 #define MC_FC_INFO ((uint32_t)(-2)) /**< Info FastCall. */
48 #define MC_FC_SLEEP ((uint32_t)(-3)) /**< enter power-sleep */
49 #define MC_FC_AFTR ((uint32_t)(-5)) /**< enter AFTR-sleep (called from core-0) */
51 #define MC_FC_CORE_X_WAKEUP ((uint32_t)(-4)) /**< wakeup/boot core-x (optional core-number in r1, not "0" ) */
52 #define MC_FC_C15_RESUME ((uint32_t)(-11)) /**< Write power control & diag registers */
53 #define MC_FC_CMD_SAVE ((uint32_t)(-6)) /**< Save core context to CP15 table(r1 is core number) */
54 #define MC_FC_CMD_SHUTDOWN ((uint32_t)(-7)) /**< Shutdown core(r1 is core number, cache flush is expected) */
56 #define MC_FC_L2X0_CTRL ((uint32_t)(-21)) /**< Write to L2X0 control register */
57 #define MC_FC_L2X0_SETUP1 ((uint32_t)(-22)) /**< Setup L2X0 register - part 1 */
58 #define MC_FC_L2X0_SETUP2 ((uint32_t)(-23)) /**< Setup L2X0 register - part 2 */
59 #define MC_FC_L2X0_INVALL ((uint32_t)(-24)) /**< Invalidate all L2 cache */
60 #define MC_FC_L2X0_DEBUG ((uint32_t)(-25)) /**< Write L2X0 debug register */
62 #define MC_FC_MEM_TRACE ((uint32_t)(-31)) /**< Enable SWd tracing via memory */
64 #define MC_FC_CP15_REG ((uint32_t)(-101)) /**< general CP15/cache register update */
66 #define MC_FC_STORE_BINFO ((uint32_t)(-201)) /**< write a 32bit value in secure DDRRAM in incremented art (max 2kB) */
68 #define MC_FC_MAX_ID ((uint32_t)(0xFFFF0000)) /**< Maximum allowed FastCall ID */