Searched defs:CPU (Results 26 - 50 of 72) sorted by relevance

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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUTargetMachine.cpp42 StringRef CPU, StringRef FS,
48 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
49 Subtarget(TT, CPU, FS),
41 AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OptLevel ) argument
/external/llvm/lib/MC/
H A DMCSubtargetInfo.cpp22 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented
25 MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) { argument
27 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
30 if (!CPU.empty())
31 CPUSchedModel = getSchedModelForCPU(CPU);
37 MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, argument
62 InitMCProcessorInfo(CPU, FS);
83 MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
95 KV.Key = CPU.data();
98 if (Found == ProcSchedModels+NumProcs || StringRef(Found->Key) != CPU) {
[all...]
/external/llvm/lib/Target/ARM/
H A DARMSubtarget.cpp60 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, argument
62 : ARMGenSubtargetInfo(TT, CPU, FS)
65 , CPUString(CPU)
70 resetSubtargetFeatures(CPU, FS);
125 std::string CPU = local
131 resetSubtargetFeatures(CPU, FS);
135 void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) { argument
153 // ARM version or CPU and then remove this.
157 // Keep a pointer to static instruction cost data for the specified CPU.
160 // Initialize scheduling itinerary for the specified CPU
[all...]
H A DARMTargetMachine.cpp46 StringRef CPU, StringRef FS,
50 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
51 Subtarget(TT, CPU, FS, Options),
71 StringRef CPU, StringRef FS,
75 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
90 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
97 StringRef CPU, StringRef FS,
101 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45 ARMBaseTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
70 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
96 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/Hexagon/
H A DHexagonTargetMachine.cpp68 StringRef CPU, StringRef FS,
73 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
77 Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
67 HexagonTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCTargetDesc.cpp46 static MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU, argument
49 InitMSP430MCSubtargetInfo(X, TT, CPU, FS);
/external/llvm/lib/Target/Mips/
H A DMipsSubtarget.cpp58 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, argument
61 MipsGenSubtargetInfo(TT, CPU, FS),
71 std::string CPUName = CPU;
80 // Initialize scheduling itinerary for the specified CPU.
H A DMipsTargetMachine.cpp56 StringRef CPU, StringRef FS, const TargetOptions &Options,
60 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
61 Subtarget(TT, CPU, FS, isLittle, RM, this),
118 StringRef CPU, StringRef FS, const TargetOptions &Options,
121 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
127 StringRef CPU, StringRef FS, const TargetOptions &Options,
130 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
55 MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
117 MipsebTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
126 MipselTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/NVPTX/MCTargetDesc/
H A DNVPTXMCTargetDesc.cpp48 createNVPTXMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { argument
50 InitNVPTXMCSubtargetInfo(X, TT, CPU, FS);
/external/llvm/lib/Target/PowerPC/
H A DPPCSubtarget.cpp32 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, argument
34 : PPCGenSubtargetInfo(TT, CPU, FS)
38 resetSubtargetFeatures(CPU, FS);
59 std::string CPU = local
65 resetSubtargetFeatures(CPU, FS);
95 void PPCSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) { argument
97 std::string CPUName = CPU;
106 // Initialize scheduling itinerary for the specified CPU.
H A DPPCTargetMachine.cpp37 StringRef CPU, StringRef FS,
42 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
43 Subtarget(TT, CPU, FS, is64Bit),
58 StringRef CPU, StringRef FS,
62 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
68 StringRef CPU, StringRef FS,
72 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
36 PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
57 PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
67 PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/R600/
H A DAMDGPUTargetMachine.cpp52 StringRef CPU, StringRef FS,
58 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
59 Subtarget(TT, CPU, FS),
51 AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OptLevel ) argument
/external/llvm/lib/Target/Sparc/
H A DSparcTargetMachine.cpp29 StringRef CPU, StringRef FS,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35 Subtarget(TT, CPU, FS, is64bit),
79 StringRef TT, StringRef CPU,
85 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
91 StringRef TT, StringRef CPU,
97 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
28 SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
78 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
90 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/XCore/MCTargetDesc/
H A DXCoreMCTargetDesc.cpp47 static MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, argument
50 InitXCoreMCSubtargetInfo(X, TT, CPU, FS);
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUTargetMachine.cpp42 StringRef CPU, StringRef FS,
48 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
49 Subtarget(TT, CPU, FS),
41 AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OptLevel ) argument
/external/chromium/base/
H A Dcpu.h16 class BASE_API CPU { class in namespace:base
19 CPU();
21 // Accessors for CPU information.
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
H A DAMDGPUMCTargetDesc.cpp49 static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU, argument
52 InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
/external/llvm/lib/CodeGen/
H A DLLVMTargetMachine.cpp77 StringRef CPU, StringRef FS,
81 : TargetMachine(T, Triple, CPU, FS, Options) {
76 LLVMTargetMachine(const Target &T, StringRef Triple, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsAsmBackend.cpp257 StringRef CPU) {
263 StringRef CPU) {
269 StringRef CPU) {
275 StringRef CPU) {
256 createMipsAsmBackendEL32(const Target &T, StringRef TT, StringRef CPU) argument
262 createMipsAsmBackendEB32(const Target &T, StringRef TT, StringRef CPU) argument
268 createMipsAsmBackendEL64(const Target &T, StringRef TT, StringRef CPU) argument
274 createMipsAsmBackendEB64(const Target &T, StringRef TT, StringRef CPU) argument
H A DMipsMCTargetDesc.cpp38 static std::string ParseMipsTriple(StringRef TT, StringRef CPU) { argument
55 if (CPU.empty() || CPU == "mips32") {
57 } else if (CPU == "mips32r2") {
61 if (CPU.empty() || CPU == "mips64") {
63 } else if (CPU == "mips64r2") {
82 static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU, argument
84 std::string ArchFS = ParseMipsTriple(TT,CPU);
92 InitMipsMCSubtargetInfo(X, TT, CPU, ArchF
[all...]
/external/llvm/lib/Target/NVPTX/
H A DNVPTXTargetMachine.cpp70 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
73 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
74 Subtarget(TT, CPU, FS, is64bit), DL(Subtarget.getDataLayout()),
84 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
87 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
92 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
95 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
69 NVPTXTargetMachine( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
83 NVPTXTargetMachine32( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
91 NVPTXTargetMachine64( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.cpp55 static MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU, argument
58 InitPPCMCSubtargetInfo(X, TT, CPU, FS);
/external/llvm/lib/Target/R600/MCTargetDesc/
H A DAMDGPUAsmBackend.cpp99 StringRef CPU) {
98 createAMDGPUAsmBackend(const Target &T, StringRef TT, StringRef CPU) argument
H A DAMDGPUMCTargetDesc.cpp50 static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU, argument
53 InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCAsmBackend.cpp147 StringRef CPU) {
146 createSystemZMCAsmBackend(const Target &T, StringRef TT, StringRef CPU) argument

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