Searched defs:TBB (Results 1 - 25 of 25) sorted by relevance

/external/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp170 MachineBasicBlock *&TBB,
200 TBB = I->getOperand(0).getMBB();
212 TBB = 0;
218 // TBB is used to indicate the unconditinal destination.
219 TBB = I->getOperand(0).getMBB();
232 FBB = TBB;
233 TBB = I->getOperand(0).getMBB();
241 assert(TBB);
245 if (TBB != I->getOperand(0).getMBB())
260 MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, argument
169 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
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/external/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp150 /// just return false, leaving TBB/FBB null.
151 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
154 /// an successor block, it sets TBB to be the branch destination block and a
159 /// block, it returns the 'true' destination in TBB, the 'false' destination
168 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
181 TBB = LastInst->getOperand(0).getMBB();
185 TBB = LastInst->getOperand(1).getMBB();
203 TBB = SecondLastInst->getOperand(1).getMBB();
213 TBB = SecondLastInst->getOperand(0).getMBB();
249 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBloc
167 AnalyzeBranch( MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
248 InsertBranch( MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
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/external/llvm/unittests/IR/
H A DIRBuilderTest.cpp81 BasicBlock *TBB = BasicBlock::Create(getGlobalContext(), "", F); local
84 BranchInst *BI = Builder.CreateCondBr(Builder.getTrue(), TBB, FBB);
88 EXPECT_EQ(TBB, TI->getSuccessor(0));
93 BI = Builder.CreateCondBr(Builder.getTrue(), TBB, FBB, Weights);
97 EXPECT_EQ(TBB, TI->getSuccessor(0));
/external/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp84 MachineBasicBlock *&TBB,
89 BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
95 MachineBasicBlock *TBB, DebugLoc DL,
110 MIB.addMBB(TBB);
114 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, argument
119 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
131 BuildCondBr(MBB, TBB, DL, Cond);
139 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
141 BuildCondBr(MBB, TBB, DL, Cond);
181 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, argument
83 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
94 BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL, const SmallVectorImpl<MachineOperand>& Cond) const argument
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H A DMipsSEISelLowering.cpp778 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); local
781 F->insert(It, TBB);
791 BB->addSuccessor(TBB);
793 TBB->addSuccessor(Sink);
796 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
804 // Fill $TBB.
806 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
812 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
/external/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp120 MachineBasicBlock *&TBB,
147 TBB = I->getOperand(0).getMBB();
158 TBB = 0;
165 TBB = I->getOperand(0).getMBB();
209 FBB = TBB;
210 TBB = I->getOperand(0).getMBB();
222 SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, argument
226 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
232 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
240 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB)
119 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
[all...]
/external/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp169 /// just return false, leaving TBB/FBB null.
170 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
173 /// an successor block, it sets TBB to be the branch destination block and a
178 /// block, it returns the 'true' destination in TBB, the 'false' destination
187 XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, argument
210 TBB = LastInst->getOperand(0).getMBB();
221 TBB = LastInst->getOperand(1).getMBB();
243 TBB = SecondLastInst->getOperand(1).getMBB();
255 TBB = SecondLastInst->getOperand(0).getMBB();
275 XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, argument
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DR600InstrInfo.cpp178 MachineBasicBlock *&TBB,
208 TBB = LastInst->getOperand(0).getMBB();
215 TBB = LastInst->getOperand(0).getMBB();
238 TBB = SecondLastInst->getOperand(0).getMBB();
262 MachineBasicBlock *TBB,
267 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
271 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB).addReg(0);
280 .addMBB(TBB)
290 .addMBB(TBB)
177 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
261 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600InstrInfo.cpp178 MachineBasicBlock *&TBB,
208 TBB = LastInst->getOperand(0).getMBB();
215 TBB = LastInst->getOperand(0).getMBB();
238 TBB = SecondLastInst->getOperand(0).getMBB();
262 MachineBasicBlock *TBB,
267 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
271 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB).addReg(0);
280 .addMBB(TBB)
290 .addMBB(TBB)
177 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
261 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
/external/llvm/lib/CodeGen/
H A DEarlyIfConversion.cpp71 // | [TF]BB FBB TBB
76 // Instructions in the conditional blocks TBB and/or FBB are spliced into the
93 MachineBasicBlock *TBB; member in class:__anon22069::SSAIfConv
98 /// isTriangle - When there is no 'else' block, either TBB or FBB will be
100 bool isTriangle() const { return TBB == Tail || FBB == Tail; }
103 MachineBasicBlock *getTPred() const { return TBB == Tail ? Head : TBB; }
135 /// Insertion point in Head for speculatively executed instructions form TBB
341 TBB = FBB = Tail = 0;
388 if (TII->AnalyzeBranch(*Head, TBB, FB
[all...]
H A DMachineBlockPlacement.cpp890 MachineBasicBlock *TBB = 0, *FBB = 0; // For AnalyzeBranch. local
891 if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond) || !FI->canFallThrough())
992 MachineBasicBlock *TBB = 0, *FBB = 0; // For AnalyzeBranch. local
993 if (!TII->AnalyzeBranch(*PrevBB, TBB, FBB, Cond)) {
1009 TBB = FBB = 0;
1010 if (TII->AnalyzeBranch(*PrevBB, TBB, FBB, Cond)) {
1012 TBB = FBB = 0;
1018 if (TBB && !Cond.empty() && FBB &&
1019 MBPI->getEdgeWeight(PrevBB, FBB) > MBPI->getEdgeWeight(PrevBB, TBB) &&
1024 << " vs " << MBPI->getEdgeWeight(PrevBB, TBB) << "\
1037 MachineBasicBlock *TBB = 0, *FBB = 0; // For AnalyzeBranch. local
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H A DBranchFolding.cpp197 MachineBasicBlock *MBB = I, *TBB = 0, *FBB = 0; local
199 if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, true))
200 MadeChange |= MBB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty());
462 MachineBasicBlock *TBB = 0, *FBB = 0; local
466 !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond, true)) {
468 if (TBB == NextBB && !Cond.empty() && !FBB) {
893 MachineBasicBlock *TBB = 0, *FBB = 0; local
895 if (!TII->AnalyzeBranch(*PBB, TBB, FBB, Cond, true)) {
899 if (!Cond.empty() && TBB == IBB) {
915 if (TBB
1577 MachineBasicBlock *TBB = 0, *FBB = 0; local
[all...]
H A DMachineBasicBlock.cpp391 MachineBasicBlock *TBB = 0, *FBB = 0;
394 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
398 if (TBB) {
401 if (isLayoutSuccessor(TBB))
410 assert(!TBB && "Found more than one non-landing-pad successor!");
411 TBB = *SI;
416 if (!TBB)
421 if (!isLayoutSuccessor(TBB))
422 TII->InsertBranch(*this, TBB, 0, Cond, dl);
429 if (isLayoutSuccessor(TBB)) {
683 MachineBasicBlock *TBB = 0, *FBB = 0; local
[all...]
H A DMachineLICM.cpp804 MachineBasicBlock *TBB = 0, *FBB = 0; local
806 if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond, false) && Cond.empty())
H A DMachineVerifier.cpp548 MachineBasicBlock *TBB = 0, *FBB = 0; local
551 TBB, FBB, Cond)) {
554 if (!TBB && !FBB) {
582 } else if (TBB && !FBB && Cond.empty()) {
587 } else if (!MBB->isSuccessor(TBB)) {
601 } else if (TBB && !FBB && !Cond.empty()) {
609 if (&*MBBI != TBB)
612 else if (TBB != *MBB->succ_begin())
618 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
632 } else if (TBB
[all...]
H A DIfConversion.cpp83 /// TargetInstrInfo::AnalyzeBranch() (i.e. TBB, FBB, and Cond), and its
216 bool MeetIfcvtSizeLimit(MachineBasicBlock &TBB, argument
222 TII->isProfitableToIfCvt(TBB, TCycle, TExtra, FBB, FCycle, FExtra,
816 // TBB FBB
833 // | TBB
856 // | TBB---> exit
958 MachineBasicBlock *TBB = NULL, *FBB = NULL; local
960 if (!TII->AnalyzeBranch(*BBI.BB, TBB, FBB, Cond))
961 BBI.BB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty());
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp129 /// setting TBB to the destination basic block and populating the Cond vector
133 static void classifyCondBranch(MachineInstr *I, MachineBasicBlock *&TBB, argument
145 TBB = I->getOperand(1).getMBB();
155 TBB = I->getOperand(2).getMBB();
164 AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, argument
188 TBB = LastInst->getOperand(0).getMBB();
192 classifyCondBranch(LastInst, TBB, Cond);
211 TBB = LastInst->getOperand(0).getMBB();
227 TBB = SecondLastInst->getOperand(1).getMBB();
233 classifyCondBranch(SecondLastInst, TBB, Con
293 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
[all...]
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h251 /// just return false, leaving TBB/FBB null.
252 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
255 /// successor block, it sets TBB to be the branch destination block and a
259 /// unconditional branch, it returns the 'true' destination in TBB, the
270 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, argument
294 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, argument
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp226 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, argument
253 TBB = LastInst->getOperand(0).getMBB();
259 TBB = LastInst->getOperand(2).getMBB();
269 TBB = LastInst->getOperand(0).getMBB();
280 TBB = LastInst->getOperand(0).getMBB();
305 TBB = SecondLastInst->getOperand(2).getMBB();
318 TBB = SecondLastInst->getOperand(0).getMBB();
332 TBB = SecondLastInst->getOperand(0).getMBB();
346 TBB = SecondLastInst->getOperand(0).getMBB();
389 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, argument
[all...]
/external/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp139 MachineBasicBlock *&TBB,
175 TBB = Branch.Target->getMBB();
188 TBB = 0;
194 // TBB is used to indicate the unconditinal destination.
195 TBB = Branch.Target->getMBB();
202 FBB = TBB;
203 TBB = Branch.Target->getMBB();
210 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
214 if (TBB != Branch.Target->getMBB())
260 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, argument
138 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp117 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, argument
125 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
152 return InsertBranch(MBB, TBB, 0, Cond, DL);
155 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
158 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
163 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
171 MachineBasicBlock *&TBB,
175 TBB = NULL;
248 TBB = LastInst->getOperand(0).getMBB();
252 TBB
170 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
[all...]
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp271 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, argument
275 TBB = 0;
305 TBB = I->getOperand(0).getMBB();
312 FBB = TBB;
313 TBB = I->getOperand(0).getMBB();
391 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, argument
403 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
410 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
412 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
414 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
[all...]
H A DARMFastISel.cpp1296 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)]; local
1309 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1310 std::swap(TBB, FBB);
1325 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1327 FuncInfo.MBB->addSuccessor(TBB);
1341 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1342 std::swap(TBB, FBB);
1348 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1351 FuncInfo.MBB->addSuccessor(TBB);
1357 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
[all...]
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp2624 MachineBasicBlock *&TBB,
2652 TBB = I->getOperand(0).getMBB();
2665 TBB = 0;
2672 // TBB is used to indicate the unconditional destination.
2673 TBB = I->getOperand(0).getMBB();
2722 FBB = TBB;
2723 TBB = I->getOperand(0).getMBB();
2732 assert(TBB);
2736 if (TBB != I->getOperand(0).getMBB())
2788 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, argument
2623 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
[all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp1381 MachineBasicBlock *TBB,
1409 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1417 NULL, TBB, FBB, CurBB);
1423 MachineBasicBlock *TBB,
1435 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1447 // jmp_if_X TBB
1450 // jmp_if_Y TBB
1455 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1458 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1465 // jmp_if_Y TBB
1380 EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB) argument
1422 FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, unsigned Opc) argument
[all...]

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