| /dalvik/vm/compiler/codegen/ |
| H A D | CodegenFactory.cpp | 54 int reg1)
58 genRegCopy(cUnit, reg1, rlSrc.lowReg);
60 loadWordDisp(cUnit, rSELF, offsetof(Thread, interpSave.retval), reg1);
64 reg1);
74 int reg1)
76 dvmCompilerClobber(cUnit, reg1);
77 dvmCompilerMarkInUse(cUnit, reg1);
78 loadValueDirect(cUnit, rlSrc, reg1);
53 loadValueDirect(CompilationUnit *cUnit, RegLocation rlSrc, int reg1) argument
73 loadValueDirectFixed(CompilationUnit *cUnit, RegLocation rlSrc, int reg1) argument
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| H A D | RallocUtil.cpp | 105 void dvmCompilerFlushRegWide(CompilationUnit *cUnit, int reg1, int reg2) argument
107 RegisterInfo *info1 = getRegInfo(cUnit, reg1);
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| /dalvik/vm/compiler/codegen/arm/ |
| H A D | ArchFactory.cpp | 74 int reg1, int reg2, int dOffset,
78 res = opRegReg(cUnit, kOpCmp, reg1, reg2);
72 genRegRegCheck(CompilationUnit *cUnit, ArmConditionCode cond, int reg1, int reg2, int dOffset, TGT_LIR *pcrLabel) argument
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| /dalvik/vm/compiler/codegen/arm/Thumb/ |
| H A D | Gen.cpp | 255 int reg1 = loadValue(cUnit, rlSrc2, kCoreReg).lowReg; local
256 newLIR2(cUnit, kThumbCmpRR, reg0, reg1);
259 newLIR2(cUnit, kThumbMovRR, reg0, reg1);
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| /dalvik/vm/compiler/codegen/mips/ |
| H A D | CodegenFactory.cpp | 48 int reg1)
52 genRegCopy(cUnit, reg1, rlSrc.lowReg);
54 loadWordDisp(cUnit, rSELF, offsetof(Thread, interpSave.retval), reg1);
58 reg1);
68 int reg1)
70 dvmCompilerClobber(cUnit, reg1);
71 dvmCompilerMarkInUse(cUnit, reg1);
72 loadValueDirect(cUnit, rlSrc, reg1);
284 int reg1, int reg2, int dOffset,
290 res = newLIR3(cUnit, kMipsSlt, tReg, reg1, reg
47 loadValueDirect(CompilationUnit *cUnit, RegLocation rlSrc, int reg1) argument
67 loadValueDirectFixed(CompilationUnit *cUnit, RegLocation rlSrc, int reg1) argument
282 genRegRegCheck(CompilationUnit *cUnit, MipsConditionCode cond, int reg1, int reg2, int dOffset, MipsLIR *pcrLabel) argument
[all...] |
| H A D | RallocUtil.cpp | 107 static void flushRegWide(CompilationUnit *cUnit, int reg1, int reg2) argument
109 RegisterInfo *info1 = getRegInfo(cUnit, reg1);
1017 int reg1, int reg2)
1019 flushRegWide(cUnit, reg1, reg2);
1016 dvmCompilerFlushRegWideForV5TEVFP(CompilationUnit *cUnit, int reg1, int reg2) argument
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| H A D | CodegenDriver.cpp | 2680 int reg1 = rlSrc1.lowReg; local
2694 test = newLIR3(cUnit, kMipsSlt, tReg, reg1, reg2);
2695 reg1 = tReg;
2701 test = newLIR3(cUnit, kMipsSlt, tReg, reg2, reg1);
2702 reg1 = tReg;
2708 test = newLIR3(cUnit, kMipsSlt, tReg, reg2, reg1);
2709 reg1 = tReg;
2715 test = newLIR3(cUnit, kMipsSlt, tReg, reg1, reg2);
2716 reg1 = tReg;
2725 genConditionalBranchMips(cUnit, opc, reg1, reg
[all...] |
| /dalvik/vm/compiler/codegen/mips/Mips32/ |
| H A D | Gen.cpp | 290 int reg1 = loadValue(cUnit, rlSrc2, kCoreReg).lowReg; local
293 newLIR3(cUnit, kMipsSlt, tReg, reg0, reg1);
296 newLIR3(cUnit, kMipsSlt, tReg, reg1, reg0);
298 newLIR3(cUnit, kMipsMovz, reg0, reg1, tReg);
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| /dalvik/vm/compiler/codegen/x86/ |
| H A D | LowerHelper.cpp | 1131 void compare_reg_reg(int reg1, bool isPhysical1, argument
1134 dump_reg_reg(m, ATOM_NORMAL, OpndSize_32, reg1, isPhysical1, reg2, isPhysical2, LowOpndRegType_gp);
1136 void compare_reg_reg_16(int reg1, bool isPhysical1, argument
1139 dump_reg_reg(m, ATOM_NORMAL, OpndSize_16, reg1, isPhysical1, reg2, isPhysical2, LowOpndRegType_gp);
1154 void compare_ss_reg_with_reg(LowOp* op, int reg1, bool isPhysical1, argument
1157 dump_reg_reg(m, ATOM_NORMAL, OpndSize_32, reg1, isPhysical1, reg2, isPhysical2, LowOpndRegType_xmm);
1171 void compare_sd_reg_with_reg(LowOp* op, int reg1, bool isPhysical1, argument
1174 dump_reg_reg(m, ATOM_NORMAL, OpndSize_64, reg1, isPhysical1, reg2, isPhysical2, LowOpndRegType_xmm);
1370 int reg1, bool isPhysical1,
1377 dump_reg_reg(m, ATOM_NORMAL_ALU, size, reg1, isPhysical
1369 alu_binary_reg_reg(OpndSize size, ALU_Opcode opc, int reg1, bool isPhysical1, int reg2, bool isPhysical2) argument
1663 conditional_move_reg_to_reg(OpndSize size, ConditionCode cc, int reg1, bool isPhysical1, int reg, bool isPhysical) argument
[all...] |
| /dalvik/vm/analysis/ |
| H A D | CodeVerify.cpp | 2073 * Assumes we've already validated reg1/reg2.
2084 static bool upcastBooleanOp(RegisterLine* registerLine, u4 reg1, u4 reg2) argument
2088 type1 = getRegisterType(registerLine, reg1);
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