Searched defs:reg2 (Results 1 - 8 of 8) sorted by relevance

/dalvik/vm/compiler/codegen/arm/
H A DArchFactory.cpp74 int reg1, int reg2, int dOffset,
78 res = opRegReg(cUnit, kOpCmp, reg1, reg2);
72 genRegRegCheck(CompilationUnit *cUnit, ArmConditionCode cond, int reg1, int reg2, int dOffset, TGT_LIR *pcrLabel) argument
/dalvik/vm/compiler/codegen/mips/
H A DCodegenFactory.cpp284 int reg1, int reg2, int dOffset,
290 res = newLIR3(cUnit, kMipsSlt, tReg, reg1, reg2);
295 res = newLIR3(cUnit, kMipsSltu, tReg, reg1, reg2);
282 genRegRegCheck(CompilationUnit *cUnit, MipsConditionCode cond, int reg1, int reg2, int dOffset, MipsLIR *pcrLabel) argument
H A DRallocUtil.cpp107 static void flushRegWide(CompilationUnit *cUnit, int reg1, int reg2) argument
110 RegisterInfo *info2 = getRegInfo(cUnit, reg2);
1017 int reg1, int reg2)
1019 flushRegWide(cUnit, reg1, reg2);
1016 dvmCompilerFlushRegWideForV5TEVFP(CompilationUnit *cUnit, int reg1, int reg2) argument
H A DCodegenDriver.cpp2681 int reg2 = rlSrc2.lowReg; local
2694 test = newLIR3(cUnit, kMipsSlt, tReg, reg1, reg2);
2696 reg2 = r_ZERO;
2701 test = newLIR3(cUnit, kMipsSlt, tReg, reg2, reg1);
2703 reg2 = -1;
2708 test = newLIR3(cUnit, kMipsSlt, tReg, reg2, reg1);
2710 reg2 = r_ZERO;
2715 test = newLIR3(cUnit, kMipsSlt, tReg, reg1, reg2);
2717 reg2 = -1;
2725 genConditionalBranchMips(cUnit, opc, reg1, reg2,
[all...]
/dalvik/vm/compiler/codegen/x86/libenc/
H A Denc_wrapper.cpp226 int reg2, bool isPhysical2, LowOpndRegType type, char * stream) {
227 if((m == Mnemonic_MOV || m == Mnemonic_MOVQ) && reg == reg2) return stream;
229 add_r(args, reg2, size); //destination
476 int reg, bool isPhysical, int reg2,
479 add_r(args, reg2, OpndSize_32); //destination
490 int reg, bool isPhysical,int reg2,
493 add_r(args, reg2, OpndSize_32); //destination
224 encoder_reg_reg(Mnemonic m, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type, char * stream) argument
475 encoder_movez_reg_to_reg(OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type, char * stream) argument
489 encoder_moves_reg_to_reg(OpndSize size, int reg, bool isPhysical,int reg2, bool isPhysical2, LowOpndRegType type, char * stream) argument
/dalvik/vm/compiler/codegen/
H A DRallocUtil.cpp105 void dvmCompilerFlushRegWide(CompilationUnit *cUnit, int reg1, int reg2) argument
108 RegisterInfo *info2 = getRegInfo(cUnit, reg2);
/dalvik/vm/compiler/codegen/x86/
H A DLowerHelper.cpp322 int reg, int reg2, LowOpndRegType type) {
325 reg-reg2, size==OpndSize_64, stream);
328 stream = encoder_reg_reg(m, size, reg, true, reg2, true, type, stream);
338 int reg2, bool isPhysical2, LowOpndRegType type) {
339 return lower_reg_reg(m, ATOM_NORMAL, size, reg, reg2, type);
352 int reg2, bool isPhysical2, LowOpndRegType type) {
356 if(isMnemonicMove(m) && regAll == reg2) return NULL;
357 return lower_reg_reg(m, ATOM_NORMAL, size, regAll, reg2, type);
359 stream = encoder_reg_reg(m, size, reg, isPhysical, reg2, isPhysical2, type, stream);
368 int reg2, boo
321 lower_reg_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, int reg2, LowOpndRegType type) argument
336 dump_reg_reg_noalloc(Mnemonic m, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type) argument
350 dump_reg_reg_noalloc_dst(Mnemonic m, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type) argument
366 dump_reg_reg_noalloc_src(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type) argument
387 dump_reg_reg(Mnemonic m, AtomOpCode m2, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2, LowOpndRegType type) argument
534 dump_movez_reg_reg(Mnemonic m, OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1131 compare_reg_reg(int reg1, bool isPhysical1, int reg2, bool isPhysical2) argument
1136 compare_reg_reg_16(int reg1, bool isPhysical1, int reg2, bool isPhysical2) argument
1154 compare_ss_reg_with_reg(LowOp* op, int reg1, bool isPhysical1, int reg2, bool isPhysical2) argument
1171 compare_sd_reg_with_reg(LowOp* op, int reg1, bool isPhysical1, int reg2, bool isPhysical2) argument
1369 alu_binary_reg_reg(OpndSize size, ALU_Opcode opc, int reg1, bool isPhysical1, int reg2, bool isPhysical2) argument
1402 alu_ss_binary_reg_reg(ALU_Opcode opc, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1410 alu_sd_binary_reg_reg(ALU_Opcode opc, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1494 movez_reg_to_reg(OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1530 move_reg_to_reg(OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1539 move_reg_to_reg_noalloc(OpndSize size, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
[all...]
/dalvik/vm/analysis/
H A DCodeVerify.cpp2073 * Assumes we've already validated reg1/reg2.
2084 static bool upcastBooleanOp(RegisterLine* registerLine, u4 reg1, u4 reg2) argument
2089 type2 = getRegisterType(registerLine, reg2);

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