Searched refs:instruction (Results 176 - 200 of 286) sorted by relevance

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/external/llvm/test/MC/SystemZ/
H A Dinsn-bad.s72 #CHECK: error: {{(instruction requires: distinct-ops)?}}
77 #CHECK: error: {{(instruction requires: distinct-ops)?}}
118 #CHECK: error: {{(instruction requires: distinct-ops)?}}
163 #CHECK: error: {{(instruction requires: distinct-ops)?}}
168 #CHECK: error: {{(instruction requires: distinct-ops)?}}
197 #CHECK: error: {{(instruction requires: distinct-ops)?}}
202 #CHECK: error: {{(instruction requires: distinct-ops)?}}
215 #CHECK: error: {{(instruction requires: distinct-ops)?}}
546 #CHECK: error: invalid instruction
548 #CHECK: error: invalid instruction
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/external/libnfc-nxp/src/
H A DphHciNfc_NfcIPMgmt.c437 uint8_t instruction=0; local
443 /* Get the instruction bits from the Message Header */
444 instruction = (uint8_t) GET_BITS8( message->msg_header,
446 if (NXP_EVT_NFC_ACTIVATED == instruction)
639 uint8_t instruction=0; local
644 /* Get the instruction bits from the Message Header */
645 instruction = (uint8_t) GET_BITS8( message->msg_header,
647 if (NXP_EVT_NFC_ACTIVATED == instruction)
756 uint8_t instruction=0; local
763 /* Get the instruction bit
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H A DphHciNfc_ISO15693.c584 uint8_t instruction=0, local
591 /* Get the instruction bits from the Message Header */
592 instruction = (uint8_t) GET_BITS8( message->msg_header,
595 if ((EVT_TARGET_DISCOVERED == instruction)
H A DphHciNfc_Jewel.c657 uint8_t instruction=0, local
664 /* Get the instruction bits from the Message Header */
665 instruction = (uint8_t) GET_BITS8( message->msg_header,
668 if ((EVT_TARGET_DISCOVERED == instruction)
H A DphHciNfc_RFReaderB.c633 uint8_t instruction=0, local
640 /* Get the instruction bits from the Message Header */
641 instruction = (uint8_t) GET_BITS8( message->msg_header,
644 if ((EVT_TARGET_DISCOVERED == instruction)
H A DphHciNfc_RFReaderA.c824 uint8_t instruction=0, local
831 /* Get the instruction bits from the Message Header */
832 instruction = (uint8_t) GET_BITS8( message->msg_header,
835 HCI_DEBUG ("HCI : instruction : %02X\n", instruction);
838 if ((EVT_TARGET_DISCOVERED == instruction)
/external/chromium/sdch/open-vcdiff/src/
H A Dvcdecoder.cc201 // Decodes a single ADD instruction, updating parent_->decoded_target_.
204 // Decodes a single RUN instruction, updating parent_->decoded_target_.
207 // Decodes a single COPY instruction, updating parent_->decoded_target_.
241 // Executes a single COPY or ADD instruction, appending data to
245 // Executes a single RUN instruction, appending data to
252 // by the number of instruction/size bytes parsed.
1095 // Reduce expected instruction segment length by bytes parsed
1211 VCDiffInstructionType instruction = local
1213 switch (instruction) {
1228 LOG(ERROR) << VCDiffInstructionName(instruction)
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/external/chromium_org/courgette/
H A Dadjustment_method.cc598 Instruction* instruction = instructions[i]; local
599 if (Label* label = program->InstructionAbs32Label(instruction))
601 if (Label* label = program->InstructionRel32Label(instruction))
/external/proguard/src/proguard/shrink/
H A DUsageMarker.java31 import proguard.classfile.instruction.*;
32 import proguard.classfile.instruction.visitor.InstructionVisitor;
834 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {} argument
/external/valgrind/main/none/tests/arm/
H A Dneon64.c43 /* test macros to generate and output the result of a single instruction */
52 #define TESTINSN_imm(instruction, QD, imm) \
58 instruction ", #" #imm "\n\t" \
65 instruction, out[1], out[0]); \
74 instruction ", #" #imm "\n\t" \
81 instruction, out[1], out[0]); \
84 #define TESTINSN_un(instruction, QD, QM, QMtype, QMval) \
91 instruction "\n\t" \
98 instruction, out[1], out[0], QMval); \
108 instruction "\
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H A Dneon128.c42 /* test macros to generate and output the result of a single instruction */
51 #define TESTINSN_imm(instruction, QD, imm) \
57 instruction ", #" #imm "\n\t" \
64 instruction, out[3], out[2], out[1], out[0]); \
73 instruction ", #" #imm "\n\t" \
80 instruction, out[3], out[2], out[1], out[0]); \
83 #define TESTINSN_un(instruction, QD, QM, QMtype, QMval) \
90 instruction "\n\t" \
97 instruction, out[3], out[2], out[1], out[0], QMval); \
107 instruction "\
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/external/chromium_org/native_client_sdk/src/doc/
H A Dfaq.rst45 * Processors with the x86-32, x86-64, or ARM instruction set
197 What are the supported instruction set architectures?
202 with the x86-32, x86-64, and ARM instruction set architectures, as well
214 portability to JavaScript and can adapt to new instruction set
369 indirect branches target a safe instruction.
479 However, to run on different instruction set architectures (such as
561 instruction set architecture (x86-32, x86-64 or ARM). You can ensure
/external/chromium_org/media/base/simd/
H A Dlinear_scale_yuv_to_rgb_mmx_x64.asm87 ; Saves two instruction. :)
/external/valgrind/main/none/tests/mips32/
H A DMIPS32int.c3 #define TESTINST1(instruction, RSval, RTval, RD, RS, RT) \
10 instruction "\n\t" \
17 instruction, out, RSval, RTval); \
20 #define TESTINST2(instruction, RSval, imm, RT, RS) \
25 instruction "\n\t" \
32 instruction, out, RSval, imm); \
35 #define TESTINST3(instruction, RSval, RD, RS) \
40 instruction "\n\t" \
47 instruction, out, RSval); \
50 #define TESTINST3a(instruction, RSva
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/external/chromium_org/third_party/WebKit/Source/core/xml/
H A DXPathParser.cpp115 nodeTypeNames.add("processing-instruction");
380 if (name == "processing-instruction")
/external/proguard/src/proguard/classfile/visitor/
H A DClassPrinter.java32 import proguard.classfile.instruction.*;
33 import proguard.classfile.instruction.visitor.InstructionVisitor;
615 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) argument
617 println(instruction.toString(offset));
/external/proguard/src/proguard/evaluation/
H A DBasicInvocationUnit.java27 import proguard.classfile.instruction.*;
/external/valgrind/main/exp-bbv/tests/ppc32-linux/
H A Dll.S52 # saves one instruction on any future load from memory
/external/chromium_org/v8/src/x64/
H A Dassembler-x64.h376 // Machine instruction Immediates
390 // Machine instruction Operands
427 // Queries related to the size of the generated instruction.
428 // Whether the generated instruction will have a REX prefix.
431 // instruction.
539 // We check before assembling an instruction that there is sufficient
540 // space to write an instruction and its relocation information.
543 // longest possible x64 instruction, 15 bytes, and the longest possible
545 // (There is a 15 byte limit on x64 instruction length that rules out some
547 // This allows for a single, fast space check per instruction
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/external/elfutils/libcpu/
H A Di386_parse.c202 struct instruction struct
231 struct instruction *next;
293 struct instruction *instr, int n);
303 static struct instruction *instructions;
1641 struct instruction *newp = xcalloc (sizeof (*newp),
2375 struct instruction *instr, int n)
2505 /* We reverse the order of the instruction list while processing it.
2508 struct instruction *reversed = NULL;
2510 struct instruction *runp = instructions;
2553 struct instruction *ol
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/external/chromium_org/third_party/openssl/openssl/crypto/
H A Dsparccpuid.S41 ! Following is V9 "rd %ccr,%o0" instruction. However! V8
245 ! Probe and instrument VIS1 instruction. Output is number of cycles it
/external/ganymed-ssh2/examples/
H A DSwingShell.java466 public String[] replyToChallenge(String name, String instruction, int numPrompts, String[] prompt, argument
473 /* Often, servers just send empty strings for "name" and "instruction" */
475 String[] content = new String[] { lastError, name, instruction, prompt[i] };
/external/llvm/
H A DREADME.android51 ==> * 96a74c5 - remove support for a bunch of obsolete instruction encodings and other backward compatibility hacks. (13 days ago) <Chris Lattner>
/external/llvm/lib/Support/Unix/
H A DSignals.inc190 // *after* the faulting instruction. Simply returning from the signal
/external/llvm/test/MC/ARM/
H A Dthumb2-mclass.s6 @ These tests test instruction encodings specific to v7m & v7m (FeatureMClass).

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